A method and system for implementing an anti-side channel attack aes encryption algorithm hardware

Abstract

The present disclosure provides an anti-side channel attack AES encryption algorithm hardware implementation method and system, which belongs to the technical field of information security, the scheme comprises: performing exclusive or operation on the to-be-processed plaintext data and the encryption key of the current round; and performing key expansion operation by using the pre-implemented S-box; wherein the key expansion operation takes four S-box periods to complete the conversion of the low 32 bits of each part, and the conversion operation of the remaining bits of each part is distributed in the subsequent execution process; based on the exclusive or operation result, sequentially performing byte substitution, column mixing and row transformation operations, wherein the byte substitution operation is realized based on the pre-implemented S-box; iteratively executing the above steps for a preset number of rounds to complete the implementation of the AES encryption algorithm; wherein the preset number of rounds is determined by the number of key bits of the AES encryption algorithm, and the row transformation is not performed in the last round.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of information security, and particularly relates to a hardware implementation method and system of an AES encryption algorithm resisting side channel attacks. BACKGROUND

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute the prior art.

[0003] Advanced Encryption Standard (AES) in cryptography, also known as Rijndael encryption, is a block encryption standard adopted by the US federal government, which is mathematically proven to be very secure and can resist mathematical attacks such as linear or differential cryptanalysis. The designer assumes a classic counter model, and the encryption operation is regarded as a black box, which only provides an input and output interface for the attacker. However, the inventors found that when it is deployed in an embedded device, some unintentional leakage signals such as instantaneous power consumption, electromagnetic radiation, etc. sensitive information will make the black box become a gray box. Side channel analysis is a cheap and scalable technology that can enable attackers to use these leaked signals and extract our keys or passwords from them, while existing methods mainly focus on creating rigorous secure algorithms from a mathematical perspective, ignoring physical security protection. SUMMARY

[0004] In order to solve the above problems, the present disclosure provides a hardware implementation method and system of an AES encryption algorithm resisting side channel attacks, which reduces the equivalent gate number of the anti-side channel mask AES encryption algorithm hardware implementation under the premise of not losing security by adopting the mask implementation of the proposed S-box, based on serial implementation, register reuse and shift register assignment, etc. to reduce the equivalent gate number of the AES S-box, thereby effectively reducing the equivalent gate number of the anti-side channel mask AES encryption algorithm hardware implementation.

[0005] According to a first aspect of the embodiments of the present disclosure, a hardware implementation method of an AES encryption algorithm resisting side channel attacks is provided, comprising:

[0006] XOR operation is performed on the to-be-processed plaintext data and the encryption key of the current round, and a key expansion operation is performed by using a pre-implemented S-box; wherein the key expansion operation takes four S-box periods to complete the conversion of the low 32 bits of each part, and the conversion operation of the remaining bits of each part is distributed in the subsequent execution process;

[0007] Based on the XOR operation result, byte substitution, column mixing and row transformation operations are sequentially performed, wherein the byte substitution operation is implemented based on a pre-implemented S-box;

[0008] The above steps are iteratively performed for a preset number of rounds to complete the implementation of the AES encryption algorithm; wherein the preset number of rounds is determined by the number of key bits of the AES encryption algorithm, and no row transformation is performed in the last round;

[0009] The implementation of the S-box includes a linear feedback shift register, a serial modular multiplication multiplier, a delta function, a Boolean mask to multiplication mask conversion, an inverse operation, a multiplication mask to Boolean mask conversion, an affine transformation, and a signal control and comprehensive processing process.

[0010] Further, the Boolean mask to multiplication mask conversion, the inverse operation, and the multiplication mask to Boolean mask conversion share a group of registers, wherein for a first-order AES implementation, a 16-bit register and an 8-bit register are selected, the lower 8 bits of the 16-bit register are used as one group of inputs of the serial multiplication multiplier, and the upper 8 bits are used to receive the output of the serial multiplication multiplier; the 8-bit register is used as another group of inputs of the serial multiplication multiplier.

[0011] Further, for a second-order AES implementation, the multiplication mask to Boolean mask conversion is based on the selection of a 16-bit register and an 8-bit register, and an additional 8-bit register is added.

[0012] Further, heuristic algorithms are used in the inverse operation and the affine transformation to optimize the number of implementation gates, wherein the heuristic algorithm is specifically: applying the previous XOR operation to the subsequent XOR operation, thereby reducing the number of XOR gates.

[0013] Further, the implementation of the delta function is specifically represented as:

[0014]

[0015] wherein x is the input when the S-box inverse is performed, and is based on The conversion of the input avoids the zero value problem.

[0016] Further, the linear feedback shift register generates the required random number by selecting a 32-bit shift register, which is used for random number generation in the delta function, the Boolean mask to multiplication mask conversion, and the multiplication mask to Boolean mask conversion.

[0017] Further, the serial modular multiplication multiplier is an 8-bit modular multiplication multiplier implemented in series, and there is only one 8-bit modular multiplication multiplier in the S-box.

[0018] Further, the plaintext data to be processed is XORed with the encryption key of the current round, specifically: the XOR of the plaintext data and the encryption key is split, calculation is performed based on the preset size of the number of bits, and after the calculation is completed, the shift register is circularly shifted to complete the XOR operation.

[0019] Further, the plaintext data is stored in a plaintext register, and the encryption key is stored in a key register.

[0020] According to a second aspect of the embodiments of the present disclosure, an anti-side channel attack AES encryption algorithm hardware implementation system is provided, which performs the steps of an anti-side channel attack AES encryption algorithm hardware implementation method as described above, specifically:

[0021] The plaintext data to be processed is XORed with the encryption key of the current round, and a pre-implemented S-box is used for key expansion operation; wherein the key expansion operation takes four S-box periods to complete the conversion of the low 32 bits of each part, and the conversion operation of the remaining bits of each part is distributed in the subsequent execution process;

[0022] Based on the XOR operation result, byte substitution, column mixing, and row transformation operations are sequentially performed, wherein the byte substitution operation is implemented based on a pre-implemented S-box;

[0023] The above steps are iteratively performed for a preset number of rounds to complete the implementation of the AES encryption algorithm; wherein the preset number of rounds is determined by the key bit number of the AES encryption algorithm, and the row transformation is not performed in the last round;

[0024] The implementation of the S-box includes the implementation of a linear feedback shift register, a serial modular multiplication multiplier, a delta function, a Boolean conversion multiplier, an inverse, a multiplication conversion Boolean, an affine transformation, and signal control and comprehensive processing.

[0025] Compared with the prior art, the present disclosure has the following beneficial effects:

[0026] The present disclosure provides an anti-side channel attack AES encryption algorithm hardware implementation method and system, which reduces the equivalent gate number of the anti-side channel mask AES encryption algorithm hardware implementation without losing security by using the proposed S-box mask implementation, based on serial implementation, register multiplexing, and shift register assignment, and effectively reduces the equivalent gate number of the anti-side channel mask AES encryption algorithm hardware implementation.

[0027] The advantages of the additional aspects of the present disclosure will be partially given in the following description, partially will become apparent from the following description, or will be understood through the practice of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are incorporated in and form a part of the specification, serve to further understand the present disclosure, and, together with the description, illustrate one or more exemplary embodiments of the present disclosure, and, are not intended to limit the present disclosure.

[0029] Figure 1 Schematic diagram for AES S-box implementation process described in embodiments of the present disclosure;

[0030] Figure 2 Schematic diagram for linear feedback shift register described in embodiments of the present disclosure;

[0031] Figure 3 Schematic diagram for serial modular multiplication multiplier described in embodiments of the present disclosure;

[0032] Figure 4 Schematic diagram for first order delta function described in embodiments of the present disclosure;

[0033] Figure 5 Schematic diagram for second order delta function described in embodiments of the present disclosure;

[0034] Figure 6 Pseudo code schematic diagram for Boolean mask to multiplication mask conversion described in embodiments of the present disclosure;

[0035] Figure 7 Pseudo code schematic diagram for inversion operation described in embodiments of the present disclosure;

[0036] Figure 8 Pseudo code schematic diagram for multiplication mask to Boolean mask conversion described in embodiments of the present disclosure;

[0037] Figure 9 Schematic diagram for AES S-box affine transformation described in embodiments of the present disclosure;

[0038] Figure 10 Schematic diagram for first order transform described in embodiments of the present disclosure;

[0039] Figure 11 Schematic diagram for second order transform described in embodiments of the present disclosure;

[0040] Figure 12 Flowchart for AES algorithm described in embodiments of the present disclosure;

[0041] Figure 13 Schematic diagram for first order AES algorithm test results described in embodiments of the present disclosure;

[0042] Figure 14 Schematic diagram for second order AES algorithm test results described in embodiments of the present disclosure;

[0043] Figure 15Fig. 1 is a schematic diagram of experimental results of the AES S-box and AES-128 according to an embodiment of the present disclosure;

[0044] wherein, represents an XOR gate; represents an AND gate; represents an inverter, i.e., taking the opposite of a bit; represents a multiplication gate. DETAILED DESCRIPTION

[0045] The present disclosure will be further described below in conjunction with the accompanying drawings and embodiments.

[0046] It should be noted that the following detailed description is illustrative only and is intended to provide further description of the present disclosure. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0047] It should be noted that the terms used herein are only intended to describe specific embodiments and are not intended to limit exemplary embodiments according to the present disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and it should also be understood that the terms "comprise" and / or "include" as used in the specification indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0048] The embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0049] Embodiment One:

[0050] The purpose of the present embodiment is to provide an anti-side channel attack AES encryption algorithm hardware implementation method, comprising:

[0051] XOR operation is performed on the to-be-processed plaintext data and the encryption key of the current round, and a pre-implemented S-box is used for key expansion operation; wherein the key expansion operation takes four S-box periods to complete the conversion of the low 32 bits of each part, and the conversion operation of the remaining bits of each part is distributed in the subsequent execution process;

[0052] Based on the XOR operation result, byte substitution, column mixing, and row transformation operations are sequentially performed, wherein the byte substitution operation is implemented based on a pre-implemented S-box;

[0053] The above steps are iteratively performed for a preset number of rounds to complete the implementation of the AES encryption algorithm; wherein the preset number of rounds is determined by the key bit number of the AES encryption algorithm, and the row transformation is not performed in the last round; (for example, AES-128, which uses a 128-bit key, has a fixed preset number of rounds of 10 rounds)

[0054] The implementation of the S-box includes a linear feedback shift register, a serial modular multiplication multiplier, a delta function, a Boolean mask to multiplication mask conversion, an inverse operation, a multiplication mask to Boolean mask conversion, an affine transformation, and an implementation of signal control and comprehensive processing.

[0055] Further, the Boolean mask to multiplication mask conversion, the inverse operation, and the multiplication mask to Boolean mask conversion operation share a group of registers, wherein, for a first-order AES implementation, a 16-bit register and an 8-bit register are selected, the lower 8 bits of the 16-bit register are used as a group of inputs of the serial multiplication multiplier, and the upper 8 bits are used to receive the output of the serial multiplication multiplier; the 8-bit register is used as another group of inputs of the serial multiplication multiplier.

[0056] Further, for a second-order AES implementation, the multiplication mask to Boolean mask conversion operation is based on the selection of a 16-bit register and an 8-bit register, and an additional 8-bit register is added.

[0057] Further, heuristic algorithms are used in the inverse operation and the affine transformation to optimize the number of implementation gates, wherein the heuristic algorithm is specifically that the previous XOR operation is applied to the subsequent XOR operation, thereby reducing the number of XOR gates.

[0058] Further, the implementation of the delta function is specifically represented as:

[0059]

[0060] wherein x is the input when the S-box is inverted, and is based on The conversion of the input avoids the zero value problem.

[0061] Further, the linear feedback shift register generates the required random number by selecting a 32-bit shift register, which is used for the generation of random numbers in the delta function, the Boolean mask to multiplication mask conversion, and the multiplication mask to Boolean mask conversion.

[0062] Further, the serial modular multiplication multiplier is an 8-bit modular multiplication multiplier implemented in series, and there is only one 8-bit modular multiplication multiplier in the S-box.

[0063] Further, the XOR operation between the to-be-processed plaintext data and the encryption key of the current round is specifically that the XOR operation between the plaintext data and the encryption key is split, calculation is performed based on a preset size of bits, and a shift register is used for circular shifting after the calculation is completed, thereby completing the XOR operation.

[0064] Further, the plaintext data is stored in a plaintext register, and the encryption key is stored in a key register.

[0065] Specifically, for ease of understanding, the scheme described in the embodiment is described in detail below in conjunction with the drawings:

[0066] In the side channel security implementation, the goal of the scheme described in the embodiment is to enable the leakage of the processed value in the implementation to be independent of the sensitive input and the sensitive intermediate variable. At the architecture level, this is achieved by masking, which means that the data processed by the mask is probabilistically divided into multiple shares, and the sensitive data can only be recovered when all the shares are known. Moreover, as the noise level increases, it will become more difficult to recover the ciphertext. In the embodiment, only first-order and second-order DPA (Differential Power Analysis) attack security implementation measures are proposed, because at a sufficient noise level, it is already very secure.

[0067] The AES-128 algorithm includes ten rounds of encryption operations. The entire algorithm includes two input interfaces and one output interface. Before entering the first round, the plaintext and the encryption key are first XORed, and then nine rounds of the same operation are entered: key expansion, byte substitution, column mixing, and row transformation. The last round is different from the first nine rounds in that there is no row transformation. In the key expansion and byte substitution, the S-box is needed, so how to securely and efficiently implement the AES S-box is the most important work. The masking implementation of the S-box mainly includes: Kronecker Delta function proposed to solve the zero value problem, Boolean mask to multiplication mask, inverse process, multiplication mask to Boolean mask, and affine transformation.

[0068] In existing papers and experiments, ideas and theoretical and technical support for implementing the S-box and the AES algorithm have been provided. Our invention optimizes the equivalent gate number of existing results through a series of techniques such as serial implementation, register reuse, and shift register assignment, without affecting its security. From the results, we greatly optimize the equivalent gate number of the first-order and second-order AES S-box algorithm implementation, and also show great optimization on the third-order AES algorithm. The second-order AES algorithm also has some optimization. At the same time, we also deploy our implementation to an FPGA that can evaluate the side channel security, and analyze the security in a low-noise environment. We collected up to 200,000 curves and found no leakage.

[0069] Specifically, an anti-side channel attack AES encryption algorithm hardware implementation method includes the implementation of the AES S-box and the implementation of the AES encryption algorithm based on the implemented S-box, which are described in detail as follows:

[0070] (I) Implementation of S-box

[0071] AsFigure 1 As shown, the mask implementation process of AES S-box includes six processes: delta function, Boolean mask to multiplication mask, inverse, multiplication mask to Boolean mask, affine transformation and finally signal control and comprehensive processing. Before implementing the six steps, we first need to implement the tool for generating random numbers, linear feedback shift register (LFSR) and the serial modulus multiplication multiplier (Multiply Serial) used in the entire conversion process. The two tools are the basis for the implementation of the entire algorithm. The following describes the implementation process of the S-box in detail. Specifically, the following describes the theoretical count and implementation process of each module of the S-box. In addition, the corresponding equivalent gate optimization scheme, register usage and signal control of the first and second orders are described in detail:

[0072] (1) Implement linear feedback shift register (LFSR)

[0073] Regardless of the first or second order, the same random number generation tool is used in the scheme described in this embodiment. Linear feedback shift register (LFSR) is used to generate the random numbers required by the algorithm in the three steps of delta function, Boolean mask to multiplication mask and step six multiplication mask to Boolean mask.

[0074] As shown in Figure 2 We choose a 32-bit shift register to generate the required random numbers. When the reset signal (rst_n) arrives, a random 32-bit number is input. When the enable signal (seed_valid) arrives, we start shifting. The result of the four-bit negation and XOR operation is assigned to the lowest bit of the shift register, and the highest bit of the shift register is output as a random number seed.

[0075] It should be noted that the random number required by the delta function is a period of 1 bit, a total of seven periods, and the random number operation is synchronized with the delta function matrix operation. The 8-bit random number required for conversion between Boolean and multiplication mask is generated in advance.

[0076] (2) Implement serial modulus multiplication multiplier (Multiply_serial)

[0077] In order to reduce the equivalent gate number, the scheme described in the embodiment has only one 8-bit modular multiplication multiplier throughout the implementation of the S-box and even the entire AES, is implemented in series, is called in series, and uses time to replace area. We set a counter, because it is a serial calculation, one bit at a time, so 8-bit numbers need 8 cycles to calculate. We calculate from high to low, the first calculation does not need to be taken modulo because the number cannot exceed GF(2 8). The remaining calculation parts are the same, first left shift the result by 1 bit, then XOR with the result of the highest bit, the second highest bit, and the lowest bit of the multiplier. From the second calculation, we need to XOR the highest bit of the result with mod to determine whether to take modulo. We have omitted the judgment logic here, and directly XOR the result with the result of the highest bit of the 9 results and mod. This means that all 0s are not XORed, and all 1s are XORed. This can reduce unnecessary logic overhead. In addition, we define the result as a register, which saves the number of gates of the intermediate register and facilitates interaction with external modules. As shown in Figure 3 The implementation diagram of the serial modular multiplication multiplier described in the embodiment is shown.

[0078] (3) Implementation of delta function (the purpose is to solve the zero value problem in the multiplication mask)

[0079] In order to solve the zero value problem in the multiplication mask, the scheme described in the embodiment follows the idea of KroneckerDelta function, and when the AES S-box is inverted, the following formula is true: -1 x for x∈{0,1}, so the delta function can be changed to: Further, we complete the conversion of the input by implementing the following formula: which avoids the zero value problem, that is, Figure 1 : described in the implementation process of the AES S-box, first XOR the input x with δ(x), after the conversion process, and then XOR with δ(x).

[0080] The following detailed description of its specific implementation, we divide the first two orders to explain in detail. When the first order, we will input x into two, one of which is the second lowest bit of the first lowest bit of the second part of the lowest bit, the other is the second part of the remaining bits and the remaining bits of the first part, note that they are each part (that is, the input of the algorithm is divided into d+1 parts by the mask technique, that is, the XOR result of the d+1 parts should be consistent with the input, the specific number of parts can be determined according to actual needs) Corresponding bit combination, then arrange from high to low, which has the advantage of facilitating our subsequent operation. Then input them into the delta function, assign them to two registers a and b respectively during reset, then we need to use a line to construct a 2*2 matrix that always participates in the operation process, each element in the matrix is the result of the bitwise and and the cross and of the lowest two bits of a and the lowest two bits of b, note that the second and third positions are XORed with random1, then after the en signal comes we can assign the value of a register to the XOR result of each row of the matrix, and the b register is cyclically right shifted by 2 bits, which completes the operation in 7 clock cycles, note that the random number is generated by the lfsr in step one, 1 bit per cycle, together with the matrix operation, together with the operation, which is instantaneous.

[0081] The difference between the second order and the first order is that we input into two, one of which is the lowest bit combination of each part, the other is the combination of the remaining bits of each part, note that here there is no negation. After inputting into the delta function and resetting by the clock, all are negated. Actually, whether it is first order or second order, we need to negate one of them, but the effect of negating all in the second order is the same. Similarly, we construct a 3*3 matrix, which naturally also programs the results of the bitwise and and the cross and of the lowest three bits of a and the lowest three bits of b. Here we need three random numbers, random1, random2 and random3 are XORed with the corresponding positions of the upper and lower triangles, and naturally we also need Figure 1 The three lfsrs shown, when the en signal comes, a is the XOR result of each row of the three rows, and b is cyclically right shifted by three bits each time, and finally the output of the delta x is completed. The following two figures are respectively the implementation diagrams of the first order and the second order delta function:

[0082] (4) Boolean mask conversion multiplication mask

[0083] No matter first or second order, the Boolean mask conversion multiplier mask with inverse and multiplication mask conversion Boolean mask multiplexing a set of registers, and can effectively save the number of gates, wherein, when we need a first 16-bit register xin and 1 8-bit register yin, 16-bit register xin lowest 8 bits as the multiplier in step two of which a set of input, the highest 8 bits are used to receive the output of each multiplier operation completed zout, another 8-bit register yin as a multiplier of another set of input, so according to Figure 6 And Figure 7 The algorithm and its implementation process of the first Boolean mask conversion multiplier mask needs 3 multiplier period to complete, we through the cnt count to reach the multiplier operation period 10 and btm signal count to 3 to mark the successful completion of the step, at the same time through the shift register xin to replace the input of the multiplier x and register with inverse and multiplication mask conversion Boolean mask multiplexing greatly reduces the equivalent gate number.

[0084] The second order, the same reason, but more than 1 8-bit register used in the multiplication mask conversion Boolean mask, wherein, the number of registers of Boolean mask conversion multiplier mask and inverse operation is not changed, is to cover the 16-bit register xin of the lowest 8 bits of each multiplier in the algorithm, the other multiplier, that is, we produce a random number in the 8-bit register yin, so after 6 multiplier period can complete the operation, we still through the cnt whether for 10 and btm whether for 6 to mark the execution and end of the algorithm.

[0085] Further, through Figure 6 The algorithm shows that the first order needs 1 8-bit random number random1, and the second order needs 3 8-bit random numbers random1, random2 and random3. Note that these random numbers are the same as the random numbers required by the multiplication mask conversion Boolean mask, but they are different from the random numbers required by the delta function. Although they are also generated by different lfsr, they are generated at the beginning of the algorithm by consuming 8 cycles. After the generation is completed, they are stored in the random number register, and then participate in the subsequent algorithm execution. These random number registers do not occupy the actual algorithm gate number, but only open them when measuring the security of the algorithm.

[0086] As Figure 6 The pseudo code of the algorithm is shown in the following table. The specific algorithm flow chart will be described in the following S box implementation combined with inverse and multiplication mask conversion Boolean mask.

[0087] (5) implementation of inverse

[0088] The inverse on the finite field is actually the 254 power of the number. According to Figure 7The algorithm is shown to be calculated, so a total of 5 multiplier cycles can be completed. Specifically through the Boolean mask conversion multiplication mask operation described in a 16-bit register xin and an 8-bit register yin, while we also need to achieve the calculation of x^2, x^4 and x^16 three functions, we optimize the three functions by a new heuristic algorithm, the technical concept is to apply the previous XOR operation to the subsequent XOR operation, which can effectively reduce the number of XOR gates; The heuristic algorithm is specifically from the paper "Boyar J, Matthews P, Peralta R. Logic Minimization Techniques with Applications to Cryptology", the specific steps are not repeated here.

[0089] Finally, the multiplier and multiplicand of each step are also input to the corresponding xin, yin, and then the smooth progress of the inverse is controlled by whether cnt is 10 and whether the iv signal reaches 5.

[0090] (6) Multiplication mask conversion Boolean mask

[0091] The first-order idea is basically the same as the Boolean mask conversion multiplication mask and the inverse operation, according to Figure 8 The algorithm shown sequentially inputs the required multiplier and multiplicand into xin and yin, which requires another random number random2 corresponding to random1 in step four, and then completes the entire process through the shift register logic. Still, whether cnt is 10 and whether the mtb signal reaches 3 is determined to ensure the smooth progress of the process.

[0092] The second-order needs to be noted that it needs an additional 8-bit register to save the intermediate result zout of a certain step, otherwise the register is not enough. Then two random numbers random4 and random5 are needed for the Boolean mask conversion multiplication mask operation corresponding to random1, random2 and random3 in the second order, at which time whether cnt is 10 and whether the mtb signal reaches 6 is determined to ensure the smooth progress of the second-order multiplication conversion Boolean algorithm, as Figure 8 The pseudo code of the algorithm is shown.

[0093] (7) Affine transformation

[0094] The affine transformation of the AES S-box is very simple, we only need to implement the affine transformation matrix of the AES S-box into the function of step five inversion, and we also optimize the number of gates by using the new heuristic algorithm, in addition, we should note that one affine transformation is only for one, that is, 8-bit number, so the first order needs two cycles to complete, and the second order needs three cycles to complete. We use the rdy signal to control the process, and note that the rdy signal also marks the end of the AES S-box execution, which should be used as the interface between the S-box and the AES algorithm. The final optimization gate number idea is: the heuristic algorithm reduces the calculation gate number, and one cycle affine transformation of one reduces the total gate number. As shown in Figure 9 The affine transformation process diagram of the AES S-box is shown.

[0095] (8) The overall implementation of the AES S-box

[0096] The cnt counter controls each signal module, wherein the en signal controls the calculation of the delta function, the load signal controls the generation of random numbers required for the subsequent algorithm process, the btm signal controls the Boolean mask multiplication mask process, the iv signal controls the inversion process, the mtb signal controls the multiplication mask to Boolean mask process, and the rdy signal controls the affine transformation and the end of the entire AES S-box execution and the interaction between the S-box and the external AES algorithm.

[0097] At the same time, the scheme described in the embodiment reuses the registers of the conversion process, uses the output of one algorithm as the input of the next algorithm, and uses the multiplexed register as the interface of a single multiplier, which greatly reduces the total gate number of the algorithm. As shown in Figure 10 and Figure 11 The key conversion process of the algorithm is shown.

[0098] (2) Implementation of the AES encryption algorithm

[0099] Based on the above S-box, the implementation of the AES encryption algorithm is as follows: first, the implementation process of the AES encryption algorithm needs 1 plaintext register and 1 key register. As shown in Figure 12 Before entering the AES algorithm, the plaintext and the encryption key are first XORed. In order to reduce the gate number, we use period instead of area, and combine this step with the addroundkey in the following step, because they are essentially the same. At the same time, we split the XOR operation of the plaintext and the encryption key, and calculate every 4 bits or every 8 bits, and then perform cyclic shift through the shift register after completion, so that the XOR operation can be completed after a corresponding number of periods. We calculate every 8 bits for the XOR operation of two 256-bit numbers in the first order, and calculate every 4 bits for the XOR operation of two 384-bit numbers in the second order, so that the num bits can be fully utilized.

[0100] After that, the key expansion operation is needed, here we need to spend 4 S-box cycles to complete the conversion of each low 32-bit, and we will distribute the conversion operation of each remaining bit in the subsequent algorithm execution process and pipeline them, which not only reduces the number of cycles, but also fully utilizes the number of bits of our counter.

[0101] Then we need 16 S-box calculation cycles to complete the subbytes operation, here we still use the shift register method, and the S-box input x is cyclically right shifted by 8 bits to transform the input of the S-box each time, and the output result sx is combined with the plaintext register to complete the update of the plaintext register.

[0102] Further back is shiftrows, here we implement it as a function that calculates one piece at a time, i.e. 128 bits, and then calls it once per cycle. It is obvious that the first order needs to spend 2 cycles, the second order needs to spend 3 cycles, and then mixcolumn we still implement it as a function, which calculates 32 bits at a time. We implement 32-bit mixcolumn through the simplest algorithm, i.e. 92 XOR gates. In this way, the first order needs 8 cycles and the second order needs 12 cycles to complete. Of course, a judgment logic is also needed here to ensure that the last round does not perform mixcolumn.

[0103] Finally, we combine these parts, control the number of rounds through the round signal, control the number of cycles through the num signal, and also through the output signal rdy of the S-box mentioned earlier to ensure the interaction between the S-box and the AES algorithm, thus realizing the AES algorithm as a whole.

[0104] Further, in order to prove the effectiveness of the scheme described in the embodiment, the following safety analysis and experimental results are provided.

[0105] (I) Safety analysis

[0106] We deploy the first-order AES algorithm and the second-order AES algorithm to Xilinx Spartan6 FPGA, then transmit it to the UART board through ISE, interact with the PC through the board, and then write the corresponding acquisition code to collect the curve through the PICO oscilloscope. The first-order AES is 27000 points, and the second-order AES is 30000 points, the clock frequency is 48mhz, the sampling frequency is 1.25GS / s, and we have collected 100-200k curves respectively.

[0107] The power consumption curves collected for the first and second order cases are as follows: Figure 13 , 14As shown, by t-test inspection, the t value is always between (-4.5-4.5), according to the t-test result analysis, it can be determined that they are all without intermediate value information leakage.

[0108] (II) Experimental results and analysis

[0109] We use tsmc90nm library, using Design Compiler to measure the equivalent gate number of algorithm, now the results are published as Figure 15 As shown, it can be seen that we greatly reduce the overall equivalent gate number of AES algorithm under the premise of not losing security by reducing the equivalent gate number of AES S-box.

[0110] We greatly reduce the equivalent gate number of anti-side channel masking AES hardware implementation through register reuse, shift register, serial implementation and the idea of using period to replace area, especially the serial idea, we almost implement the entire AES S-box and even the entire AES algorithm implementation process, and we ensure that the optimized algorithm does not leak sensitive information such as intermediate values, that is, without losing security, from the experimental results and security analysis, our experimental results are very successful.

[0111] Example two:

[0112] The purpose of this embodiment is to provide an anti-side channel attack AES encryption algorithm hardware implementation system.

[0113] An anti-side channel attack AES encryption algorithm hardware implementation system, which performs the steps of an anti-side channel attack AES encryption algorithm hardware implementation method as described above, specifically:

[0114] XOR operation is performed on the to-be-processed plaintext data and the encryption key of the current round, and key expansion operation is performed using the pre-implemented S-box; wherein the key expansion operation takes four S-box periods to complete the conversion of the low 32 bits of each part, and the conversion operation of the remaining bits of each part is distributed in the subsequent execution process;

[0115] Based on the XOR operation result, byte substitution, column mixing and row transformation operations are sequentially performed, wherein the byte substitution operation is implemented based on the pre-implemented S-box;

[0116] The above steps are iteratively performed for a preset number of rounds to complete the implementation of the AES encryption algorithm; wherein the preset number of rounds is determined by the key bit number of the AES encryption algorithm, and the row transformation is not performed in the last round;

[0117] The implementation of the S-box includes the implementation of linear feedback shift register, serial modular multiplication multiplier, delta function, Boolean conversion multiplier, inverse, multiplication to Boolean, affine transformation and signal control and comprehensive processing process.

[0118] Further, the system described in the embodiment corresponds to the method described in embodiment one, the technical details of which have been described in detail in embodiment one, and therefore will not be described here.

[0119] The anti-side channel attack AES encryption algorithm hardware implementation method and system provided by the above embodiment can be implemented and has a broad application prospect.

[0120] The above merely describes preferred embodiments of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art can make various modifications and changes to the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for implementing an AES encryption algorithm in hardware resistant to side-channel attacks, characterized in that, The method comprises the following steps: XOR operation is performed between plaintext data to be processed and an encryption key of a current round; and a pre-implemented S-box is used for key expansion operation; wherein the key expansion operation takes four S-box periods to complete conversion of low 32 bits of each part, and conversion of remaining bits of each part is distributed in subsequent execution processes; based on the XOR operation result, byte substitution, column mixing and row transformation operations are sequentially performed, wherein the byte substitution operation is implemented based on a pre-implemented S-box; the above steps are iteratively performed for a preset number of rounds to complete implementation of the AES encryption algorithm; wherein the preset number of rounds is determined by the number of key bits of the AES encryption algorithm, and row transformation is not performed in the last round; wherein implementation of the S-box includes implementation of a linear feedback shift register, a serial modular multiplication multiplier, a delta function, a Boolean mask to multiplication mask conversion, inversion, multiplication mask to Boolean mask conversion, affine transformation and signal control and comprehensive processing processes; the Boolean mask to multiplication mask conversion, inversion and multiplication mask to Boolean mask conversion operations share a group of registers, wherein for first-order AES implementation, a 16-bit register and an 8-bit register are selected, the lower 8 bits of the 16-bit register are used as a group of inputs of the serial modular multiplication multiplier, and the upper 8 bits are used to receive an output of the serial modular multiplication multiplier; the 8-bit register is used as another group of inputs of the serial modular multiplication multiplier; for second-order AES implementation, the multiplication mask to Boolean mask conversion operation is based on the selection of a 16-bit register and an 8-bit register, and an additional 8-bit register is added.

2. The method of claim 1, wherein the AES encryption algorithm is implemented in hardware, and the method further comprises: using a plurality of registers to store the intermediate values of the AES encryption algorithm; and using a plurality of multiplexers to select the intermediate values of the AES encryption algorithm from the plurality of registers. inversion and affine transformation, heuristic algorithms are used to optimize the number of gates, wherein the heuristic algorithm specifically applies the XOR operation performed previously to subsequent XOR operations, thereby reducing the number of XOR gates.

3. The hardware implementation method of the AES encryption algorithm resistant to side-channel attacks as described in claim 1, characterized in that, implementation of the delta function is specifically represented as: where x is the input of the inverse S-box, based on The conversion of the input avoids the zero-value problem.

4. The method of claim 1, wherein the method further comprises: the linear feedback shift register generates the required random number by selecting a 32-bit shift register, which is used for random number generation in the delta function, Boolean mask to multiplication mask conversion and multiplication mask to Boolean mask conversion processes.

5. The method of claim 1, wherein the method further comprises: the serial modular multiplication multiplier is an 8-bit modular multiplication multiplier implemented in series, and there is only one 8-bit modular multiplication multiplier in the S-box.

6. The method of claim 1, wherein the method further comprises: the XOR operation between the plaintext data to be processed and the encryption key of the current round is specifically splitting XOR operation between the plaintext data and the encryption key, calculating based on a preset size of bits, and performing cyclic shift through a shift register after calculation is completed, thereby completing the XOR operation.

7. The hardware implementation method of the AES encryption algorithm resistant to side-channel attacks as described in claim 1, characterized in that, the plaintext data is stored in a plaintext register, and the encryption key is stored in a key register.

8. A side-channel attack resistant hardware implementation of the AES encryption algorithm system, characterized in that, The method executes the steps of any one of claims 1-7, specifically: XOR operation is performed between plaintext data to be processed and an encryption key of a current round; and a pre-implemented S-box is used for key expansion operation; wherein the key expansion operation takes four S-box periods to complete conversion of low 32 bits of each part, and conversion of remaining bits of each part is distributed in subsequent execution processes; Based on the XOR operation result, sequentially perform byte substitution, column mixing and row transformation operations, wherein the byte substitution operation is based on a pre-implemented S-box implementation; Iteratively perform the above steps for a preset number of rounds to complete the implementation of the AES encryption algorithm; wherein the preset number of rounds is determined by the key bit number of the AES encryption algorithm, and the row transformation is not performed in the last round; Wherein, the implementation of the S-box includes the implementation of linear feedback shift register, serial modular multiplication multiplier, delta function, Boolean conversion multiplier, inverse, multiplication to Boolean, affine transformation and signal control and comprehensive processing process.

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