Root cause analysis based on wafer bin map

Abstract

A template for assigning the most likely root causes of wafer defects. Bin map data for a target wafer can be compared to bin map data for previous wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the target wafer, and if the same root cause should be applied to the target wafer, the wafer can be marked accordingly with the root cause.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. Provisional Application No. 63 / 018884, filed on May 1, 2020, entitled “Improving Root Cause Analysis using Active Learning Frameworks,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to semiconductor manufacturing processes, and more particularly, to systems and methods for classifying images from semiconductor manufacturing processes to identify root causes of wafer defects. Background Art

[0004] Identifying wafers in a semiconductor manufacturing process and assigning tags to all wafer issues as well as identifying the associated root causes of wafer defects is ideal but difficult to achieve. Classification and assignment of tags is performed during a wafer sorting step after manufacturing by performing multiple electrical tests on the individual chips on the wafer. The test results are typically expressed as classification values ​​for all chips, which results in a spatial map called a wafer bin map. Different defect modes are apparent from the wafer bin map, and for each defect mode, it is important to identify the root cause of the process failure that caused the specific defect so that the problem can be corrected. The present disclosure relates to an improved method for achieving this purpose. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a flow chart illustrating a high-level process for implementing a template for analyzing a wafer map.

[0006] Figure 2 is a flow chart illustrating a process for setting boundary conditions for relevant wafer parameters.

[0007] Figure 3A and Figure 3B is a flow chart illustrating a process for marking wafers with root causes.

[0008] Figures 4 to 6 An example of a user interface in which a wafer bin map for a target wafer is compared to a wafer bin map from a previous production run and viewed in a template configured to illustrate determining a root cause using a nearest neighbor algorithm.

[0009] Figures 7 and 8 is an example of a user interface where a wafer bin map from a previous production run is viewed in a template configured to determine root cause using a cluster generation algorithm.

[0010] Figures 9 and 10is an example of a user interface for a wafer bin map viewed in a template configured to identify outliers with unknown root causes.

[0011] Fig.11 is an example of an alternative representation of a network type analysis based on the underlying reason for cluster analysis.

[0012] Fig.12 is a flow chart illustrating an alternative process for determining parameter limits. DETAILED DESCRIPTION

[0013] The present disclosure relates to methods and systems for generating and providing templates as a graphical user interface ("GUI") for wafer map based analysis to assist users in identifying important "critical" wafers from a semiconductor manufacturing process to mark defects and associated root causes.

[0014] A GUI is a processor-based tool that provides a visual display of information in a formatted manner, having widgets of various designs for enabling user interaction with at least the displayed information and for providing control functions, all of which are well known. In conjunction with the use of machine learning algorithms, the templates benefit from user input in a collaborative manner to improve predictive capabilities.

[0015] The processor may be desktop-based (i.e., stand-alone) or part of a networked system; however, given the large amount of information to be processed and interactively displayed, the processor power (CPU, RAM, etc.) should be state-of-the-art to maximize efficiency. In a semiconductor foundry environment, The analysis platform is a useful choice for building GUI templates. In one embodiment, the coding of the underlying processing routines can be used The analysis software is completed with version 7.11 or higher, which is compatible with the Python object-oriented programming language primarily used to encode machine language models.

[0016] In this application, for incoming wafers marked as abnormal, the GUI based template should have the following features:

[0017] (i) Compare the incoming wafer's data with the retrieved data from existing wafers. The comparison with the existing wafer data should be specific to the product stream of the incoming wafer, ensuring that the most relevant data is retrieved and compared.

[0018] (ii) Tagging incoming wafers with the most likely root causes (e.g., process modules or process steps) that are associated with the bin pattern of the incoming wafers, or the lack of bin pattern of the incoming wafers.

[0019] (iii) Displays basic information about the incoming wafer, such as individual wafer identification (WaferlD), lot number, etc.

[0020] (iv) Drill down into the data to analyze anomalous neighbors of incoming wafers, including die maps, clusters, zone statistics, user-provided comments, etc.

[0021] (v) Cover and update the listed major and minor root causes, such as process steps or process modules.

[0022] (vi) Save the updated results for comparison and marking of future incoming wafers.

[0023] To reduce the burden of generating labels, an active learning framework can be used to identify critical wafers for labeling. Critical wafers can include (i) wafers for which uncertainty is modeled by observing each individual wafer, and (ii) wafers that improve the overall confidence of the model, such as unlabeled wafers that are actually closest to wafers in the test set.

[0024] refer to Figure 1 , illustrating a high-level process 100 for implementing a template for wafer map based analysis. In step 102, the relevant product flow is identified, and then the existing wafer data set for the relevant product flow is retrieved from one or more databases in step 104 and loaded into the template as input in step 106. By product flow, we mean the combination of process steps and / or process modules that are performed for this specific product type or product family (ProductlD) of the incoming wafer sample. Therefore, during a production run, many wafers are produced in different batches for a specific ProductlD, each wafer having a unique WaferlD. Static processes produce only one product type, while dynamic processes change the steps and / or modules to produce different product types.

[0025] As described below, boundary conditions or parameter cutoffs for this product flow are identified in step 108 and can be set manually or automatically. In step 110, the user checks the results to provide a sanity check that the results make sense. Finally, in step 112, the wafer data and boundary conditions are saved to a database for future comparison.

[0026] In use, a template is built to obtain pre-existing customer wafer data as input, for example from accessing one or more databases storing customer wafer data from previous production runs. The general principle is that previous wafer bin map data can provide an effective comparison to determine whether the current incoming wafer has the same problem, or the current incoming wafer does not have the problem. However, if the size of the die is significantly different, then the wafer map will also be significantly different, and the described method may not work. Therefore, the analysis may generally be limited to the same or similar products.

[0027] The following types of information, or subsets thereof, are typically stored in one or more databases and may be loaded into the template as input in step 106:

[0028] (i) A table with a list of previous wafers including the known and verified major and minor root causes for the corresponding wafer issues / defects.

[0029] (ii) Wafer Equipment History (WEH), metrology data, metrics for Fault Detection and Classification (FDC), and other relevant wafer manufacturing data for past wafers (not available for fabless customers). If past wafers came from a static manufacturing process, i.e., a dedicated process path such as A→B→C→D for a single product type, then the WEH includes the process and tool history for the product type. If past wafers came from a dynamic manufacturing process, i.e., different types of products can be manufactured with different process steps and / or process modules, then the WEH includes the process and tool history for a given WaferlD as well as the product type.

[0030] (iii) For each WaferlD, wafer bin data for each die, and the associated x-coordinate (Diex) and y-coordinate (Diey). The results of each die test are recorded by a technician and include problems with the die, such as current leakage, etc. Wafer-level root causes are initially provided by subject matter experts, taking into account die failure modes within the wafer. Subject matter experts encode the different root causes of various wafer defects into wafer bins, with each bin used to collect and store wafer data for the same defects and root causes. Modern manufacturing operations can have hundreds, or even thousands of different wafer bins, where similar defects in different bins are typically grouped together for easy retrieval and analysis.

[0031] (iv) For each WaferlD, output such as Automatic Feature Classification (ASC), including regional bin increments from regional medians for each wafer bin type (number), as well as general pattern markers (classifications) and detail patterns (classifications). For example, statistics can be calculated to determine where defects appear in different spatial regions of the wafer. For example, it can be determined that a large percentage of defects in the center region are classified as bin A, while other smaller percentages of defects are classified as bin B, bin C, etc. Therefore, the statistics indicate that there is a high probability that defects in the center of the wafer bin map are classified as bin A, and the wafer can be marked with general pattern markers, such as "Center Problem Only" and more descriptive pattern details, such as "Full Bull's Eye", "Upper Right IQ Edge", and "Left Half Edge".

[0032] For each WaferlD, the output clusters include the presence of each statistically significant cluster identified by the cluster's center Diex, Diey location (number), the cluster's bounding box, and all Diex, Diey locations within the cluster. This tells us the size and continuous shape (circle, crescent, etc.) of the defect clusters.

[0033] When the user chooses to manually set the boundary conditions in step 108, the following parameters should be defined:

[0034] dc is the distance between the incoming wafer and the adjacent wafer, measured in die count, which is considered close enough to label the incoming wafers as identical, and any differences between wafers can be attributed to random noise;

[0035] df is the distance, measured in number of dies, between the incoming wafer and the neighboring wafers that are considered too far to have similarity between the wafer bin cluster and the training set. Any overlap should be considered as random chance only;

[0036] k is the number of neighbors considered by an algorithmic solution, such as the k-nearest neighbor (KNN) algorithm; and

[0037] D is the metric used to calculate the distance. Many known distance metrics can be used, including the Euclidean distance metric, the Minkowski space tensor, the Mahalanobis distance metric, L1, L∞, etc.

[0038] The automatic setting of the boundary conditions set in step 108 is as follows Figure 2 This is illustrated by the simple process 200 shown. In step 210, statistical simulations are run to find parameter limits, and in step 220 the limits are adjusted.

[0039] In the statistical simulation, each df and dc should be a function of a specific wafer map and the associated defect density. For example, these df and dc parameters can be estimated by using Monte Carlo simulation, varying the amount of defects on the wafer, and fitting the simulation results using response surface methodology (RSM). The primary signal generated by the simulation will be used to determine the primary root cause, while the secondary signal will be used to determine one or more secondary root causes.

[0040] Hyperparameter tuning is then applied, such as by using n-fold cross validation on the simulation results based on the labels determined by the subject matter experts for the wafer problem, to identify the best k parameters to apply to the data set. Different D metrics can be used or associated with different wafer problems, or different die sizes, or different inputs, and can be determined based on empirical results to select and apply the metric that best suits the specific application.

[0041] These parameters are saved and can be applied when a new wafer comes in for analysis. It should be noted that each tag type is considered independent, i.e. one k-parameter is derived for each process module, chamber ID, tool and process step.

[0042] Reference now Figure 3A , three different alternative methods are presented for implementing an engine that analyzes a wafer map and predicts a root cause for a new sample wafer received in step 302. In a first method, die clusters are calculated for the sample wafer in step 310. In a second method, regional bin deltas are calculated in step 320. In a third method, the wafer map is convolved in step 310. Each of the three methods then proceeds to step 340 where the distances from the new wafer to all previous wafers with known root causes are calculated, preferably using several different methods of calculating distances.

[0043] The analysis continues with considering whether there are any neighbors within distance df of the sample wafer in step 350. If not, then in step 354 the wafer problem is marked as "unknown".

[0044] If there are neighbors within the distance df of the sample wafer in step 302, the next case to consider in step 356 is whether at least some of the neighbors are within the distance dc of the sample wafer. If so, in step 358, a subset of k neighbors is selected and the subset is typically weighted equally in the prediction engine. The next query in step 360 is whether all k neighbors in the subset have the same label. If so, in step 362, the label is returned as a single label for the WaferlD. If not, in step 364, labels can be returned that are proportional to their frequency and, for example, as a function of distance.

[0045] In each of the different methods, the prediction engine can be implemented in a variety of different ways, such as collaborative filters or a classification algorithm, such as a spatial K-nearest neighbor (KNN) algorithm, a convolutional neural network (CNN), a random forest, XGBoost, etc. Different labeling methods can be combined, such as using an ensemble method including but not limited to majority voting and boosted decision trees.

[0046] In one embodiment, the stored knowledge and patterns can be transferred from one product to another by rescaling the bin map, although using too large a scaling factor may introduce errors. However, rescaling should be limited to the manufacturing processes of similar products, for example, it may not be practical to use a knowledge base of 3D NAND flash memory to predict the root cause of CPU chips. In addition, the bin code of each product should be standardized so that bin XYZ of product A is similar to bin XYZ of product B.

[0047] The output of the root cause analysis to the user GUI can take different forms. For example, in one form, a view shows a bin map of incoming wafers and nearest neighboring wafers in the database, and identifies the root causes of these most similar neighbors and the predicted most likely root cause of the target incoming wafer. Figures 4 to 6 An example of a GUI presentation showing root cause analysis using the nearest neighbor method.

[0048] exist Figure 4 , the user interface 450 includes a first window 460 that displays a new bin map 400 for a first incoming wafer, the new bin map being shown with a wafer lot number and an axis line indicating distance measured as a number of dies. Below the bin map 400 is a second window 470 that displays the ten closest bin map matches 401-410 to a database of previous data based on image analysis by lot number and axis line, but also lists the statistical distances of the neighbors to the target bin map. In this example, the three bin maps 401, 403, and 405 are all identified with a problem root cause A, and since root cause A is the largest common root cause, there is a high probability that the incoming wafers have the same root cause. Therefore, a label with root cause A is also assigned to the bin map 400 and the corresponding wafer.

[0049] User controls and other data are included in typical GUI implementations, and some examples are shown in Figure 4 450 . Other wafer map GUIs will include similar functionality. For example, general system controls 480 such as File, Edit, View, Tools are included in a ribbon or taskbar at the top of the GUI 450. A first window 460 includes a panel 462 that describes a product map of a new wafer, and a user can select or drill down on any listed item. A second window 470 includes a similar panel 472 that describes a product map of a previous wafer, and a user can select or drill down on any listed item. A third window 452 lists adjacent wafers that are similar to the new wafer, and a fourth window 454 lists the primary and secondary root causes of similar adjacent wafers. It should be noted that optional drill-down capabilities can be provided directly from the wafer map or from other panels or wafer lists, typically linking to one or more pages with more detailed wafer information such as WEH, FDC indicators, metrology, etc.

[0050] Similarly, in Figure 5In FIG. 5 , a new bin map 500 for the second incoming wafer is shown with wafer lot number and axis, and below the bin map are the ten closest bin map matches 501 to 510 in the database with neighboring statistical distances listed. In this case, six of the ten previous bin maps (i.e., 501 to 505 and 509) all have the problem root cause B, indicating a high probability that the bin map 500 also has root cause B, and a label with root cause B is assigned to the bin map 500 and the corresponding wafer.

[0051] Figure 6 A new bin map 600 for the third incoming wafer is shown with wafer lot number and axis, and below the bin map are the ten closest bin map matches 601 to 610 in the database listing the neighboring statistical distances. Although initially an unknown pattern, the five closest previous bin maps (i.e., 601, 602, 605, 608) have the problem root cause C, so based on probability, a label with root cause C is assigned to the bin map 600 and the corresponding wafer.

[0052] Another form of output is cluster generation, which groups together sets of previous bins that are considered similar. Thus, the target incoming bins are compared to groups or clusters of bins rather than to individual bins. For example, Figure 7 A first set of bin graphs 700 is shown, each bin graph having defects clustered in the center of the bin graph. Figure 8 A second set of bin graphs 800 is shown, each with defects concentrated on the edges of the corresponding bin graph. Thus, before comparing with each previous bin graph, the incoming bin graph can be compared with the generalized group (e.g. Figure 7 Central defect or Figure 8 If all wafers within a cluster have the same known root cause, the probability that the wafers have the same root cause is higher. If wafers within a cluster have different root causes, WEH, FDC metrics, and metrology data may be needed to help with the analysis.

[0053] Another form of output is to look at outliers to determine which incoming wafers do not have any similarities to previous wafers. By calculating the distribution of wafers to their nearest neighbors, wafers that do not have any nearest neighbors can be determined. Fig. 9 An incoming wafer 900 and the ten closest matches 901 to 910 in the database are shown. Although the bin map can be described as a high density pattern across the wafer, none of the closest matches are really close. Similarly, Fig.10 1000 and the ten closest matches in the database 1001 to 1010 are shown. In this example, the upper left corner of the bin map is bad and also propagates to the outer edges, but Fig. 9 As shown, there is no close match, so user input may be needed in this example to make better predictions in the future.

[0054] In another embodiment, by calculating the wafer-to-wafer distance, the output can be represented as a network. Thus, network-based analysis can be used and combined with WEH data to help identify the root cause of a wafer sample. Fig.11 The output for viewing in a template based on network analysis is shown, where a top-down view is expected to illustrate which wafer clusters are close to each other. The point 1104 at the center of the graphical representation 1102 is the most tightly concentrated cluster, thus indicating a primary root cause. Additional points 1106 extend away from the center, which are not as tightly clustered, thus indicating secondary root causes.

[0055] Another method for automatically determining the boundary conditions for random defects for each of the three different solution paths discussed previously is as follows: Fig.12 As described. In step 1202, defect locations and counts are randomly assigned based on the defect locations and counts found by clustering. In step 1210, matches are compared based on the clustered data, and in step 1212, distances from the incoming wafer are calculated using two different methods such as Mahalanobis distance and Euclidean distance. When enough distances are calculated in step 1214 by moving random locations to generate a statistically useful distribution, the p-value threshold of the distribution can be used to determine the parameters df and dc in step 1216; and if not, more distances are calculated in step 1212 until there is enough data.

[0056] In the second solution path, bin increments are calculated from randomly assigned locations in step 1220. Distance differences are then calculated using three different methods in step 1222. In step 1224, have enough distances been calculated to generate a statistically useful distribution? If so, the p-value threshold for the distribution can be used to determine the parameters df and dc in step 1226; if not, more distances are calculated in step 1222 until there is enough data.

[0057] Instead of an aggregated data set from cluster and regional increments, the third solution path acquires wafer bin data from master signals at randomly assigned locations and convolves the wafer bin map data in step 1230 by running the third solution path through a machine learning model that is configured to determine a classification or bin of the target wafer.

[0058] In step 1232, the distance to the incoming wafer is calculated using different methods, and this step is repeated until enough distances are calculated by moving random positions to generate a statistically useful distribution in step 1234. At this point, the parameters df and dc are determined in step 1236 using a p-value threshold for the distribution.

[0059] As mentioned previously, the machine learning model is configured to implement any different solution paths based on the convolution algorithm. An example of an effective convolution is to use a blur matrix to eliminate small differences in the locations of similar patterns.

[0060] The foregoing written description is intended to enable one of ordinary skill in the art to make and use the techniques described herein, but one of ordinary skill will understand that the description is not limiting and will also understand that there are variations, combinations, and equivalents of the specific embodiments, methods, and examples described herein.

Claims

1. A computer-implemented method for a graphical user interface (GUI) for semiconductor processing, the method comprising: Obtaining a first wafer bin map of a first semiconductor wafer manufactured in a current production run and displaying the first wafer bin map in a first window within the GUI, the first wafer bin map being characterized as having a current defect; identifying a product flow of the first semiconductor wafer; retrieving a first plurality of previous wafer bin maps corresponding to previous production runs of semiconductor wafers manufactured using the identified product flow and determined to be similar to the first wafer bin map, and displaying the plurality of previous wafer bin maps in a second window within the GUI; determining a probability that a first root cause associated with at least some of the first plurality of previous bin maps is a primary root cause for the current defect on the first bin map; When the probability exceeds a threshold, assigning a mark to the first wafer bin map, the mark indicating that the first root cause is the primary root cause; as well as User controls are provided within the GUI for (i) selecting at least one of the previous wafer bin maps for visual comparison with the first wafer bin map, (ii) drilling down into information about the selected at least one previous wafer bin map, and (iii) overriding and updating the root cause of an assignment.

2. The method according to claim 1, further comprising: A first statistical distance dc between the first semiconductor wafer and a plurality of neighboring wafers is determined, the first statistical distance being deemed close enough to associate a root cause of the neighboring wafers with the first semiconductor wafer.

3. The method according to claim 2, further comprising: A second statistical distance df between the first semiconductor wafer and the plurality of neighboring wafers is determined, the second statistical distance being deemed too far to be associated with the root cause.

4. The method according to claim 1, further comprising: determining a first statistical distance dc between the first semiconductor wafer and a plurality of neighboring wafers, the first statistical distance being deemed close enough to associate a root cause of the neighboring wafers with the first semiconductor wafer; determining a second statistical distance df between the first semiconductor wafer and the plurality of neighboring wafers, the second statistical distance being deemed too far to associate the root cause of the neighboring wafers with the first semiconductor wafer; When all k adjacent wafers are within the distance dc, weighting the first number k of adjacent wafers equally; When all k adjacent wafers have the same root cause label, assigning the root cause of the k adjacent wafers to the first semiconductor wafer; as well as When all k adjacent wafers do not have the same root cause label, a plurality of root causes of the k adjacent wafers are assigned to the first semiconductor wafer.

5. The method according to claim 1, further comprising: retrieving a second plurality of previous wafer bin maps corresponding to previous production runs of semiconductor wafers manufactured using a product flow similar to the identified product flow; as well as Zoom the retrieved wafer bin map as needed.

6. The method according to claim 1, further comprising: evaluating a possible match of the first wafer bin map based on clustering of previous patterns of the first plurality of previous wafer bin maps; generating a statistical distribution of a plurality of calculated distances between the first semiconductor wafer and a plurality of adjacent wafers based on the clustering; determining a first statistical distance dc between the first semiconductor wafer and a plurality of neighboring wafers, the first statistical distance being deemed close enough to associate a root cause of the neighboring wafers with the first semiconductor wafer; as well as A second statistical distance df between the first semiconductor wafer and the plurality of neighboring wafers is determined, the second statistical distance being deemed too far to associate the root cause of the neighboring wafers with the first semiconductor wafer.

7. The method according to claim 1, further comprising: calculating region bin increments for a previous pattern of said first plurality of previous wafer bin maps; generating a statistical distribution of a plurality of calculated distances between the first semiconductor wafer and a plurality of adjacent wafers based on the regional bin increments; determining a first statistical distance dc between the first semiconductor wafer and a plurality of neighboring wafers, the first statistical distance being deemed close enough to associate a root cause of the neighboring wafers with the first semiconductor wafer; as well as A second statistical distance df between the first semiconductor wafer and the plurality of neighboring wafers is determined, the second statistical distance being deemed too far to associate the root cause of the neighboring wafers with the first semiconductor wafer.

8. The method according to claim 1, further comprising: convolving the previous patterns of the first plurality of previous wafer bin maps; generating a statistical distribution of a plurality of calculated distances between the first semiconductor wafer and a plurality of adjacent wafers based on the convolution pattern; determining a first statistical distance dc between the first semiconductor wafer and a plurality of neighboring wafers, the first statistical distance being deemed close enough to associate a root cause of the neighboring wafers with the first semiconductor wafer; as well as A second statistical distance df between the first semiconductor wafer and the plurality of neighboring wafers is determined, the second statistical distance being deemed too far to associate the root cause of the neighboring wafers with the first semiconductor wafer.

9. A computer-implemented method for a graphical user interface (GUI) for semiconductor processing, the method comprising: receiving a first wafer bin map of first semiconductor wafers manufactured in a current production run having a first product flow and displaying the first wafer bin map in a first window within the GUI, the first wafer bin map being characterized as having current defects; retrieving a plurality of previous wafer bin maps corresponding to previous production runs of semiconductor wafers having the first product flow and determined to be similar to the first wafer bin map, and displaying the plurality of previous wafer bin maps in a second window within the GUI; Calculating a plurality of statistical distances of a corresponding wafer bin map in the previous wafer bin map and the first wafer bin map, i.e., a first statistical distance dc between a target wafer and a plurality of neighboring wafers is considered to be close enough to associate the root causes of the neighboring wafers with the target wafer, and a second statistical distance df between the target wafer and the plurality of neighboring wafers is considered to be too far to associate the root causes of the neighboring wafers with the first semiconductor wafer; When the first wafer bin map and each of a subset of the plurality of previous wafer bin maps have a first statistical distance dc less than a threshold value and each of the subsets has a single root cause, assigning the single root cause to the first wafer bin map; as well as When each of the subsets has a first statistical distance dc less than the threshold value, but each of the subsets does not have the single root cause, assigning a plurality of root causes to the first wafer bin map, each of the plurality of root causes being assigned as a function of a corresponding calculated first statistical distance dc; as well as User controls are provided within the GUI for (i) selecting at least one of a subset of previous wafer bin maps for visual comparison with the first wafer bin map, (ii) drilling down into information about the selected at least one previous wafer bin map, and (iii) overriding and updating an assigned single root cause or multiple assigned root causes.

10. The method of claim 9, further comprising clustering the previous wafer bin maps before calculating the statistical distance.

11. The method of claim 9, further comprising calculating a region bin increment of the previous wafer bin map before calculating the statistical distance.

12. The method of claim 9, further comprising convolving the previous wafer bin map before calculating the statistical distance.

13. The method according to claim 9, further comprising: setting wafer limits for a plurality of selected wafer parameters; comparing the first wafer bin map to the plurality of previous wafer bin maps to identify a first group of the plurality of previous wafer bin maps that are similar to the first wafer bin map based on the wafer constraints; as well as The plurality of statistical distances between the first set of the previous wafer bin maps and the first wafer bin map are calculated.

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