A transient boost circuit, chip system and device for LDO

Abstract

The present application provides a transient boost circuit, chip system, and device for an LDO, which are used to improve the transient performance of the LDO while reducing the chip area occupied by the capacitor. The circuit includes: an LDO for outputting a first voltage; at least one detection circuit coupled to the LDO, each of the at least one detection circuits including a first capacitor, an amplifier, and a second capacitor; wherein the first capacitor is used to generate a coupling voltage based on changes in the first voltage and couple the coupling voltage to the amplifier; the amplifier is used to amplify the coupling voltage to obtain a second voltage; and the second capacitor is used to couple the second voltage to the LDO, and the second voltage is used to adjust the first voltage to maintain the first voltage constant.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a LDO transient boost circuit, chip system, and device. Background Art

[0002] With the rapid development of the Internet of Things (IoT), the application scenarios of IoT chips, such as wearables and implantables, are expanding. Within IoT systems, highly sensitive subsystems such as radio frequency (RF) transceivers, analog-to-digital converters, high-speed digital circuits, and phase-locked loops (PLLs) have high transient power requirements. Therefore, these subsystems are often powered by low-dropout linear regulators (LDOs) with high transient performance.

[0003] In the prior art, these subsystems are typically powered by LDOs with large on-chip capacitance or LDOs with external capacitance (typically in the uF range). These on-chip or external capacitance can reduce voltage ripple caused by load transients, thereby ensuring the LDO's transient response. However, if an LDO with on-chip capacitance is used, the on-chip capacitance occupies a large chip area; if an LDO with external capacitance is used, the external capacitance takes up additional PCB area. Summary of the Invention

[0004] The present application provides a transient boost circuit, chip system and device for LDO, which are used to improve the transient of LDO while reducing the chip area occupied by capacitors.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a transient boost circuit for a low-dropout linear regulator (LDO) is provided. The circuit includes: an LDO for outputting a first voltage, which may be a voltage used to power various subsystems or systems and may also be referred to as the output voltage of the LDO; at least one detection circuit coupled to the LDO, each of the at least one detection circuit including a first capacitor, an amplifier, and a second capacitor; wherein the first capacitor is configured to generate a coupling voltage based on changes in the first voltage and couple the coupling voltage to the amplifier, wherein the first capacitor couples the first voltage to the amplifier via AC coupling; the amplifier is configured to amplify the coupling voltage to obtain a second voltage, and may be, for example, a non-inverting amplifier or an inverting amplifier; and a second capacitor for coupling the second voltage to the LDO, i.e., the second capacitor couples the second voltage to the LDO via AC coupling to form negative feedback, and the second voltage is used to regulate the first voltage to maintain the first voltage constant.

[0007] In the above technical solution, the first voltage output by the LDO is coupled to the amplifier via a first capacitor, which amplifies it. This improves the transient response of the LDO while allowing the use of a smaller first capacitor to achieve coupling of the first voltage, reducing the chip area occupied by the first capacitor. Simultaneously, the second voltage output by the amplifier is coupled to the LDO via a second capacitor, so that the second voltage does not directly act on the LDO's inherent loop, thereby not destroying the LDO's DC characteristics and ensuring the stability of the LDO loop. Furthermore, the amplifier is coupled to the LDO via the first and second capacitors, separating the amplifier's bias from the DC component of the first voltage, effectively reducing the difficulty and complexity of the amplifier's bias. Specifically, the amplifier design does not need to consider requirements such as offset and matching, further reducing chip area and achieving low power consumption and high energy efficiency.

[0008] In a possible implementation of the first aspect, the amplifier includes: a first transistor, a second transistor, a third transistor, and a first resistor; wherein one electrode of the first transistor, one electrode of the second transistor, and one end of the first resistor are coupled as the output of the amplifier, the control end of the first transistor, the control end of the second transistor, and the other end of the first resistor are coupled as the input of the amplifier, the other electrode of the second transistor is coupled to one electrode of the third transistor, one of the other electrodes of the first transistor and the other electrode of the third transistor is coupled to a power supply terminal, and the other is coupled to a ground terminal, and the control end of the third transistor is coupled to a bias voltage terminal. Optionally, the first transistor is an NMOS transistor, and the second and third transistors are both PMOS transistors, wherein the first electrode is a drain, the other electrode is a source, and the control end is a gate. In the above possible implementation, the amplifier is an inverter-based amplifier, and the transconductance of the amplifier is the sum of the transconductance of the first transistor and the transconductance of the second transistor. Under the same power consumption, its transconductance is twice that of an ordinary amplifier, thereby effectively improving energy efficiency; the third transistor is used to provide bias current for the amplifier to prevent the amplifier's power consumption from varying with changes in the power supply voltage and process corner. In addition, the amplifier is coupled to the LDO via the first capacitor and the second capacitor, so that the DC operating point of the amplifier can be biased solely using the first resistor, effectively reducing the matching requirements of the amplifier.

[0009] In one possible implementation of the first aspect, the at least one detection circuit includes a first detection circuit, which further includes a compensation circuit coupled between the second capacitor and the LDO; the compensation circuit is configured to adjust the first voltage based on the second voltage to maintain the first voltage constant. In this possible implementation, the compensation circuit can quickly and effectively compensate the first voltage output by the LDO based on the second voltage, thereby improving the transient performance of the LDO.

[0010] In a possible implementation of the first aspect, the compensation circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a second resistor, and a third resistor; wherein one electrode of the fourth transistor, one end of the third resistor, and one electrode of the sixth transistor are coupled to a first node; the other electrode of the fourth transistor, the control terminal of the fifth transistor, and one end of the second resistor are coupled as an input of the compensation circuit; one electrode of the fifth transistor and the other end of the second resistor are coupled to a second node; the other electrode of the fifth transistor, the control terminal of the sixth transistor, and the other end of the third resistor are coupled; and the other electrode of the sixth transistor serves as an output of the compensation circuit; one of the first node and the second node is coupled to a power supply terminal, and the other is coupled to a ground terminal. Optionally, the fifth transistor is an NMOS transistor, and the fourth and sixth transistors are both PMOS transistors; or the fifth transistor is a PMOS transistor, and the fourth and sixth transistors are both NMOS transistors; the first electrode is a drain, the other electrode is a source, and the control terminal is a gate. In the above possible implementation, the provided compensation circuit is simple and effective, thereby improving the transient performance of the LDO while further reducing the chip area.

[0011] In one possible implementation of the first aspect, the LDO has an output terminal, and the output terminal of the compensation circuit is coupled to the output terminal of the LDO. In this possible implementation, the compensation circuit is fed back to the output terminal of the LDO to compensate for the first voltage output by the LDO, thereby improving the transient performance of the LDO.

[0012] In one possible implementation of the first aspect, the compensation circuit includes: a fourth transistor, a fifth transistor, and a second resistor; wherein one electrode of the fourth transistor is coupled to a first node, the other electrode of the fourth transistor, the control terminal of the fifth transistor, and one end of the second resistor are coupled as an input terminal of the compensation circuit, one electrode of the fifth transistor and the other end of the second resistor are coupled to a second node, and the other electrode of the fifth transistor serves as an output terminal of the compensation circuit; one of the first node and the second node is coupled to a power supply terminal, and the other is coupled to a ground terminal. Optionally, the fourth transistor is a PMOS transistor, and the fifth transistor is an NMOS transistor, wherein the first electrode is a drain, the other electrode is a source, and the control terminal is a gate. In the above possible implementation, the provided compensation circuit is simple and effective, thereby further reducing the chip area while improving the transient performance of the LDO.

[0013] In one possible implementation of the first aspect, the LDO includes an operational amplifier, a voltage regulating transistor, and a sampling circuit. The output of the operational amplifier is coupled to the control terminal of the voltage regulating transistor, one electrode of the voltage regulating transistor is coupled to a power supply, and the other electrode of the voltage regulating transistor is coupled to the input of the sampling circuit to serve as the output of the LDO. The output of the sampling circuit is coupled to the positive input of the operational amplifier, and the negative input of the operational amplifier is used to receive a reference voltage. The output of the compensation circuit is coupled to the control terminal of the voltage regulating transistor. In this possible implementation, the compensation circuit is fed back to the control terminal of the voltage regulating transistor to compensate for the first voltage output by the LDO, thereby improving the transient performance of the LDO.

[0014] In a possible implementation of the first aspect, the LDO includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a fourth resistor; wherein one electrode of the seventh transistor and one electrode of the eighth transistor are both coupled to a power supply terminal, the other electrode of the seventh transistor is coupled to one electrode of the ninth transistor as an output terminal of the LDO, the other electrode of the eighth transistor, one electrode of the tenth transistor, and a control terminal of the seventh transistor are coupled, the other electrode of the ninth transistor, the other electrode of the tenth transistor, and one electrode of the eleventh transistor are coupled, the other electrode of the eleventh transistor is coupled to a ground terminal, the control terminal of the eleventh transistor is coupled to one end of a fourth resistor, and the other end of the fourth resistor is connected to a bias voltage terminal. Optionally, the seventh, eighth, and ninth transistors are all PMOS transistors, the tenth and eleventh transistors are both NMOS transistors, the one electrode of the seventh to ninth transistors is a source, the other electrode is a drain, the one electrode of the tenth and eleventh transistors is a drain, the other electrode is a source, and the control terminal is a gate. In the above possible implementation manner, a FVF LDO is provided, so that at least one detection circuit coupled to the FVF LDO can improve the transient state of the LDO while reducing the chip area occupied by the capacitor.

[0015] In one possible implementation of the first aspect, the at least one detection circuit further includes a second detection circuit, wherein a second capacitor in the second detection circuit is coupled between the output terminal of the amplifier and the control terminal of the eighth transistor. In this possible implementation, the first voltage output by the LDO is compensated by feeding back the detection circuit to the control terminal of the eighth transistor, thereby improving the transient performance of the LDO.

[0016] In one possible implementation of the first aspect, the at least one detection circuit further includes a third detection circuit, wherein a second capacitor in the third detection circuit is coupled between the output terminal of the amplifier and the control terminal of the tenth transistor. In this possible implementation, the first voltage output by the LDO is compensated by feeding back the detection circuit to the control terminal of the tenth transistor, thereby improving the transient performance of the LDO.

[0017] In one possible implementation of the first aspect, the at least one detection circuit further includes a fourth detection circuit, wherein a second capacitor in the fourth detection circuit is coupled between the output terminal of the amplifier and the control terminal of the eleventh transistor. In this possible implementation, the first voltage output by the LDO is compensated by feeding back the detection circuit to the control terminal of the eleventh transistor, thereby improving the transient performance of the LDO.

[0018] In a second aspect, a chip system is provided, comprising a load circuit and a transient boost circuit for a low-dropout linear regulator (LDO) as provided in the first aspect or any possible implementation of the first aspect; wherein the transient boost circuit comprises an LDO and at least one detection circuit coupled to the LDO, the LDO being used to power the load circuit, and the at least one detection circuit being used to improve the transient of the LDO.

[0019] In a third aspect, a device is provided, comprising a load circuit and a circuit board, the circuit board comprising a transient boost circuit for a low-dropout linear regulator (LDO) as provided in the first aspect or any possible implementation of the first aspect; wherein the transient boost circuit comprises an LDO and at least one detection circuit coupled to the LDO, the LDO being used to power the load circuit, and the at least one detection circuit being used to improve the transient of the LDO.

[0020] It can be understood that any of the chip systems and devices provided above include the transient boost circuit for LDO provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the transient boost circuit for LDO provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of an LDO provided in an embodiment of the present application;

[0022] Figure 2 A schematic structural diagram of a transient boost circuit for an LDO provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of an amplifier provided in an embodiment of the present application;

[0024] Figure 4A schematic structural diagram of another transient boost circuit for LDO provided in an embodiment of the present application;

[0025] Figure 5 A schematic structural diagram of another transient boost circuit for LDO provided in an embodiment of the present application;

[0026] Figure 6 A schematic diagram of the structure of an operational amplifier provided in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of the structure of a FVF LDO provided in an embodiment of the present application;

[0028] Figure 8 A schematic structural diagram of another transient boost circuit for LDO provided in an embodiment of the present application;

[0029] Figure 9 A schematic structural diagram of another transient boost circuit for LDO provided in an embodiment of the present application;

[0030] Figure 10 A schematic structural diagram of another transient boost circuit for LDO provided in an embodiment of the present application;

[0031] Figure 11 A schematic structural diagram of another transient boost circuit for LDO provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use this description and technology and do not limit the scope of this application.

[0033] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0034] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

[0036] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0037] In addition, the transistors involved in the embodiments of the present application may be metal oxide semiconductor (MOS) field effect transistors (hereinafter referred to as MOS transistors). The control terminal of the transistor in the embodiments of the present application may refer to the gate of the transistor; in one possible embodiment, one electrode of the transistor may refer to the source, and the other electrode may refer to the drain; in another possible embodiment, one electrode of the transistor may refer to the drain, and the other electrode may refer to the source.

[0038] The technical solution of the present application can be applied to various subsystems or systems powered by low dropout regulators (LDOs). For example, the technical solution of the present application can be applied to radio frequency (RF) transceivers, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), high-speed digital circuits (e.g., chip systems (SoCs), and phase-locked loops (PLLs) powered by LDOs.

[0039] Figure 1A circuit diagram of a general LDO provided in an embodiment of the present application is provided. The LDO may include: an operational amplifier A0, a voltage regulating transistor M0, a sampling circuit, and a load capacitor C0. The sampling circuit may include resistors Ra and Rb. Taking the voltage regulating transistor M0 as a PMOS transistor as an example, the output terminal of the operational amplifier A0 is coupled to the control terminal of the voltage regulating transistor M0 (i.e., the gate of the PMOS), one electrode of the voltage regulating transistor M0 (i.e., the source of the PMOS) is coupled to the voltage input terminal (VDD), and the other electrode of the voltage regulating transistor M0 (i.e., the drain of the PMOS) is coupled to the input terminal of the sampling circuit as the output terminal of the LDO. The output terminal of the sampling circuit is coupled to the positive input terminal of the operational amplifier A0, and the negative input terminal of the operational amplifier A0 is used to receive the reference voltage V REF One end of the load capacitor C0 is coupled to the output end of the LDO, and the other end is coupled to the ground end (GND).

[0040] When the LDO is working, the sampling circuit samples the output voltage V through the resistors Ra and Rb. OUT The sampling is performed and the collected voltage is fed back to the positive input terminal of the operational amplifier; the collected voltage and the reference voltage V received by the negative input terminal of the operational amplifier are fed back to the positive input terminal of the operational amplifier. REF The amplified voltage is compared and amplified, and is fed back to the input terminal through the gate of the voltage regulating transistor M0, and is dynamically output by the conduction voltage drop of the voltage regulating transistor M0.

[0041] Among them, when the LDO is powered on or the subsequent load changes sharply, the output voltage V OUT Overshoot or undershoot may occur, resulting in poor transient performance of the LDO. Overshoot can refer to the actual output voltage peak or valley value being greater than the set output voltage range, while undershoot can refer to the actual output voltage peak or valley value being less than the set output voltage range. Currently, to ensure that the LDO has a better transient response, an LDO with a large on-chip capacitor or an LDO with an off-chip capacitor is generally used. However, if an LDO with an on-chip capacitor is used, the on-chip capacitor will occupy a larger chip area; if an LDO with an off-chip capacitor is used, the off-chip capacitor will occupy additional PCB area. Based on this, an embodiment of the present application provides a transient boost circuit for an LDO. The principle is to improve the transient performance of the LDO by using at least one detection circuit coupled to the LDO. The at least one detection circuit can provide feedback to any node in the LDO (e.g., the output node or an internal node of the LDO), simply forming negative feedback. This circuit can be used to improve the transient performance of the LDO while reducing the area occupied by the capacitor in the LDO, thereby reducing the area of ​​the chip where the LDO is located.

[0042] Figure 2A schematic diagram of a transient boost circuit for LDO provided in an embodiment of the present application is provided. Figure 2 The circuit includes: an LDO 1 and at least one detection circuit 2 coupled to the LDO 1. The at least one detection circuit 2 may include one or more detection circuits.

[0043] Among them, LDO 1 is used to output a first voltage V1. The first voltage V1 may refer to a voltage used to power various subsystems or systems. The first voltage V1 may also be called the output voltage of LDO 1. For example, LDO 1 is Figure 1 The LDO shown, the first voltage V1 is Figure 1 The output voltage V OUT .

[0044] In addition, each detection circuit in at least one detection circuit 2 includes: a first capacitor C1, an amplifier 21, and a second capacitor C2. The first capacitor C1 is used to generate a coupling voltage based on changes in the first voltage V1 and couple the coupling voltage to the inverting amplifier 21. That is, the first capacitor C1 couples the first voltage V1 to the amplifier 21 through AC coupling, and the DC component in the first voltage V1 can be filtered out by the first capacitor. The amplifier 21 is used to amplify the coupling voltage to obtain a second voltage V2. That is, the second voltage V2 is the amplified voltage of the coupling voltage. For example, the amplifier 21 can be a positive-phase amplifier or an inverting amplifier, and is used to amplify the coupling voltage to obtain the second voltage V2. The second capacitor C2 is used to couple the second voltage V2 to the LDO 1. That is, the second capacitor C2 couples the second voltage V2 to the LDO 1 through AC coupling. The second voltage V2 is used to adjust the first voltage V1 to maintain the first voltage V1 constant.

[0045] It is understood that the second capacitor C2 is used to couple the second voltage V2 to the LDO 1, which may include: the second capacitor C2 directly coupling the second voltage V2 to the LDO 1, so as to maintain the first voltage V1 constant by adjusting the first voltage V1 internally in the LDO 1; or, the second capacitor C2 indirectly coupling the second voltage V2 to the LDO 1, for example, the second capacitor C2 couples the second voltage V2 to the LDO 1 through an intermediate circuit, and the intermediate circuit can be used to adjust the first voltage V1 to maintain the first voltage V1 constant, for example, the intermediate circuit is the compensation circuit 22 described below. In addition, maintaining the constancy of the first voltage V1 can be understood as maintaining the first voltage V1 equal to a preset voltage value, or maintaining the first voltage V1 fluctuating within a small range near the preset voltage value. For example, if the preset voltage value is 5V and the first voltage V1 fluctuates within the range of [4.9V, 5.1V], it can be understood that the first voltage V1 is constant.

[0046] Optionally, the amplifier 21 may be an integrated amplifier module, for example, the amplifier 21 may be an operational transimpedance amplifier (OTA) module; or, the amplifier 21 may be an amplifier constructed of electronic components. Figure 3 As shown, the amplifier 21 may include: a first transistor M1, a second transistor M2, a third transistor M3, and a first resistor R1. One electrode of the first transistor M1, one electrode of the second transistor M2, and one end of the first resistor R1 are coupled as an output end of the amplifier 21; a control end of the first transistor M1, a control end of the second transistor M2, and the other end of the first resistor R1 are coupled as an input end of the amplifier 21; the other electrode of the second transistor M2 is coupled to one electrode of the third transistor M3; one of the other electrodes of the first transistor M1 and the other electrode of the third transistor M3 is coupled to a power supply end, and the other is coupled to a ground end; and the control end of the third transistor M3 is coupled to a bias voltage end VBP.

[0047] The bias voltage terminal VBP is used to provide a bias voltage for the third transistor M3, which acts as a current source to provide a bias current for the amplifier 21. The first transistor M1 and the second transistor M2 form a common source amplifier. The first resistor R1 provides a static DC bias voltage through direct coupling, so that the first transistor M1 and the second transistor M2 are both in the saturation region or the subthreshold region. Specifically, when the first voltage V1 is coupled to the input terminal of the amplifier 21 through the first capacitor C1, it is reversely amplified by the first transistor M1 and the second transistor M2, and the second voltage V2 is output from the output terminal of the amplifier 21.

[0048] It should be noted that Figure 3 In the figure, the first transistor M1 is an NMOS transistor, the second transistor M2 and the third transistor M3 are both PMOS transistors, one of the electrodes is a drain, the other electrode is a source, and the control terminal is a gate. In practical applications, the first transistor M1, the second transistor M2 and the third transistor M3 can also be replaced by other transistors with similar functions. Figure 3 It does not limit the embodiments of the present application.

[0049] The amplifier 21 is an inverter-based amplifier. Its transconductance is the sum of the transconductance of the first transistor M1 and the transconductance of the second transistor M2. With the same power consumption, its transconductance is twice that of a conventional amplifier. The third transistor M3 is used to provide a bias current for the amplifier 21, preventing its power consumption from varying with changes in the power supply voltage and process corners. The amplifier 21 is coupled to the LDO 1 via the first capacitor C1 and the second capacitor C2, allowing the DC operating point of the amplifier 21 to be biased solely using the first resistor R1, effectively reducing the matching requirements for the amplifier 21.

[0050] In the embodiment of the present application, the first voltage V1 output by LDO 1 is coupled to amplifier 21 via first capacitor C1, which amplifies it. This improves the transient response of the LDO while allowing the use of a smaller first capacitor C1 to couple the first voltage V1, thereby reducing the chip area occupied by first capacitor C1. Simultaneously, the second voltage V2 output by amplifier 21 is coupled to LDO 1 via second capacitor C2, preventing the second voltage V2 from directly acting on the inherent loop of LDO 1, thereby preventing the DC characteristics of LDO 1 and ensuring the stability of the LDO 1 loop. Furthermore, amplifier 21 is coupled to LDO 1 via first capacitor C1 and second capacitor C2, thereby separating the bias of amplifier 21 from the DC component of first voltage V1. This effectively reduces the difficulty and complexity of biasing amplifier 21. Specifically, the design of amplifier 21 does not need to consider requirements such as offset and matching, thereby further reducing chip area and achieving low power consumption and high energy efficiency.

[0051] Furthermore, depending on whether the second capacitor C2 directly couples the second voltage V2 to the LDO 1, the detection circuit can be divided into two types: the first type is a detection circuit that includes a compensation circuit, i.e., the second capacitor C2 indirectly couples the second voltage V2 to the LDO 1; the second type is a detection circuit that does not include a compensation circuit, i.e., the second capacitor C2 directly couples the second voltage V2 to the LDO 1. The at least one detection circuit 2 can include at least one of the above two types of detection circuits. These two types of detection circuits are described below.

[0052] The first detection circuit includes a compensation circuit, that is, the second capacitor C2 indirectly couples the second voltage V2 to the LDO 1 .

[0053] Specifically, at least one detection circuit 2 includes a first detection circuit 2a. First detection circuit 2a includes a compensation circuit 22 coupled between a second capacitor C2 and LDO 1. Compensation circuit 22 is configured to adjust first voltage V1 based on second voltage V2 to maintain first voltage V1 constant. Herein, first detection circuit 2a may refer to the detection circuit including compensation circuit 22.

[0054] In one possible embodiment, Figure 4 As shown, the compensation circuit 22 includes: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a second resistor R2, and a third resistor R3. One electrode of the fourth transistor M4, one end of the third resistor R3, and one electrode of the sixth transistor M6 are coupled to a first node ①. The other electrode of the fourth transistor M4, the control end of the fifth transistor M5, and one end of the second resistor R2 are coupled as an input end of the compensation circuit 22. One electrode of the fifth transistor M5 and the other end of the second resistor R2 are coupled to a second node ②. The other electrode of the fifth transistor M5, the control end of the sixth transistor M6, and the other end of the third resistor R3 are coupled. The other electrode of the sixth transistor M6 serves as an output end of the compensation circuit 22. One of the first node ① and the second node ② is coupled to the power supply, and the other is coupled to the ground.

[0055] Optionally, the at least one detection circuit 2 may include one or more first detection circuits, and the output terminals of the one or more first detection circuits may be coupled to different nodes or the same node of the LDO 1, that is, the multiple first detection circuits feed back to different nodes or the same node of the LDO 1. For example, Figure 4 As shown, it is assumed that at least one detection circuit 2 includes two first detection circuits, one of which ( Figure 4 The first node ① of the compensation circuit 22 (denoted as 2a-1) is coupled to the power supply terminal, the second node ② is coupled to the ground terminal, and another first detection circuit ( Figure 4 In the compensation circuit 22 (denoted as 2a-2), the first node ① is coupled to the ground terminal, and the second node ② is coupled to the power terminal. Figure 4 In the embodiment, the output terminals of the two first detection circuits are coupled to the output terminal of LDO 1 (ie, the two first detection circuits are fed back to the output terminal of LDO 1), and the LDO is Figure 1 The LDO shown in FIG. 1 is used as an example for explanation, where VBP and VBN represent different bias voltage terminals.

[0056] It should be noted that, in the first detection circuit 2a-1, the fifth transistor M5 is an NMOS transistor, the fourth transistor M4 and the sixth transistor M6 are both PMOS transistors, and in the first detection circuit 2a-2, the fifth transistor M5 is a PMOS transistor, the fourth transistor M4 and the sixth transistor M6 are both NMOS transistors, the one terminal is a drain, the other terminal is a source, and the control terminal is a gate. In actual applications, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 can also be replaced by other transistors with similar functions. Figure 4 It does not limit the embodiments of the present application.

[0057] in addition, Figure 4 The second resistor R2 and the third resistor R3 can also be replaced by other devices with similar functions. For example, the second resistor R2 can be replaced by an NMOS transistor, and the third resistor R3 can be replaced by a PMOS transistor. The gate of the NMOS transistor and the gate of the PMOS transistor can be connected to the bias voltage terminal.

[0058] above Figure 4 In the embodiment, the first detection circuit 2a-1 can be referred to as an undershoot detection circuit, and is configured to provide boost compensation for the first voltage V1 when the first voltage V1 output by the LDO 1 undershoots. Specifically, when the first voltage V1 output by the LDO 1 undershoots, the first detection circuit 2a-1 detects the undershoot glitch of the first voltage V1 via the first capacitor C1 (i.e., generates a coupled voltage based on the change in the first voltage V1). The undershoot glitch is amplified by the amplifier 21 formed by M1, M2, M3, and R1 to generate a second voltage V2. The second voltage V2 is coupled to the gate of the fifth transistor M5 in the compensation circuit 22 via the second capacitor C2. At this time, the fifth transistor M5 is turned on, and the gate voltage of the sixth transistor M6 is pulled down, thereby turning on the sixth transistor M6. The drain voltage of the sixth transistor M6 is used to compensate for the first voltage V1 output by the LDO 1, thereby providing boost compensation for the first voltage V1, i.e., providing transient compensation for the undershoot of the first voltage V1.

[0059] During the operation of the first detection circuit 2a-1, transient compensation is triggered only when the second voltage V2 output by the amplifier 21 exceeds the threshold voltage of the fifth transistor M5. The drain current of the fourth transistor M4 forms a bias voltage after passing through the second resistor R2, which can lower the threshold voltage of the fifth transistor M5, so that the signal coupled through the second capacitor C2 can immediately turn on the fifth transistor M5. In addition, when the first voltage V1 output by the LDO 1 does not undershoot, or the undershoot is less than the threshold voltage of the fifth transistor M5, the fifth transistor M5 in the compensation circuit 22 is turned off, and the third resistor R3 pulls up to turn off the sixth transistor M6, so that the first detection circuit 2a-1 has no effect on the LDO 1.

[0060] above Figure 4 In the embodiment, the first detection circuit 2a-2 can be referred to as an overshoot detection circuit, and is configured to implement voltage reduction adjustment of the first voltage V1 when the first voltage V1 output by the LDO 1 overshoots. Specifically, when the first voltage V1 output by the LDO 1 overshoots, the first detection circuit 2a-2 detects the overshoot glitch of the first voltage V1 via the first capacitor C1 (i.e., generates a coupling voltage based on the change in the first voltage V1). The overshoot glitch is amplified by the amplifier 21 formed by M1, M2, M3, and R1 to generate a second voltage V2. The second voltage V2 is coupled to the gate of the fifth transistor M5 in the compensation circuit 22 via the second capacitor C2. At this time, the fifth transistor M5 is turned on, and the gate voltage of the sixth transistor M6 is pulled down, thereby turning on the sixth transistor M6. The drain voltage of the sixth transistor M6 is used to pull down the first voltage V1 output by the LDO 1, thereby implementing voltage reduction adjustment of the first voltage V1, i.e., achieving transient compensation when the first voltage V1 overshoots.

[0061] During the operation of the first detection circuit 2a-2, transient compensation is triggered only when the second voltage V2 output by the amplifier 21 exceeds the threshold voltage of the fifth transistor M5. The drain current of the fourth transistor M4 forms a bias voltage after passing through the second resistor R2, which can lower the threshold voltage of the fifth transistor M5, so that the signal coupled through the second capacitor C2 can immediately turn on the fifth transistor M5. In addition, when the first voltage V1 output by the LDO 1 does not overshoot, or the overshoot is less than the threshold voltage of the fifth transistor M5, the fifth transistor M5 in the compensation circuit 22 is turned off, and the third resistor R3 pulls down to turn off the sixth transistor M6, so that the first detection circuit 2a-2 has no effect on the LDO 1.

[0062] In another possible embodiment, Figure 5 As shown, the compensation circuit 22 includes: a fourth transistor M4, a fifth transistor M5, and a second resistor R2. One electrode of the fourth transistor M4 is coupled to a first node ①, and the other electrode of the fourth transistor M4, the control terminal of the fifth transistor M5, and one end of the second resistor R2 are coupled as an input end of the compensation circuit 22. One electrode of the fifth transistor M5 and the other end of the second resistor R2 are coupled to a second node ②, and the other electrode of the fifth transistor M5 serves as an output end of the compensation circuit 22. One of the first node ① and the second node ② is coupled to a power supply terminal, and the other is coupled to a ground terminal.

[0063] Optionally, the at least one detection circuit 2 may include one or more first detection circuits, and the output terminals of the one or more first detection circuits may be coupled to different nodes or the same node of the LDO 1, that is, multiple first detection circuits may feed back to multiple first detection circuits. For example, Figure 5 As shown, it is assumed that at least one detection circuit 2 includes a first detection circuit 2a, a first node ① in a compensation circuit 22 of the first detection circuit 2a is coupled to a power supply terminal, and a second node ② is coupled to a ground terminal; the LDO is Figure 1 In the LDO shown, the output end of the first detection circuit 2a is coupled to the gate of the voltage regulating transistor M0 in the LDO 1, that is, the first detection circuit 2a feeds back to the gate of the voltage regulating transistor M0 in the LDO 1). The operating principle of the first detection circuit 2a is similar to the operating principle of the first detection circuit 2a-1 described above, and will not be repeated herein in this embodiment of the present application.

[0064] It should be noted that Figure 5 In the example, the fourth transistor M4 is a PMOS transistor, the fifth transistor M5 is an NMOS transistor, the one terminal is a drain, the other terminal is a source, and the control terminal is a gate. In actual applications, the fourth transistor M4 and the fifth transistor M5 can also be replaced by other transistors with similar functions. In addition, Figure 5 In the description, at least one detection circuit 2 includes a first detection circuit 2a as an example. Figure 5 It does not limit the embodiments of the present application.

[0065] Furthermore, the above Figure 4 and Figure 5 The first detection circuit shown is applied to the above Figure 1 In addition to the LDO 1 shown, the LDO can also be applied to LDOs with other structures. For example, the operational amplifier A0 in the LDO 1 can be an operational amplifier constructed using multiple transistors, or the LDO can be a flipped voltage follower (FVF) LDO.

[0066] For example, Figure 6 As shown, the operational amplifier A0 in the LDO 1 may include 12 transistors, T1 to T12. The connection relationship of the transistors T1 to T12 is specifically shown in the figure, and VBP and VBN represent bias voltages, respectively. Among them, at least one detection circuit 2 can be fed back to any node in the operational amplifier A0 to form negative feedback. For example, at least one detection circuit 2 feeds back to the gate of the transistor T2 (also called the gate of the transistor T3), or at least one detection circuit 2 feeds back to the gate of the transistor T5 (also called the gate of the transistor T6). It should be noted that Figure 6In the example, transistors T1, T4, T8, T9, T10, T11 and T12 are all PMOS transistors, and T2, T3, T5, T6 and T7 are all NMOS transistors. The above transistors T1 to T12 can also be replaced by other transistors with similar functions, or the operational amplifier A0 includes more or fewer transistors. Figure 6 It does not limit the embodiments of the present application.

[0067] For example, Figure 7 As shown, when the LDO 1 is a FVF LDO, the LDO 1 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11 and a fourth resistor R4. Among them, one electrode of the seventh transistor M7 and one electrode of the eighth transistor M8 are coupled to the power supply terminal, the other electrode of the seventh transistor M7 and one electrode of the ninth transistor M9 are coupled to serve as the output terminal of the LDO 1, and the other electrode of the eighth transistor M8, one electrode of the tenth transistor M10 and the control terminal of the seventh transistor M7 are coupled (the voltage at the coupling point is represented by V FB2 ), the other electrode of the ninth transistor M9, the other electrode of the tenth transistor M10 and one electrode of the eleventh transistor M11 are coupled (the voltage at the coupling point is expressed as V FB1 ), the other electrode of the eleventh transistor M11 is coupled to the ground end, the control end of the eleventh transistor M11 is coupled to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the bias voltage end VBN1.

[0068] It should be noted that Figure 7 In the description, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are all PMOS transistors, the tenth transistor M10 and the eleventh transistor M11 are all NMOS transistors, the one electrode of the seventh transistor M7 to the ninth transistor is a source, the other electrode is a drain, the one electrode of the tenth transistor M10 and the eleventh transistor M11 is a drain, the other electrode is a source, and the control end is a gate. In actual applications, the seventh transistor M7 to the eleventh transistor M11 can also be replaced by other transistors with similar functions. Figure 7 It does not limit the embodiments of the present application.

[0069] above Figure 4 or Figure 5The output end of the first detection circuit shown may also be coupled to the output end of the FVF LDO or other nodes inside the FVF LDO. For example, the output end of the first detection circuit may be coupled to the control end of the seventh transistor M7 in the FVF LDO, or the output end of the first detection circuit may be coupled to the control end of the eighth transistor M8 in the FVF LDO, or the output end of the first detection circuit may be coupled to the control end of the tenth transistor M10 in the FVF LDO, or the output end of the first detection circuit may be coupled to the control end of the eleventh transistor M11 in the FVF LDO, and so on.

[0070] The second detection circuit does not include a compensation circuit, that is, the second capacitor C2 directly couples the second voltage V2 to LDO1. Figure 7 The structure of the FVF LDO shown is used as an example for explanation.

[0071] In one possible embodiment, Figure 8 As shown, at least one detection circuit 2 includes a second detection circuit 2b. The second capacitor C2 in the second detection circuit 2b is coupled between the output end of the amplifier 21 and the control end (i.e., the gate) of the eighth transistor M8. That is, the second detection circuit 2b feeds back to the gate of the eighth transistor M8 in the FVF LDO.

[0072] Specifically, when the first voltage V1 output by the FVF LDO is normal, the second detection circuit 2b does not work. Assuming that the current flowing through the eleventh transistor M11 is I11, the current flowing through the eighth transistor M8 is I8, the current flowing through the tenth transistor M10 is I10, and the current flowing through the ninth transistor M9 is I9, I11=I9+I8, and I8=I10.

[0073] When the FVF LDO undershoots, the second detection circuit 2b detects the undershoot burr of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to the change of the first voltage V1). The undershoot burr is amplified by the amplifier 21 to obtain the second voltage V2; the second voltage V2 is coupled to the gate of the eighth transistor M8 in the FVF LDO through the second capacitor C2, and the gate-source voltage (i.e., Vgs) of the eighth transistor M8 decreases to control the current I8 flowing through the eighth transistor M8 to decrease. At the same time, since the current I10 flowing through the tenth transistor M10 remains unchanged, at this time I10 is greater than I8, so that the gate voltage V BF2 will be pulled down, and the gate-source voltage (ie, Vgs) of the seventh transistor M7 will increase rapidly, thereby increasing the output current of the FVF LDO, that is, achieving transient compensation when the first voltage V1 undershoots.

[0074] When the FVF LDO has an overshoot, the second detection circuit 2b detects the overshoot burr of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to the change of the first voltage V1). The overshoot burr is amplified by the amplifier 21 to obtain the second voltage V2; the second voltage V2 is coupled to the gate of the eighth transistor M8 in the FVF LDO through the second capacitor C2. At this time, the gate-source voltage (i.e., Vgs) of the eighth transistor M8 increases to control the current I8 flowing through the eighth transistor M8 to increase. At the same time, since the current I10 flowing through the tenth transistor M10 remains unchanged, I10 is less than I8 at this time, so that the gate voltage V BF2 will be pulled up, and the gate-source voltage (ie, Vgs) of the seventh transistor M7 will decrease, thereby reducing the output current of the FVF LDO, that is, achieving transient compensation when the first voltage V1 overshoots.

[0075] In another possible embodiment, Figure 9 As shown, the at least one detection circuit 2 includes a third detection circuit 2c. The second capacitor C2 in the third detection circuit 2c is coupled between the output end of the inverting amplifier 21 and the control end (i.e., the gate) of the tenth transistor M10. That is, the third detection circuit 2c feeds back to the gate of the tenth transistor M10 in the FVF LDO.

[0076] Specifically, when the first voltage V1 output by the FVF LDO is normal, the second detection circuit 2b does not work. Assuming that the current flowing through the eleventh transistor M11 is I11, the current flowing through the eighth transistor M8 is I8, the current flowing through the tenth transistor M10 is I10, and the current flowing through the ninth transistor M9 is I9, I11=I9+I8, and I8=I10.

[0077] When the FVF LDO undershoots, the third detection circuit 2c detects the undershoot burr of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to the change of the first voltage V1). The undershoot burr is amplified by the inverting amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the tenth transistor M10 in the FVF LDO through the second capacitor C2. At this time, the gate-source voltage (i.e., Vgs) of the tenth transistor M10 increases to control the current I10 flowing through the tenth transistor M10 to increase. At the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, I10 is greater than I8 at this time, so that the gate voltage V BF2 will be pulled down, and the gate-source voltage (ie, Vgs) of the seventh transistor M7 will increase rapidly, thereby increasing the output current of the FVF LDO, that is, achieving transient compensation when the first voltage V1 undershoots.

[0078] When the FVF LDO has an overshoot, the third detection circuit 2c detects the overshoot burr of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to the change of the first voltage V1). The overshoot burr is amplified by the inverting amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the tenth transistor M10 in the FVF LDO through the second capacitor C2. At this time, the gate-source voltage (i.e., Vgs) of the tenth transistor M10 decreases to control the current I10 flowing through the tenth transistor M10 to decrease. At the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, I10 is less than I8 at this time, so that the gate voltage V BF2 will be pulled up, and the gate-source voltage (ie, Vgs) of the seventh transistor M7 will decrease, thereby reducing the output current of the FVF LDO, that is, achieving transient compensation when the first voltage V1 overshoots.

[0079] In another possible embodiment, Figure 10 As shown, the at least one detection circuit 2 includes a fourth detection circuit 2d. The second capacitor C2 in the fourth detection circuit 2d is coupled between the output end of the inverting amplifier 21 and the control end (i.e., the gate) of the eleventh transistor M11. That is, the fourth detection circuit 2d feeds back to the gate of the eleventh transistor M11 in the FVF LDO.

[0080] Specifically, when the first voltage V1 output by the FVF LDO is normal, the second detection circuit 2b does not work. Assuming that the current flowing through the eleventh transistor M11 is I11, the current flowing through the eighth transistor M8 is I8, the current flowing through the tenth transistor M10 is I10, and the current flowing through the ninth transistor M9 is I9, I11=I9+I8, and I8=I10.

[0081] When the FVF LDO undershoots, the fourth detection circuit 2d detects the undershoot burr of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to the change of the first voltage V1). The undershoot burr is amplified by the inverting amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the eleventh transistor M11 in the FVF LDO through the second capacitor C2. At this time, the gate-source voltage (i.e., Vgs) of the eleventh transistor M11 increases to control the current I10 flowing through the eleventh transistor M10 to increase. At the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, the current I9 flowing through the ninth transistor M9 decreases, and the current I10 flowing through the tenth transistor M10 increases. At this time, I10 is greater than I8, so that the gate voltage V BF2 will be pulled down, and the gate-source voltage (ie, Vgs) of the seventh transistor M7 will increase rapidly, thereby increasing the output current of the FVF LDO, that is, achieving transient compensation when the first voltage V1 undershoots.

[0082] When the FVF LDO has an overshoot, the fourth detection circuit 2d detects the overshoot burr of the first voltage V1 through the first capacitor C1 (i.e., a coupling voltage is generated according to the change of the first voltage V1). The overshoot burr is amplified by the amplifier 21 to obtain a second voltage V2; the second voltage V2 is coupled to the gate of the eleventh transistor M11 in the FVF LDO through the second capacitor C2. At this time, the gate-source voltage (i.e., Vgs) of the eleventh transistor M11 decreases to control the current I11 flowing through the eleventh transistor M11 to decrease. At the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, the current I9 flowing through the ninth transistor M9 increases, and the current I10 flowing through the tenth transistor M10 decreases. At this time, I10 is less than I8, so that the gate voltage V BF2 will be pulled up, and the gate-source voltage (ie, Vgs) of the seventh transistor M7 will decrease, thereby reducing the output current of the FVF LDO, that is, achieving transient compensation when the first voltage V1 overshoots.

[0083] Furthermore, for overshoot compensation or undershoot compensation of LDO 1, multiple detection circuits can be used to implement transient compensation of LDO 1. The output ends of the multiple detection circuits can be coupled to different nodes in LDO 1. It is only necessary to ensure that the coupling between each detection circuit and LDO 1 forms negative feedback.

[0084] For example, Figure 11 As shown, taking the undershoot compensation of the FVF LDO as an example, the at least one detection circuit 2 may include four detection circuits, which are respectively represented by 201 to 204, wherein the output end of the detection circuit 201 is coupled to the output end of the FVF LDO, the output end of the detection circuit 202 is coupled to the gate of the seventh transistor M7 in the FVF LDO, the output end of the detection circuit 203 is coupled to the gate of the eighth transistor M8 in the FVF LDO, and the output end of the detection circuit 204 is coupled to the gate of the eleventh transistor M11 in the FVF LDO.

[0085] The working principle of the detection circuit 201 is the same as that of the above Figure 4 The working principle of the first detection circuit 2a-1 is similar to that of the detection circuit 202. Figure 5 The working principle of the first detection circuit 2a is similar to that of the detection circuit 203. Figure 8 The working principle of the second detection circuit 2b is similar to that of the detection circuit 204. Figure 10 The working principle of the fourth detection circuit 2d shown is similar. Please refer to the relevant description above for details, and the embodiments of the present application will not be repeated here.

[0086] In the embodiment of the present application, by performing transient compensation for the overshoot or undershoot of LDO 1 through multiple detection circuits, transient compensation of LDO 1 can be achieved more quickly, thereby improving the transient performance of LDO 1. In addition, when the first voltage V1 output by LDO 1 is normal or has little variation, these multiple detection circuits can be in a closed state, thereby not affecting the DC characteristics of LDO 1 and ensuring the stability of the LDO 1 loop.

[0087] Based on this, an embodiment of the present application further provides a chip system, comprising a load circuit and any of the above-mentioned transient boost circuits for LDOs, wherein the transient boost circuit comprises an LDO and at least one detection circuit coupled to the LDO, the LDO being used to power the load circuit, and the at least one detection circuit being used to improve the transient state of the LDO. Optionally, the load circuit may comprise at least one of the following: an RF transceiver, a DAC, an ADC, a high-speed digital circuit (e.g., a chip system-on-chip), or a PLL.

[0088] The present application also provides a device comprising a load circuit and a circuit board, the circuit board including any of the aforementioned transient boost circuits for LDOs, the transient boost circuit including an LDO and at least one detection circuit coupled to the LDO, the LDO being used to power the load circuit, and the at least one detection circuit being used to improve the transient state of the LDO. Optionally, the load circuit may include at least one of the following: an RF transceiver, a DAC, an ADC, a high-speed digital circuit (e.g., a system-on-chip (SoC)), or a PLL. Furthermore, the device may be a communications device or a voltage stabilization device. The present application does not impose any specific limitations on this.

[0089] It should be noted that the above descriptions of the transient boost circuit for LDO can be applied to the chip system or the device, and will not be repeated in the embodiments of the present application.

[0090] In another aspect of the present application, a non-transitory computer-readable storage medium for use with a computer having software for creating an integrated circuit is provided. The computer-readable storage medium has one or more computer-readable data structures stored thereon, each of the one or more computer-readable data structures having photomask data for manufacturing a transient boost circuit for an LDO as provided in any of the above-provided figures.

[0091] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A transient boost circuit for a low dropout linear regulator (LDO), characterized in that: include: An LDO, configured to output a first voltage; at least one detection circuit coupled to the LDO, each detection circuit of the at least one detection circuit comprising a first capacitor, an amplifier, and a second capacitor; The first capacitor is configured to generate a coupling voltage according to a change in the first voltage, and couple the coupling voltage to the amplifier; The amplifier is used to amplify the coupling voltage to obtain a second voltage; The second capacitor is used to couple the second voltage to the LDO, and the second voltage is used to adjust the first voltage to maintain the first voltage constant; The at least one detection circuit includes a first detection circuit, the first detection circuit further comprising: a compensation circuit coupled between the second capacitor and the LDO; The compensation circuit is configured to adjust the first voltage according to the second voltage to maintain the first voltage constant; The compensation circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a second resistor, and a third resistor; wherein one electrode of the fourth transistor, one end of the third resistor, and one electrode of the sixth transistor are coupled to a first node, the other electrode of the fourth transistor, the control end of the fifth transistor, and one end of the second resistor are coupled as an input end of the compensation circuit, one electrode of the fifth transistor and the other end of the second resistor are coupled to a second node, the other electrode of the fifth transistor, the control end of the sixth transistor, and the other end of the third resistor are coupled, and the other electrode of the sixth transistor serves as an output end of the compensation circuit; one of the first node and the second node is coupled to a power supply terminal, and the other is coupled to a ground terminal; Alternatively, the compensation circuit includes: a fourth transistor, a fifth transistor and a second resistor; wherein, one electrode of the fourth transistor is coupled to a first node, the other electrode of the fourth transistor, the control terminal of the fifth transistor and one end of the second resistor are coupled as an input end of the compensation circuit, one electrode of the fifth transistor and the other end of the second resistor are coupled to a second node, and the other electrode of the fifth transistor serves as an output end of the compensation circuit; one of the first node and the second node is coupled to a power supply end, and the other is coupled to a ground end.

2. The circuit according to claim 1, wherein: The amplifier includes: a first transistor, a second transistor, a third transistor and a first resistor; One electrode of the first transistor, one electrode of the second transistor, and one end of the first resistor are coupled as the output end of the amplifier; the control end of the first transistor, the control end of the second transistor, and the other end of the first resistor are coupled as the input end of the amplifier; the other electrode of the second transistor is coupled to one electrode of the third transistor; one of the other electrodes of the first transistor and the other electrode of the third transistor is coupled to the power supply end, and the other is coupled to the ground end; the control end of the third transistor is coupled to the bias voltage end.

3. The circuit according to claim 1, wherein: The LDO has an output terminal, and the output terminal of the compensation circuit is coupled to the output terminal of the LDO.

4. The circuit according to claim 1, wherein: The LDO includes an operational amplifier, a voltage regulating transistor, and a sampling circuit. The output terminal of the operational amplifier is coupled to the control terminal of the voltage regulating transistor. One electrode of the voltage regulating transistor is coupled to the power supply terminal. The other electrode of the voltage regulating transistor is coupled to the input terminal of the sampling circuit to serve as the output terminal of the LDO. The output terminal of the sampling circuit is coupled to the positive phase input terminal of the operational amplifier. The negative phase input terminal of the operational amplifier is used to receive a reference voltage. Wherein, the output end of the compensation circuit is coupled to the control end of the voltage regulating transistor.

5. The circuit according to any one of claims 1 to 3, characterized in that: The LDO includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a fourth resistor; One electrode of the seventh transistor and one electrode of the eighth transistor are both coupled to a power supply terminal, the other electrode of the seventh transistor is coupled to one electrode of the ninth transistor as an output terminal of the LDO, the other electrode of the eighth transistor, one electrode of the tenth transistor, and a control terminal of the seventh transistor are coupled, the other electrode of the ninth transistor, another electrode of the tenth transistor, and one electrode of the eleventh transistor are coupled, the other electrode of the eleventh transistor is coupled to a ground terminal, the control terminal of the eleventh transistor is coupled to one end of the fourth resistor, and the other end of the fourth resistor is connected to a bias voltage terminal.

6. The circuit according to claim 5, characterized in that The at least one detection circuit further includes a second detection circuit, and the second capacitor in the second detection circuit is coupled between the output terminal of the amplifier and the control terminal of the eighth transistor.

7. The circuit according to claim 5, characterized in that The at least one detection circuit further includes a third detection circuit, and the second capacitor in the third detection circuit is coupled between the output terminal of the amplifier and the control terminal of the tenth transistor.

8. The circuit according to claim 5, characterized in that The at least one detection circuit further includes a fourth detection circuit, and the second capacitor in the fourth detection circuit is coupled between the output terminal of the amplifier and the control terminal of the eleventh transistor.

9. A chip system, characterized in that: The chip system includes a load circuit and a transient boost circuit for a low-dropout linear regulator (LDO) according to any one of claims 1 to 8; wherein the transient boost circuit includes an LDO and at least one detection circuit coupled to the LDO, the LDO is used to power the load circuit, and the at least one detection circuit is used to improve the transient of the LDO.

10. A communication device, characterized in that: The device includes a load circuit and a circuit board, wherein the circuit board includes the transient boost circuit for a low-dropout linear regulator (LDO) according to any one of claims 1 to 8; wherein the transient boost circuit includes an LDO and at least one detection circuit coupled to the LDO, the LDO is used to power the load circuit, and the at least one detection circuit is used to improve the transient of the LDO.

Images