Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate (10) comprises a base substrate (200), a first signal line (210) and a second signal line (Data) arranged on the base substrate (200), and a sub-pixel. The sub-pixel comprises a pixel circuit (101), and the pixel circuit (101) comprises: a light emitting element (121), a driving transistor (T1), a data writing transistor (T2), and a storage capacitor (Cst). The data writing transistor (T2) is configured to transmit a data signal (Vd) to the driving transistor (T1) under the control of a first scanning signal (Ga1), the first scanning signal (Ga1) is transmitted on a first signal line (210), and the data signal (Vd) is transmitted on a second signal line (Data); the driving transistor (T1) is configured to control the magnitude of a driving current flowing through the light emitting device (121) according to the data signal (Vd), and the light emitting device (121) is configured to receive the current and be driven by the driving current to emit light; the driving transistor (T1) includes an active pattern (T1a) and a gate (T1g), the active pattern (T1a) of the driving transistor (T1) includes a channel region (C1), the positive projection of the channel region (C1) on the substrate (200) is located at least partially overlapping with the positive projection of the gate (T1g) on ​​the substrate (200); the storage capacitor (Cst) includes: a first electrode plate (Cst 1) and a second electrode plate (Cst2). The first electrode plate (Cst1) is electrically connected to the gate electrode (T1g) of the driving transistor; the orthographic projection of the second electrode plate (Cst2) on the base substrate (200) partially overlaps with the orthographic projection of the first electrode plate (Cst 1) on the base substrate (200), and does not overlap with the orthographic projection of the channel region (C1) of the driving transistor (T1) on the base substrate (200).

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0002] In the display field, organic light-emitting diode (OLED) display panels have the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, simple manufacturing, etc., and have broad development prospects. In order to enrich the functions of display panels, components with other functions are usually integrated, such as imaging elements with photosensitivity, etc., to realize functions such as camera and fingerprint recognition. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a substrate substrate, a first signal line and a second signal line arranged on the substrate substrate, and a sub-pixel. The sub-pixel includes a pixel circuit, and the pixel circuit includes a light-emitting device, a driving transistor, a data writing transistor, and a storage capacitor. The data writing transistor is configured to transmit a data signal to the driving transistor under the control of a first scanning signal, the first scanning signal is transmitted on the first signal line, and the data signal is transmitted on the second signal line; the driving transistor is configured to control the size of the driving current flowing through the light-emitting device according to the data signal, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; the driving transistor includes an active pattern and a gate, and the active pattern of the driving transistor includes a channel region, and the positive projection of the channel region on the substrate substrate is located at least partially overlapped with the positive projection of the gate on the substrate substrate; the storage capacitor includes: a first electrode plate and a second electrode plate. The first electrode plate is electrically connected to the gate of the driving transistor; the positive projection of the second electrode plate on the substrate substrate overlaps at least partially with the positive projection of the first electrode plate on the substrate substrate, and does not overlap with the positive projection of the channel region of the driving transistor on the substrate substrate.

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first electrode plate includes a first portion and a second portion. The orthographic projection of the first portion on the base substrate does not overlap with the orthographic projection of the second electrode plate on the base substrate; the second portion is connected to the first portion and protrudes from the first portion, and the orthographic projection of the second portion on the base substrate overlaps with the orthographic projection of the second electrode plate on the base substrate.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel circuit also includes a first connection structure, which is electrically connected to the gate of the driving transistor and the first electrode plate, wherein the orthographic projection of the first connection structure on the base substrate does not overlap with the orthographic projection of the second electrode plate on the base substrate, and at least partially overlaps with the orthographic projection of the first part on the base substrate.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first connection structure is arranged in the same layer as the first electrode of the driving transistor, and is electrically connected to the first electrode plate through a first via hole; the orthographic projection of the first via hole on the base substrate overlaps with the orthographic projection of the first part of the first electrode plate on the base substrate.

[0007] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first electrode plate and the gate electrode of the driving transistor are arranged in the same layer and are an integrated structure.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first signal line is connected to the gate of the data write transistor and is configured to provide the first scanning signal to the gate of the data write transistor; the first signal line includes a first transverse portion extending along a first direction as a whole and a first longitudinal portion extending along a second direction as a whole, the first transverse portion is connected to the first longitudinal portion, and the first direction intersects with the second direction; the data write transistor includes an active pattern, and the orthographic projection of the active pattern of the data write transistor on the base substrate at least partially overlaps with the orthographic projection of the first longitudinal portion on the base substrate.

[0009] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit further includes a first light-emitting control transistor and a first light-emitting control line. The first light-emitting control transistor is connected to the first electrode and the first voltage terminal of the driving transistor, and is configured to apply the first power supply voltage of the first voltage terminal to the gate of the driving transistor under the control of the first light-emitting control signal; the first light-emitting control line is connected to the gate of the first light-emitting control transistor and is configured to provide the first light-emitting control signal to the gate of the first light-emitting control transistor; the first light-emitting control line includes a second transverse portion extending along the first direction as a whole and a second longitudinal portion extending along the second direction as a whole, the first light-emitting control transistor includes an active pattern, and the positive projection of the active pattern of the first light-emitting control transistor on the substrate substrate at least partially overlaps with the positive projection of the second longitudinal portion on the substrate substrate.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit further includes a second light-emitting control transistor and a second light-emitting control line. The second light-emitting control transistor is connected to the second light-emitting control terminal, the light-emitting device, and the second electrode of the driving transistor, and is configured to apply the driving current to the light-emitting device under the control of a second light-emitting control signal; the second light-emitting control line is connected to the gate of the second light-emitting control transistor and is configured to provide the second light-emitting control signal to the gate of the second light-emitting control transistor; the first light-emitting control line is multiplexed as the second light-emitting control line, and the second light-emitting control transistor includes an active pattern, and the positive projection of the active pattern of the second light-emitting control transistor on the substrate substrate at least partially overlaps with the positive projection of the second longitudinal portion on the substrate substrate.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, the storage capacitor is located between the first longitudinal portion and the second longitudinal portion, and between the first transverse portion and the second transverse portion.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the active pattern of the first light-emitting control transistor includes a channel region, and the active pattern of the second light-emitting control transistor includes a channel region; in the first direction, the distance between the channel region of the first light-emitting control transistor and the channel region of the driving transistor is equal to the distance between the channel region of the second light-emitting control transistor and the channel region of the driving transistor, and, in the second direction, the distance between the channel region of the first light-emitting control transistor and the channel region of the driving transistor is equal to the distance between the channel region of the second light-emitting control transistor and the channel region of the driving transistor.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the aspect ratio of the channel region of the first light emission control transistor is the same as the aspect ratio of the channel region of the second light emission control transistor.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit further includes a first power line, the first power line is connected to the first voltage terminal and is configured to provide the first power supply voltage to the pixel circuit, is arranged in the same layer as the first electrode of the driving transistor, and includes a third longitudinal portion and a third transverse portion. The third longitudinal portion extends along the second direction as a whole and is connected to the adjacent sub-pixel; the third transverse portion is connected to the third longitudinal portion and extends from the third longitudinal portion toward the second electrode plate, and the third transverse portion is electrically connected to the second electrode plate through a second via.

[0015] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second signal line is arranged on the same layer as the first power line, and includes a fourth transverse portion extending as a whole along the first direction and a fourth longitudinal portion extending as a whole along the second direction; in the second direction, the fourth transverse portion is at least partially opposite to the third transverse portion, and the orthographic projection of the fourth longitudinal portion on the base substrate does not overlap with the orthographic projection of the third transverse portion on the base substrate.

[0016] For example, in the display substrate provided by at least one embodiment of the present disclosure, the third longitudinal portion is located on the first side of the storage capacitor in the first direction, the orthographic projection of the fourth longitudinal portion on the base substrate at least partially overlaps with the orthographic projection of the storage capacitor on the base substrate, and does not overlap with the orthographic projection of the second via on the base substrate.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit includes a semiconductor layer, the semiconductor layer includes a channel region of the driving transistor, and the orthographic projection of the third lateral portion on the base substrate is located within the orthographic projection of the semiconductor layer on the base substrate.

[0018] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit further includes a compensation transistor configured to compensate the gate of the driving transistor in response to the second scanning signal and the data signal applied to the gate of the compensation transistor; the first lateral portion of the first signal line providing the first scanning signal to the data writing transistor is configured to provide the second scanning signal to the compensation transistor; the compensation transistor includes an active pattern, and the active pattern of the compensation transistor is arranged in the same layer as the active pattern of the driving transistor; the sub-pixel further includes a shielding portion. The shielding portion is located on a side of the active pattern of the compensation transistor away from the base substrate, wherein the orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active pattern of the compensation transistor on the base substrate; the pixel circuit further includes a reset signal line reset signal line, and the shielding portion is electrically connected to the reset signal line.

[0019] For example, in the display substrate provided in at least one embodiment of the present disclosure, the shielding portion and the reset signal line are provided in the same layer and are integrally formed.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit includes a semiconductor layer, and the semiconductor layer includes an active pattern of the driving transistor; the semiconductor layer includes a first part and a second part, the first part of the semiconductor layer and the second part of the semiconductor layer are separated by an opening, the orthographic projection of the opening on the base substrate overlaps with the orthographic projection of the second lateral part on the base substrate, and the orthographic projections of the first part of the semiconductor layer and the second part of the semiconductor layer on the base substrate do not overlap with the orthographic projection of the second lateral part on the base substrate.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the planar shape of the channel region of the driving transistor is a strip extending along the second direction as a whole.

[0022] For example, in the display substrate provided by at least one embodiment of the present disclosure, the planar shape of the channel region of the driving transistor is a straight strip extending along the second direction.

[0023] For example, in the display substrate provided by at least one embodiment of the present disclosure, the sub-pixel includes a first electrode, which is electrically connected to one of the first electrode and the second electrode of the driving transistor; the base substrate includes a plurality of the sub-pixels, and the plurality of the sub-pixels include a first sub-pixel and two adjacent second sub-pixels, and the two adjacent second sub-pixels are an upper second sub-pixel and a lower second sub-pixel, respectively, and the orthographic projection of the first electrode of the upper second sub-pixel on the base substrate and the orthographic projection of the first connection structure of the upper second sub-pixel on the base substrate at least partially overlap, and the orthographic projection of the first electrode of the lower second sub-pixel on the base substrate and the orthographic projection of the first connection structure of the lower second sub-pixel on the base substrate at least partially overlap.

[0024] For example, in a display substrate provided by at least one embodiment of the present disclosure, the first sub-pixel emits red light, and the second sub-pixel emits green light.

[0025] At least one embodiment of the present disclosure provides a display device, which includes any one of the display substrates provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0027] Figure 1 A schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0028] Figure 2AA schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

[0029] Figure 2B for Figure 2A A circuit diagram of a specific example of a pixel circuit shown;

[0030] Figure 2C A signal timing diagram of a driving method for a pixel circuit provided by at least one embodiment of the present disclosure;

[0031] Figure 3A A schematic diagram of the structure of a sub-pixel of a display substrate provided in one embodiment of the present disclosure;

[0032] Figure 3B for Figure 3A A schematic plan view of a semiconductor layer in a display substrate shown;

[0033] Figure 3C for Figure 3A A schematic plan view of a first conductive layer in a display substrate shown;

[0034] Figure 3D for Figure 3A A schematic plan view of a semiconductor layer and a first conductive layer stacked in a display substrate shown;

[0035] Figure 3E for Figure 3A A schematic plan view of a second conductive layer in a display substrate shown;

[0036] Figure 3F for Figure 3A A schematic plan view of a stack of semiconductor layers, a first conductive layer and a second conductive layer in a display substrate shown;

[0037] Figure 3G for Figure 3A A schematic plan view of a third conductive layer in the display substrate shown;

[0038] Figure 3H A schematic plan view of a first electrode provided for at least one embodiment of the present disclosure;

[0039] Fig. 3I for Figure 3A The semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the Figure 3H A schematic plan view of a first electrode stack is shown;

[0040] Figure 4A For along Figure 3A A cross-sectional view of the line A-A';

[0041] Figure 4B For along Figure 3AA cross-sectional view of the line BB' in FIG.

[0042] Figure 4C For along Figure 3A A cross-sectional view of the line C-C';

[0043] Figure 4D For along Figure 3A A cross-sectional view of the line D-D';

[0044] Figure 4E For along Figure 3A A cross-sectional view of the line E-E';

[0045] Figure 4F A schematic plan view of a channel region of another driving transistor of a display substrate provided in at least one embodiment of the present disclosure;

[0046] Figure 4G for Figure 5A A local enlarged schematic diagram of a sub-pixel in FIG.

[0047] Figure 5A A schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure;

[0048] Figure 5B for Figure 5A A schematic plan view of a semiconductor layer in a display substrate shown;

[0049] Figure 5C for Figure 5A A schematic plan view of a first conductive layer in a display substrate shown;

[0050] Figure 5D for Figure 5A A schematic plan view of a semiconductor layer and a first conductive layer stacked in a display substrate shown;

[0051] Figure 5E for Figure 5A A schematic plan view of a second conductive layer in a display substrate shown;

[0052] Fig. 5F for Figure 5A A schematic plan view of a stack of semiconductor layers, a first conductive layer and a second conductive layer in a display substrate shown;

[0053] Figure 5G for Fig. 5F The structure shown and the plan view of each via;

[0054] Figure 5H for Figure 5A A schematic plan view of a third conductive layer in the display substrate shown;

[0055] Fig.5I A schematic plan view of a first electrode provided for at least one embodiment of the present disclosure;

[0056] Figure 5J for Figure 5A The semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the Fig.5I A schematic plan view of a first electrode stack is shown;

[0057] Fig. 6A For along Figure 5A A cross-sectional view of the line F-F';

[0058] Figure 6B for Figure 5A A local enlarged schematic diagram of a sub-pixel in FIG.

[0059] Fig. 7A A schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure;

[0060] Figure 7B for Fig. 7A A schematic plan view of a semiconductor layer in a display substrate shown;

[0061] Figure 7C for Fig. 7A A schematic plan view of a first conductive layer in a display substrate shown;

[0062] Fig.7D for Fig. 7A A schematic plan view of a semiconductor layer and a first conductive layer stacked in a display substrate shown;

[0063] Fig. 7E for Fig. 7A A schematic plan view of a second conductive layer in a display substrate shown;

[0064] Figure 7F for Fig. 7A A schematic plan view of a stack of semiconductor layers, a first conductive layer and a second conductive layer in a display substrate shown;

[0065] Figure 7G for Fig. 7A A schematic plan view of a third conductive layer in the display substrate shown;

[0066] Figure 7H A schematic plan view of a first electrode provided for at least one embodiment of the present disclosure;

[0067] Fig.7I for Fig. 7A The semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the Figure 7H A schematic plan view of a first electrode stack is shown;

[0068] Fig. 8A For along Fig. 7A A cross-sectional view of the line G-G';

[0069] Figure 8B For along Fig. 7A A cross-sectional view of the line H-H';

[0070] Figure 8C For along Fig. 7A A cross-sectional view of line II' in FIG.

[0071] Fig.8D Fig. 7A A local enlarged schematic diagram of a sub-pixel in FIG.

[0072] Fig.9A A schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure;

[0073] Fig. 9B for Fig.9A A schematic plan view of a semiconductor layer in a display substrate shown;

[0074] Fig. 9C for Fig.9A A schematic plan view of a first conductive layer in a display substrate shown;

[0075] Fig.9D for Fig.9A A schematic plan view of a semiconductor layer and a first conductive layer stacked in a display substrate shown;

[0076] Fig.9E for Fig.9A A schematic plan view of a second conductive layer in a display substrate shown;

[0077] Fig.9F for Fig.9A A schematic plan view of a stack of semiconductor layers, a first conductive layer and a second conductive layer in a display substrate shown;

[0078] Figure 9G for Fig.9A A schematic plan view of a third conductive layer in the display substrate shown;

[0079] Figure 9H A schematic plan view of a first electrode provided for at least one embodiment of the present disclosure;

[0080] Fig.9I for Fig.9A The semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer and the Figure 9H A schematic plan view of a first electrode stack is shown;

[0081] Figure 9J for Fig.9A A local enlarged schematic diagram of a sub-pixel in FIG.

[0082] Fig. 10A For along Fig.9A A cross-sectional view of the line J-J';

[0083] Fig. 10B For along Fig.9A A cross-sectional view of the line K-K' in FIG.

[0084] Fig. 10C For along Fig.9A A cross-sectional view along line L-L'. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. The embodiments described below are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0086] Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0087] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure.

[0088] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first signal line arranged on the base substrate and extending along a first direction as a whole, and a second signal line extending along a second direction intersecting the first direction as a whole, wherein the first signal line transmits a first scan signal, and the second signal line transmits a data signal; the sub-pixel includes a pixel circuit; the pixel circuit includes: a light-emitting device and a driving transistor, and a data writing transistor; the data writing transistor is configured to transmit the data signal to the driving transistor under the control of a first scan signal, the first scan signal is transmitted on the first signal line, and the data signal is transmitted on the second signal line; the driving transistor is configured to control the size of the driving current flowing through the light-emitting device according to the data signal, the driving transistor includes an active pattern and a gate, the active pattern includes a channel region, the orthographic projection of the channel region on the base substrate is located to overlap with the orthographic projection of the gate on the base substrate; the planar shape of the channel region of the driving transistor is a strip extending along the second direction as a whole; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. In the display substrate provided by the embodiment of the present disclosure, the channel region of the driving transistor is in the shape of a strip extending along the second direction as a whole, which increases the aspect ratio of the channel region of the driving transistor and helps to save the layout space of the pixel circuit.

[0089] At least one embodiment of the present disclosure provides a display substrate, which includes a substrate substrate, a first signal line and a second signal line arranged on the substrate substrate, and a sub-pixel. The sub-pixel includes a pixel circuit, and the pixel circuit includes: a light-emitting device, a driving transistor, a data writing transistor and a storage capacitor. The data writing transistor is configured to transmit a data signal to the driving transistor under the control of a first scanning signal, the first scanning signal is transmitted on the first signal line, and the data signal is transmitted on the second signal line; the driving transistor is configured to control the size of the driving current flowing through the light-emitting device according to the data signal, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; the driving transistor includes an active pattern and a gate, and the active pattern of the driving transistor includes a channel region, and the positive projection of the channel region on the substrate substrate is located at least partially overlapped with the positive projection of the gate on the substrate substrate; the storage capacitor includes: a first electrode plate and a second electrode plate. The first electrode plate is electrically connected to the gate of the driving transistor; the positive projection of the second electrode plate on the substrate substrate overlaps at least partially with the positive projection of the first electrode plate on the substrate substrate, and does not overlap with the positive projection of the channel region of the driving transistor on the substrate substrate. In the display panel provided in the embodiment of the present disclosure, since the second electrode plate is connected to the first power supply voltage for voltage stabilization, the first power supply voltage signal will affect the channel region of the driving transistor. In order to reduce its influence on the channel region of the driving transistor, the second electrode plate is avoided from the channel region of the driving transistor to avoid affecting the performance of the driving transistor.

[0090] For example, Figure 1 Schematic diagram of a display substrate provided by at least one embodiment of the present disclosure. Figure 1 As shown, for example, the display substrate 10 includes a plurality of pixels 100 arranged in an array, at least some of the plurality of pixels 100 include a plurality of sub-pixels, and at least some of the plurality of sub-pixels include a light-emitting device and a pixel circuit that drives the light-emitting device to emit light. For example, the pixel circuit may include a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, or nTmC (n, m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit may further include a compensation subcircuit, the compensation subcircuit includes an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include a transistor, a capacitor, etc. For example, as needed, the pixel circuit may further include a reset circuit, a light-emitting control subcircuit, a detection circuit, etc.

[0091] For example, Figure 1As shown, a plurality of pixels 100 are located in the display area. For example, in the display substrate 10 provided in some embodiments, some of the plurality of pixels 100 are dummy pixels 1000, which do not participate in the display work, and each dummy pixel 1000 includes a plurality of dummy sub-pixels, but does not include a sub-pixel that plays a display driving role.

[0092] For example, the display substrate 10 is an organic light emitting diode (OLED) display substrate, and the light emitting device is an OLED. The display substrate 10 may also include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels. As required, the display substrate 10 may further include power lines, detection lines, etc.

[0093] Figure 2A Schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure. Figure 2A As shown, the pixel circuit unit 100 includes a driving subcircuit 122, a compensation subcircuit 128, a data writing subcircuit 126, a storage subcircuit 127, a first light-emitting control subcircuit 123, a second light-emitting control subcircuit 124, a first reset subcircuit 125 and a second reset subcircuit 129.

[0094] For example, the driving sub-circuit 122 includes a control terminal 122a, a first terminal 122b, and a second terminal 122c, and is configured to be connected to the light emitting device 121 and control a driving current flowing through the light emitting device 121. The control terminal 122a of the driving sub-circuit 122 is connected to the first node N1, the first terminal 122b of the driving sub-circuit 122 is connected to the second node N2 and is configured to receive the first power supply voltage VDD, and the second terminal 122c of the driving sub-circuit 122 is connected to the third node N3.

[0095] For example, the data writing subcircuit 126 includes a control terminal 126a, a first terminal 126b, and a second terminal 126c, wherein the control terminal 126a is configured to receive a first scanning signal Ga1, the first terminal 126b is configured to receive a data signal Vd, and the second terminal 126c is connected to a first terminal 122b (i.e., a second node N2) of the driving subcircuit 122. The data writing subcircuit 126 is configured to write the data signal Vd into the first terminal 122b of the driving subcircuit 122 in response to the first scanning signal Ga1. For example, the first terminal 126b of the data writing subcircuit 126 is connected to the data line 12 to receive the data signal Vd, and the control terminal 126a is connected to the gate line 11 as a scanning line to receive the first scanning signal Ga1. For example, in the data writing and compensation stage, the data writing sub-circuit 126 can be turned on in response to the first scanning signal Ga1, so that the data signal can be written to the first end 122b (the second node N2) of the driving sub-circuit 122, and the data signal can be stored in the storage sub-circuit 127, so that a driving current can be generated according to the data signal to drive the light-emitting device 121 to emit light, for example, in the light-emitting stage.

[0096] For example, the compensation sub-circuit 128 includes a control terminal 128a, a first terminal 128b and a second terminal 128c. The control terminal 128a of the compensation sub-circuit 128 is configured to receive a second scanning signal Ga2. The first terminal 128b and the second terminal 128c of the compensation sub-circuit 128 are electrically connected to the second terminal 122c and the control terminal 122a of the driving sub-circuit 122, respectively. The compensation sub-circuit 128 is configured to perform threshold compensation on the driving sub-circuit 122 in response to the second scanning signal Ga2.

[0097] For example, the first scan signal Ga1 may be the same as the second scan signal Ga2. For example, the first scan signal Ga1 may be connected to the same signal output terminal as the second scan signal Ga2. For example, the first scan signal Ga1 may be transmitted through the same scan line as the second scan signal Ga2.

[0098] In some other examples, the first scanning signal Ga1 may be different from the second scanning signal Ga2. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be connected to different signal output terminals. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be transmitted through different scanning lines.

[0099] For example, the storage sub-circuit 127 includes a first terminal 127a and a second terminal 127b. The first terminal 127a of the storage sub-circuit is configured to receive the first power supply voltage VDD, and the second terminal 127b of the storage sub-circuit is electrically connected to the control terminal 122a of the driving sub-circuit.

[0100] For example, the storage subcircuit 127 is electrically connected to the control terminal 122a and the first voltage terminal vdd of the driving subcircuit 122, and is configured to store the data signal written by the data writing subcircuit 126. For example, in the data writing and compensation stage, the compensation subcircuit 128 can be turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing subcircuit 126 can be stored in the storage subcircuit 127. For example, in the data writing and compensation stage, the compensation subcircuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving subcircuit 122, so that the relevant information of the threshold voltage of the driving subcircuit 122 can also be correspondingly stored in the storage subcircuit, so that, for example, in the light emitting stage, the stored data signal and the threshold voltage can be used to control the driving subcircuit 122, so that the output of the driving subcircuit 122 is compensated.

[0101] For example, the first light emitting control subcircuit 123 is connected to the first terminal 122b (the second node N2) and the first voltage terminal vdd of the driving subcircuit 122, and is configured to apply the first power supply voltage VDD of the first voltage terminal vdd to the first terminal 122b of the driving subcircuit 122 in response to the first light emitting control signal EM1. Figure 2A As shown, the first light emitting control sub-circuit 123 is connected to the first light emitting control terminal EM1, the first voltage terminal vdd and the second node N2.

[0102] For example, the second light emitting control subcircuit 124 is connected to the second light emitting control terminal EM2, the first terminal 134 of the light emitting device 121 and the second terminal 122c of the driving subcircuit 122, and is configured to respond to the second light emitting control signal so that the driving current can be applied to the light emitting device 121.

[0103] For example, in the light-emitting stage, the second light-emitting control subcircuit 124 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving subcircuit 122 can be electrically connected to the light-emitting device 121 through the second light-emitting control subcircuit 124, thereby driving the light-emitting device 121 to emit light under the control of the driving current; while in the non-light-emitting stage, the second light-emitting control subcircuit 124 is turned off in response to the second light-emitting control signal EM2, thereby avoiding current flowing through the light-emitting device 121 to cause it to emit light, which can improve the contrast of the corresponding display device.

[0104] For another example, in the initialization phase, the second light emitting control sub-circuit 124 may also be turned on in response to the second light emitting control signal EM2 , so that the reset sub-circuit may be combined to perform a reset operation on the driving sub-circuit 122 and the light emitting device 121 .

[0105] For example, the second light emitting control signal EM2 may be the same as the first light emitting control signal EM1, for example, the second light emitting control signal EM2 may be connected to the same signal output terminal as the first light emitting control signal EM1, for example, the second light emitting control signal EM2 may be transmitted through the same light emitting control line as the first light emitting control signal EM1.

[0106] In some other examples, the second light emitting control signal EM2 may be different from the first light emitting control signal EM1. For example, the second light emitting control signal EM2 and the first light emitting control signal EM1 may be connected to different signal output terminals, respectively. For example, the second light emitting control signal EM2 and the first light emitting control signal EM1 may be transmitted through different light emitting control lines, respectively.

[0107] For example, the first reset subcircuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (first node N1) of the driving subcircuit 122, and is configured to apply the first reset voltage Vinit1 to the control terminal 122a of the driving subcircuit 122 in response to the first reset control signal Rst1.

[0108] For example, the second reset subcircuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 134 (fourth node N4) of the light emitting device 121, and is configured to apply the second reset voltage Vinit2 to the first terminal 134 of the light emitting device 121 in response to the second reset control signal Rst2.

[0109] For example, the first reset sub-circuit 125 and the second reset sub-circuit 129 can be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, so that the second reset voltage Vinit2 can be applied to the first node N1 and the first reset voltage Vinit1 can be applied to the first end 134 of the light-emitting device 121, respectively, so that the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting device 121 can be reset to eliminate the influence of the previous light-emitting stage.

[0110] For example, the second reset control signal Rst2 of each row of sub-pixels may be the same signal as the first scan signal Ga1 of the row of sub-pixels, and the two may be connected through the same gate line (eg Figure 3A For example, the first reset control signal Rst1 of each row of sub-pixels can be transmitted through the same gate line (eg, Figure 3A The reset control line 220a) is transmitted.

[0111] For example, Figure 2AThe light emitting device 121 includes a first terminal 134 and a second terminal 135. The first terminal 134 of the light emitting device 121 is configured to be connected to the second terminal 122c of the driving sub-circuit 122, and the second terminal 135 of the light emitting device 121 is configured to be connected to the second voltage terminal VSS. For example, in one example, Figure 2A As shown, the first terminal 134 of the light emitting device 121 may be connected to the fourth node N4 through the second light emitting control sub-circuit 124. The embodiments of the present disclosure include but are not limited to this case.

[0112] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual existing components, but represent the junction points of related circuit connections in the circuit diagram.

[0113] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd can represent both the data signal terminal and the level of the data signal. Similarly, the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal, and can also represent the first scan signal terminal and the second scan signal terminal. The symbol Rst1 can represent both the first reset control terminal and the first reset control signal. The symbol Rst2 can represent both the second reset control terminal and the second reset control signal. The symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage terminal and can also represent the first reset voltage and the second reset voltage. The symbol VDD can represent both the first power supply voltage and the first power supply line. The symbol VSS can represent both the common power supply voltage and the common power supply line. The following embodiments are the same as this and will not be repeated.

[0114] Figure 2B for Figure 2A A circuit diagram of a specific implementation example of a pixel circuit is shown. Figure 2B As shown, the pixel circuit includes first to seventh transistors T1, T2, T3, T4, T5, T6, T7 and a storage capacitor Cst. For example, the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.

[0115] For example, Figure 2B As shown, the driving subcircuit 122 can be implemented as a first transistor T1. The gate of the first transistor T1 serves as a control terminal 122a of the driving subcircuit 122 and is connected to the first node N1; the first electrode of the first transistor T1 serves as a first terminal 122b of the driving subcircuit 122 and is connected to the second node N2; the second electrode of the first transistor T1 serves as a second terminal 122c of the driving subcircuit 122 and is connected to the third node N3.

[0116] For example, Figure 2BAs shown, the data writing subcircuit 126 can be implemented as a second transistor T2. The gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first electrode of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second electrode of the second transistor T2 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122.

[0117] For example, Figure 2B As shown, the compensation subcircuit 128 can be implemented as a third transistor T3. The gate, the first electrode, and the second electrode of the third transistor T3 serve as the control terminal 128a, the first terminal 128b, and the second terminal 128c of the compensation subcircuit, respectively. The gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, the first electrode T3s of the third transistor T3 is connected to the second electrode T1d (the third node N3) of the first transistor T1, and the second electrode T3d of the third transistor T3 is electrically connected to the gate T1g (the first node N1) of the first transistor T1. For example, Figure 2B As shown, the storage subcircuit 127 can be implemented as a storage capacitor Cst, which includes a first plate Cst1 and a second plate Cst2. The first plate Cst2 is electrically connected to the first voltage terminal vdd, and the second plate Cst1 is electrically connected to the gate T1g (first node N1) of the first transistor T1.

[0118] For example, Figure 2B As shown, the first light-emitting control subcircuit 123 can be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is connected to the first light-emitting control line (first light-emitting control terminal EM1) to receive the first light-emitting control signal, the first electrode of the fourth transistor T4 is connected to the first voltage terminal vdd to receive the first power supply voltage, and the second electrode of the fourth transistor T4 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122.

[0119] For example, the light emitting device 121 is specifically implemented as a light emitting diode (LED), for example, an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED) or an inorganic light emitting diode, for example, a micro light emitting diode (Micro LED) or a micro OLED. For example, the light emitting device 121 can be a top emission structure, a bottom emission structure or a double-sided emission structure. The light emitting device 121 can emit red light, green light, blue light or white light, etc. The embodiments of the present disclosure do not limit the specific structure of the light emitting device.

[0120] For example, the first end of the light emitting device 121 includes a first electrode (for example, an anode), which is connected to the fourth node N4 and configured to be connected to the second end 122c of the driving subcircuit 122 through the second light emitting control subcircuit 124. The second end of the light emitting device 121 includes a second electrode (for example, a cathode), which is configured to be connected to the common power supply voltage terminal VSS to receive the common power supply voltage VSS. The circuit that flows from the second end 122c of the driving subcircuit 122 into the light emitting device 121 determines the brightness of the light emitting device. For example, the common power supply voltage terminal VSS can be grounded, that is, VSS can be 0V. For example, the common power supply voltage VSS can be a negative voltage.

[0121] For example, the second light emitting control subcircuit 124 can be implemented as a fifth transistor T5. The gate of the fifth transistor T5 is connected to the second light emitting control line (the second light emitting control terminal EM2) to receive the second light emitting control signal, the first electrode of the fifth transistor T5 is connected to the second terminal 122c (the third node N3) of the driving subcircuit 122, and the second electrode of the fifth transistor T5 is connected to the first terminal 134 (the fourth node N4) of the light emitting device 121.

[0122] For example, the first reset subcircuit 125 can be implemented as a sixth transistor T6, and the second reset subcircuit can be implemented as a seventh transistor T7. The gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, the first electrode of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1, and the second electrode of the sixth transistor T6 is configured to be connected to the first node N1. The gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, the first electrode of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2, and the second electrode of the seventh transistor T7 is configured to be connected to the fourth node N4.

[0123] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as examples. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0124] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages). For example, Figure 2B As shown, the first to seventh transistors T1-T7 are all P-type transistors, such as low temperature polysilicon thin film transistors. However, the disclosed embodiment does not limit the type of transistors, and when the type of transistors changes, the connection relationship in the circuit can be adjusted accordingly.

[0125] The following combination Figure 2C The signal timing diagram shown is Figure 2B The working principle of the pixel circuit shown in FIG. Figure 2C As shown, the display process of each frame of image includes three stages, namely initialization stage 1, data writing and compensation stage 2, and light emitting stage 3.

[0126] like Figure 2C As shown, in this embodiment, the first scanning signal Ga1 and the second scanning signal Ga2 use the same signal, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 use the same signal; and the second reset control signal Rst2 and the first scanning signal Ga1 / the second scanning signal Ga2 have the same waveform, that is, the second reset control signal Rst2 and the first scanning signal Ga1 / the second scanning signal Ga2 can use the same signal; the first reset signal Rst1 of the sub-pixel in this row has the same waveform as the first scanning signal Ga1 / the second scanning signal Ga2 of the sub-pixel in the previous row, that is, the same signal is used. However, this is not a limitation to the present disclosure, and in other embodiments, different signals can be used as the first scanning signal Ga1, the second scanning signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, and different signals can be used as the first light-emitting control signal EM1 and the second light-emitting control signal EM2.

[0127] In the initialization phase 1, the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.

[0128] In the data writing and compensation stage 2, the first scanning signal Ga1, the second scanning signal Ga2 and the data signal Vd are input, the second transistor T2 and the third transistor T3 are turned on, the data signal Vd is written into the second node N2 by the second transistor T2, and the first node N1 is charged through the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd+Vth, and the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1. The potential of the first node N1 is stored in the storage capacitor Cst and maintained, that is, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, so as to provide grayscale display data and compensate the threshold voltage of the first transistor T1 itself in the subsequent light-emitting stage.

[0129] In the data writing compensation phase 2, the second reset control signal Rst2 may be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 may be applied to the fourth node N4, thereby resetting the fourth node N4. For example, the fourth node N4 may also be reset in the initialization phase 1, for example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same. The embodiments of the present disclosure are not limited to this.

[0130] In the light emitting stage 3, the first light emitting control signal EM1 and the second light emitting control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5 and the first transistor T1, and the fifth transistor T5 applies the driving current to the OLED to make it emit light. The value of the driving current Id flowing through the OLED can be obtained according to the following formula:

[0131] Id=K(VGS-Vth)2=K[(Vd+Vth-VDD)-Vth]2=K(Vd-VDD)2, wherein K is the conductivity of the first transistor.

[0132] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate and the source (here, the first electrode) of the first transistor T1, and K is a constant value related to the first transistor T1 itself. It can be seen from the above calculation formula of Id that the driving current Id flowing through the OLED is no longer related to the threshold voltage Vth of the first transistor T1, thereby achieving compensation for the pixel circuit, solving the problem of threshold voltage drift caused by the process and long-term operation of the driving transistor (the first transistor T1 in the embodiment of the present disclosure), eliminating its influence on the driving current Id, and thus improving the display effect of the display device using it.

[0133] Figure 3A A schematic diagram of the structure of a sub-pixel of a display substrate provided in one embodiment of the present disclosure is shown in FIG. Figure 3B-3I for Figure 3A A schematic diagram of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a first electrode of a display substrate shown in FIG. Figure 4A For along Figure 3A A cross-sectional view of the line A-A' in FIG. Figure 4B For along Figure 3A A cross-sectional view of the line B-B' in FIG. Figure 4C For along Figure 3A A cross-sectional view of the line C-C' in FIG. Figure 4D For along Figure 3A A cross-sectional view of the line D-D' in FIG. Figure 4E For along Figure 3A A cross-sectional view of the line E-E' in FIG. Figure 4F A schematic plan view of a channel region of another driving transistor of a display substrate provided in at least one embodiment of the present disclosure, Figure 4G for Figure 3A A partial enlarged schematic diagram of a sub-pixel in Figure 2B As an example, the pixel circuit shown in FIG. Figure 3B-3I and Figures 4A-4G The structure of a display substrate provided in at least one embodiment of the present disclosure is exemplarily described.

[0134] Combination Figure 3A , Figure 4B and Figure 4G, the display substrate 10 includes a base substrate 200, a first signal line extending along a first direction D1 as a whole on the base substrate 200, and a second signal line extending along a second direction D2 intersecting the first direction D1 as a whole; for example, the first signal line intersects with the second signal line to define a sub-pixel, for example, to define a plurality of sub-pixels. It should be noted that the boundary of each of the plurality of sub-pixels is not necessarily the first signal line and the second signal line, and the intersection of the first signal line and the second signal line to define the sub-pixel means that the arrangement of the plurality of sub-pixels is consistent with the arrangement of the plurality of regions defined by the intersection of the first signal line and the second signal line, that is, the plurality of sub-pixels correspond to the region one by one. For example, the first signal line is a gate line as a scanning signal line, and the second signal line is a data line; or, in some other embodiments, the first signal line is a data line, and the second signal line is a gate line as a scanning signal line. Each of at least some of the plurality of sub-pixels includes a pixel circuit 101, and the pixel circuit 101 includes the above-mentioned light-emitting device and a driving transistor T1 and a data writing transistor T2. For example, at least some of the sub-pixels are sub-pixels that perform display functions, not dummy sub-pixels. The data writing transistor T2 is configured to transmit the data signal Vd to the driving transistor T1 under the control of the first scanning signal Ga1, the first scanning signal Ga1 is transmitted on the first signal line, and the data signal Vd is transmitted on the second signal line; the driving transistor T1 is configured to control the magnitude of the driving current flowing through the light-emitting device 121 according to the data signal Vd, and the driving transistor T1 includes an active pattern T1a and a gate T1g, and the active pattern T1a includes a channel region C1( Figure 3A The dotted box in the plan view and Figure 4A As shown), the positive projection of the channel region C1 on the substrate 200 overlaps with the positive projection of the gate T1g on the substrate 200; the planar shape of the channel region C1 of the driving transistor T1 is a bar extending along the second direction D2 as a whole; the light emitting device is configured to receive a driving current and be driven by the driving current to emit light. In the display substrate 10 provided in the embodiment of the present disclosure, the planar shape of the channel region C1 of the driving transistor T1 is a bar extending along the second direction D2 as a whole. This feature can increase the length of the channel region of the driving transistor (the length along the second direction D2), thereby increasing the aspect ratio of the channel region of the driving transistor to ensure that in the black state, the leakage of the driving transistor T1 will be small and the driving will be stable; the longer the length of the channel region of the driving transistor T1, the closer the output curve of the driving transistor T1 is to the ideal linear situation in the saturation region, so that the display substrate, such as the OLED display substrate, works in the saturation region of the driving transistor T1, so that the brightness of the display panel using the display substrate is better controlled by the driving transistor T1; and this feature is conducive to saving the layout space of the pixel circuit. The channel region C1 is different from the existing X-shaped channel, S-shaped channel, etc. with obvious bends extending along the first direction D1.

[0135] It should be noted that the “strip extending along the second direction D2 as a whole” includes extending substantially along the second direction D2, or at least along the second direction D2 as a whole. For example, in some examples, the strip extending along the second direction D2 as a whole may have a certain curved portion, such as Figure 4F Alternatively, in some examples, the edge of the strip extending along the second direction D2 may not be a smooth line, for example, its edge may have burrs or saw teeth. In short, it is sufficient to satisfy the requirement of being a strip extending along the second direction D2.

[0136] For example, Figure 3A and Figure 3B As shown, the planar shape of the channel region C1 of the driving transistor T1 is a straight bar extending along the second direction D2, so as to better increase the aspect ratio of the channel region C1 of the driving transistor T1, and make the planar shape of the channel region C1 of the driving transistor T1 more regular, thereby facilitating manufacturing and better saving the layout space of the pixel circuit.

[0137] Combination Figure 3B-3G and Figures 4A-4D It can be seen that the display substrate 10 includes a semiconductor layer 107, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, a second conductive layer 202, a third insulating layer 303, a third conductive layer 203, a fourth insulating layer 304 and a fourth conductive layer 204 which are sequentially arranged on a base substrate 200.

[0138] For example, Figure 3B As shown, the semiconductor layer 107 includes active patterns T1a-T7a of first to seventh transistors T1-T7, wherein. Figure 3B As shown, the active patterns T1a-T7a of the first to seventh transistors T1-T7 are connected to each other as an integrated structure. For example, the semiconductor layers 107 in each column of sub-pixels are connected to each other as an integrated structure, and the semiconductor layers in two adjacent columns of sub-pixels are spaced apart from each other.

[0139] For example, Figure 3C-3D As shown, the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines. Figure 3A The area where the pixel circuit of each sub-pixel is located is shown by a large dotted box. Figure 3D 1 and 2 , gates T1g to T7g of the first to seventh transistors T1 to T7 in one pixel circuit unit 100 are shown by small dotted line boxes.

[0140] For example, Figure 3C-3DAs shown, the first conductive layer 201 includes gate electrodes T1g-T7g of the first to seventh transistors T1-T7. For example, the display substrate 10 adopts a self-alignment process, and uses the first conductive layer 201 as a mask to perform a conductorization process (e.g., a doping process) on the semiconductor layer 107, so that the portion of the semiconductor layer 107 not covered by the first conductive layer 201 is conductorized, so that the portion of the active pattern of each transistor located on both sides of the channel region is conductorized to form the first electrode and the second electrode of the transistor respectively.

[0141] For example, the first conductive layer 201 further includes a plurality of gate lines insulated from each other, the gate lines for example including a plurality of scan lines 210, a plurality of reset control lines 220a / 220b and a plurality of light emitting control lines 230. Here, the gate line refers to a signal line directly connected to the gate of the transistor to provide a scan signal or a control signal. For example, each row of sub-pixels is respectively connected to a scan line 210, two reset control lines and a light emitting control line 230, the two reset control lines being a first reset control line 220a and a second reset control line 220b.

[0142] For example, Figure 3A and Figure 3D As shown, the gate T6g of the sixth transistor T6 of the pixel circuit of this row is electrically connected to the first reset control line 220a corresponding to the row to receive the first reset control signal Rst1. The gate of the seventh transistor T7 of the pixel circuit of this row is electrically connected to the second reset control line 220b corresponding to the pixel circuit of the next row (i.e., the pixel circuit row where the scan line that is sequentially turned on after the scan line of this row is located according to the scan order of the scan lines) to receive the second reset control signal Rst2.

[0143] The scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or is an integrated structure) to provide a first scan signal Ga1, a reset control line 220 is electrically connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset control signal Rst1, and the light-emitting control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide a first light-emitting control signal EM1.

[0144] For example, Figure 3AAs shown, the scan line 210 is also electrically connected to the gate T3g1 / T3g2 of the third transistor T3 to provide the second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 can be the same signal; a part of the scan line 210 constitutes the first gate T3g1 and the second gate T3g2 of the third transistor T3. The light-emitting control line 230 is also electrically connected to the gate T5g of the fifth transistor T5 to provide the second light-emitting control signal EM2, that is, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are the same signal; a part of the light-emitting control line 230 constitutes the gate T5g of the fifth transistor T5.

[0145] For example, combined with Figure 3A and Figure 4B , the pixel circuit 101 further includes a storage capacitor Cst, and the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2. The first plate Cst1 is electrically connected to the gate T1g of the driving transistor T1; the orthographic projection of the second plate Cst2 on the substrate substrate 200 at least partially overlaps with the orthographic projection of the first plate Cst1 on the substrate substrate 200, and does not overlap with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate substrate 200. Since the second plate Cst2 is connected to the first power supply voltage VDD for voltage stabilization, the first power supply voltage signal will affect the channel region C1 of the driving transistor T1. In order to reduce its influence on the channel region C1 of the driving transistor T1, the second plate Cst2 is avoided from the channel region C1 of the driving transistor T1 to avoid affecting the performance of the driving transistor.

[0146] For example, the first electrode plate Cst1 includes a first portion Cst11 and a second portion Cst12. The first portion Cst11 of the first electrode plate Cst1 extends along the second direction D2, for example, the plane figure of the first electrode plate Cst1 is L-shaped; and the orthographic projection of the first portion Cst11 of the first electrode plate Cst1 on the substrate 200 overlaps with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200; the second portion Cst12 of the first electrode plate Cst1 is connected to the first portion Cst11, and extends from the first portion Cst11 of the first electrode plate Cst1 along the first direction D1 and protrudes from the first portion Cst11 of the first electrode plate Cst1, and the orthographic projection of the second portion Cst12 of the first electrode plate Cst1 on the substrate 200 overlaps with the orthographic projection of the second electrode plate Cst2 on the substrate 200 at least partially.

[0147] For example, Figure 4BAs shown, the first electrode plate Cst1 and the gate T1g of the driving transistor T1 are arranged in the same layer and have an integral structure, for example, both are located in the first conductive layer 201, so as to simplify the structure of the display substrate 10, and the first electrode plate Cst1 and the gate T1g of the driving transistor T1 can be formed by performing the same patterning process on the same film layer through the same mask, thereby simplifying the manufacturing process of the display substrate 10. At this time, the first part Cst11 of the first electrode plate Cst1 is the first part T1ga of the gate of the driving transistor T1, and the second part Cst12 is the second part T1gb of the gate of the driving transistor T1.

[0148] It should be noted that the "same-layer arrangement" referred to in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same composition process, and their materials may be the same or different. The "integrated structure" in the present disclosure refers to a structure in which the two (or more) structures are connected to each other by the same film layer being patterned by the same composition process, and their materials may be the same or different.

[0149] For example, combined with Figure 3A and Figure 4A , the pixel circuit further includes a first connection structure P1, the first connection structure P1 is electrically connected to the gate T1g of the driving transistor T1 and the first electrode Cst1, and the orthographic projection of the first connection structure on the base substrate 200 does not overlap with the orthographic projection of the second electrode Cst2 on the base substrate 200. For example, the second electrode Cst2 is located on the second conductive layer 202, the second conductive layer 202 is located on the side of the first conductive layer 201 away from the base substrate 200, and a second insulating layer 302 exists between the second conductive layer 202 and the first conductive layer 201. In this way, the first connection structure P1 needs to be electrically connected to the first electrode Cst1 through a via, and the first connection structure P1 will not pass through the second electrode Cst2 of the storage capacitor Cst, thereby increasing the area of ​​the second electrode Cst2 to increase the capacitance of the storage capacitor.

[0150] For example, Figure 3A , Figure 3G and Figure 4A As shown, the first connection structure P1 is arranged in the same layer as the first electrode T1s of the driving transistor T1, and is electrically connected to the first electrode plate Cst1 (i.e., the gate T1g of the driving transistor T1) through the first via hole V1; the orthographic projection of the first via hole V1 on the base substrate 200 overlaps with the orthographic projection of the second part Cst12 of the first electrode plate Cst1 on the base substrate 200, and does not overlap with the orthographic projection of the second electrode plate Cst2 on the base substrate 200. Therefore, the first via hole V1 will not pass through the second electrode plate Cst2 of the storage capacitor Cst, thereby increasing the area of ​​the second electrode plate Cst2 to increase the capacitance of the storage capacitor.

[0151] For example, Figure 3A and Figure 4A The orthographic projection of the first connection structure P1 on the base substrate 200 does not overlap with the orthographic projection of the channel region C1 of the driving transistor T1 on the base substrate 200. The orthographic projection of the first connection structure P1 on the base substrate 200 at least partially overlaps with the orthographic projection of the second portion of the first electrode plate Cst1 on the base substrate 200 to avoid the electrical signal on the first connection structure P1 from affecting the channel region C1 of the driving transistor T1.

[0152] For example, in Figure 3A In the illustrated embodiment, the first connection structure P1 is a straight bar extending along the second direction D2, which is conducive to saving space and arranging other structures of the pixel circuit while rationally utilizing limited space. This is very important for the pixel design of the display substrate and can solve the important technical problem of how to effectively improve the PPI.

[0153] For example, Figure 3A , Figure 3G and Figure 4B As shown, the pixel circuit also includes a first power line VDD, which is connected to the first voltage terminal and configured to provide a first power supply voltage to the pixel circuit, and is arranged in the same layer as the first electrode T1s of the driving transistor T1, for example, both are located in the third conductive layer 203. And includes a first vertical portion VDD1 and a first horizontal portion VDD2. The first vertical portion VDD1 extends along the second direction D2 and is connected to the adjacent sub-pixel; the first horizontal portion VDD2 is connected to the vertical portion and extends from the vertical portion toward the second electrode plate Cst2; the first horizontal portion VDD2 is electrically connected to the second electrode plate Cst2 through the second via hole V2.

[0154] For example, the orthographic projection of one end of the first transverse portion VDD2 away from the first vertical portion VDD1 on the base substrate does not exceed the orthographic projection of the second electrode plate Cst2 on the base substrate in the first direction D1.

[0155] For example, in Figure 3A In the illustrated embodiment, the first power line VDD and the data line Data are located on the same side of the storage capacitor Cst; in other embodiments, the first power line VDD and the data line Data may be located on different sides of the storage capacitor Cst.

[0156] For example, in Figure 3AIn the illustrated embodiment, the first power line VDD and the data line Data are located in the same layer, both located in the third metal layer 203; in other embodiments, the first power line VDD and the data line Data may be located in different layers. For example, in at least one embodiment, the display substrate further includes a fourth metal layer located in the third metal layer 203 and away from the base substrate 200. For example, the first power line VDD is located in the third metal layer 203, and the data line Data is located in the fourth metal layer; or, the first power line VDD is located in the fourth metal layer, and the data line Data is located in the third metal layer 203.

[0157] For example, Figure 3A , Figure 3C and Figure 4G As shown, the first portion Cst11 of the first electrode Cst1 has a first end in the second direction D2, and the first end and the second portion Cst12 of the first electrode Cst1 form a blank gap H ( Figure 4G The first signal line, i.e., the scanning line 210, which provides the first scanning signal to the data writing transistor, i.e., the second transistor T2, is in the same layer as the first electrode plate Cst1 and is arranged at intervals, and the scanning line 210 includes a main body 2101 and a protrusion 2102. The main body 2101 passes through the sub-pixel along the first direction D1, i.e., extends along the first direction D1 and connects from one sub-pixel to an adjacent sub-pixel, and the main body 2101 is located on the first side of the first electrode plate Cst1 in the second direction D2; the protrusion 2102 is connected to the main body 2101 and protrudes from the main body 2101 toward the first electrode plate Cst1, and the protrusion 2102 is at least partially located in the notch H. This design makes the arrangement compact and makes reasonable use of limited space.

[0158] For example, a portion of the main body 2101 of the scan line 210 constitutes the first gate T3g1 of the third transistor T3, and the protruding portion 2102 of the scan line 210 constitutes the second gate T3g2.

[0159] For example, the pixel circuit further includes a compensation transistor, namely a third transistor T3, which is configured to compensate the gate T1g of the driving transistor T1 in response to the second scanning signal Ga2 and the data signal Vd applied to the gate T3g of the compensation transistor T3. Figure 3AAs shown, the first signal line 210, i.e., the scanning line 210, which provides the first scanning signal Ga1 to the data writing transistor T2, is also configured to provide the second scanning signal Ga2 to the compensation transistor T3. The compensation transistor T3 includes a first gate T3g1 and a second gate T3g2; at least part of the protrusion 2102 of the scanning line 210 constitutes the first gate T3g1 of the compensation transistor, and part of the main body 2101 of the scanning line 210 constitutes the second gate T3g2 of the compensation transistor T3 and the gate T2g of the data writing transistor T2. The first gate T3g1 extends along the first direction D1, and the second gate T3g2 extends along the second direction D2.

[0160] For example, Figure 3B As shown, the compensation transistor T3 includes an active pattern T3a, and the active pattern T3a of the compensation transistor T3 is disposed on the same layer as the active pattern T1a of the driving transistor T1. Figure 4C As shown, the sub-pixel further includes a shielding portion 31, which is located on a side of the active pattern T3a of the compensation transistor T3 away from the substrate 200, and the orthographic projection of the shielding portion 31 on the substrate 200 at least partially overlaps with the orthographic projection of the active pattern T3a of the compensation transistor T3 on the substrate 200, and the shielding portion 31 is electrically connected to the first connection structure P1. Thus, the shielding portion 31 shields the active pattern T3a of the compensation transistor T3, for example, shields the channel region of the compensation transistor T3, to prevent light from affecting the performance of the channel region of the compensation transistor T3, and the shielding portion 31 is connected to the first connection structure P1, that is, Figure 2B It should be noted that the active pattern T3a shielded by the shielding portion 31 is the conductive portion around the channel region of the compensation transistor T3, but does not include the channel region of the compensation transistor T3.

[0161] For example, Figure 4B and Figure 4C As shown, the shielding portion 31 and the second electrode Cst2 are arranged in the same layer, for example, both are located in the second metal layer 202, so that the two can be formed by performing a composition process on the same film layer using the same mask, simplifying the structure and manufacturing process of the display substrate. For example, the orthographic projection of the first connection structure P1 on the base substrate 200 overlaps with the orthographic projection of the shielding portion 31 on the base substrate 200 at least partially, and the first connection structure P1 is electrically connected to the shielding portion 31 through the third via V3, so as to realize the electrical connection between the first connection structure P1 and the shielding portion 31.

[0162] For example, the pixel circuit 101 further includes a reset transistor, for example, a first reset transistor, namely a sixth transistor T6, and a second reset transistor, namely a seventh transistor T7; Figure 3A and Figure 3EAs shown, the pixel circuit further includes a reset voltage line 240, and the reset voltage line 240 is in the same layer as the second electrode plate Cst2, for example, both are located in the second conductive layer 202; and Figure 4D As shown, the reset voltage line 240 is electrically connected to the first electrode T6s of the first reset transistor T6 to provide the first reset voltage Vinit1 to the first reset transistor T6.

[0163] For example, Figure 3A and Figure 3E As shown, the second conductive layer 202 includes a plurality of reset voltage lines 240 extending along the first direction D1, and the plurality of reset voltage lines 240 are connected one-to-one with a plurality of rows of sub-pixels. The reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in the corresponding row of sub-pixels to provide the first reset voltage Vinit1 for the sixth transistor T6 in the row of sub-pixels, and the first electrode T7s of the seventh transistor T7 in the row of sub-pixels is electrically connected to the reset voltage line 240 corresponding to the next row of sub-pixels to receive the second reset voltage Vinit2.

[0164] For example, Figure 3A , Figure 3G and Figure 4D As shown, the pixel circuit 101 further includes a second connection structure P2, and the reset voltage line 240 is electrically connected to the first electrode T6s of the first reset transistor T6 through the second connection structure P2. For example, the second connection structure P2 is in the same layer as the first connection structure P1, and the first end of the second connection structure P2 is electrically connected to the reset voltage line 240 through the fourth via hole V4, and the second end of the second connection structure P2 opposite to the first end is electrically connected to the first electrode T6s of the first reset transistor T6 through the fifth via hole V5.

[0165] For example, Figure 3A and Figure 4E As shown, the orthographic projection of the first power line VDD on the substrate 200 overlaps with the orthographic projection of the channel region C1 of the driving transistor T1 on the substrate 200, so that the first power line VDD blocks the channel region C1 of the driving transistor T1, so as to save layout space and utilize the existing structure to prevent the influence of light on the performance of the channel region C1 of the driving transistor T1.

[0166] For example, Figure 4CAs shown, the light-emitting device 121 of the sub-pixel includes a first electrode 40, a second electrode (not shown in the figure), and a light-emitting layer (not shown in the figure) located between the first electrode 40 and the second electrode; the sub-pixel also includes a pixel defining layer 306 located on the side of the first electrode 40 of the light-emitting device away from the base substrate 200, and an opening is formed in the pixel defining layer 306 to expose at least part of the first electrode 40 so as to define the opening area (i.e., the light-emitting area) 600 of each sub-pixel of the display substrate. The light-emitting layer of the light-emitting device is at least formed in the opening area 600 (the light-emitting layer can also cover part of the surface of the pixel defining layer away from the first electrode), and the second electrode is formed on the light-emitting layer to form the light-emitting device. For example, the second electrode is a common electrode, which is arranged in the display substrate 10 on the whole surface. For example, the first electrode 40 is the anode of the light-emitting device, and the second electrode is the cathode of the light-emitting device.

[0167] For example, the light emitting device 121 is a top emission structure, the first electrode 40 is reflective and the second electrode is transmissive or semi-transmissive. For example, the first electrode 40 is a material with a high work function to act as an anode, such as an ITO / Ag / ITO stacked structure; the second electrode is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0168] In one sub-pixel, the first electrode 40 is electrically connected to one of the first electrode T1s and the second electrode T1d of the driving transistor T1. Figures 3H-3I As shown, the plurality of sub-pixels of the display substrate 10 include a first sub-pixel, two adjacent second sub-pixels and a third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel respectively emit light of different colors, and the first electrodes of the first sub-pixel, the second sub-pixel and the third sub-pixel are respectively the first electrode 41, the first electrode 42 and the first electrode 43 in the figure. The two adjacent second sub-pixels are respectively the upper second sub-pixel 100a and the lower second sub-pixel 100b, the upper second sub-pixel 100a includes the first electrode 421, and the lower second sub-pixel 100b includes the first electrode 422. For example, the display substrate includes a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, thereby including a plurality of first electrodes 41, a plurality of first electrodes 42 and a plurality of first electrodes 43; the plurality of first electrodes 42 include the first electrode 421 and the first electrode 422; the plurality of first electrodes 41 include Fig. 3IThe first electrode 41 a in the embodiment is a first electrode of a first sub-pixel adjacent to the upper second sub-pixel 100 a. For example, the orthographic projection of the first connection structure P1-1 of the upper second sub-pixel 100a on the substrate substrate 200 and the orthographic projection of the first electrode 41a of the first sub-pixel adjacent to the upper second sub-pixel 100a on the substrate substrate 200 at least partially overlap, and the orthographic projection of the first connection structure P1-2 of the lower second sub-pixel 100b on the substrate substrate 200 and the orthographic projection of the first electrode 422 of the lower second sub-pixel 100b on the substrate substrate 200 and the orthographic projection of the first electrode 421 of the upper second sub-pixel 100a on the substrate substrate 200 both at least partially overlap, that is, the first connection structure P1 of two adjacent second sub-pixels (corresponding to the N1 node in the circuit diagram) is respectively blocked by the first electrode 41 of the adjacent first sub-pixel, the first electrode 421 of the upper second sub-pixel 100a and the first electrode 422 of the lower second sub-pixel 100b, so that the first connection structures P1 of the two adjacent second sub-pixels are basically blocked by the first electrodes, so that the luminous brightness of the two adjacent second sub-pixels tends to be consistent.

[0169] It should be noted that, in the present application, the first electrode of a sub-pixel refers to the first electrode connected to the pixel circuit of the sub-pixel through the ninth via V9, and it is not required that the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the pixel circuit (such as each thin film transistor, each signal line, etc.) on the substrate.

[0170] like Fig. 3I As shown, in each sub-pixel having a first electrode, taking the second sub-pixel 100a as an example, the first electrode 421 is electrically connected to the second end T1d of the driving transistor T1 through the ninth via hole V9.

[0171] For example, the first sub-pixel emits red light, the second sub-pixel emits green light, and the third sub-pixel emits blue light.

[0172] For example, the upper second sub-pixel 100a and the lower second sub-pixel 100b are arranged along the second direction D2, and the upper second sub-pixel 100a and the first sub-pixel adjacent to the upper second sub-pixel 100a are arranged along the first direction D1. Of course, in other embodiments, the upper second sub-pixel 100a and the lower second sub-pixel 100b may also be arranged along the first direction D1, and the upper second sub-pixel 100a and the first sub-pixel adjacent to the upper second sub-pixel 100a are arranged along the second direction D2. The embodiments disclosed herein are not limited to this.

[0173] For example, Figure 3AAs shown, the first end of the first connection structure P1 is electrically connected to the semiconductor layer through the sixth via V6, and the second end of the first connection structure P1 opposite to the first end is electrically connected to the first electrode Cst1 (i.e., the gate T1g of the driving transistor T1) through the first via V1; the data line Data is electrically connected to the semiconductor layer through the seventh via V7.

[0174] For example, refer to Figures 4A-4E The display substrate 10 further includes a buffer layer 200a on the base substrate 200, and the first semiconductor layer 107 is located on the buffer layer 200a. The buffer layer 200a can prevent contamination and damage to the base substrate 200 during the manufacturing process, making other structures formed thereon purer and smoother.

[0175] In the embodiment of the present disclosure, the first end of the transistor is a source, and the second end is a drain; or, the first end is a drain, and the second end is a source.

[0176] In the display substrate 10 provided in the embodiment of the present disclosure, for example, the base substrate 200 can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc.

[0177] For example, the material of the semiconductor layer 107 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).

[0178] For example, the materials of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by combinations of the above metals; or transparent conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0179] For example, the first insulating layer 301, the second insulating layer 302, the third insulating layer 303, and the fourth insulating layer 304 are inorganic insulating layers, and their materials include, for example, at least one of silicon oxides, silicon nitrides, or silicon oxynitrides such as silicon oxide, silicon nitride, or silicon oxynitride, or include metal nitride oxide insulating materials such as aluminum oxide and titanium nitride. For example, the pixel defining layer 306 and the fourth insulating layer 304 can be organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), and other organic insulating materials. For example, the fourth insulating layer 304 is a planarization layer. The embodiments of the present disclosure are not limited to this.

[0180] Figure 5A A schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure, Figure 5B-5J for Figure 5A Schematic diagram of the semiconductor layer, the first conductive layer, the second conductive layer, various via holes, the third conductive layer and the first electrode of the display substrate shown in FIG. Fig. 6A For along Figure 5A A cross-sectional view of the line F-F' in FIG. Figure 6B for Figure 5A A locally enlarged schematic diagram of a sub-pixel in FIG. Figure 5B-5J and Figure 6A-6B The pixel circuit of the display substrate provided in the embodiment shown is still the same as Figure 2B As shown, Figure 5B-5J and Figure 6A-6B The display substrate provided in the embodiment shown is Figure 3A The display substrate provided in the illustrated embodiment has the following differences.

[0181] Figure 5A The routing design of the first signal line 210 in the embodiment shown is similar to Figure 3A The difference between Figure 5A and Figure 5C As shown, the first part Cst11 of the first electrode Cst1 has a first end in the first direction D1, and the first signal line 210 (i.e., the scanning line 210) that provides the first scanning signal Ga1 to the data writing transistor T2 is bent to include a bending part 2103, and the bending part 2103 is arranged around the first end of the first part Cst11 of the first electrode Cst1; the first end of the first part Cst11 of the first electrode Cst1 in the second direction D2 and the second part Cst12 of the first electrode Cst1 form a blank gap H; the part of the bending part 2103 located on the first side of the first electrode Cst1 in the second direction D2 is at least partially located in the blank gap H, so as to reasonably wire and utilize limited space, which is beneficial to improve the PPI and aperture ratio of the display panel using the display substrate.

[0182] like Figure 5A , Figure 5E and Fig. 6A As shown, the sub-pixel includes a shielding portion 31, which is located on the side of the active pattern T3a of the compensation transistor T3 away from the base substrate 200, and the orthographic projection of the shielding portion 31 on the base substrate 200 overlaps at least partially with the orthographic projection of the active pattern T3a of the compensation transistor T3 on the base substrate 200; the shielding portion 31 is electrically connected to the active pattern T3a of the compensation transistor T3 through the eighth via hole V8. Thus, the shielding portion 31 shields the active pattern T3a of the compensation transistor T3, and the shielding portion 31 is connected to the first connection structure P1, i.e. Figure 2B The electrical signal of the N1 node can better stabilize the potential of the N1 node.

[0183] For example, Figure 5A , Figure 5E and Fig. 6A As shown, the shielding portion 31 and the second electrode Cst2 are arranged in the same layer, for example, both are located in the second metal layer 202, so that the two can be formed by performing a composition process on the same film layer using the same mask, simplifying the structure and manufacturing process of the display substrate.

[0184] Figure 5B-5J and Figure 6A-6B Other unmentioned features and corresponding technical effects of the display substrate shown in the figure are similar to those of the Figure 3A The display substrate shown is the same as that shown, please refer to the previous description and will not be repeated.

[0185] Fig. 7A A schematic diagram of a sub-pixel structure of another display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 7B-7H for Fig. 7A Schematic diagram of the semiconductor layer, the first conductive layer, the second conductive layer, various via holes, the third conductive layer and the first electrode of the display substrate shown in FIG. Fig. 8A For along Fig. 7A A cross-sectional view of the line G-G' in FIG. Figure 8B For along Fig. 7A A cross-sectional view of the line H-H' in FIG. Figure 8C For along Fig. 7A A cross-sectional view of the line II' in FIG. Fig.8D for Fig. 7A A locally enlarged schematic diagram of a sub-pixel in FIG. Figure 7B-7H and Figures 8A-8D The pixel circuit of the display substrate provided in the embodiment shown is still the same as Figure 2B As shown, Figure 7B-7H and Figures 8A-8D The display substrate provided in the embodiment shown is Figure 3A The display substrate provided in the illustrated embodiment has the following differences.

[0186] like Fig. 7A , Figure 5E and Fig. 6A As shown, for example, the orthographic projection of the first connection structure P1 of the sub-pixel on the base substrate 200 at least partially overlaps with the orthographic projection of the channel region C1 of the driving transistor T1 on the base substrate 200, so as to save layout space, thereby facilitating improving the PPI and aperture ratio of the display panel using the display substrate.

[0187] For example, refer to Fig. 7A , Figure 7G and Fig. 8A The first connection structure P1 is disposed in the same layer as the first electrode T1s of the driving transistor T1, for example, both are located in the third conductive layer 203; the first connection structure P1 is electrically connected to the first electrode plate Cst1 of the storage capacitor Cst through the first via V1.

[0188] refer to Fig. 7A The orthographic projection of the first via hole V1 on the base substrate 200 overlaps with the orthographic projection of the first portion Cst11 of the first electrode plate Cst1 on the base substrate 200 , and does not overlap with the orthographic projections of the second portion Cst12 of the first electrode plate Cst1 and the second electrode plate Cst2 on the base substrate 200 .

[0189] Different from Figure 3A In the embodiment shown, the first connection structure P1 is a strip extending along the second direction as a whole, for example, a straight strip. Fig. 7A and Figure 7G The first connection structure P1 includes a first inclined portion P1-3, which extends along a third direction intersecting the first direction D1 and the second direction D2, and the orthographic projection of the first inclined portion P1-3 on the base substrate 200 at least partially overlaps with the orthographic projection of the channel region C1 of the driving transistor T1 on the base substrate 200.

[0190] For example, Fig. 7A and Figure 7C-7D As shown, the first portion Cst11 of the first electrode Cst1 has a first end in the first direction D1, and the first signal line 210 providing the first scan signal Ga1 to the data writing transistor T2 includes a bent portion 2103, which surrounds the first end of the first portion Cst11.

[0191] For example, the first signal line 210, i.e., the scanning line 210, which provides the first scanning signal Ga1 to the data writing transistor T2, is also configured to provide the second scanning signal Ga2 to the compensation transistor T3. For example, the compensation transistor T3 includes an active pattern T3a, and the active pattern T3a of the compensation transistor T3 is arranged in the same layer as the active pattern T1a of the driving transistor T1, for example, both are located in the semiconductor layer. The sub-pixel also includes a shielding portion 31, which is located on the side of the active pattern T3a of the compensation transistor T3 away from the base substrate 200, and the orthographic projection of the shielding portion 31 on the base substrate 200 overlaps at least partially with the orthographic projection of the active pattern T3a of the compensation transistor T3 on the base substrate 200, so that the shielding portion 31 shields the active pattern T3a of the compensation transistor T3, for example, shields the channel region of the shielding portion 31, to prevent light from affecting the performance of the channel region of the compensation transistor T3. For example, the shielding portion 31 is electrically connected to the first power line to provide the shielding portion 31 with a first power voltage VDD signal for voltage stabilization to prevent the voltage on the shielding portion 31 from unstable jumps and affecting the stable operation of the pixel circuit.

[0192] For example, refer to Fig. 7E The shielding portion 31 and the second electrode Cst2 are disposed in the same layer, for example, both are located in the second metal layer 202, so that the shielding portion 31 and the second electrode Cst2 can be formed by performing the same patterning process on the same film layer through the same mask, thereby simplifying the manufacturing process of the display substrate 10. For example, the orthographic projection of the first power line VDD on the base substrate 200 overlaps with the orthographic projection of the shielding portion 31 on the base substrate 200 at least partially, and the first power line VDD is electrically connected to the shielding portion 31 through the second via V2.

[0193] For example, in Fig. 7A In the display substrate 10 shown, the first power line VDD of the pixel circuit is connected to the first voltage terminal and is configured to provide the first power supply voltage to the pixel circuit, and is disposed in the same layer as the first electrode T1s of the driving transistor T1, for example, both are located in the third conductive layer 203. Fig. 7A , Figure 7G and Figure 8B , the first power line VDD includes a second vertical portion VDD3 and a second inclined portion VDD4. The second vertical portion VDD3 extends along the second direction D2; the second inclined portion VDD4 extends along a fourth direction intersecting the first direction D1 and the second direction D2, and is electrically connected to the second electrode plate Cst2 through the second via V2. The second electrode plate Cst2 has a first side and a second side opposite to each other in the second direction D2, the second vertical portion VDD3 is located on the first side of the second electrode plate Cst2, the second inclined portion VDD4 is connected to the first vertical portion VDD3, and extends from the first side of the second electrode plate Cst2 to the second side of the second electrode plate Cst2 along the fourth direction.

[0194] exist Fig. 7AIn the display substrate 10 shown, the first power line VDD and the data line Data are located on different sides of the storage capacitor Cst.

[0195] For example, in Figure 3A In the illustrated embodiment, the first power line VDD and the data line Data are located in the same layer, both located in the third metal layer 203; in other embodiments, the first power line VDD and the data line Data may be located in different layers. For example, in at least one embodiment, the display substrate further includes a fourth metal layer located in the third metal layer 203 and away from the base substrate 200. For example, the first power line VDD is located in the third metal layer 203, and the data line Data is located in the fourth metal layer; or, the first power line VDD is located in the fourth metal layer, and the data line Data is located in the third metal layer 203.

[0196] Figure 7B-7I and Figures 8A-8D Other unmentioned features and corresponding technical effects of the display substrate shown in the figure are similar to those of the Figure 3A The display substrate shown is the same as that shown, please refer to the previous description and will not be repeated.

[0197] Fig.9A A schematic diagram of the structure of a sub-pixel of another display substrate provided in an embodiment of the present disclosure; Figure 9B-9I for Fig.9A A schematic diagram of a semiconductor layer, a first conductive layer, a second conductive layer, various via holes, a third conductive layer and a first electrode of a display substrate shown; Figure 9J Fig.9A A local enlarged schematic diagram of a sub-pixel in FIG. Fig. 10A For along Fig.9A A cross-sectional view of the line J-J'; Fig. 10B For along Fig.9A A cross-sectional view of the line K-K' in FIG. Fig. 10C For along Fig.9A A cross-sectional view of the line L-L' in FIG. Figure 2B As an example, the pixel circuit shown in FIG. Figure 9B-9I and Figures 10A-10C The structure of a display substrate provided in at least one embodiment of the present disclosure is exemplarily described.

[0198] like Fig.9A and Fig. 10B, the display substrate 10 includes a base substrate 200, a first signal line and a second signal line arranged on the base substrate 200, and a sub-pixel. For example, a plurality of sub-pixels arranged in an array are arranged on the base substrate 200. At least some of the sub-pixels in the plurality of sub-pixels each include a pixel circuit 101, for example, at least some of the sub-pixels refer to sub-pixels that perform a display function, not dummy sub-pixels. For example, the pixel circuit 101 includes: a first signal line and a second signal line, a light-emitting device, a driving transistor T1, a data writing transistor T2, and a storage capacitor Cst. The data writing transistor T2 is configured to transmit the data signal transmitted on the second signal line, for example, to the driving transistor T1 under the control of the first scanning signal Ga1, and the first scanning signal Ga1 is transmitted on the first signal line 210; the driving transistor T1 is configured to control the size of the driving current flowing through the light-emitting device 121 according to the data signal Vd, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; the driving transistor T1 includes an active pattern T1a and a gate T1g, and the active pattern T1a of the driving transistor T1 includes a channel region C1, and the positive projection of the channel region C1 on the substrate 200 is located at least partially overlapped with the positive projection of the gate on the substrate 200; the storage capacitor Cst includes: a first electrode plate Cst1 and a second electrode plate Cst2. The first electrode plate Cst1 is electrically connected to the gate of the driving transistor T1; the positive projection of the second electrode plate Cst2 on the substrate 200 at least partially overlaps with the positive projection of the first electrode plate Cst1 on the substrate 200, and does not overlap with the positive projection of the channel region C1 of the driving transistor T1 on the substrate 200. In the display substrate 10 provided in the embodiment of the present disclosure, since the second electrode plate Cst2 is connected to the first power supply voltage VDD for voltage stabilization, the first power supply voltage signal will affect the channel region C1 of the driving transistor T1. In order to reduce its influence on the channel region C1 of the driving transistor T1, the second electrode plate Cst2 is avoided from the channel region C1 of the driving transistor T1 to avoid affecting the performance of the driving transistor T1.

[0199] For example, the first signal line is a gate line serving as a scanning signal line, and the second signal line is a data line; or, in some other embodiments, the first signal line is a data line, and the second signal line is a gate line serving as a scanning signal line.

[0200] and Figure 3A Similar to the embodiment shown, Figure 9B-9G and Figures 10A-10C It can be seen that the display substrate 10 includes a semiconductor layer 107, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, a second conductive layer 202, a third insulating layer 303, a third conductive layer 203, a fourth insulating layer 304 and a fourth conductive layer 204 which are sequentially arranged on a base substrate 200.

[0201] For example, Fig. 9B The semiconductor layer 107 is shown to include active patterns T1a-T7a of first to seventh transistors T1-T7.

[0202] For example, Figure 9C-9D As shown, the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines. Fig.9A The area where the pixel circuit of each sub-pixel is located is shown by a large dotted box. Fig. 9B 1 and 2 , gates T1g to T7g of the first to seventh transistors T1 to T7 in one pixel circuit unit 100 are shown by small dotted line boxes.

[0203] For example, Figure 9C-9D As shown, the first conductive layer 201 includes gate electrodes T1g-T7g of the first to seventh transistors T1-T7. For example, the display substrate 10 adopts a self-alignment process, and uses the first conductive layer 201 as a mask to perform a conductorization process (e.g., a doping process) on the semiconductor layer 107, so that the portion of the semiconductor layer 107 not covered by the first conductive layer 201 is conductorized, so that the portion of the active pattern of each transistor located on both sides of the channel region is conductorized to form the first electrode and the second electrode of the transistor respectively.

[0204] For example, Fig.9A As shown, the gate T6g of the sixth transistor T6 of the pixel circuit of this row is electrically connected to the first reset control line 220a corresponding to the row to receive the first reset control signal Rst1. The gate of the seventh transistor T7 of the pixel circuit of this row is electrically connected to the second reset control line 220b corresponding to the pixel circuit of the next row (i.e., the pixel circuit row where the scan line that is sequentially turned on after the scan line of this row is located according to the scan order of the scan lines) to receive the second reset control signal Rst2.

[0205] The scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or is an integrated structure) to provide a first scan signal Ga1, a reset control line 220 is electrically connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset control signal Rst1, and the light-emitting control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide a first light-emitting control signal EM1.

[0206] For example, Fig.9A and Fig. 9CAs shown, the planar shape of the channel region C1 of the driving transistor T1 is a strip extending along the second direction D2 as a whole. This feature can increase the length of the channel region of the driving transistor (the length along the second direction D2), thereby increasing the aspect ratio of the channel region of the driving transistor to ensure that in the black state, the leakage of the driving transistor T1 will be small and the driving will be stable; the longer the length of the channel region of the driving transistor T1, the closer the output curve of the driving transistor T1 is to the ideal linear condition in the saturation region, so that the display substrate, such as an OLED display substrate, works in the saturation region of the driving transistor T1, so that the brightness of the display panel using the display substrate is better controlled by the driving transistor T1; and this feature is conducive to saving the layout space of the pixel circuit. The channel region C1 is different from the existing "X"-shaped channel, S-shaped channel, etc. with obvious bends extending along the first direction D1. The first direction D1 and the second direction D2 are Figure 3A The same as in.

[0207] It should be noted that the “strip extending along the second direction D2 as a whole” includes extending substantially along the second direction D2, or at least extending along the second direction D2 as a whole. For example, in some examples, the strip extending along the second direction D2 as a whole may have a certain curved portion, such as Figure 4F Alternatively, in some examples, the edge of the strip extending along the second direction D2 may not be a smooth line, for example, its edge may have burrs or saw teeth. In short, it is sufficient to satisfy the requirement of being a strip extending along the second direction D2.

[0208] For example, Fig.9A and Fig. 9C As shown, the planar shape of the channel region C1 of the driving transistor T1 is a straight strip extending along the second direction D2, so as to better increase the aspect ratio of the channel region C1 of the driving transistor T1 and make it more regular, thereby facilitating manufacturing and better saving the layout space of the pixel circuit.

[0209] For example, refer to Figures 9A-9D , the first electrode plate Cst1 includes a first portion Cst11 and a second portion Cst12. The orthographic projection of the first portion Cst11 of the storage capacitor Cst on the base substrate 200 does not overlap with the orthographic projection of the first electrode plate Cst2 on the base substrate 200; the second portion Cst12 of the storage capacitor Cst is connected to the first portion Cst11 and protrudes from the first portion Cst11, and the orthographic projection of the second portion Cst12 on the base substrate 200 at least partially overlaps with the orthographic projection of the first electrode plate Cst2 on the base substrate 200.

[0210] For example, in Fig.9AIn the illustrated embodiment, the first electrode Cst1 and the gate T1g of the driving transistor T1 are disposed in the same layer and are an integral structure, for example, both are located in the first conductive layer 201, so as to simplify the structure of the display substrate 10, and the first electrode Cst1 and the gate T1g of the driving transistor T1 can be formed by performing the same patterning process on the same film layer through the same mask, thereby simplifying the manufacturing process of the display substrate 10. For example, the first portion Cst11 of the first electrode Cst1 is a strip extending along the second direction D2, and the second portion Cst12 of the first electrode Cst1 protrudes from the first portion Cst11 along the first direction D1.

[0211] For example, Fig.9A and Fig. 10B As shown, the pixel circuit 101 further includes a first connection structure P1, the first connection structure P1 is electrically connected to the gate T1g of the driving transistor T1 and the first electrode Cst1; the orthographic projection of the first connection structure P1 on the base substrate 200 does not overlap with the orthographic projection of the first electrode Cst2 on the base substrate 200. For example, the second electrode Cst2 is located on the second conductive layer 202, the second conductive layer 202 is located on the side of the first conductive layer 201 away from the base substrate 200, and there is a second insulating layer 302 between the second conductive layer 202 and the first conductive layer 201. In this way, the first connection structure P1 needs to be electrically connected to the first electrode Cst1 through a via, and the first connection structure P1 will not pass through the second electrode Cst2 of the storage capacitor Cst, thereby increasing the area of ​​the second electrode Cst2 to increase the capacitance of the storage capacitor.

[0212] For example, Fig.9A and Fig. 10B As shown, the first connection structure P1 at least partially overlaps with the positive projection of the first part Cst11 on the base substrate 200, for example, overlaps with the channel region C1 of the driving transistor T1, so as to save space and facilitate the arrangement of other structures of the pixel circuit while rationally utilizing limited space. This is very important for the pixel design of the display substrate and can solve the important technical problem of how to effectively improve the PPI.

[0213] For example, the first connection structure P1 is disposed in the same layer as the first electrode T1s of the driving transistor T1, for example, both are located in the third conductive layer 203. The first connection structure P1 is electrically connected to the first electrode plate Cst1 through the first via hole V1; the orthographic projection of the first via hole V1 on the base substrate 200 overlaps with the orthographic projection of the first part Cst11 of the first electrode plate Cst1 on the base substrate 200, that is, it does not overlap with the orthographic projection of the second electrode plate Cst2 on the base substrate 200.

[0214] For example, the first conductive layer 201 further includes a plurality of gate lines insulated from each other, the gate lines for example including a plurality of scan lines 210, a plurality of reset control lines 220a / 220b and a plurality of light emitting control lines 230. Here, the gate line refers to a signal line directly connected to the gate of the transistor to provide a scan signal or a control signal. For example, each row of sub-pixels is respectively connected to a scan line 210, two reset control lines and a light emitting control line 230, the two reset control lines being a first reset control line 220a and a second reset control line 220b.

[0215] For example, Fig.9A As shown in FIG. 9C, the first signal line 210, i.e., the first scanning signal line, is connected to the gate of the data writing transistor T2 and is configured to provide the first scanning signal Ga1 to the gate of the data writing transistor T2. The first signal line 210 includes a first transverse portion 210a extending along the first direction D1 as a whole and a first longitudinal portion 210b extending along the second direction D2 as a whole, and the first transverse portion 210a is connected to the first longitudinal portion 210b. Fig. 9B As shown, the data writing transistor T2 includes an active pattern T2a, and the positive projection of the active pattern T2a of the data writing transistor T2 on the base substrate 200 overlaps at least partially with the positive projection of the first longitudinal portion 210b on the base substrate 200, so that a portion of the first longitudinal portion 210b is used to form the gate T2g of the data writing transistor T2. In this way, the first scanning signal Ga1 enters the sub-pixel along the first direction D1, and is applied to the gate T2g of the data writing transistor T2 along the second direction D2, that is, the data writing transistor T2 is driven along the second direction D2, which can drive the data writing transistor T2 more stably, and at the same time, the limited space of the sub-pixel is reasonably used to arrange the wiring.

[0216] For example, Fig.9A and Fig. 9C As shown, the first light emission control transistor T4 of the pixel circuit 101 is connected to the first electrode T1s of the driving transistor T1 and the first voltage terminal vdd, and is configured to apply the first power supply voltage VDD of the first voltage terminal vdd to the first electrode T1s of the driving transistor T1 under the control of the first light emission control signal EM1. The plurality of light emission control lines 230 include a first light emission control line 231, which is connected to the gate of the first light emission control transistor T4 and is configured to provide the first light emission control signal to the gate of the first light emission control transistor T4.

[0217] For example, Figures 9A-9CAs shown, the first light-emitting control line 231 includes a second transverse portion 231a extending along the first direction D1 as a whole and a second longitudinal portion 231b extending along the second direction D2 as a whole, and the first light-emitting control transistor T4 includes an active pattern T4a, and the positive projection of the active pattern T4a of the first light-emitting control transistor T4 on the substrate 200 overlaps at least partially with the positive projection of the second longitudinal portion 231b on the substrate 200, so that a portion of the second longitudinal portion 231b is used to form the gate T4g of the first light-emitting control transistor T4. In this way, the first light-emitting control signal EM1 enters the sub-pixel along the first direction D1, and is applied to the gate T4g of the first light-emitting control transistor T4 along the second direction D2, that is, the first light-emitting control transistor T4 is driven along the second direction D2, which can drive the first light-emitting control transistor T4 more stably, and at the same time, the limited space of the sub-pixel is reasonably used to arrange the wiring.

[0218] For example, Figures 9A-9C As shown, the second light-emitting control transistor T5 of the pixel circuit 101 is connected to the second light-emitting control terminal vss, the light-emitting device and the second electrode T1d of the driving transistor T1, and is configured to apply the driving current to the light-emitting device under the control of the second light-emitting control signal EM2. The plurality of light-emitting control lines 230 also include a second light-emitting control line 232, which is connected to the gate T5g of the second light-emitting control transistor T5 and is configured to provide the second light-emitting control signal EM2 to the gate T5g of the second light-emitting control transistor T5. The first light-emitting control line 231 is reused as the second light-emitting control line 232, that is, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 share a light-emitting control line; and the second light-emitting control transistor T5 includes an active pattern, and the positive projection of the active pattern T5a of the second light-emitting control transistor T5 on the substrate 200 overlaps at least partially with the positive projection of the second longitudinal portion 231b on the substrate 200, so that a portion of the second longitudinal portion 231b is used to form the gate T5g of the second light-emitting control transistor T5. In this way, the second light-emitting control signal EM2 enters the sub-pixel along the first direction D1, and is applied to the gate T4g of the second light-emitting control transistor T5 along the second direction D2, that is, the second light-emitting control transistor T5 is driven along the second direction D2, which can drive the second light-emitting control transistor T5 more stably, and at the same time, the limited space of the sub-pixel is reasonably used to arrange the wiring. The second longitudinal portion 231b is used to form the gate T4g of the first light-emitting control transistor T4 and the gate T5g of the second light-emitting control transistor T5, and the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are driven (longitudinally driven) along the second direction D2, simplifying the structure of the pixel circuit.

[0219] For example, the storage capacitor Cst is located between the first longitudinal portion 210b and the second longitudinal portion 231b, and between the first transverse portion 210a and the second transverse portion 210b, so as to utilize the limited space to reasonably layout the first light-emitting control line and the second light-emitting control line having the transverse portion and the longitudinal portion respectively, which is beneficial to improve the PPI and aperture ratio of the display panel using the display substrate.

[0220] For example, Fig. 9B As shown, the active pattern of the first light-emitting control transistor T4 includes a channel region, and the active pattern of the second light-emitting control transistor T5 includes a channel region C5; in the first direction D1, the distance between the channel region C4 of the first light-emitting control transistor T4 and the channel region C1 of the driving transistor T1 is h1, the distance between the channel region C5 of the second light-emitting control transistor T5 and the channel region C1 of the driving transistor T1 is h2, and, in the second direction D2, the distance between the channel region of the first light-emitting control transistor T4 and the channel region C1 of the driving transistor T1 is equal to the distance between the channel region of the second light-emitting control transistor T5 and the channel region C1 of the driving transistor T1.

[0221] It should be noted that the distance h1 refers to the distance between the edge of the channel region C4 close to the channel region C1 in the first direction D1 and the edge of the channel region C1 close to the channel region C4 in the first direction D1, and the distance h2 refers to the distance between the edge of the channel region C5 close to the channel region C1 in the first direction D1 and the edge of the channel region C1 close to the channel region C5 in the first direction D1; the distance h3 refers to the distance between the edge of the channel region C4 close to the channel region C1 in the second direction D2 and the edge of the channel region C1 close to the channel region C4 in the second direction D2, and the distance h4 refers to the distance between the edge of the channel region C5 close to the channel region C1 in the second direction D2 and the edge of the channel region C1 close to the channel region C5 in the second direction D2.

[0222] For example, the length-to-width ratio of the channel region C4 of the first light emission control transistor T4 is the same as the length-to-width ratio of the channel region C5 of the second light emission control transistor T5. For example, the ratio of the length of the channel region C4 in the first direction D1 to its width in the second direction D2 is the same as the ratio of the length of the channel region C5 in the first direction D1 to its width in the second direction D2. This makes the driving effects of the first light emission control transistor T4 and the second light emission control transistor T5 similar, makes the display effect more stable, and reduces the difficulty of the manufacturing process.

[0223] For example, Fig.9A and Figure 9GAs shown, the pixel circuit 101 further includes a first power line VDD, the first power line VDD is connected to the first voltage terminal vdd and is configured to provide a first power supply voltage to the pixel circuit, and is arranged in the same layer as the first electrode T1s of the driving transistor T1, for example, both are located in the third metal layer 203. The first power line VDD includes a third longitudinal portion VDD1 and a third transverse portion VDD2. The third longitudinal portion VDD1 extends along the second direction D2 as a whole, and is connected to adjacent sub-pixels to provide a power supply voltage to multiple sub-pixels in the same column; the third transverse portion VDD2 is connected to the third longitudinal portion VDD1 and extends from the third longitudinal portion VDD1 toward the second electrode plate Cst2, and the third transverse portion VDD2 is electrically connected to the second electrode plate Cst2 through the second via V2.

[0224] For example, Fig.9A and Figure 9G As shown, the second signal line, such as the data line Data, is arranged in the same layer as the first power line VDD, and both are located in the third metal layer 203; and includes a fourth transverse portion Data1 extending along the first direction D1 as a whole and a fourth longitudinal portion Data2 extending along the second direction D2 as a whole; in the second direction D2, the fourth transverse portion Data1 of the data line Data and the third transverse portion VDD2 of the first power line VDD are at least partially opposite to each other, that is, the projections of the two in the second direction D2 overlap. The positive projection of the fourth longitudinal portion Data2 of the data line Data on the base substrate 200 does not overlap with the positive projection of the third transverse portion VDD2 of the first power line VDD on the base substrate 200, so that when the data line Data and the first power line VDD are in the same layer, the data line Data avoids the first power line VDD to prevent the two from short circuiting or signal crosstalk.

[0225] For example, in Fig.9A In the illustrated embodiment, the first power line VDD and the data line Data are located in the same layer, both located in the third metal layer 203; in other embodiments, the first power line VDD and the data line Data may be located in different layers. For example, in at least one embodiment, the display substrate further includes a fourth metal layer located in the third metal layer 203 and away from the base substrate 200. For example, the first power line VDD is located in the third metal layer 203, and the data line Data is located in the fourth metal layer; or, the first power line VDD is located in the fourth metal layer, and the data line Data is located in the third metal layer 203. In the case where the first power line VDD and the data line Data may be located in different layers, the orthographic projections of the two on the base substrate may have overlapping portions.

[0226] For example, Fig.9A and Fig. 10BAs shown, the third longitudinal portion VDD1 is located on the first side of the storage capacitor Cst in the first direction D1, and the fourth longitudinal portion Data2 of the data line Data at least partially overlaps with the orthographic projection of the storage capacitor Cst on the substrate 200, and does not overlap with the orthographic projection of the second via V2 on the substrate 200, so as to save space and allow the data line Data to avoid the first power line VDD arranged on the same layer as it.

[0227] For example, Fig.9A As shown, the compensation transistor T3 of the pixel circuit 101 is configured to compensate the gate T1g of the driving transistor T1 in response to the second scanning signal Ga2 and the data signal Vd applied to the gate T3g of the compensation transistor T3. The first transverse portion 210a of the first signal line 210 that provides the first scanning signal Ga1 to the data writing transistor T2 is configured to provide the second scanning signal to the compensation transistor T3. Fig. 9B As shown, the compensation transistor T3 includes an active pattern T3a, and the active pattern T3a of the compensation transistor T3 is arranged in the same layer as the active pattern T1a of the driving transistor T1, and both are located in the semiconductor layer 107. The sub-pixel also includes a shielding portion 31, and the shielding portion 31 is located on a side of the active pattern T3a of the compensation transistor T3 away from the substrate 200, and the orthographic projection of the shielding portion 31 on the substrate 200 overlaps with the orthographic projection of the active pattern T3a of the compensation transistor T3 on the substrate 200 at least partially, so that the shielding portion 31 is used to shield the active pattern T3a of the compensation transistor T3, for example, to shield the channel region of the compensation transistor T3, to prevent light from affecting the performance of the channel region of the compensation transistor T3. The shielding portion 31 shields the active pattern T3a of the compensation transistor T3, for example, to shield the channel region of the compensation transistor T3, to prevent light from affecting the performance of the channel region of the compensation transistor T3. For example, the shielding portion 31 and the reset signal line 240 are arranged in the same layer, for example, both are located in the second metal layer 202. For example, the shielding portion 31 and the reset signal line 240 are arranged in the same layer and are integrally formed, so that the two can be formed by performing a composition process on the same film layer using the same mask, simplifying the structure and manufacturing process of the display substrate. It should be noted that the active pattern T3a shielded by the shielding portion 31 here is the conductive part around the channel region of the compensation transistor T3, and does not include the channel region of the compensation transistor T3.

[0228] For example, Figures 9A-9BAs shown, the semiconductor layer 107 includes an active pattern T1a of the driving transistor T1; the semiconductor layer 107 includes a first portion 107a and a second portion 107b, the first portion 107a of the semiconductor layer is separated from the second portion 107b of the semiconductor layer by an opening O, the orthographic projection of the opening O on the substrate substrate 200 overlaps with the orthographic projection of the second lateral portion 231a of the first light-emitting control line 231 on the substrate substrate 200, and the orthographic projections of the first portion 107a of the semiconductor layer and the second portion 107b of the semiconductor layer on the substrate substrate 200 do not overlap with the orthographic projection of the second lateral portion 231a of the first light-emitting control line 231 on the substrate substrate 200.

[0229] Each light emitting device of a sub-pixel performing a display function includes a first electrode 40, and the first electrode 40 is electrically connected to one of a first electrode T1s and a second electrode T1d of a driving transistor T1. The substrate 200 includes a plurality of sub-pixels, for example, Figures 9H-9I As shown, the plurality of sub-pixels of the display substrate 10 include a first sub-pixel, two adjacent second sub-pixels and a third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel respectively emit light of different colors and respectively include a first electrode 41, a first electrode 42 and a first electrode 43; the two adjacent second sub-pixels are respectively an upper second sub-pixel 101a and a lower second sub-pixel 101b, the upper second sub-pixel 101a includes a first electrode 421, and the lower second sub-pixel 101b includes a first electrode 422. For example, the display substrate includes a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, thereby including a plurality of first electrodes 41, a plurality of first electrodes 42 and a plurality of first electrodes 43; for example, the plurality of first electrodes 42 include Fig.9I The orthographic projection of the first connection structure P1-1 of the upper second sub-pixel 101a on the substrate substrate 200 and the orthographic projection of the first electrode 421 of the upper second sub-pixel 101a on the substrate substrate 200 at least partially overlap, and the orthographic projection of the first connection structure P1-2 of the lower second sub-pixel 101b on the substrate substrate 200 and the orthographic projection of the first electrode 422 of the lower second sub-pixel 101b on the substrate substrate 200 at least partially overlap, so that the first connection structures of the two adjacent second sub-pixels are basically blocked by the first electrodes of the sub-pixels where they are located, so that the luminous brightness of the two adjacent second sub-pixels tends to be consistent.

[0230] like Fig.9I As shown, in each sub-pixel having a first electrode, taking the second sub-pixel 101 a as an example, the first electrode 421 is electrically connected to the second end T1 d of the driving transistor T1 through the ninth via hole V9 .

[0231] For example, the first sub-pixel emits red light, the second sub-pixel emits green light, and the third sub-pixel emits blue light.

[0232] For example, the upper second sub-pixel 101a and the lower second sub-pixel 101b are arranged along the second direction D2, and the upper second sub-pixel 101a and the first sub-pixel adjacent to the upper second sub-pixel 101a are arranged along the first direction D1. Of course, in other embodiments, the upper second sub-pixel 101a and the lower second sub-pixel 101b may also be arranged along the first direction D1, and the upper second sub-pixel 101a and the first sub-pixel adjacent to the upper second sub-pixel 101a are arranged along the second direction D2. The embodiments disclosed herein are not limited to this.

[0233] Fig.9A Other unmentioned features and technical effects of the illustrated embodiment, such as the type of transistors, the materials of each film layer, etc., are the same as the corresponding structures in the previous embodiments, and reference may be made to the previous description.

[0234] At least one embodiment of the present disclosure provides a display device, including any display substrate provided in the embodiments of the present disclosure. The display device may be, for example, an organic light emitting diode display device, a quantum dot light emitting diode display device, or other types of devices having a display function. The embodiments of the present disclosure are not limited thereto.

[0235] The structure, function, technical effect, etc. of the display device provided by the embodiment of the present disclosure can refer to the corresponding description of the display substrate 10 provided by the above embodiment of the present disclosure, and will not be repeated here.

[0236] For example, the display device provided in at least one embodiment of the present disclosure may be a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiments of the present disclosure are not limited thereto.

[0237] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined according to the scope defined in the claims.

Claims

1. A display substrate, include: substrate substrate; A first signal line and a second signal line are provided on the base substrate; as well as A sub-pixel, wherein the sub-pixel comprises a pixel circuit, and the pixel circuit comprises: A light emitting device, a driving transistor, a data writing transistor and a storage capacitor, wherein: The data writing transistor is configured to transmit a data signal to the driving transistor under the control of a first scanning signal, the first scanning signal is transmitted on the first signal line, and the data signal is transmitted on the second signal line; the driving transistor is configured to control the magnitude of a driving current flowing through the light emitting device according to the data signal, and the light emitting device is configured to receive the driving current and be driven by the driving current to emit light; The driving transistor comprises an active pattern and a gate, the active pattern of the driving transistor comprises a channel region, and an orthographic projection of the channel region on the substrate overlaps at least partially with an orthographic projection of the gate on the substrate; The storage capacitor comprises: a first electrode plate electrically connected to the gate of the driving transistor; and The orthographic projection of the second electrode plate on the base substrate at least partially overlaps with the orthographic projection of the first electrode plate on the base substrate, and does not overlap with the orthographic projection of the channel region of the driving transistor on the base substrate.

2. The display substrate according to claim 1, in, The first electrode plate comprises: The orthographic projection of the first portion on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate; and The second part is connected to the first part and protrudes from the first part, wherein the orthographic projection of the second part on the base substrate overlaps with the orthographic projection of the second electrode plate on the base substrate.

3. The display substrate according to claim 2, in, The pixel circuit further comprises: A first connection structure is electrically connected to the gate of the driving transistor and the first electrode plate, wherein the orthographic projection of the first connection structure on the substrate does not overlap with the orthographic projection of the second electrode plate on the substrate, and at least partially overlaps with the orthographic projection of the first part on the substrate.

4. The display substrate according to claim 3, in, The first connection structure is disposed in the same layer as the first electrode of the driving transistor and is electrically connected to the first electrode plate through a first via hole; An orthographic projection of the first via hole on the base substrate overlaps with an orthographic projection of the first portion of the first electrode plate on the base substrate.

5. The display substrate according to claim 2, in, The first electrode plate and the gate electrode of the driving transistor are arranged in the same layer and are an integrated structure.

6. The display substrate according to claim 1, in, The first signal line is connected to the gate of the data writing transistor and is configured to provide the first scanning signal to the gate of the data writing transistor, wherein: The first signal line includes a first transverse portion extending along a first direction as a whole and a first longitudinal portion extending along a second direction as a whole, the first transverse portion is connected to the first longitudinal portion, and the first direction intersects with the second direction; The data write transistor includes an active pattern, and an orthographic projection of the active pattern of the data write transistor on the base substrate at least partially overlaps with an orthographic projection of the first longitudinal portion on the base substrate.

7. The display substrate according to claim 6, in, The pixel circuit further includes: a first light emitting control transistor connected to the first electrode and the first voltage terminal of the driving transistor and configured to apply a first power supply voltage of the first voltage terminal to the gate of the driving transistor under the control of a first light emitting control signal; and a first light emission control line connected to the gate of the first light emission control transistor and configured to provide the first light emission control signal to the gate of the first light emission control transistor, wherein: The first light-emitting control line includes a second lateral portion extending as a whole along the first direction and a second longitudinal portion extending as a whole along the second direction, the first light-emitting control transistor includes an active pattern, and the positive projection of the active pattern of the first light-emitting control transistor on the substrate at least partially overlaps with the positive projection of the second longitudinal portion on the substrate.

8. The display substrate according to claim 7, in, The pixel circuit further includes: a second light emitting control transistor connected to the second light emitting control terminal, the light emitting device and the second electrode of the driving transistor, and configured to enable the driving current to be applied to the light emitting device under the control of a second light emitting control signal; and A second light emitting control line is connected to the gate of the second light emitting control transistor and is configured to provide the second light emitting control signal to the gate of the second light emitting control transistor, wherein: The first light emission control line is reused as the second light emission control line, and the second light emission control transistor includes an active pattern, and an orthographic projection of the active pattern of the second light emission control transistor on the base substrate at least partially overlaps with an orthographic projection of the second longitudinal portion on the base substrate.

9. The display substrate according to claim 8, in, The storage capacitor is located between the first longitudinal portion and the second longitudinal portion, and between the first transverse portion and the second transverse portion.

10. The display substrate according to claim 9, in, The active pattern of the first light emission control transistor includes a channel region, and the active pattern of the second light emission control transistor includes a channel region; In the first direction, the distance between the channel region of the first light emission control transistor and the channel region of the driving transistor is equal to the distance between the channel region of the second light emission control transistor and the channel region of the driving transistor, and, In the second direction, a distance between a channel region of the first light emission control transistor and a channel region of the driving transistor is equal to a distance between a channel region of the second light emission control transistor and a channel region of the driving transistor.

11. The display substrate according to claim 10, in, The aspect ratio of the channel region of the first light emission control transistor is the same as the aspect ratio of the channel region of the second light emission control transistor.

12. The display substrate according to claim 6, in, The pixel circuit further includes: A first power line, connected to the first voltage terminal and configured to provide a first power supply voltage to the pixel circuit, is disposed in the same layer as the first electrode of the driving transistor, and includes: a third longitudinal portion extending entirely along the second direction and passing through adjacent sub-pixels; and The third transverse portion is connected to the third longitudinal portion and extends from the third longitudinal portion toward the second electrode plate, wherein the third transverse portion is electrically connected to the second electrode plate through a second via hole.

13. The display substrate according to claim 12, in, The second signal line is disposed in the same layer as the first power line, and includes a fourth transverse portion extending along the first direction as a whole and a fourth longitudinal portion extending along the second direction as a whole; In the second direction, the fourth transverse portion is at least partially opposite to the third transverse portion, and an orthographic projection of the fourth longitudinal portion on the substrate does not overlap with an orthographic projection of the third transverse portion on the substrate.

14. The display substrate according to claim 13, in, The third longitudinal portion is located on the first side of the storage capacitor in the first direction, and the orthographic projection of the fourth longitudinal portion on the substrate at least partially overlaps with the orthographic projection of the storage capacitor on the substrate, and does not overlap with the orthographic projection of the second via on the substrate.

15. The display substrate according to claim 6, in, The pixel circuit further includes: a compensation transistor configured to compensate the gate of the driving transistor in response to a second scanning signal and the data signal applied to the gate of the compensation transistor, wherein: a first lateral portion of the first signal line providing the first scan signal to the data write transistor configured to provide the second scan signal to the compensation transistor; The compensation transistor comprises an active pattern, and the active pattern of the compensation transistor is arranged in the same layer as the active pattern of the driving transistor; The sub-pixel further includes: a shielding portion located on a side of the active pattern of the compensation transistor away from the base substrate, wherein an orthographic projection of the shielding portion on the base substrate at least partially overlaps with an orthographic projection of the active pattern of the compensation transistor on the base substrate; and A reset signal line, wherein the shielding portion is electrically connected to the reset signal line.

16. The display substrate according to claim 15, in, The shielding portion is arranged in the same layer as the reset signal line and is integrally formed.

17. The display substrate according to claim 7, in, The pixel circuit includes a semiconductor layer, and the semiconductor layer includes an active pattern of the driving transistor; The semiconductor layer includes a first part and a second part, the first part of the semiconductor layer is separated from the second part of the semiconductor layer by an opening, the orthographic projection of the opening on the substrate overlaps with the orthographic projection of the second lateral part on the substrate, and the orthographic projections of the first part of the semiconductor layer and the second part of the semiconductor layer on the substrate do not overlap with the orthographic projection of the second lateral part on the substrate.

18. The display substrate according to claim 6, in, The planar shape of the channel region of the driving transistor is a strip shape extending along the second direction as a whole.

19. The display substrate according to claim 18, in, A planar shape of the channel region of the driving transistor is a straight strip extending along the second direction.

20. The display substrate according to any one of claims 1 to 19, in, The sub-pixel comprises a first electrode, the first electrode being electrically connected to one of a first electrode and a second electrode of the driving transistor; The base substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a first sub-pixel and two adjacent second sub-pixels, wherein the two adjacent second sub-pixels are an upper second sub-pixel and a lower second sub-pixel respectively, and the orthographic projection of the first electrode of the upper second sub-pixel on the base substrate at least partially overlaps with the orthographic projection of the first connection structure of the upper second sub-pixel on the base substrate, and the orthographic projection of the first electrode of the lower second sub-pixel on the base substrate at least partially overlaps with the orthographic projection of the first connection structure of the lower second sub-pixel on the base substrate.

21. The display substrate according to claim 20, in, The first sub-pixel emits red light, and the second sub-pixel emits green light.

22. A display device comprising the display substrate according to any one of claims 1-21.

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