Semiconductor device

Abstract

A transistor with high withstand voltage is provided. A first nitride semiconductor layer and a second nitride semiconductor layer are stacked in a first direction. The first and second nitride semiconductor layers form a heterojunction, and a two-dimensional carrier gas is induced in the first nitride semiconductor layer. A drain electrode faces a source electrode with a gate electrode interposed therebetween in a third direction. The source electrode and the drain electrode are in conduction with the first nitride semiconductor layer. The first and second nitride semiconductor layers form a Schottky junction with the gate electrode. A first layer is located between the gate electrode and the drain electrode in the third direction and in contact with the gate electrode, and is in contact with the second nitride semiconductor layer in a second direction. The first layer is any of an insulator, an intrinsic semiconductor, and a semiconductor having a conductivity type opposite to that of the second nitride semiconductor layer, and a two-dimensional carrier gas is suppressed from being induced in the first nitride semiconductor layer facing the first layer in the first direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] In a communication system using wireless communication such as satellite communication, a semiconductor device that operates at high frequency with high output is employed. A transistor using a nitride semiconductor is employed as the semiconductor device, and the performance of the semiconductor device is improved.

[0003] In a transistor using a nitride semiconductor, two kinds of compound semiconductors having different band gaps form a heterojunction. A two-dimensional carrier gas (2DCG) is induced at the interface of the heterojunction (hereinafter referred to as "hetero interface"). The two-dimensional carrier gas is a general term for a two-dimensional electron gas (2DEG) and a two-dimensional hole gas (2DHG).

[0004] A high electron mobility transistor (hereinafter referred to as "HEMT") utilizes the two-dimensional carrier gas. The HEMT is high in output and operates at high frequency.

[0005] In recent years, along with the digitization of communication and the rise in bit rate, low distortion of a communication system is required. In order to cope with the above-mentioned requirement, not only a distortion compensation circuit needs to be applied, but also the improvement of the linearity of the HEMT itself is required.

[0006] The transconductance of the HEMT has a nonlinearity in which it temporarily increases as the drain current increases, and rapidly decreases after reaching a peak value. When the gate length of the HEMT is shortened for the purpose of high frequency, the nonlinearity increases. In order to solve the increase in the above-mentioned nonlinearity, various studies are made using technologies developed in a semiconductor device using silicon.

[0007] For example, in Non-Patent Literature 1, a configuration is disclosed in which a plurality of gate electrodes each having a columnar shape are arranged in one direction and buried in an epitaxial layer in which a hetero interface is formed. In Patent Literature 4, a similar configuration is also disclosed. In the configuration (hereinafter referred to as "buried gate arrangement configuration"), a plurality of gate electrodes each having a columnar shape are arranged in one direction and buried in an epitaxial layer in which a hetero interface is formed. The plurality of gate electrodes are connected to each other at a position away from the epitaxial layer. In the buried gate arrangement configuration, a depletion layer spreads to the side surface and the bottom surface of the buried gate electrodes, and a channel is turned off in the epitaxial layer between the buried gate electrodes.

[0008] For example, in Patent Literature 1, Patent Literature 2, and Patent Literature 3, a configuration in which a channel is narrowed (hereinafter referred to as "narrow channel configuration") is disclosed. In the narrow channel configuration, a gate electrode is formed in adhesion on an epitaxial layer that is processed in a thin line shape. In the narrow channel configuration, the area of the epitaxial layer that contacts the source electrode and the drain electrode is small, and the contact resistance is large. The length of the epitaxial layer in the direction connecting the drain electrode and the source electrode is shortened, and the contact resistance is reduced.

[0009] Prior Art Documents

[0010] Patent Literature

[0011] Patent Literature 1: Japanese Patent Application Publication No. 2009-212291

[0012] Patent Literature 2: Japanese Patent Application Publication No. 2016-512927

[0013] Patent Literature 3: Japanese Patent Application Publication No. H5-275436

[0014] Patent Literature 4: Japanese Patent Application Publication No. 2020-526921

[0015] Non-Patent Literature

[0016] Non-Patent Literature 1: K. Shinohara et. al, "GaN-Based Field-Effect Transistors With Laterally Gated Two-Dimensional Electron Gas", IEEE Electron Device Lett. 39-3, 417, 2018. SUMMARY

[0017] In a transistor having a gate electrode, it is preferable to moderate the concentration of an electric field (electric field concentration) in the vicinity of the gate electrode from the viewpoint of the withstand voltage of the transistor. In this moderation, a so-called field plate configuration is used, for example. The field plate configuration is considered to increase the electrostatic capacitance between the gate electrode and other electrodes (for example, the gate-drain capacitance and the gate-source capacitance).

[0018] The semiconductor device disclosed herein comprises: a semiconductor layer group including a first nitride semiconductor layer and a second nitride semiconductor layer stacked in a first direction; a plurality of gate electrodes each contacting the second nitride semiconductor layer in a second direction different from the first direction and arranged along the second direction; a conductor electrically connecting the plurality of gate electrodes to each other and located away from the semiconductor layer group; a source electrode opposing the plurality of gate electrodes in a third direction different from both the first and second directions and electrically connected to the first nitride semiconductor layer; a drain electrode opposing the source electrode in the third direction with the plurality of gate electrodes interposed therebetween and electrically connected to the first nitride semiconductor layer; and a first layer located between the plurality of gate electrodes and the drain electrode in the third direction and in contact with the plurality of gate electrodes, and in contact with the second nitride semiconductor layer in the second direction. The first nitride semiconductor layer and the second nitride semiconductor layer form a heterojunction, generating a two-dimensional carrier gas in the first nitride semiconductor layer. The first nitride semiconductor layer and the second nitride semiconductor layer form a Schottky junction with each of the plurality of gate electrodes. The first layer is any one of an insulator, an intrinsic semiconductor, and a semiconductor having a conductivity type opposite to that of the second nitride semiconductor layer, and suppresses the generation of a two-dimensional carrier gas in the first nitride semiconductor layer that opposes the first layer in the first direction.

[0019] Provided is a semiconductor device with high withstand voltage.

[0020] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a perspective view illustrating the structure of the semiconductor device according to the first embodiment.

[0022] Figure 2 This is a plan view illustrating the structure of the semiconductor device according to the first embodiment.

[0023] Figure 3 This is an example Figure 2 1 is a cross-sectional view of the semiconductor device according to the first embodiment at position AA.

[0024] Figure 4 This is an example Figure 2 1 is a cross-sectional view of the semiconductor device according to the first embodiment at position BB.

[0025] Figure 5 This is an example Figure 2 1 is a cross-sectional view of the semiconductor device of Embodiment 1 at position CC.

[0026] Figure 6 is a top view illustrating a structure of the semiconductor device of Embodiment 2.

[0027] Figure 7 is a sectional view of a cross section of the semiconductor device of Embodiment 2 at a position AA. Figure 6

[0028] Figure 8 is a top view illustrating a structure of the semiconductor device of Embodiment 3.

[0029] Figure 9 is a sectional view of a cross section of the semiconductor device of Embodiment 3 at a position AA. Figure 8

[0030] Figure 10 is a top view illustrating a structure of the semiconductor device of Embodiment 4.

[0031] Figure 11 is a sectional view of a cross section of the semiconductor device of Embodiment 4 at a position AA. Figure 10

[0032] Figure 12 is a top view illustrating a structure of the semiconductor device of Embodiment 5.

[0033] Figure 13 is a sectional view of a cross section of the semiconductor device of Embodiment 5 at a position AA. Figure 12

[0034] Figure 14 is a top view illustrating a structure of the semiconductor device of Embodiment 6.

[0035] Figure 15 is a sectional view of a cross section of the semiconductor device of Embodiment 6 at a position AA. Figure 14

[0036] Figure 16 is a top view illustrating a structure of the semiconductor device of Embodiment 7.

[0037] Figure 17 is a sectional view of a cross section of the semiconductor device of Embodiment 7 at a position AA. Figure 16

[0038] Figure 18 is a top view illustrating a structure of the semiconductor device of Embodiment 8.

[0039] Figure 19 is a sectional view of a cross section of the semiconductor device of Embodiment 8 at a position AA. Figure 18 ​​​​​​​

[0040] Figure 20 is a cross-sectional view of a cross section of the semiconductor device of Embodiment 8 at a position CC. Figure 18

[0041] Figure 21 is a plan view of a configuration of the semiconductor device of Embodiment 9.

[0042] Figure 22 is a cross-sectional view of a cross section of the semiconductor device of Embodiment 9 at a position AA. Figure 21

[0043] Figure 23 is a cross-sectional view of a cross section of the semiconductor device of Embodiment 9 at a position BB. Figure 21

[0044] Figure 24 is a cross-sectional view of a cross section of the semiconductor device of Embodiment 9 at a position CC. Figure 21

[0045] Figure 25 is a cross-sectional view of a configuration of the semiconductor device of Embodiment 10.

[0046] Figure 26 is a cross-sectional view of a configuration of a modification of the semiconductor device of Embodiment 10.

[0047] Figure 27 is a cross-sectional view of a configuration of the semiconductor device of Embodiment 11.

[0048] Figure 28 is a graph of a band configuration of the semiconductor device of Embodiment 12.

[0049] Figure 29 is a plan view of a gate electrode.

[0050] (Symbol Explanation)

[0051] 2, 3, 21 to 23, 31 to 33: nitride semiconductor layer; 4: semiconductor layer group; 5: source electrode; 6: drain electrode; 8: gate electrode; 9: conductor; 10: 1st layer; 12: 2nd layer; 13: 3rd layer; 101 to 111: semiconductor device; X, Y, Z: direction. DETAILED DESCRIPTION

[0052] As for any one of the semiconductor devices exemplified in the following embodiments, a main part of a field effect transistor is exemplified. The field effect transistor is utilized by forming an element isolation region, a wiring connected to an electrode, a via, in addition to the following disclosure. The exemplification in the following embodiments does not exclude application of the semiconductor device related to the present disclosure to an element other than the field effect transistor.​​​​

[0053] Implementation method 1.

[0054] [Structure and Action]

[0055] Figure 1 1 is a perspective view illustrating the structure of the semiconductor device 101 according to the first embodiment. Figure 1 The directions X, Y, and Z mentioned in the figure are different from each other, and any plane parallel to the directions X and Y is not parallel to the direction Z. In the present disclosure, the case where the directions X, Y, and Z are orthogonal to each other is exemplified.

[0056] For the sake of convenience, the second element located in the direction Z side when viewed from the first element is described as being above the first element. The first element is described as being below the second element. In this disclosure, "above" and "below" are terms that indicate the relative positional relationship of constituent elements, and are not necessarily terms based on the direction of gravity. Figure 1 2 , a cross section of the semiconductor device 101 perpendicular to the direction Y and a cross section perpendicular to the direction X are illustrated.

[0057] Hereinafter, the length along the direction X may be simply referred to as “length”, the length along the direction Y may be referred to as “width”, and the length along the direction Z may be referred to as “thickness”.

[0058] Figure 2 It is a plan view illustrating the structure of the semiconductor device 101 . Figure 2 is Figure 1 1 is a plan view of the semiconductor device 101 as viewed in a direction opposite to the direction Z in the range illustrated in FIG.

[0059] Figure 3 This is an example Figure 2 1 is a cross-sectional view of the semiconductor device 101 at position AA. Figure 4 This is an example Figure 2 1 is a cross-sectional view of the semiconductor device 101 at position BB. Figure 5 This is an example Figure 2 1 is a cross-sectional view of the semiconductor device 101 at position CC.

[0060] Semiconductor device 101 includes a semiconductor layer group 4, a source electrode 5, a drain electrode 6, a gate electrode 8, a conductor 9, and a first layer 10. Semiconductor layer group 4 includes nitride semiconductor layers 2 and 3 stacked along direction Z. Nitride semiconductor layers 2 and 3 are, for example, epitaxial layers grown epitaxially on substrate 1. In this disclosure, substrate 1 is described as being included in semiconductor layer group 4.

[0061] The semiconductor device 101 further includes a protective film 14. Figure 1 、 Figure 2The protective film 14 is omitted from the illustration. In Figure 2 The conductor 9 is depicted by a double-dot chain line.

[0062] The number of the gate electrodes 8 is plural, and they are arranged in the direction Y. Each of the gate electrodes 8 contacts the nitride semiconductor layer 3 in the direction Y. The gate electrodes 8 have faces 8c, 8d, for example. The face 8c appears on the direction Y side of the gate electrode 8 having the face 8c. The face 8d appears on the side opposite to the direction Y of the gate electrode 8 having the face 8d. The gate electrodes 8 have a face 8e, which appears on the side opposite to the direction Z of the gate electrode 8 having the face 8e. It is also possible to leave a groove 7 in which a part of the gate electrode 8 is buried in the semiconductor layer group 4.

[0063] In the present disclosure, each of the gate electrodes 8 reaches the nitride semiconductor layer 2 by penetrating the nitride semiconductor layer 3 in the direction opposite to the direction Z. In this case, the faces 8c, 8d also contact the nitride semiconductor layer 2 in the direction Y.

[0064] The conductor 9 is located away from the semiconductor layer group 4. The conductor 9 electrically connects the gate electrodes 8 to each other. In the present disclosure, the conductor 9 has a shape extending in the direction Y on the upper side of the semiconductor layer group 4.

[0065] The source electrode 5 opposes the gate electrode 8 in the direction X. The drain electrode 6 opposes the source electrode 5 across the gate electrode 8 in the direction X. The source electrode 5, the gate electrode 8, and the drain electrode 6 are arranged in this order in the direction X. The gate electrode 8 has a face 8b on the source electrode 5 side. The gate electrode 8 has a face 8a on the drain electrode 6 side.

[0066] The source electrode 5 and the drain electrode 6 are in communication with the nitride semiconductor layer 2. The case where the source electrode 5 and the drain electrode 6 reach the nitride semiconductor layer 2 by penetrating the nitride semiconductor layer 3 from the upper side of the nitride semiconductor layer 3 in the semiconductor device 101 is illustrated.

[0067] The number of the first layers 10 is plural, and they exist in correspondence with the gate electrodes 8. The first layer 10 is located between the gate electrode 8 and the drain electrode 6 in the direction X and contacts the gate electrode 8. In the semiconductor device 101, the first layer 10 contacts the face 8a and the drain electrode 6. The first layer 10 contacts the nitride semiconductor layer 3 in the direction Y.

[0068] The case where the first layer 10 reaches the nitride semiconductor layer 2 by penetrating the nitride semiconductor layer 3 from the upper side of the nitride semiconductor layer 3 in the semiconductor device 101 is illustrated. In the drawing, a shape in which the first layer 10 protrudes to the direction Z side than the nitride semiconductor layer 3 is exemplified, but the above-mentioned protrusion is not necessarily required.

[0069] The first layer 10 has a function of relaxing the electric field concentration as described later. The first layer 10 is an insulator, for example.

[0070] The nitride semiconductor layer 2 and the nitride semiconductor layer 3 form a heterojunction. The nitride semiconductor layers 2, 3 form a Schottky junction with the gate electrode 8.

[0071] By forming the heterojunction, a two-dimensional carrier gas is induced in the nitride semiconductor layer 2 side at a heterointerface between the nitride semiconductor layer 2 and the nitride semiconductor layer 3. This two-dimensional carrier gas is used for a current (so-called "drain current") flowing between the source electrode 5 and the drain electrode 6 in the semiconductor device 101. The current is controlled by a relationship of voltages applied between the source electrode 5, the drain electrode 6, and the gate electrode 8. The above-mentioned control is known per se, and will not be described in detail in the present disclosure.

[0072] Hereinafter, a case where the two-dimensional carrier gas is a two-dimensional electron gas will be described as an example unless specifically described. For example, the nitride semiconductor layer 2 and the nitride semiconductor layer 3 both have an n-type conduction type.

[0073] In the semiconductor device 101, a plurality of gate electrodes 8 are arranged so as to be connected to each other by a conductor 9. Electrons moving from the source electrode 5 pass between the gate electrodes 8 adjacent in the direction Y along the direction X, and go to the drain electrode 6.

[0074] In the nitride semiconductor layers 2, 3 sandwiched by the gate electrodes 8 in the direction Y, a depletion layer due to the Schottky junction is formed. The width of the depletion layer is controlled by a voltage applied between the gate electrode 8 and the source electrode 5. Controlling the width of the depletion layer contributes to control of the drain current. When the semiconductor device 101 is used as a switching element, the semiconductor device 101 is turned on / off by controlling the width of the depletion layer.

[0075] For example, when a voltage negative with respect to the source electrode 5 (hereinafter also simply referred to as "negative voltage") is applied to the gate electrode 8, the depletion layer spreads from the surfaces 8b, 8c, 8d, 8e of the gate electrode 8 toward the nitride semiconductor layers 2, 3. By the spread of the depletion layer, a channel in the nitride semiconductor layers 2, 3 sandwiched by the gate electrodes 8 in the direction Y is shut off, and the semiconductor device 101 becomes off.

[0076] Discretely arranging the gate electrodes 8 in the direction Y contributes to reduction of a gate-drain capacitance and a gate-source capacitance of the semiconductor device 101. The reduction improves linearity of operation of the semiconductor device 101.

[0077] In the region opposite to the first layer 10 in the direction Z, the generation of two-dimensional electron gas in the nitride semiconductor layer 2 is suppressed. By the above suppression, the distance supporting the voltage between the gate electrode 8 and the drain electrode 6 substantially becomes longer. The longer the distance, the smaller the electric field between the gate electrode 8 and the drain electrode 6, and the more gentle the electric field concentration on the drain electrode 6 side of the gate electrode 8.

[0078] The first layer 10 mitigates the electric field concentration on the drain electrode 6 side of the gate electrode 8. The above mitigation contributes to the improvement of the withstand voltage of the semiconductor device 101. The improvement of the withstand voltage contributes to the improvement of the output power of the semiconductor device 101. There is a region where the first layer 10 exists between the nitride semiconductor layer 2 and the gate electrode 8, so the reduction of the leakage current (so-called "gate leakage current") in the gate electrode 8 of the semiconductor device 101 is also contributed.

[0079] When the generation of two-dimensional electron gas in the nitride semiconductor layer 2 is suppressed, the gate-drain capacitance and the source-drain capacitance are reduced. The reduction of these static capacitances contributes to the improvement of the drain efficiency and the power load efficiency.

[0080] The first layer 10 is disposed between the gate electrode 8 and the drain electrode 6 in the direction X. The first layer 10 does not need to be arranged in the direction Y in alignment with the gate electrode 8. The drain current flows through the nitride semiconductor layer 2 by the two-dimensional electron gas in the nitride semiconductor layer 2 in the region (for example, the position BB) sandwiched by the gate electrode 8 arranged in the direction Y. Even if the first layer 10 does not exist in the region, the first layer 10 mitigates the electric field concentration on the drain electrode 6 side of the gate electrode 8. The freedom of the correlation with the position of the first layer 10 is easy to avoid the reduction of the drain current. The possibility that the first layer 10 is located between the gate electrode 8 and the drain electrode 6 in the direction X and contacts the gate electrode 8 results in the degradation of the drain current of the semiconductor device 101 is small. When the first layer 10 is arranged in the direction Y in alignment with the gate electrode 8, it can hinder the switching of the on / off of the transistor.

[0081] The protective film 14 covers the semiconductor layer group 4. The protective film 14 contributes to the difficulty of the semiconductor device 101 to be affected from the outside of the semiconductor device 101. The protective film 14 exposes a part of the upper side of each of the source electrode 5, the drain electrode 6, and the gate electrode 8. Above the protective film 14, the conductor 9 connects the plurality of gate electrodes 8 to each other. It is also possible that the protective film 14 also covers the conductor 9. The substrate 1 and the protective film 14 are not necessarily essential in the operation of the semiconductor device 101.

[0082] In the narrow channel structure shown in Patent Document 1, Patent Document 2, and Patent Document 3, in addition to the gate structure using the Schottky junction, the MIS (Metal-Insulator-Semiconductor) gate structure is also proposed.

[0083] In the MIS gate structure, an insulating film is provided between the gate electrode and the semiconductor layer. In general, in a transistor employing the MIS gate structure, the gate leakage current is reduced. In addition, in the MIS gate structure, in a transistor employing the structure, a contribution is made to the enlargement of the range of the gate voltage in which the forward direction is controlled. The above contribution improves the power output of the transistor.

[0084] In the buried gate arrangement structure of Non-Patent Literature 1, when the MIS gate structure is employed, the depletion layer does not spread in the side direction of the gate electrode, and the transistor does not operate.

[0085] In the semiconductor device 101 of Embodiment 1, the gate electrode 8 forms a Schottky junction between the nitride semiconductor layers 2, 3. The semiconductor device 101 spreads the depletion layer in the direction Y in which the gate electrode 8 is arranged, and has a structure different from the MIS structure of the narrow channel structure.

[0086] The drain electrode 6 side of the gate electrode 8 is in contact with the first layer 10, and is a structure different from both the buried gate arrangement structure of Non-Patent Literature 1. The first layer 10 contributes to the reduction of the gate leakage current.

[0087] [Variation of the Structure]

[0088] It is also possible that other nitride semiconductor layers exist in any region between the nitride semiconductor layer 2 and the nitride semiconductor layer 3, between the substrate 1 and the nitride semiconductor layer 2, and on the nitride semiconductor layer 3 on the side opposite to the nitride semiconductor layer 2 (the direction Z side of the nitride semiconductor layer 3).

[0089] For example, a nitride semiconductor layer having AlN (aluminum nitride) as a base material is arranged as a spacer layer between the nitride semiconductor layer 2 and the nitride semiconductor layer 3. For example, a nitride semiconductor layer having AlN as a base material is arranged as a nucleation layer between the substrate 1 and the nitride semiconductor layer 2. For example, a nitride semiconductor layer having GaN as a base material is arranged as a cap layer on the nitride semiconductor layer 3.

[0090] The two-dimensional electron gas moves and flows through the drain current. The two-dimensional electron gas flows through the nitride semiconductor layer 2. The source electrode 5 and the drain electrode 6 are in conduction with the nitride semiconductor layer 2, and do not need to penetrate the nitride semiconductor layer 3. For example, the source electrode 5 can be located on the nitride semiconductor layer 3. In this case, for example, the nitride semiconductor layers 2, 3 are doped to have a concentration at which an ohmic contact can be obtained between the nitride semiconductor layers 2, 3 and the source electrode 5. With respect to the drain electrode 6, the same arrangement and doping can be employed.

[0091] The first layer 10 need not penetrate the nitride semiconductor layer 3. The suppression of the two-dimensional electron gas in the nitride semiconductor layer 2 in the region opposite the first layer 10 is premised on the first layer 10 not being in contact with the nitride semiconductor layer 2.

[0092] For example, there can be a case where the first layer 10 also contacts at least the nitride semiconductor layer 3 in the direction Y without contacting the nitride semiconductor layer 2. If the two-dimensional electron gas is suppressed in the semiconductor layer group 4 side (the side opposite the direction Z) with respect to the first layer 10, a function of mitigating the concentration of the electric field by the first layer 10 can be obtained. Even if the nitride semiconductor layer 3 is interposed between the first layer 10 and the nitride semiconductor layer 2 in the direction Z, the two-dimensional electron gas is sometimes suppressed in the nitride semiconductor layer 2 by the nitride semiconductor layer 3 being thin.

[0093] As exemplified by the semiconductor device 101, the contact of the first layer 10 with the nitride semiconductor layer 2 contributes to the suppression of the two-dimensional electron gas in the nitride semiconductor layer 2 in the region opposite the first layer 10.

[0094] From the viewpoint of suppressing the two-dimensional electron gas, it is advantageous for the first layer 10 to exist below (the side opposite the direction Z) the position in the direction Z at which the two-dimensional electron gas is induced in the region where the first layer 10 is not formed, for example, the position BB.

[0095] The gate electrode 8 need not penetrate the nitride semiconductor layer 3. For example, the nitride semiconductor layer 3 can be interposed between the gate electrode 8 and the nitride semiconductor layer 2. Even in this case, the depletion layer extends along the direction Y by applying a negative voltage to the gate electrode 8.

[0096] As exemplified by the semiconductor device 101, the extension of the gate electrode 8 to below the two-dimensional electron gas contributes to the ease of contact of the depletion layers adjacent in the direction Y with each other.

[0097] [Specifications of Constituent Elements]

[0098] As examples of the material of the substrate 1, SiC (silicon carbide), Si, GaN (gallium nitride), AlN, sapphire, for example, can be given.

[0099] As examples of the material of the nitride semiconductor layers 2, 3, In x Al y Ga (1-x-y)N (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). The nitride semiconductor can be undoped, or can have a p-type conductivity type or an n-type conductivity type. For example, ion implantation of silicon into the nitride semiconductor for the purpose of adding an n-type conductivity type is performed, and heat treatment is performed to activate the silicon as a donor. The composition of the compound of the nitride semiconductor, and the concentration of the doping do not need to be constant with respect to the position, and can continuously or stepwise vary.

[0100] The configuration in which the nitride semiconductor layer 2 and the nitride semiconductor layer 3 are stacked is a configuration in which a two-dimensional electron gas is generated by a heterojunction. As an example of the material of the nitride semiconductor layer 2, GaN can be given, and as an example of the material of the nitride semiconductor layer 3, AlGaN can be given. 0.25 Ga 0.75 N.

[0101] The thickness of the nitride semiconductor layer 2 is a thickness that is sufficient for electrons to flow therethrough. For example, the thickness of the nitride semiconductor layer 2 is 200 nm. The thickness of the nitride semiconductor layer 3 is a thickness that is sufficient for the nitride semiconductor layer 2 to cause a two-dimensional electron gas. For example, the thickness of the nitride semiconductor layer 3 is 15 nm.

[0102] The distance between the source electrode 5 and the drain electrode 6 in the direction X is, for example, 2.0 μm.

[0103] An ohmic contact can be obtained in any region between the source electrode 5 and the semiconductor layer group 4, and between the drain electrode 6 and the semiconductor layer group 4, which contributes to a reduction in the on-resistance of the semiconductor device 101. For example, the source electrode 5 and the drain electrode 6 are each formed using a single layer or a stack that includes a metal exemplified by Ti, Al, and Au.

[0104] For example, the gate electrode 8 and the conductor 9 are each formed using a single layer or a stack that includes a metal exemplified by Ni, Pt, and Au.

[0105] The interval between the gate electrodes 8 in the direction Y, and the thickness of the gate electrode 8 are set so that, when a negative voltage is applied to the gate electrodes 8, the depletion layers that are adjacent to each other in the direction Y come into contact with each other.

[0106] For example, the gate electrode 8 is a square in plan view, the width and the length of the gate electrode 8 are each 150 nm, and the thickness of the portion that contacts the semiconductor layer group 4 is 60 nm. For example, the interval between the gate electrodes 8 in the direction Y is 250 nm. The interval at which the plurality of gate electrodes 8 are arranged in the direction Y can not be equal to each other.

[0107] If the plurality of gate electrodes 8 are arranged at equal intervals, when forming the trench 7 in the semiconductor layer group 4, for example, it is easy to make a mask used in photolithography. The above-described easiness contributes to the improvement of uniformity with respect to the configuration of the gate electrode 8.

[0108] The width of the first layer 10 can also be wider than the width of the gate electrode 8. The width of the first layer 10 being the same as or smaller than the width of the gate electrode 8 contributes to a large drain current.

[0109] In the portion in contact with the semiconductor layer group 4, the thickness of the first layer 10 and the thickness of the gate electrode 8 can be either of them larger or equal to each other.

[0110] The first layer 10 in the semiconductor device 101 is in contact not only with the gate electrode 8 but also with the drain electrode 6. The length of the first layer 10 is, for example, 1.5 μm. The width of the first layer 10 is, for example, 150 nm. The first layer 10 is arranged at intervals of, for example, 250 nm in the direction Y. In the portion in contact with the semiconductor layer group 4, the thickness of the first layer 10 is, for example, 60 nm.

[0111] As the material of the first layer 10, an insulator is adopted to contribute to the relaxation of the concentration of the electric field described above. As the material of the first layer 10, for example, Al2O3, SiN (silicon nitride), SiO2 is exemplified. Air can also be adopted in the first layer 10.

[0112] Alternatively, the first layer 10 can also be obtained by making the conductivity of the surface on the direction Z side of the semiconductor layer group 4 lost. For example, by injecting Ar in the semiconductor layer group 4, it is possible to make the conductivity of the nitride semiconductor layer 3 or further the nitride semiconductor layer 2 lost and change them to an insulator.

[0113] As long as it is a material that suppresses the occurrence of two-dimensional electron gas in the nitride semiconductor layer 2 in the region opposite to the first layer 10, it can be used as the first layer 10. From the above-described viewpoint, the first layer 10 can also be formed by a semiconductor having the same conductivity type as the nitride semiconductor layer 3. For example, it is also possible to adopt a nitride semiconductor layer having the same conductivity type as the nitride semiconductor layer 3 but a lower doping concentration in the first layer 10.

[0114] However, the effect of making it difficult to cause two-dimensional electron gas is higher in the case where an insulator, a semiconductor having the opposite conductivity type to the nitride semiconductor layer 3, or an intrinsic semiconductor is adopted in the first layer 10 than in the case where a semiconductor having the same conductivity type as the nitride semiconductor layer 3 is adopted in the first layer 10. With respect to the case where a semiconductor having the opposite conductivity type to the nitride semiconductor layer 3 is adopted in the first layer 10, the description is also made in Embodiment 12.

[0115] When a conductor is used in the first layer 10, even if a two-dimensional electron gas is not generated in the nitride semiconductor layer 2, the effect of alleviating electric field concentration is small. It is believed that when a conductor is used in the first layer 10, the first layer 10 is electrically connected to the gate electrode 8, essentially functioning as the gate electrode 8. When a conductor is used in the first layer 10, the gate electrode 8 and the drain electrode 6 are electrically connected. This electrical connection hinders the operation of the transistor.

[0116] As with the gate electrode 8, at least a portion of the first layer 10 can be buried in the semiconductor layer group 4. For example, the first layer 10 can be formed by forming a trench in the semiconductor layer group 4 and then performing a buildup process to fill the trench. For example, the trench can be formed in parallel with the trench 7. This parallel formation contributes to reducing damage to the semiconductor layer group 4. Either the first layer 10 or the gate electrode 8 can be formed first.

[0117] For example, the gate electrode 8 and the conductor 9 can be formed by sputtering. For example, the gate electrode 8 and the conductor 9 can be formed by chemical vapor deposition (CVD).

[0118] The protective film 14 has insulating properties and contributes to preventing short circuits between the source electrode 5, the drain electrode 6, and the gate electrode 8. Examples of materials for the protective film 14 include SiN, Al2O3, SiO2, and resins. The protective film 14 does not need to be a single layer. The protective film 14 may be a laminated film comprising a first film that suppresses surface traps in the nitride semiconductor layer 3 and a second film disposed on the first film to provide moisture resistance.

[0119] Implementation method 2.

[0120] Figure 6 This is a plan view illustrating the structure of the semiconductor device 102 according to the second embodiment. Figure 6 The semiconductor device 101 is shown in FIG. Figure 2 The same range as the range exemplified in . Figure 6 In, record together with Figure 2 The positions AA, BB, CC shown in the example are the same as the positions AA, BB, CC. Figure 6 Illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a two-dot chain line.

[0121] Figure 7 This is an example Figure 6 1 is a cross-sectional view of the semiconductor device 102 at position AA. Figure 6 The cross section of the semiconductor device 102 at position BB is different from that at Figure 4 The cross section of the semiconductor device 101 shown in FIG. 1 appears similarly. Figure 6 The cross section of the semiconductor device 102 at position CC is different from that atFigure 5 The cross section of the semiconductor device 101 shown in FIG. 1 is similarly present.

[0122] The semiconductor device 102 has a configuration in which the second layer 12 is added to the semiconductor device 101.

[0123] The number of the second layers 12 is plural, and exists corresponding to the gate electrode 8. The second layer 12 is located between the gate electrode 8 and the source electrode 5 in the direction X and contacts the gate electrode 8. The second layer 12 contacts the surface 8b and the source electrode 5 in the semiconductor device 102. The second layer 12 contacts the nitride semiconductor layer 3 in the direction Y.

[0124] FIG. 1 illustrates a case where the second layer 12 reaches the nitride semiconductor layer 2 from above the nitride semiconductor layer 3 through the nitride semiconductor layer 3 in the semiconductor device 102. In the drawing, a shape is exemplified in which the second layer 12 protrudes to the direction Z side than the nitride semiconductor layer 3, but the above protrusion is not necessarily required.

[0125] The second layer 12 is formed of, for example, an insulator or a semiconductor similarly to the first layer 10. The semiconductor is preferably an intrinsic semiconductor or has a conduction type opposite to that of the nitride semiconductor layer 3 similarly to the first layer 10.

[0126] The position of the second layer 12 in the direction Z can also be selected similarly to the position of the first layer 10 in the direction Z. For example, the second layer 12 and the nitride semiconductor layer 2 can sandwich the nitride semiconductor layer 3 in the direction Z. The second layer 12 can also penetrate the nitride semiconductor layer 3 in the direction Z and contact the nitride semiconductor layer 2. The second layer 12 can exist below the position of the two-dimensional electron gas in the direction Z caused by a region where the second layer 12 is not formed, for example, the position BB. The position of the second layer 12 in the direction Z can also be different from the position of the first layer 10 in the direction Z.

[0127] In a region opposite to the second layer 12 in the direction Z, the two-dimensional electron gas is suppressed from being caused in the nitride semiconductor layer 2. The above suppression reduces the gate-source capacitance and the source-drain capacitance. The reduction of these electrostatic capacitances contributes to improvement of the drain efficiency and the power load efficiency.

[0128] For example, when a charged human body contacts the semiconductor device 102 (for example, refer to the human body model (HBM) JEDEC standard JESD22-A114 in the electrostatic breakdown test), electrostatic discharge (ESD) occurs. The electrostatic discharge causes an increase in the electric field in the source electrode 5. The second layer 12 mitigates the electric field concentration on the source electrode 5 side of the gate electrode 8. The above mitigation contributes to reduction in the possibility of electrostatic discharge of the semiconductor device 102.

[0129] The second layer 12, like the first layer 10, mitigates the electric field concentration on the source electrode 5 side of the gate electrode 8 even in a region (for example, the position BB) that is not present between the gate electrodes 8 arranged in the direction Y. The associated freedom of the position of the second layer 12 easily avoids the reduction of the drain current. The possibility of the degradation of the drain current of the semiconductor device 102 is small because the second layer 12 is located between the gate electrode 8 and the source electrode 5 in the direction X and in contact with the gate electrode 8.

[0130] As the material of the second layer 12, for example, the examples exemplified as the material of the first layer 10 are adopted. The material of the first layer 10 and the material of the second layer 12 need not be consistent. The consistency of the material of the first layer 10 and the material of the second layer 12 contributes to easily forming the first layer 10 and the second layer 12.

[0131] Embodiment 3.

[0132] Figure 8 is a plan view that exemplifies the configuration of the semiconductor device 103 of Embodiment 3. Figure 8 The same range as that exemplified in Embodiment 1 is exemplified in Embodiment 3. In Embodiment 3, the same positions AA, BB, CC as those exemplified in Embodiment 1 are collectively described. In Embodiment 3, the illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a double dotted line. Figure 2 The same range as that exemplified in Embodiment 1 is exemplified in Embodiment 3. In Embodiment 3, the same positions AA, BB, CC as those exemplified in Embodiment 1 are collectively described. In Embodiment 3, the illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a double dotted line. Figure 8 The same range as that exemplified in Embodiment 1 is exemplified in Embodiment 3. In Embodiment 3, the same positions AA, BB, CC as those exemplified in Embodiment 1 are collectively described. In Embodiment 3, the illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a double dotted line. Figure 2 The same range as that exemplified in Embodiment 1 is exemplified in Embodiment 3. In Embodiment 3, the same positions AA, BB, CC as those exemplified in Embodiment 1 are collectively described. In Embodiment 3, the illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a double dotted line. Figure 8 The same range as that exemplified in Embodiment 1 is exemplified in Embodiment 3. In Embodiment 3, the same positions AA, BB, CC as those exemplified in Embodiment 1 are collectively described. In Embodiment 3, the illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a double dotted line.

[0133] Figure 9 is a cross-sectional view that exemplifies the cross section of the semiconductor device 103 at the position AA of Figure 8 is a cross-sectional view that exemplifies the cross section of the semiconductor device 103 at the position AA of Figure 8 The cross section of the semiconductor device 103 at the position BB is the same as that of the semiconductor device 101 shown in Embodiment 1. Figure 4 The cross section of the semiconductor device 103 at the position CC is the same as that of the semiconductor device 101 shown in Embodiment 1. Figure 8 The cross section of the semiconductor device 103 at the position CC is the same as that of the semiconductor device 101 shown in Embodiment 1. Figure 5 The cross section of the semiconductor device 103 at the position CC is the same as that of the semiconductor device 101 shown in Embodiment 1.

[0134] The semiconductor device 103 is different from the semiconductor device 101 in that the length of the first layer 10 is shorter than the distance between the gate electrode 8 and the drain electrode 6. In the semiconductor device 103, the first layer 10 and the drain electrode 6 sandwich the nitride semiconductor layers 2, 3 along the direction X.

[0135] The electrons in the semiconductor device 101 that move from the gate electrode 8 toward the drain electrode 6 between the first layers 10 that are adjacent in the direction Y move between the first layers 10 that are adjacent in the direction Y. The electrons in the semiconductor device 103 that move from the gate electrode 8 toward the drain electrode 6 not only move between the first layers 10 that are adjacent in the direction Y but also move in the region sandwiched by the first layers 10 and the drain electrode 6. The semiconductor device 103 has a wider region of the two-dimensional electron gas that contributes to the drain current than the semiconductor device 101, and a larger drain current can be obtained. The large drain current increases the power of the transistor output achieved by the semiconductor device 101, and improves the efficiency.

[0136] Embodiment 4.

[0137] Figure 10 is a plan view that illustrates the configuration of the semiconductor device 104 of Embodiment 4. Figure 10 Embodiment 4 is illustrated in the same range as that illustrated in Figure 2 Embodiment 4 is illustrated in the same range as that illustrated in Figure 10 Embodiment 4 is illustrated in the same range as that illustrated in Figure 2 Embodiment 4 is illustrated in the same range as that illustrated in Figure 10 The illustration of the protective film 14 is omitted in

[0138] Figure 11 is a cross-sectional view that illustrates the cross section of the semiconductor device 104 at the position AA of Figure 10 Embodiment 4 is illustrated in the same range as that illustrated in Figure 10 The cross section of the semiconductor device 104 at the position BB of Figure 4 Embodiment 4 is illustrated in the same range as that illustrated in Figure 10 The cross section of the semiconductor device 104 at the position CC of Figure 5 Embodiment 4 is illustrated in the same range as that illustrated in

[0139] The semiconductor device 104 differs from the semiconductor device 102 in that the length of the first layer 10 is shorter than the distance between the gate electrode 8 and the drain electrode 6 and the length of the second layer 12 is shorter than the distance between the gate electrode 8 and the source electrode 5.

[0140] The semiconductor device 104 has the configuration in which the second layer 12 is added to the semiconductor device 103. The second layer 12 is located between the gate electrode 8 and the source electrode 5 in the direction X and contacts the gate electrode 8. The second layer 12 contacts the surface 8b in the semiconductor device 104. The length of the second layer 12 is shorter than the distance between the gate electrode 8 and the source electrode 5. The above-described second layer 12 can also be added to the semiconductor device 101.

[0141] In the semiconductor device 104, the first layer 10 and the drain electrode 6 sandwich the nitride semiconductor layers 2, 3 along the direction X, and the second layer 12 and the source electrode 5 sandwich the nitride semiconductor layers 2, 3.

[0142] In the semiconductor device 102, electrons between the second layers 12 that abut each other in the direction Y from the source electrode 5 toward the gate electrode 8 move between each other. In the semiconductor device 104, electrons between the second layers 12 that abut each other in the direction Y from the source electrode 5 toward the gate electrode 8 move not only between each other but also in a region sandwiched by the second layer 12 and the drain electrode 6.

[0143] The semiconductor device 104 has a wider region of the two-dimensional electron gas that contributes to the drain current than the semiconductor device 102, and can obtain a larger drain current.

[0144] The semiconductor device 104 mitigates the concentration of the electric field on the source electrode 5 side of the gate electrode 8 compared to the semiconductor device 103.

[0145] Embodiment 5.

[0146] Figure 12 is a plan view that illustrates the configuration of the semiconductor device 105 of Embodiment 5. Figure 12 Embodiment 5 is illustrated in the same range as that in Figure 2 Embodiment 5 is illustrated in the same range as that in Figure 12 Embodiment 5 is illustrated in the same range as that in Figure 2 Embodiment 5 is illustrated in the same range as that in Figure 12 The illustration of the protective film 14 is omitted in

[0147] Figure 13 is a cross-sectional view that illustrates the cross section of the semiconductor device 105 at the position AA of Figure 12 Embodiment 5 is illustrated in the same range as that in Figure 12 The cross section of the semiconductor device 105 at the position BB of Figure 4 Embodiment 5 is illustrated in the same range as that in Figure 12 The cross section of the semiconductor device 105 at the position CC of Figure 5 Embodiment 5 is illustrated in the same range as that in

[0148] The semiconductor device 105 has a feature that the width of the drain electrode 6 side of the first layer 10 is narrower than the width of the gate electrode 8 side compared to the semiconductor device 103. The length of the first layer 10 along the direction Y decreases as it is away from the gate electrode 8 along the direction X. For example, the width of the first layer 10 coincides with the width of the surface 8a at a position in contact with the surface 8a, and becomes narrower as it is closer to the drain electrode 6.

[0149] In semiconductor device 105, similarly to semiconductor device 103, electrons traveling from source electrode 5 toward gate electrode 8 not only move between adjacent second layers 12 in direction Y but also move within the region sandwiched between second layer 12 and drain electrode 6. As these electrons travel from between gate electrodes 8 toward direction X, they spread and move in both direction Y and the direction opposite to direction Y. Compared to the first layer 10 in semiconductor device 104, first layer 10 in semiconductor device 105 is less likely to inhibit the spread of these electrons.

[0150] The semiconductor device 105 is less likely to hinder the movement of the two-dimensional electron gas that contributes to the drain current than the semiconductor device 103 , and can obtain a large drain current.

[0151] The first layer 10 may have a shape that tapers in a stepwise manner toward the direction X. From the perspective of widening the area where the electric field is concentrated and alleviating the concentration, it is advantageous to have the first layer 10 have a shape that tapers linearly or curvilinearly toward the direction X.

[0152] The structure in which the width of the first layer 10 on the drain electrode 6 side is narrower than the width on the gate electrode 8 side can be applied to any structure of the semiconductor devices 101 to 104 and contributes to obtaining a large drain current.

[0153] Implementation method 6.

[0154] Figure 14 This is a plan view illustrating the structure of the semiconductor device 106 according to the sixth embodiment. Figure 14 The semiconductor device 101 is shown in FIG. Figure 2 The same range as the range exemplified in . Figure 14 In, record together with Figure 2 The positions AA, BB, CC shown in the example are the same as the positions AA, BB, CC. Figure 14 Illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a two-dot chain line.

[0155] Figure 15 This is an example Figure 14 1 is a cross-sectional view of the semiconductor device 106 at position AA. Figure 14 The cross section of the semiconductor device 106 at position BB is different from that at Figure 4 The cross section of the semiconductor device 101 shown in FIG. 1 appears similarly. Figure 14 The cross section of the semiconductor device 106 at position CC is different from that at Figure 5 The cross section of the semiconductor device 101 shown in FIG. 1 appears similarly.

[0156] The semiconductor device 106 has a configuration in which the second layer 12 is added to the semiconductor device 105. The second layer 12 is located between the gate electrode 8 and the source electrode 5 in the direction X and is in contact with the gate electrode 8. The second layer 12 is in contact with the surface 8b in the semiconductor device 106. The length of the second layer 12 is shorter than the distance between the gate electrode 8 and the source electrode 5. The width of the source electrode 5 side of the second layer 12 is narrower than the width of the gate electrode 8 side.

[0157] The semiconductor device 106 has a feature in which the width of the drain electrode 6 side of the first layer 10 is narrower than the width of the gate electrode 8 side and the width of the source electrode 5 side of the second layer 12 is narrower than the width of the gate electrode 8 side, as compared with the semiconductor device 104.

[0158] The length of the first layer 10 in the direction Y decreases as it is away from the gate electrode 8 in the direction X. For example, the width of the first layer 10 coincides with the width of the surface 8a at the position in contact with the surface 8a and becomes narrower as it is closer to the drain electrode 6.

[0159] The length of the second layer 12 in the direction Y increases as it is closer to the gate electrode 8 in the direction X. For example, the width of the second layer 12 coincides with the width of the surface 8b at the position in contact with the surface 8b and becomes narrower as it is closer to the source electrode 5.

[0160] The semiconductor device 106 moderates the concentration of the electric field on the source electrode 5 side of the gate electrode 8, as compared with the semiconductor device 105.

[0161] In the semiconductor device 106, as well as in the semiconductor device 104, the electrons between the source electrode 5 and the gate electrode 8 move not only between the second layers 12 which are adjacent to each other in the direction Y but also in the region sandwiched by the second layer 12 and the drain electrode 6. The electrons move more narrowly toward either one of the direction Y and the side opposite to the direction Y as they advance between the drain electrode 6 and the gate electrode 8 in the direction X. The second layer 12 in the semiconductor device 106 is more difficult to obstruct the electrons from narrowing, as compared with the second layer 12 in the semiconductor device 104.

[0162] The semiconductor device 106 is more difficult to obstruct the movement of the two-dimensional carrier gas which contributes to the drain current, as compared with the semiconductor device 104, and is able to obtain a large drain current.

[0163] As the shape of the second layer 12, a shape in which the width increases stepwise toward the direction X can also be adopted. In the view of moderating the concentration of the electric field at the site where the concentration is large, it is advantageous to adopt a shape in which the width increases linearly or curvilinearly toward the direction X as the shape of the second layer 12.

[0164] The structure in which the length of the second layer 12 along the direction Y increases as it approaches the gate electrode 8 along the direction X can be applied to any of the semiconductor devices 101 to 105 .

[0165] Implementation method 7.

[0166] Figure 16 This is a plan view illustrating the structure of the semiconductor device 107 according to the seventh embodiment. Figure 16 Examples and descriptions of the semiconductor device 101 in Figure 2 The same range as the range exemplified in . Figure 16 In, record together with Figure 2 The positions AA, BB, CC shown in the example are the same as the positions AA, BB, CC. Figure 16 Illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a two-dot chain line.

[0167] Figure 17 This is an example Figure 16 1 is a cross-sectional view of the semiconductor device 107 at position AA. Figure 16 The cross section of the semiconductor device 107 at position BB is different from that at Figure 4 The cross section of the semiconductor device 101 shown in FIG. 1 appears similarly. Figure 16 The cross section of the semiconductor device 107 at position CC is different from that at Figure 5 The cross section of the semiconductor device 101 shown in FIG. 1 appears similarly.

[0168] The semiconductor device 107 has a structure in which a fourth layer 16 is added to the semiconductor device 103 .

[0169] There are a plurality of fourth layers 16, each existing in correspondence with the gate electrode 8. The fourth layer 16 is located between the first layer 10 and the drain electrode 6 in the direction X and is in contact with both the first layer 10 and the drain electrode 6. The fourth layer 16 is in contact with the nitride semiconductor layer 3 in the direction Y.

[0170] The figure shows a semiconductor device 107 in which the fourth layer 16 extends from above the nitride semiconductor layer 3 through the nitride semiconductor layer 3 to the nitride semiconductor layer 2. The figure shows a shape in which the fourth layer 16 protrudes in the direction Z relative to the nitride semiconductor layer 3, but this protrusion is not essential.

[0171] The fourth layer 16 is formed of, for example, an insulator or a semiconductor, similarly to the first layer 10. The semiconductor, similarly to the first layer 10, is preferably an intrinsic semiconductor or has a conductivity type opposite to that of the nitride semiconductor layer 3. Similar to the first layer 10, the fourth layer 16 has the function of alleviating electric field concentration.

[0172] The position of the fourth layer 16 in the direction Z can also be selected similarly to the position of the first layer 10 in the direction Z. For example, the fourth layer 16 and the nitride semiconductor layer 2 can sandwich the nitride semiconductor layer 3 in the direction Z. The fourth layer 16 can also penetrate the nitride semiconductor layer 3 in the direction Z and contact the nitride semiconductor layer 2. The fourth layer 16 can also exist below the position of the two-dimensional electron gas in the direction Z caused by a region where the fourth layer 16 is not formed, for example, the position BB. The position of the fourth layer 16 in the direction Z can also be different from the position of the first layer 10 in the direction Z.

[0173] The dielectric constant of the fourth layer 16 is smaller than the dielectric constant of the first layer 10. A high dielectric constant is apt to moderate the concentration of the electric field. Moderation of the concentration of the electric field contributes to improvement of the power output of the semiconductor device 107. A low dielectric constant is apt to reduce the gate-drain capacitance and the source-drain capacitance. Reduction of these static capacitances contributes to improvement of the drain efficiency and the power load efficiency.

[0174] The closer to the gate electrode 8, the more apt the electric field is to concentrate, so from the viewpoint of reducing the gate-drain capacitance and the source-drain capacitance and from the viewpoint of moderating the concentration of the electric field, it is advantageous that the dielectric constant of the first layer 10 closer to the gate electrode 8 than the fourth layer 16 is higher.

[0175] If the fourth layer 16 is regarded as a part of the first layer 10, it can be said that, in terms of the semiconductor device 101, the semiconductor device 107 is a configuration in which the dielectric constant of the first layer 10 decreases stage by stage toward the direction X. In terms of the first layer 10 in the semiconductor device 101, it is also possible that the dielectric constant of the first layer 10 decreases stage by stage by three or more stages. It is also possible that the dielectric constant of the first layer 10 decreases continuously toward the direction X.

[0176] The fourth layer 16 can also, similarly to the semiconductor device 103, not contact the drain electrode 6 but sandwich the nitride semiconductor layer 3 between the fourth layer 16 and the drain electrode 6.

[0177] The configuration in which the dielectric constant of the first layer 10 decreases toward the direction X can be applied to any of the semiconductor devices 101 to 107 and contributes to reduction of the gate-drain capacitance and the source-drain capacitance and moderation of the concentration of the electric field.

[0178] In the semiconductor devices 102, 104, and 106, it is also possible that the dielectric constant of the second layer 12 decreases toward the direction opposite to the direction X. This feature contributes to reduction of the gate-source capacitance and the source-drain capacitance.

[0179] Embodiment 8.

[0180] Figure 18is a plan view illustrating the configuration of the semiconductor device 108 of Embodiment 8. Figure 18 Embodiment 8 is illustrated in the same range as that of the semiconductor device 101 in Figure 2 Embodiment 8 is illustrated in the same range as that of the semiconductor device 101 in Figure 18 Embodiment 8 is illustrated in the same range as that of the semiconductor device 101 in Figure 2 Embodiment 8 is illustrated in the same range as that of the semiconductor device 101 in Figure 18 The illustration of the protective film 14 is omitted in Embodiment 8, and the conductor 9 is depicted by a double-dot chain line.

[0181] Figure 19 is a sectional view illustrating the section of the semiconductor device 108 at the position AA of Embodiment 8. Figure 18 The section of the semiconductor device 108 at the position BB is the same as that of the semiconductor device 101 shown in Embodiment 1. Figure 18 Figure 4 is a sectional view illustrating the section of the semiconductor device 108 at the position CC of Embodiment 8. Figure 20 Figure 18 The semiconductor device 108 has the configuration in which the 3rd layer 13 is added to the semiconductor device 103. The 3rd layer 13 is in contact with the face 8e.

[0182] As the material of the 3rd layer 13, for example, the example illustrated as the material of the 1st layer 10 is employed. The material of the 1st layer 10 and the material of the 3rd layer 13 need not be identical. The material of the 1st layer 10 and the material of the 3rd layer 13 being identical contributes to easy formation of the 1st layer 10 and the 3rd layer 13.

[0183] The 3rd layer 13 is located between the gate electrode 8 and the semiconductor layer group 4 in the direction Z and is in contact with the gate electrode 8. In

[0184] The 3rd layer 13 is located between the face 8e and the nitride semiconductor layer 2 in the direction Z in Embodiments 1 and 2. The 3rd layer 13 mitigates the electric field concentration on the face 8e side of the gate electrode 8. The 3rd layer 13 being located between the gate electrode 8 and the nitride semiconductor layer 2 contributes to reduction of the gate leakage current. Figure 19 Figure 20 The above-described suppression has no direct relation to the 3rd layer 13 being in contact with the 1st layer 10. When the 3rd layer 13 is in contact with the 1st layer 10, for example, during a period from formation of the trench 7 to formation of the gate electrode 8, the 3rd layer 13 is easily formed in parallel with the 1st layer 10.

[0185] The 3rd layer 13 can be added to any of the semiconductor devices 101 to 107, and contributes to reduction of the gate leakage current.

[0186] Embodiment 9.

[0187] Embodiment 9.

[0188] Figure 21 ​​​This is a plan view illustrating the structure of a semiconductor device 109 according to a ninth embodiment. Figure 21 The semiconductor device 101 is shown in FIG. Figure 2 The same range as the range exemplified in . Figure 21 In, record together with Figure 2 The positions AA, BB, CC shown in the example are the same as the positions AA, BB, CC. Figure 21 Illustration of the protective film 14 is omitted, and the conductor 9 is depicted by a two-dot chain line.

[0189] Figure 22 This is an example Figure 21 1 is a cross-sectional view of the semiconductor device 109 at position AA. Figure 23 This is an example Figure 21 1 is a cross-sectional view of the semiconductor device 109 at position BB. Figure 24 This is an example Figure 21 1 is a cross-sectional view of the semiconductor device 109 at position CC.

[0190] The semiconductor device 109 differs from the semiconductor device 103 in the structures of the nitride semiconductor layers 2 and 3. Specifically, the nitride semiconductor layer 2 includes nitride semiconductor layers 21, 22, and 23, and the nitride semiconductor layer 3 includes nitride semiconductor layers 31, 32, and 33.

[0191] The nitride semiconductor layer 21 forms a heterojunction with the nitride semiconductor layer 31. The nitride semiconductor layer 31 forms a heterojunction with the nitride semiconductor layer 22. The nitride semiconductor layer 22 forms a heterojunction with the nitride semiconductor layer 32. The nitride semiconductor layer 32 forms a heterojunction with the nitride semiconductor layer 23. The nitride semiconductor layer 23 forms a heterojunction with the nitride semiconductor layer 33.

[0192] If the nitride semiconductor layer 21 is regarded as the nitride semiconductor layer 2 in the semiconductor device 103 , it can be said that the semiconductor device 109 has a structure in which nitride semiconductor layers 31 , 22 , 32 , 23 , and 33 are sequentially added along the direction Z as the nitride semiconductor layer 3 on the semiconductor layer group 4 in the semiconductor device 103 .

[0193] If nitride semiconductor layers 21 and 31 are respectively regarded as nitride semiconductor layers 2 and 3 in semiconductor device 103 , semiconductor device 109 can be said to have a structure in which nitride semiconductor layers 22 , 32 , 23 , and 33 are sequentially added in direction Z to semiconductor layer group 4 in semiconductor device 103 .

[0194] If the nitride semiconductor layers 21, 31, 22 are regarded as the nitride semiconductor layer 2 in the semiconductor device 103, it can be said that the semiconductor device 109 has a configuration in which the nitride semiconductor layers 32, 23, 33 are sequentially added as the nitride semiconductor layer 3 on the semiconductor layer group 4 in the semiconductor device 103 in the direction Z.

[0195] If the nitride semiconductor layers 21, 31, 22, 32, 23 are regarded as the nitride semiconductor layer 2 in the semiconductor device 103, it can be said that the semiconductor device 109 has a configuration in which the nitride semiconductor layer 33 is added as the nitride semiconductor layer 3 on the semiconductor layer group 4 in the semiconductor device 103 in the direction Z side.

[0196] It can also be said that the nitride semiconductor layer 2 has a plurality of nitride semiconductor layers (temporarily referred to as "first sub layer" in the present disclosure), the nitride semiconductor layer 3 has a plurality of nitride semiconductor layers (temporarily referred to as "second sub layer" in the present disclosure), and the first sub layer and the second sub layer are alternately laminated.

[0197] It can also be said that the semiconductor layer group 4 has a plurality of nitride semiconductor layers 21, 22, 23 and a plurality of nitride semiconductor layers 31, 32, 33, and they are alternately laminated.

[0198] A region in which a two-dimensional carrier gas is induced exists at a plurality of positions along the direction Z in the semiconductor device 109. The region in which the two-dimensional carrier gas is induced contributes to an increase in the amount of the two-dimensional carrier gas that contributes to the drain current in the semiconductor device 109. The semiconductor device 109 has a larger drain current than the semiconductor device 103.

[0199] The laminated configuration constituted by the nitride semiconductor layers 21, 31, 22, 32, 23, 33 can also be obtained by a periodic superlattice configuration. The number of the above-described laminations can also be more, and the nitride semiconductor layers 23, 33 can also be omitted.

[0200] The composition, the doping concentration, and the film thickness of the nitride semiconductor layers 21, 22, 23 can be the same as each other or different from each other. The composition, the doping concentration, and the film thickness of the nitride semiconductor layers 31, 32, 33 can be the same as each other or different from each other.

[0201] The laminated configuration in such a nitride semiconductor layer 2, 3 can be applied to any of the semiconductor devices 101 to 108 and contributes to an increase in the drain current.

[0202] Embodiment 10.

[0203] Figure 25is a cross-sectional view illustrating a configuration of the semiconductor device 110 of Embodiment 10. The plan view of the semiconductor device 110 appears similarly to the plan view of the semiconductor device 103 of Embodiment 3 (refer to Figure 8 ), for example. In this case, Figure 25 shows a cross section of the semiconductor device 110 at a position equivalent to the position AA illustrated in Figure 8 . The cross section of the semiconductor device 110 at a position equivalent to the position BB illustrated in Figure 8 appears similarly to the cross section of the semiconductor device 101 shown in Figure 4 . The cross section of the semiconductor device 110 at a position equivalent to the position CC illustrated in Figure 8 appears similarly to the cross section of the semiconductor device 101 shown in Figure 5 .

[0204] or the plan view of the semiconductor device 110 appears similarly to the plan view of the semiconductor device 105 of Embodiment 5 (refer to Figure 12 ), for example. In this case, Figure 25 shows a cross section of the semiconductor device 110 at a position equivalent to the position AA illustrated in Figure 12 . The cross section of the semiconductor device 110 at a position equivalent to the position BB illustrated in Figure 12 appears similarly to the cross section of the semiconductor device 101 shown in Figure 4 . The cross section of the semiconductor device 110 at a position equivalent to the position CC illustrated in Figure 12 appears similarly to the cross section of the semiconductor device 101 shown in Figure 5 .

[0205] The semiconductor device 110, compared to the semiconductor devices 103, 105, has a length (thickness) of the first layer 10 in the direction Z decreasing as the first layer 10 departs from the gate electrode 8 in the direction X. For example, a position in the direction Z of the surface 10e on the side opposite to the direction Z of the first layer 10 coincides with a position in the direction Z of the surface 8e at a position in contact with the gate electrode 8, and the closer to the drain electrode 6, the more toward the side of the direction Z.

[0206] Figure 26 is a cross-sectional view illustrating a configuration of a modification of the semiconductor device 110. Figure 26 illustrates a cross section of this modification at the same position as shown in Figure 25 . In Figure 25 , the surface 10e has a shape in which an absolute value of a slope of the surface 10e with respect to the direction X increases only as toward the direction X when viewed in the cross section. Figure 26 the surface 10e in has a portion in which the absolute value decreases as toward the direction X.

[0207] Similar to the semiconductor devices 105 and 106, Figure 25 The cross section of the first layer 10 shown and having Figure 26 The first layer 10 of the cross section shown is advantageous in terms of widening the area where the electric field is concentrated and alleviating the concentration. The first layer 10 may have a shape in which the thickness of the first layer 10 decreases in a stepwise manner toward the direction X.

[0208] The structure in which the thickness of the first layer 10 on the drain electrode 6 side decreases as it moves away from the gate electrode 8 can be applied to the structure of any of the semiconductor devices 101 to 109 and contributes to obtaining a large drain current.

[0209] Electric field concentration tends to occur not near the two-dimensional electron gas but at the end of gate electrode 8 on the drain electrode 6 side, for example, at surface 8a. Based on the above viewpoint, the thickness variation of first layer 10 in nitride semiconductor layer 2 as well as in nitride semiconductor layer 3 as described above contributes to mitigating electric field concentration.

[0210] Implementation method 11.

[0211] Figure 27 This is a cross-sectional view illustrating the structure of a semiconductor device 111 according to the eleventh embodiment. The top view of the semiconductor device 111 is similar to the top view of the semiconductor device 104 according to the fourth embodiment (see FIG. Figure 10 ) appears in the same way. In this case, Figure 27 Shown with Figure 10 The cross section of the semiconductor device 111 at a position corresponding to the position AA shown in FIG. Figure 10 The cross section of the semiconductor device 111 at a position corresponding to the position BB shown in FIG. Figure 4 The cross section of the semiconductor device 101 shown in FIG. Figure 10 The cross section of the semiconductor device 111 at a position corresponding to the position CC shown in FIG. Figure 5 The cross section of the semiconductor device 101 shown in FIG. 1 appears similarly.

[0212] Or the top view of the semiconductor device 111 is similar to the top view of the semiconductor device 106 of the sixth embodiment (see Figure 14 ) appears in the same way. In this case, Figure 27 Shown with Figure 14 The cross section of the semiconductor device 111 at a position corresponding to the position AA shown in FIG. Figure 14 The cross section of the semiconductor device 111 at a position corresponding to the position BB shown in FIG. Figure 4 The cross section of the semiconductor device 101 shown in FIG. Figure 14 The cross section of the semiconductor device 111 at a position corresponding to the position CC shown in FIG.Figure 5 The cross section of the semiconductor device 101 shown in FIG. 12 similarly occurs.

[0213] The semiconductor device 111, compared to the semiconductor devices 104, 106, has a configuration in which the length (thickness) of the second layer 12 in the direction Z increases as the second layer 12 approaches the gate electrode 8 in the direction X. For example, the position in the direction Z of the surface 12e of the second layer 12 on the side opposite to the direction Z coincides with the position in the direction Z of the surface 8e at the position in contact with the gate electrode 8, and the closer to the source electrode 5, the more the position in the direction Z approaches the side in the direction Z.

[0214] The second layer 12 having such a cross section is also advantageous in the semiconductor device 106 in the point of view of relaxing the concentration of the electric field at the portion where the concentration is large.

[0215] As the shape of the second layer 12, a shape in which the thickness of the second layer 12 increases in stages toward the direction X can also be adopted. In this case, the surface 12e has a shape in which the absolute value of the slope of the surface 12e with respect to the direction X when viewed in the cross section decreases only toward the direction X. The surface 12e can also have a portion in which the absolute value increases toward the direction X. Figure 27

[0216] The configuration in which the thickness of the second layer 12 on the source electrode 5 side increases as it approaches the gate electrode 8 can be applied to the configuration of any of the semiconductor devices 101 to 110, and contributes to obtaining a large drain current.

[0217] Embodiment 12.

[0218] In the present embodiment, the first layer 10 is a semiconductor having a conduction type opposite to the conduction type of the nitride semiconductor layer 3. For example, the conduction type of the nitride semiconductor layer 3 is n-type, and a semiconductor having a conduction type of p-type is adopted in the first layer 10. The first layer 10 adopting the above-described semiconductor can also be applied to the configuration of any of the semiconductor devices 101 to 111.

[0219] Figure 28 FIG. 13 is a diagram illustrating the energy band configuration of the semiconductor device of Embodiment 12. Figure 28 The energy band configuration that the nitride semiconductor layer 3 has at a specific position in the directions Y, Z is shown. The specific position refers to the position of the first layer 10 with respect to the direction Y, which corresponds to the above-described position AA. The specific position refers to the position (depth) of the nitride semiconductor layer 3 with respect to the direction Z.

[0220] ​On the horizontal axis, shown are a region R8 in which the gate electrode 8 exists at a certain position (omitted is the boundary on the side opposite to the direction X), a region R10 in which the first layer 10 exists at a certain position, a region R3 in which the nitride semiconductor layer 3 exists at a certain position, and a region R6 in which the drain electrode 6 exists at a certain position (omitted is the boundary on the side of the direction X). On the vertical axis, the potential energy for an electron is taken.

[0221] The bottom Ec1 of the conduction band and the top Ev1 of the valence band of the nitride semiconductor layer 3 are exemplified when the source electrode 5, the drain electrode 6, and the gate electrode 8 are at the same potential. The bottom Ec2 of the conduction band and the top Ev2 of the valence band of the nitride semiconductor layer 3 are exemplified when the source electrode 5 and the drain electrode 6 are at the same potential and the potential of the gate electrode 8 is positive with respect to the potentials of the source electrode 5 and the drain electrode 6.

[0222] By the potential of the gate electrode 8 becoming positive with respect to the potential of the drain electrode 6, the following phenomenon occurs: holes are injected from the first layer 10 having a p-type conductivity type to the nitride semiconductor layer 2 having an n-type conductivity type; the potential for the holes is lowered in the nitride semiconductor layer 3; and the injected holes function as a two-dimensional hole gas close to the nitride semiconductor layer 3 having a low potential for the holes.

[0223] The two-dimensional hole gas functions as a carrier in the drain current in the same manner as the two-dimensional electron gas, and thus the occurrence of the above phenomenon contributes to an increase in the drain current. The increase in the drain current improves the current driving capability, and improves the linearity of the transconductance based on the conductivity modulation. The improvement in the linearity of the transconductance contributes to the low distortion of the communication system using the semiconductor device of the present embodiment.

[0224] A pn junction is formed at the interface of the first layer 10 and the nitride semiconductor layer 3. This pn junction occurs a static capacitance based on a depletion layer, and lowers the static capacitance between the gate electrode 8 and the drain electrode 6. The lowering of the above static capacitance contributes to at least any one of an increase in the drain efficiency in the power conversion and an increase in the power added efficiency of the semiconductor device using the present embodiment.

[0225] Any of the second layer 12 in the semiconductor devices 102, 104, 106, 111 and the third layer 13 in the semiconductor device 108 can likewise obtain any one or both of the above improvements and contributions by employing a semiconductor having a conductivity type opposite to that of the nitride semiconductor layer 3.

[0226] Regarding the deformation of the surfaces 8a, 8b, 8c, 8d.

[0227] Figure 29is a plan view of the gate electrode 8 viewed in a direction opposite to the direction Z. In Figure 29 In the present embodiment, a case where the gate electrode 8 appears circular in plan view is exemplified. For example, the gate electrode 8 appears cylindrical. The configuration of the above-described gate electrode 8 is disclosed in, for example, Non-Patent Literature 1.

[0228] The imaginary lines J, K, L, M pass through the center 8f of the gate electrode 8 in plan view. The imaginary line J is parallel to the direction X, and is parallel to the direction in which the source electrode 5 and the drain electrode 6 are arranged. The imaginary line K is parallel to the direction Y, and is parallel to the direction in which the plurality of gate electrodes 8 are arranged. The imaginary lines L, M each have a slope of 45 degrees with respect to the directions X, Y. The imaginary line L is directed toward the direction Y as it is directed toward the direction X.

[0229] The imaginary lines L, M are boundaries of the regions 8ar, 8br of the gate electrode 8. The region 8ar is located more toward the direction X than the region 8br. In Figure 29 In the present embodiment, the regions 8ar, 8br are represented by thick lines in order to improve visual recognition.

[0230] For example, the region 8ar is treated as the face 8a. The first layer 10 contacts the gate electrode 8 without passing over the region 8ar. For example, the region 8br is treated as the face 8b. The second layer 12 contacts the gate electrode 8 without passing over the region 8br.

[0231] The first layer 10 contacts the gate electrode 8 within a range of plus or minus 45 degrees in plan view with respect to the direction from the source electrode 5 toward the drain electrode 6.

[0232] The second layer 12 contacts the gate electrode 8 within a range of plus or minus 45 degrees in plan view with respect to the direction from the source electrode 5 toward the drain electrode 6.

[0233] Further, each of the embodiments can be freely combined or appropriately modified or omitted.

[0234] While the present disclosure has been described in detail, the above description is illustrative in all aspects, not restrictive. It should be understood that numerous modifications unexemplified can be envisaged.

Claims

1. A semiconductor device comprising: a semiconductor layer group including a first nitride semiconductor layer and a second nitride semiconductor layer stacked in a first direction; a plurality of gate electrodes, each of which contacts the second nitride semiconductor layer in a second direction different from the first direction and is arranged along the second direction; a conductor electrically connecting the plurality of gate electrodes to each other and located at a position away from the semiconductor layer group; a source electrode facing the plurality of gate electrodes in a third direction different from both the first direction and the second direction, and conductively connected to the first nitride semiconductor layer; a drain electrode, facing the source electrode in the third direction with the plurality of gate electrodes interposed therebetween, and electrically connected to the first nitride semiconductor layer; as well as The first layer is located between the plurality of gate electrodes and the drain electrode in the third direction and in contact with the plurality of gate electrodes, and is in contact with the second nitride semiconductor layer in the second direction. The first nitride semiconductor layer and the second nitride semiconductor layer form a heterojunction, a two-dimensional carrier gas is generated in the first nitride semiconductor layer, The first nitride semiconductor layer and the second nitride semiconductor layer form a Schottky junction with each of the plurality of gate electrodes. The first layer is any one of an insulator, an intrinsic semiconductor, and a semiconductor having a conductivity type opposite to that of the second nitride semiconductor layer, and suppresses the first nitride semiconductor layer facing the first layer in the first direction from generating the two-dimensional carrier gas.

2. The semiconductor device according to claim 1, wherein The first layer is a semiconductor having a conductivity type opposite to that of the second nitride semiconductor layer.

3. The semiconductor device according to claim 1 or 2, wherein: The first layer is in contact with the drain electrode.

4. The semiconductor device according to claim 1 or 2, wherein In the third direction, the length of the first layer is shorter than the distance between the plurality of gate electrodes and the drain electrode.

5. The semiconductor device according to claim 1 or 2, wherein The length of the first layer in the second direction decreases as it moves away from the plurality of gate electrodes along the third direction.

6. The semiconductor device according to claim 1 or 2, wherein: A length of the first layer in the first direction decreases as it moves away from the plurality of gate electrodes along the third direction.

7. The semiconductor device according to claim 1, wherein further comprising a second layer located between the plurality of gate electrodes and the source electrode in the third direction and in contact with the plurality of gate electrodes, The second layer is any one of an insulator, an intrinsic semiconductor, and a semiconductor having a conductivity type opposite to that of the second nitride semiconductor layer, and suppresses the first nitride semiconductor layer facing the second layer in the first direction from generating the two-dimensional carrier gas.

8. The semiconductor device according to claim 7, wherein The second layer is a semiconductor having a conductivity type opposite to that of the second nitride semiconductor layer.

9. The semiconductor device according to claim 7 or 8, wherein The second layer is in contact with the source electrode.

10. The semiconductor device according to claim 7 or 8, wherein In the third direction, the length of the second layer is shorter than the distance between the plurality of gate electrodes and the source electrode.

11. The semiconductor device according to claim 7 or 8, wherein The length of the second layer in the second direction increases as it approaches the plurality of gate electrodes along the third direction.

12. The semiconductor device according to claim 7 or 8, wherein The length of the second layer in the first direction increases as it approaches the plurality of gate electrodes along the third direction.

13. The semiconductor device according to claim 1, 2, 7 or 8, wherein: The dielectric constant of the first layer decreases toward the third direction.

14. The semiconductor device according to claim 7 or 8, wherein The dielectric constant of the second layer decreases toward a direction opposite to the third direction.

15. The semiconductor device according to claim 1, 2, 7 or 8, wherein: further comprising a third layer located between the plurality of gate electrodes and the first nitride semiconductor layer in the first direction and in contact with the plurality of gate electrodes, The third layer is an insulator or a semiconductor having a conductivity type opposite to that of the second nitride semiconductor layer.

16. The semiconductor device according to claim 15, wherein The third layer is a semiconductor having a conductivity type opposite to that of the second nitride semiconductor layer.

17. The semiconductor device according to claim 1, 2, 7, 8 or 16, wherein: The semiconductor layer group includes a plurality of the first nitride semiconductor layers and a plurality of the second nitride semiconductor layers alternately stacked in the first direction.

18. The semiconductor device according to claim 1, 2, 7, 8 or 16, wherein: Each of the plurality of gate electrodes penetrates the second nitride semiconductor layer and is in contact with the first nitride semiconductor layer.

19. The semiconductor device according to claim 1, 2, 7, 8 or 16, wherein: Each of the first layers penetrates the second nitride semiconductor layer and is in contact with the first nitride semiconductor layer.

20. The semiconductor device according to claim 19, wherein Each of the first layers exists on the side opposite to the first direction relative to the position of the induced two-dimensional carrier gas in the first direction.

21. The semiconductor device according to claim 7 or 8, wherein Each of the second layers penetrates the second nitride semiconductor layer and is in contact with the first nitride semiconductor layer.

22. The semiconductor device according to claim 21, wherein Each of the second layers exists on the side opposite to the first direction relative to the position of the induced two-dimensional carrier gas in the first direction.

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