Package structure and method of forming the same

Abstract

This invention discloses a packaging structure and a method for forming the same. The packaging structure includes: a substrate; an optical integrated circuit located above the substrate, the upper surface of which has a first light guide component; an optical fiber array located above the first light guide component of the optical integrated circuit and having a second light guide component; and a light guide material located between the optical integrated circuit and the optical fiber array, wherein the second light guide component of the optical fiber array passes through the light guide material and is optically coupled to the first light guide component of the optical integrated circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a packaging structure and a method for forming the same. Background Technology

[0002] exist Figure 1 In the packaging structure shown, the fiber array (FAU) 20 and the optical integrated circuit (PIC) 10 are coupled using grating coupling. This method allows for precise coupling because it utilizes the multiple insulating layers 32 above the PIC 10 as a passive alignment structure. However, the multiple fibers 25 of the FAU 20 and the wave guides (WGs) 15 above the PIC 10 pass through holes 36 in the insulating layers 32 and are disposed within a cavity 35. The signal-to-noise ratio between the various optical paths needs further improvement, and mutual interference can easily lead to and consequently improve the optical signal quality of each of the multiple WGs 15. Summary of the Invention

[0003] To address the aforementioned problems in related technologies, this invention proposes a packaging structure and a method for forming the same.

[0004] According to one aspect of the present invention, a packaging structure is provided, comprising: a substrate; an optical integrated circuit located above the substrate, the upper surface of the optical integrated circuit having a first light guide component; an optical fiber array located above the first light guide component of the optical integrated circuit and having a second light guide component; and a light guide material located between the optical integrated circuit and the optical fiber array, wherein the second light guide component of the optical fiber array passes through the light guide material and is optically coupled to the first light guide component of the optical integrated circuit.

[0005] In some embodiments, the bottom surface of the fiber array forms an acute angle with the upper surface of the optical integrated circuit.

[0006] In some embodiments, the encapsulation structure further includes a colloid, which is located at least between the fiber array and the optical guiding material.

[0007] In some embodiments, the light-guiding material has a cavity that extends through the light-guiding material and is located above the first light-guiding component of the optical integrated circuit, and the second light-guiding component of the optical fiber array is optically coupled to the first light-guiding component via the cavity.

[0008] In some embodiments, the cavity is filled with a colloid that covers the second light guide component.

[0009] In some embodiments, the packaging structure further includes a molding compound positioned above the substrate and surrounding the optical integrated circuit and the light-guiding material.

[0010] In some embodiments, protrusions are provided on opposite sides of the fiber array.

[0011] In some embodiments, the packaging structure further includes: an electrical integrated circuit located above the photoconductive material; a power management integrated circuit located on opposite sides of the optical fiber array; and two protrusions of the optical fiber array located above the electrical integrated circuit and the power management integrated circuit, respectively.

[0012] In some embodiments, the package structure further includes a heat dissipation component that extends at least on the upper surfaces of the electrical integrated circuit and the power management integrated circuit, with the two protrusions of the fiber array located above the heat dissipation component.

[0013] In some embodiments, the package structure further includes: a circuit layer located below the electrical integrated circuit and the power management integrated circuit; and conductive pillars located below the circuit layer below the power management integrated circuit, wherein the conductive pillars connect the circuit layer to the substrate.

[0014] According to another aspect of the present invention, a method for forming a package structure is provided, comprising: forming an optical integrated circuit and a light guide material on a substrate, wherein the optical integrated circuit has a first light guide component on a surface opposite to the substrate, and the light guide material covers the surface of the optical integrated circuit; forming an optical fiber array above the light guide material, wherein a second light guide component of the optical fiber array passes through the light guide material and is optically coupled to the first light guide component of the optical integrated circuit.

[0015] In some embodiments, forming an optical fiber array includes: the bottom surface of the optical fiber array forming an acute angle with the upper surface of the optical integrated circuit.

[0016] In some embodiments, forming an optical fiber array includes: placing the optical fiber array at an angle above the light-conducting material; and forming an adhesive between the optical fiber array and the light-conducting material to fix the optical fiber array in an inclined position.

[0017] In some embodiments, after forming the light guide material, the method further includes: forming a cavity in the light guide material, the cavity penetrating the light guide material and located above the first light guide component of the optical integrated circuit, wherein the second light guide component of the fiber array is optically coupled to the first light guide component via the cavity.

[0018] In some embodiments, the cavity is filled with a colloid that covers the second light guide component.

[0019] In some embodiments, a molding is also formed over the substrate surrounding the optical integrated circuit and the photoconductive material.

[0020] In some embodiments, protrusions are provided on two opposite sidewalls of the fiber array, wherein the two protrusions on the two opposite sidewalls have different thicknesses to tilt the fiber array.

[0021] In some embodiments, the method further includes: forming an electrical integrated circuit on top of the optical guide material; forming a power management integrated circuit, wherein the power management integrated circuit and the electrical integrated circuit are located on opposite sides of the optical fiber array, wherein the two protruding portions of the optical fiber array are respectively located above the electrical integrated circuit and the power management integrated circuit.

[0022] In some embodiments, the device further includes: forming a heat dissipation component extending at least on the upper surfaces of the electrical integrated circuit and the power management integrated circuit, wherein the fiber array passes through the heat dissipation component and the two protrusions of the fiber array are located above the heat dissipation component.

[0023] In some embodiments, the method further includes: forming a circuit layer on a carrier; forming conductive pillars on the substrate, the conductive pillars being disposed on the substrate at intervals from the optical integrated circuit; bonding the circuit layer to the conductive pillars and the photoconductive material, and removing the carrier; and bonding the electrical integrated circuit and the power management integrated circuit over the circuit layer. Attached Figure Description

[0024] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0025] Figure 1 This is a schematic diagram of an existing packaging structure.

[0026] Figure 2 This is a schematic diagram of the packaging structure according to an embodiment of the present invention.

[0027] Figure 3 The dimensional configuration of a portion of the packaging structure according to an embodiment of the present invention is shown.

[0028] Figures 4 to 7 This is a schematic diagram of a packaging structure according to other embodiments of the present invention.

[0029] Figures 8A to 8MSchematic diagrams are shown of the various stages of a method for forming a packaging structure according to an embodiment of the present invention.

[0030] Figures 9A to 9H A schematic diagram of the various stages of an example method for forming the circuit layer 2 in the encapsulation structure is shown. Specific Implementation

[0031] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0032] Figure 2 This is a schematic diagram of a packaging structure according to an embodiment of the present invention. The packaging structure includes a substrate 210, a PIC 220 located above the substrate 210, and a FAU 230 located above the PIC 220. The upper surface of the PIC 220 has a plurality of first light guide components 222. The FAU 230 is located above the first light guide components 222 of the PIC 220, and the FAU 230 has a plurality of second light guide components 232. In some embodiments, the second light guide components 232 of the FAU 230 may be optical fibers. A light guide material 240 is disposed between the PIC 220 and the FAU 230. The second light guide components 232 of the FAU 230 pass through the light guide material 240 and are optically coupled to the first light guide components 222 of the PIC 220. Figure 2 As shown, in each of two adjacent second light guide components 232 of FAU 230, there is an isolation portion 249 formed of light guide material between the two second light guide components 232, and each of the two adjacent second light guide components 232 is separated from each other by the isolation portion 249.

[0033] The above-described technical solution of the present invention, by providing a light guide material 240 above the PIC 220, allows the light guide material 240 to have a passive alignment function and can also prevent mutual interference between adjacent first light guide components 222 and adjacent second light guide components 232. Since the light guide material 240 exists between the FAU 230 and the PIC 220, the light guide material 240 can also be used to ensure that the path of light from the FAU 230 can reach the corresponding first light guide component 222.

[0034] Furthermore, in a conventional packaging structure, the FAU is connected to a portion of the lower surface of the PIC, and the light guide component of the FAU is coupled to the PIC from the side and above. In this approach, it is difficult for the PIC to provide a larger area to receive the light guide component of the FAU. The packaging structure of the present invention also provides a larger area for the FAU 230 on the upper surface of the PIC 220 to receive more of the second light guide component 232 of the FAU 230.

[0035] Continue to refer to Figure 2 As shown, the photoconductor material 240 may have multiple cavities 242, with adjacent cavities 242 separated by isolation portions 249. These cavities 242 are located above the first photoconductor component 222 of the PIC 220, and each cavity 242 penetrates the photoconductor material 240 in the vertical direction. The multiple cavities 242 may correspond to multiple second photoconductor components 232 of the FAU 230. The second photoconductor components 232 of the FAU 230 are optically coupled to the first photoconductor component 222 via the cavities 242 in the photoconductor material 240. Since the multiple second photoconductor components 232 of the FAU 230 are respectively inserted into the corresponding cavities 242 of the photoconductor material 240, the photoconductor material 240 can be made of a suitable optical adhesive material to protect the exposed second photoconductor components 232 between the FAU 230 and the PIC 220. This can mitigate the risk of breakage of the exposed second photoconductor components 232 during subsequent reliability testing.

[0036] During the placement of FAU 230 above PIC 220, FAU 230 may also be tilted, causing the bottom surface of FAU 230 to form an acute angle A with the top surface of PIC 220, meaning the bottom surface of FAU 230 and the top surface of PIC 220 are not parallel. In some embodiments, the acute angle A between the bottom surface of FAU 230 and the top surface of PIC 220 is in the range of 1 to 15 degrees. The operational accuracy error in the aforementioned placement of FAU 230 process can be improved by setting up a light guide material 240 and correspondingly introducing the second light guide component 232 of FAU 230 into the first light guide component 222 of PIC 220 through cavities in the light guide material 240.

[0037] A molding compound (CPD) 250 is also disposed above the substrate 210, surrounding the PIC 220 and the photoconductor material 240. This is achieved by covering the photoconductor material 240 with the molding compound 250. In some embodiments, the molding compound 250 may use organic photosensitive liquid materials, organic photosensitive dry film materials, photosensitive liquid materials, photosensitive dry film materials, etc. The molding compound 250 can also be used to protect the PIC 220. In some embodiments, the material of the molding compound 250 may include polyimide (PI), epoxy resin, insulating dielectric film (ABF), and / or molding materials, etc.

[0038] In some embodiments, the molded material 250 has conductive pillars 252 extending through it, and the molded material 250 can also protect the conductive pillars 252. The width of the conductive pillars 252 can be in the range of 20 μm to 50 μm, the height of the conductive pillars 252 can be in the range of 50 μm to 500 μm, and the pitch (distance between the center lines of adjacent conductive pillars 252) between the conductive pillars 252 can be in the range of 30 μm to 100 μm. The sidewalls of the molded material 250 can be aligned with the sidewalls of the substrate 210. The distance between the sidewalls of the molded material 250 can be equal to the width of the package structure. In some embodiments, the width of the package structure is in the range of 20 micrometers to 80 micrometers.

[0039] In the illustrated embodiment, electrical connectors 211, such as microbumps and C4 bumps, are provided below the lower surface of the substrate 210. In other embodiments, the electrical connectors 211 at the lower surface of the substrate 210 may also be formed as conductive pillars. In embodiments where the electrical connectors 211 are microbumps, the width of the electrical connectors 211 is in the range of 10 μm to 30 μm, and the pitch between the electrical connectors 211 is in the range of 15 μm to 60 μm. In embodiments where the electrical connectors 211 are C4 bumps, the width of the electrical connectors 211 is in the range of 30 μm to 100 μm, and the pitch between the electrical connectors 211 is in the range of 50 μm to 150 μm.

[0040] Electrical integrated circuit (EIC) 262 and power management integrated circuit (PMIC) 264 are disposed above the photoconductor material 240 and are adjacent to the FAU 230, with EIC 262 and PMIC 264 located on opposite sides of the FAU 230. In some embodiments, the thickness of PMIC 264 is in the range of 20 μm to 100 μm, the thickness of PIC 220 is in the range of 20 μm to 100 μm, and the thickness of EIC 262 is in the range of 20 μm to 100 μm. Underfill material 265 may be disposed below EIC 262 and PMIC 264, respectively. In some embodiments, the underfill material 265 may be an organic photosensitive liquid material, an organic photosensitive dry film material, a photosensitive liquid material, or a photosensitive dry film material. In some embodiments, the material of the underfill material 265 may include polyimide (PI), epoxy resin, insulating dielectric film (ABF), and / or molding material, etc.

[0041] The FAU 230 has protrusions 235 on its two opposite sides. The two protrusions 235 are higher than EIC 262 and PMIC 264 and extend above EIC 262 and PMIC 264 respectively. The two protrusions 235 above EIC 262 and PMIC 264 have different thicknesses, which causes the FAU 230 to tilt.

[0042] exist Figure 2 In the illustrated embodiment, heat dissipation components 270 may also be provided on EIC 262 and PMIC 264 respectively. The heat dissipation components 270 extend on the upper surfaces of EIC 262 and PMIC 264, and may also extend vertically adjacent to the sidewalls of EIC 262 and PMIC 264. Two protrusions 235 of FAU 230 are located above the heat dissipation components 270, that is, the heat dissipation components 270 may extend between FAU 230 and EIC 262 and PMIC 264.

[0043] At least between FAU 230 and photoconductor material 240, a colloid 282 is also disposed. The colloid 282 fills the cavity 242 in the photoconductor material 240, and also covers the second photoconductor component 232 of FAU 230. The colloid 282 may also be disposed around the lower portion of FAU 230. The colloid 282 fills the gap between FAU 230, PMIC 264, EIC 262, and heat sink 270. The colloid 282 is also disposed above the heat sink 270 to securely connect the heat sink 270 and FAU 230. Furthermore, solder 284 is provided between FAU 230 and heat sink 270 to securely connect the heat sink 270 and FAU 230. In some embodiments, the colloid 282 may be an organic photosensitive liquid material, an organic photosensitive dry film material, a photosensitive liquid material, or a photosensitive dry film material. In some embodiments, the material of colloid 282 may include polyimide (PI), epoxy resin, insulating dielectric film (ABF), and / or molding material, etc. Colloid 282 can be used to fix FAU 230, and can also be used to pre-bond FAU 230 during placement (described in detail later).

[0044] The circuit layer 290 is located below EIC 262 and PMIC 264 and above the molding 250. The circuit layer 290 includes a dielectric layer 292 and circuits 294 located within the dielectric layer 292. The circuits 294 include traces at different levels and vias connecting the traces. In some embodiments, the dielectric layer 292 in the circuit layer 290 may use organic photosensitive liquid materials, organic photosensitive dry film materials, photosensitive liquid materials, photosensitive dry film materials, etc. In some embodiments, the material of the dielectric layer 292 in the circuit layer 290 may include polyimide (PI), epoxy resin, insulating dielectric film (ABF), and / or molding materials, etc. In some embodiments, the material of the dielectric layer 292 in the circuit layer 290 may include inorganic materials, such as oxides (SiOx, SiNx, TaOx). In some embodiments, the material of the dielectric layer 292 in the circuit layer 290 may include glass, silicon, ceramics, etc.

[0045] In some embodiments, the thickness of the circuit layer 290 is in the range of 3 μm to 10 μm. PMIC 264 and EIC 262 are connected to lines 294 in the circuit layer 290, and conductive pillars 252 in the molding 250 are electrically connected to lines 294 in the circuit layer 290. The conductive pillars 252 can connect the circuit layer 290 to the substrate 210. The circuit layer 290 can provide electrical connections between PMIC 264, EIC 262, conductive pillars 252, and PIC 220. In some embodiments, the circuit layer 290 can be a fanout circuit layer. In some embodiments, the linewidth, spacing, and ratio of the traces in the circuit layer 290 can be in the range of 1 μm to 10 μm / 1 μm to 10 μm, and the pitch between traces can be in the range of 2 μm to 20 μm.

[0046] Figure 3 The dimensional configuration of a portion of the packaging structure according to an embodiment of the present invention is shown. For example... Figure 3 As shown, the FID / FOD ratio of the FAU 230 is in the range of 0.5 to 1. The ratio of the FID to the maximum width W of the FAU 230 is in the range of 1 to 10. The output angle θ of the FAU 230 is in the range of 10° to 80°, and the tilt angle α of the FAU 230 is in the range of 1° to 15°.

[0047] Figure 4 A schematic diagram of a packaging structure according to another embodiment of the present invention is shown. Figure 2 The difference in the embodiments shown is that, Figure 4 The heat dissipation component 270 is omitted from the package structure. For example... Figure 4 As shown, FAU 230 is directly connected and fixed to EIC 262 and PMIC 264 via solder 284 and colloid 282. Figure 4 Other aspects of the illustrated embodiments and Figure 2 The embodiments shown are similar and will not be described again here.

[0048] Figure 5 A schematic diagram of a packaging structure according to another embodiment of the present invention is shown. Figure 2 The difference shown in the embodiments is that, Figure 5 In the package structure, EIC 262 and PMIC 264 are formed on the same side of FAU 230. Furthermore, conductive post 252 is located on the same side of FAU 230 as EIC 262 and PMIC 264. Figure 2 Compared to the FAU 230, which is located in the middle area of ​​the package structure, Figure 5 The FAU 230 is located in the edge region of the package structure. Figure 5 Other aspects of the illustrated embodiments and Figure 2 The embodiments shown are similar and will not be described again here.

[0049] Figure 6A and Figure 6B A schematic diagram of a packaging structure according to another embodiment of the present invention is shown. Figure 2 The difference in the embodiments shown is that, Figure 6A and Figure 6B The embodiments employ wire bonding. For example... Figure 6A As shown, in addition to being connected to the circuit layer 290 via solder bumps, the PMIC 264 can also be bonded to the circuit layer 290 via lead 269. Figure 6B As shown, the bonding pads on the photoconductor material 240 can be connected to the bonding pads on the surface of the substrate 210 via the lead 269, and then electrically connected to the circuit layer 290 via the substrate 210 and the conductive post 252. Figure 6A and Figure 6B Other aspects of the illustrated embodiments and Figure 2 The embodiments shown are similar and will not be described again here.

[0050] Figure 7 A schematic diagram of a packaging structure according to another embodiment of the present invention is shown. Figure 2 The embodiment shown differs in that, instead of Figure 2 The conductive pillar 252 in the molded object 250, in Figure 7 In the packaging structure, a through-hole 254 can be formed through the circuit layer 290 and the molding 250. Figure 7 Other aspects of the illustrated embodiments and Figure 2 The embodiments shown are similar and will not be described again here.

[0051] According to embodiments of the present invention, a method for forming an encapsulation structure is also provided. Figures 8A to 8M Schematic diagrams are shown illustrating the various stages of a method for forming a packaging structure according to an embodiment of the present invention. For example... Figure 8A As shown, a substrate 210 is provided, and bonding pads 211 are formed on the upper and lower surfaces of the substrate 210. Conductive pillars 252 are also formed on the upper surface of the substrate 210. The top of the conductive pillars 252 may have solder bumps 251.

[0052] like Figure 8B As shown, a bonding head is used to place the PIC 220 and the light guide material 240 above the PIC 220 onto the bonding pads 211 on the upper surface of the substrate 210. The upper surface of the PIC 220 has multiple first light guide components 222, and the light guide material 240 covers these components. An etch stop layer 243 is provided on the upper surface of the light guide material 240 corresponding to the multiple first light guide components 222. Multiple bonding pads 241 are also provided on the upper surface of the light guide material 240.

[0053] like Figure 8C As shown, the circuit layer 290 pre-formed on the carrier 310 is bonded to the conductive pillar 252 and the bonding pad 241 on the optical guide material 240. The fabrication process for forming the circuit layer 290 will be described in the following reference. Figures 9A to 9H The following explanation is provided. The circuit layer 290 can be bonded to the solder bump 251 on the top of the conductive pillar 252 via solder bumps on its surface, and the circuit layer 290 can be bonded to the bonding pad 241 on the upper surface of the optical guide material 240. Furthermore, as... Figure 8C As shown, a molding compound 250 is filled between the circuit layer 290 and the substrate 210. The molding compound 250 covers the PIC 220, the light guide material 240, and the conductive pillars 252 between the circuit layer 290 and the substrate 210.

[0054] Then, as Figure 8D As shown, the surface of the substrate 210 opposite to the circuit layer 290 is exposed by removing the carrier 310. For example, the portion of the circuit layer 290 above the etch stop layer 243 is removed by chemical etching, thereby forming a cavity 245 in the circuit layer 290, such as... Figure 8E As shown. The process of forming cavity 245 stops at etch stop layer 243.

[0055] like Figure 8FAs shown, the etch stop layer 243 below the cavity 245 and the light guide material 240 above each first light guide component 222 on the PIC 220 are removed. This forms a plurality of cavities 242 in the light guide material 240, which are separated from each other by the light guide material 240, and each cavity 242 exposes a corresponding first light guide component 222.

[0056] like Figure 8G As shown, PMIC 264 and EIC 262 are positioned above circuit layer 290 using connector 315. PMIC 264 and EIC 262 can be located on opposite sides of cavity 245, respectively. In other embodiments, the positions of PMIC 264 and EIC 262 can be configured in other suitable ways. PMIC 264 and EIC 262 can be bonded to the circuitry of circuit layer 290 via solder bumps.

[0057] like Figure 8H As shown, underfill 265 is formed below PMIC 264 and EIC 262 using nozzle 316, with underfill 265 filling the space between PMIC 264 and EIC 262 and the circuit layer 290. Then as... Figure 8I As shown, adhesive material 266 is formed on PMIC 264 and EIC 262 using nozzle 316.

[0058] like Figure 8J As shown, the FAU 230 and the heat sink 270 are positioned using a connector 315. In some embodiments, the FAU 230 and the heat sink 270 may be secured together by solder 284 before placement. The FAU 230 may be secured to the heat sink 270 at an angle. The end of the heat sink 270 away from the FAU 230 may have solder bumps to engage with bonding pads on the circuit layer 290.

[0059] like Figure 8K As shown, the FAU 230 is placed within a cavity 245 in the circuit layer 290, and multiple second light guide components 232 of the FAU 230 are respectively inserted into corresponding cavities 242 within the light guide material 240. The heat dissipation component 270 is bonded to bonding pads on the circuit layer 290 via its solder bumps.

[0060] like Figure 8K As shown, colloid 282 is formed within the cavity 242 of the light-conducting material 240, and within the gaps between the FAU 230, PMIC 264, EIC 262, and heat sink 270, using nozzle 316. Colloid 282 is also disposed above the heat sink 270 to connect the heat sink 270 and the FAU 230. Figure 8KThe structure is inverted, and an electrical connector 211 is formed on the bonding pads on the surface of the substrate 210, such as... Figure 8L As shown. Then, Figure 8L The structure inverted, such as Figure 8M As shown. Along Figure 8M The dashed lines in the diagram represent the cutting process, resulting in, for example, a cutting process. Figure 2 The individual packaging structure shown.

[0061] The following is for reference Figures 9A to 9H It is the formation Figure 8C The example method at line layer 290 is explained below.

[0062] like Figure 9A As shown, a seed layer 412 and a first photoresist layer 414 are formed on the carrier 401. The first photoresist layer 414 is exposed and developed, and a plurality of first openings 415 are formed in the first photoresist layer 414, such as... Figure 9B As shown, a metallic material 420 is electroplated in the first opening 415.

[0063] Then, the first photoresist layer 414 and the seed layer 412 below the first photoresist layer 414 are removed, as follows: Figure 9C As shown. Figure 9D As shown, a dielectric layer 292 is covered on the retained seed layer 412 and the metal material 420. The dielectric layer 292 is patterned, and the process can be repeated. Figures 9A to 9B The steps involve forming a patterned seed layer 412 and a metal material 420 on top of the dielectric layer 292, such as... Figure 9E As shown. The seed layer 412 and the metal material 420 thereon are formed as vias in the circuit layer 290, where traces extend in the lateral direction and interconnect traces are connected in the vertical direction. This process can be repeated as needed. Figures 9A to 9B The steps are to form a seed layer 412 with an appropriate number of layers and a metallic material 420.

[0064] like Figure 9F As shown, an additional dielectric material is formed above the dielectric layer 292, raising the surface of the dielectric layer 292 to cover the traces of the uppermost layer. The dielectric layer 292 is patterned to form second openings 446 that expose the traces. Seed layers 412 are deposited within the plurality of second openings 446 and on the surface of the dielectric layer 292.

[0065] like Figure 9GAs shown, a photoresist layer 448 is covered on the seed layer 412. The photoresist layer 448 is exposed and developed, forming a fourth opening 449 in the photoresist layer 448. Subsequently, a metal material 420 and solder 455 are electroplated on the seed layer 412 in the fourth opening 449. The photoresist layer 448 and the seed layer 412 located below the photoresist layer 448 are removed, forming solder bumps connected to the circuit layer 290, as shown. Figure 9H As shown.

[0066] The method for forming a package structure provided by the present invention firstly fabricates a circuit layer 290 on a carrier, and then bonds conductive pillars 252 and PIC 220 to a substrate 210. Next, the circuit layer 290 is bonded to the bonding pads of the conductive pillars 252 and PIC 220. Then, a cavity 245 and multiple cavities 242 in the photoconductive material 240 are formed in the circuit layer 290 using a laser. Finally, a second photoconductive component 232 of the FAU 230, which connects to the heat dissipation component 270, is inserted into the cavity 242, and the edge of the heat dissipation component 270 is soldered to the surface of the circuit layer 290 to form the package structure.

[0067] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A packaging structure, characterized in that, include: substrate; An optical integrated circuit is located above the substrate, and a first light guide component is provided on the upper surface of the optical integrated circuit; An optical fiber array is located above the first optical guide component of the optical integrated circuit and has a second optical guide component; An optical guiding material is located between the optical integrated circuit and the optical fiber array; An electrical integrated circuit is located above the photoconductive material; A power management integrated circuit is located on opposite sides of the electrical integrated circuit in the fiber optic array; A heat dissipation component extends at least on the upper surfaces of the electrical integrated circuit and the power management integrated circuit; The circuit layer is located below the electrical integrated circuit and the power management integrated circuit; A conductive pillar is located below the circuit layer below the power management integrated circuit, wherein the conductive pillar connects the circuit layer to the substrate; A cavity is located between the electrical integrated circuit and the power management integrated circuit, and passes through the circuit layer and the optical guide material. The optical fiber array penetrates through the upper surface of the heat dissipation component and is partially disposed in the cavity. The optical fiber array is spaced apart from the optical integrated circuit and is optically coupled to the first optical guide component of the optical integrated circuit by passing through the optical guide material from the cavity via the second optical guide component.

2. The packaging structure according to claim 1, characterized in that, The bottom surface of the fiber array forms an acute angle with the upper surface of the optical integrated circuit.

3. The packaging structure according to claim 2, characterized in that, Also includes: The colloid is located at least between the optical fiber array and the optical guiding material.

4. The packaging structure according to claim 1, characterized in that, The optical guide material has a cavity that extends through the optical guide material and is located above the first optical guide component of the optical integrated circuit. The second optical guide component of the optical fiber array is optically coupled to the first optical guide component via the cavity.

5. The packaging structure according to claim 4, characterized in that, The cavity is filled with a colloid that coats the second optical guide component.

6. The packaging structure according to claim 1, characterized in that, Also includes: A molded material is located above the substrate and surrounds the optical integrated circuit and the light-conducting material.

7. The packaging structure according to claim 1, characterized in that, The fiber array has protrusions on its opposite sides.

8. The packaging structure according to claim 7, characterized in that, The two protruding portions of the fiber array are located above the electrical integrated circuit and the power management integrated circuit, respectively.

9. The packaging structure according to claim 7, characterized in that, The two protrusions of the fiber array are located above the heat dissipation component.

10. The packaging structure according to claim 4, characterized in that, The cavity is connected to the hollow cavity.

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