Pic structure with barrier around optical element opening to prevent stress damage

Abstract

The present invention relates to a PIC structure with a barrier around an opening for an optical element to prevent stress damage. A photonic integrated circuit (PIC) structure includes an active region located at least in an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are located over the active region; and an opening is defined through the plurality of dielectric interconnect layers. The opening extends at least to the active layer. A barrier is located within the plurality of dielectric interconnect layers and around the opening. An optical element is located in the opening. The barrier prevents stress damage, such as cracks and / or delamination, from propagating from or to the opening and maintains a hermetic seal of the PIC structure.

Description

Technical Field

[0001] This disclosure relates to photonic integrated circuits (PICs), and more specifically to PIC structures including barriers located within multiple dielectric interconnect layers. The barriers surround openings for optical elements within the active region of the PIC structure. The barriers prevent stress damage from affecting the integration of the PIC structure. Background Technology

[0002] Current photonic integrated circuit (PIC) architectures require complex packaging and integration schemes. One challenge is providing optical coupling between the PIC architecture and optical components such as lasers. To attach and mount separately fabricated optical components to the PIC architecture, deep openings, such as cavities or trenches, can be created in or near the center of the PIC die. To create these openings, an area must be etched to remove all back-end (BEOL) and mid-end (MOL) dielectric interconnect layers above the active layer of the PIC architecture, down to and into the substrate. The optical components can then be mounted in the openings and optically connected to other components in the PIC die, such as waveguides, photodetectors, etc. These openings can generate stress and strain in the PIC die adjacent to the active region. Therefore, cracks and / or delamination may originate from or propagate from other parts of the PIC die to the openings. The formation of these openings also compromises the hermetic seal of the dielectric interconnect layers, potentially allowing moisture to enter the active region. Summary of the Invention

[0003] One aspect of this disclosure relates to a photonic integrated circuit (PIC) structure, comprising: an active region located at least in an active layer above a substrate; a plurality of dielectric interconnect layers located above the active region; an opening extending through the plurality of dielectric interconnect layers and defined within the active region, the opening extending at least to the active layer; and a barrier located within the plurality of dielectric interconnect layers and surrounding the opening.

[0004] Another aspect of this disclosure includes a photonic integrated circuit (PIC) structure comprising: an active region located at least in an active layer above a substrate; a plurality of dielectric interconnect layers located above the active region; an opening defined through the plurality of dielectric interconnect layers and located within the active region, the opening extending at least to the active layer; and a barrier located within the plurality of dielectric interconnect layers and surrounding the opening; wherein the barrier includes a first wall portion meeting a second wall portion at a corner, and a chamfered wall portion spanning across the corner between the first wall portion and the second wall portion.

[0005] One aspect of this disclosure relates to a method comprising: forming a barrier having a plurality of dielectric interconnect layers over an active layer of an active region of a photonic integrated circuit (PIC) structure, the barrier surrounding a reserved area within the active region; forming an opening in the reserved area, the opening passing through the plurality of dielectric interconnect layers to at least the active layer of the active region; wherein the barrier includes a first wall portion meeting a second wall portion at a corner, and a chamfered wall portion spanning the corner between the first wall portion and the second wall portion.

[0006] The above and other features of this disclosure will become apparent from the following more detailed description of embodiments thereof. Attached Figure Description

[0007] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein like reference numerals denote like elements, and wherein:

[0008] Figure 1 A schematic plan view of a photonic integrated circuit (PIC) structure according to an embodiment of the present disclosure is shown.

[0009] Figure 2 The view is shown as a section along line AA. Figure 1 A schematic partial cross-sectional view of the PIC structure.

[0010] Figure 3 The view is shown as a section along line BB. Figure 1 A cross-sectional view of the PIC structure.

[0011] Figure 4 A schematic plan view of a barrier in a PIC structure according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A schematic plan view of a barrier in a PIC structure according to another embodiment of the present disclosure is shown.

[0013] Figure 6 A schematic plan view of a barrier in a PIC structure according to other embodiments of the present disclosure is shown.

[0014] Figure 7 An enlarged partial cross-sectional view of the barrier and optical elements in a PIC structure according to an embodiment of the present disclosure is shown.

[0015] Figure 8 An enlarged cross-sectional view of a barrier for a PIC structure according to an embodiment of the present disclosure is shown.

[0016] Figure 9 An enlarged cross-sectional view of a barrier for a PIC structure according to an embodiment of the present disclosure is shown.

[0017] Figure 10 A plan view of a barrier for a plurality of optical elements in a PIC structure according to an embodiment of the present disclosure is shown.

[0018] Figure 11 A cross-sectional view of a barrier and optical elements in a PIC structure according to other embodiments of the present disclosure is shown.

[0019] Figure 12 A cross-sectional view of a barrier and optical elements in a PIC structure according to other embodiments of the present disclosure is shown.

[0020] Figure 13 A perspective view of a barrier with waveguides passing through it for a PIC structure according to other embodiments of the present disclosure is shown.

[0021] Figure 14 A schematic plan view of a barrier in a PIC structure according to other embodiments of the present disclosure is shown.

[0022] Figure 15 A cross-sectional view of a barrier and optical elements in a PIC structure according to another embodiment of the present disclosure is shown.

[0023] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0024] In the following description, reference is made to the accompanying drawings, which form a part of this invention, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0025] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0026] References to "specific embodiment," "an embodiment," or "embodiment" and other variations thereof in this specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of " / ," "and / or," and "at least one" in cases such as "A / B," "A and / or B," and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0027] Embodiments of this disclosure include a photonic integrated circuit (PIC) structure. The PIC structure includes an active region in an active layer located at least above a substrate. Among possible other components, the active region may include a plurality of transistors located therein. A plurality of dielectric interconnect layers (e.g., back-end process (BEOL) or mid-end process (MOL) interconnect layers) are located above the active region. The PIC structure may also include various optical elements, such as waveguides, photodetectors, etc. An opening is defined through the plurality of dielectric interconnect layers and located within the active region, for example, in the middle of the active region. The opening extends at least into the active layer. A barrier is located within the plurality of dielectric interconnect layers and surrounds the opening. The barrier may be within the active region, for example, within all components of the active region. Optical elements, such as lasers, are located in the opening. Optical communication between the optical elements and the active region can be provided in various ways. The barrier prevents stress damage (e.g., cracks and / or delamination) from or to the opening, and the barrier hermetically seals the dielectric interconnect layers despite the opening being formed in the interconnect layers. The barrier also reinforces the dielectric interconnect layers adjacent to the opening.

[0028] Figures 1 to 3 Various views of a PIC structure 100 according to an embodiment of this disclosure are shown. Figure 1 A schematic plan view of the PIC structure 100 is shown. Figure 2 It shows along Figure 1 A schematic partial cross-sectional view taken along the centerline AA, and Figure 3It shows along Figure 1 A magnified cross-sectional view of line BB. The PIC structure 100 can provide any now-known or later-developed photonic integrated circuit functions and any necessary active components to provide those functions. Common References Figure 1 and Figure 2 The PIC structure 100 includes a body 102, within which an active region 104 is included. The active region 104 may include a plurality of transistors 106 and other integrated circuit components. The active region 104 may take any form now known or later developed. In a non-limiting example, the active region 104 may include a plurality of transistors 106 formed in and / or on an active layer 108. However, any component typically present in the active region of a PIC structure may be used. In a non-limiting example shown, the active region 104 may be formed over a semiconductor-on-insulator (SOI) substrate 109. The SOI substrate 109 may include an active (SOI) layer 108 comprising a semiconductor such as silicon, silicon-germanium, or other semiconductor materials. As known in the art, the active layer 108 may be doped in certain regions to form portions of transistors 106, interconnects, or other components. In the non-limiting example shown, the active layer 108 is located over a buried insulator layer 110, which is located over a base substrate 112. The buried insulating layer 110 may include, for example, silicon dioxide, and the base substrate 112 may include a semiconductor, such as silicon. Although the active region 104 is shown using an SOI substrate 109, it should be understood that the teachings of this disclosure apply to any form of IC substrate, such as a bulk substrate.

[0029] The PIC structure 100 also includes multiple dielectric interconnect layers 114 located above the active region 104. The dielectric interconnect layers 114 may include any now-known or later-developed interlayer dielectric material, such as, but not limited to: silicon dioxide materials, fluorinated silicate glass (FSG), organic polymeric thermosetting materials, silicon carbide, hydrogenated silicon carbide (SiCOH) dielectrics, fluorine-doped silicon oxide, spin-coated glass, silsesquioxane, etc. The dielectric interconnect layers 114 may also include any now-known or later-developed electrical interconnects (not shown for clarity) located within the respective layers, such as horizontal metal wiring and vertical vias, for example, for various portions of the active region 104 for electrical interconnection. The metal wiring and vias may comprise a body of any now-known or later-developed conductive material (e.g., copper, aluminum, tungsten, etc.) and may include a refractory metal liner such as tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh), and platinum (Pt), or mixtures thereof. Any thin-film technology can be used to form the electrical interconnects.

[0030] The active region 104 and the dielectric interconnect layer 114 can be formed using any thin-film technology now known or developed in the future. The dielectric interconnect layer 114 may include any back-to-offline (BEOL) or mid-to-offline (MOL) interconnect layer, i.e., an interconnect layer formed during device fabrication after the first metallization.

[0031] Continue to refer to Figure 1 and Figure 2 In some embodiments, the PIC structure 100 may optionally include a crack arresting ring 120 extending near the periphery 122 of the PIC structure 100 (e.g., Figure 1 (As shown by the lines in the diagram). Crack arresting ring 120, for example, is located in multiple dielectric interconnect layers 114 ( Figure 2 The crack arrest ring 120 is located outside the active region 104. It may be formed during the formation of the dielectric interconnect layer 114 (and the barrier 140 described herein), extending along the periphery 122 of the PIC structure 100 (i.e., the body 102) and located outside the outer extent 124 of the active region 104, i.e., outside all components of the active region 104. The crack arrest ring 120 may include any crack arrest ring structure now known or developed later. For example, the crack arrest ring 120 may include a plurality of interconnecting (metallic) lines and via layers 126. The metallic lines and via layers of the crack arrest ring 120 may include the same material as the electrical interconnects (not shown) in the dielectric interconnect layer 114 and may be formed using any thin-film technology.

[0032] Refer again Figures 1 to 3 The PIC structure 100 also includes an opening 130 defined through a plurality of dielectric interconnect layers 114. The opening 130 is located within the active region 104. That is, most of the components of the active region 104 are radially located outside the opening 130. In some embodiments, the opening 130 may be located within an inner range 132 of the active region, meaning that all components of the active region 104 are radially located outside the opening 130. In any case, during the fabrication of the active region 104 and the dielectric interconnect layers 114, a reserved region 134 may be located within the body 102 and within the active region 104. The reserved region 134 is reserved for the opening 130. The opening 130 is formed in the reserved region 134 and extends through the plurality of dielectric interconnect layers 114, reaching at least the active layer 108 of the active region 104. Figure 2 and Figure 3As shown, opening 130 can be formed into the base substrate 112. Opening 130 can be formed in the retention region 134 using any suitable etching process for any residual structures in layer 114 and / or retention region 134, for example, using a patterned mask (not shown) and reactive ion etching (RIE). Retention region 134 may be free of residual IC structures such as transistors, resistors, interconnects, etc., but it may include some residual IC structures that can be removed during the formation of opening 130. Although opening 130 is shown extending into the base substrate 112, it should be understood that opening 130 may extend at least into the active layer 108.

[0033] The PIC structure 100 may also include an optical element 138 located in an opening 130. The opening 130 may have any bottom surface shape and any horizontal cross-sectional shape to accommodate the optical element 138 to be located therein. Any now-known or later-developed support structure (not labeled) necessary to support and / or position the optical element 138 in the opening 130 may be provided. The optical element 138 may include any now-known or later-developed optical or photonics-based structure, which may, for example, be added to the body 102 after the formation of the body 102 and the opening 130. In some embodiments, the optical element 138 may be located outside the rest of the PIC, i.e., the optical element 138 is not integrated with the layers of the body 102 and is not formed simultaneously with the body 102 of the PIC structure 100. In one example, the optical element 138 may be a separately manufactured component, such as a laser, which is added to the body 102 after the formation of the opening 130. The optical element 138 may be coupled in the opening 130 using any now-known or later-developed processing (e.g., ball grid array technology) and may use any solution (e.g., polymer 139). Figure 1 It is sealed in place. In any case, coupling ensures that optical element 138 can optically communicate with the rest of PIC structure 100. More specifically, as further described herein, optical element 138 can optically communicate with one or more components of at least one of dielectric interconnect layer 114, buried insulating layer 110, active layer 108, and base substrate 112.

[0034] The opening 130 generates stress and strain in the body 102. It has been found that the corner regions of the opening 130 and the lower metal layer in the dielectric interconnect layer 114 near the edge of the opening 130 exhibit the highest stress. This stress can be caused, for example, by a mismatch in the coefficient of thermal expansion (CTE) between different materials during solder reflow in portions of the PIC structure 100 used for electrical interconnection. The formation of the opening 130 also compromises the hermetic seal of the dielectric interconnect layer 114, potentially allowing moisture to enter the active region 104. To address this issue, the PIC structure 100 may also include a barrier 140 located within the plurality of dielectric interconnect layers 114 and surrounding the opening 130. Figure 1 (The line in the middle). Barrier 140 is located within active region 104, that is, barrier 140 can be inside most (if not all) of active region 104 and its components. In some embodiments, barrier 140 can be within the internal range 132 of active region 104, meaning it is within all components of active region 104. In this case, barrier 140 can be shaped as a continuous loop within a certain cross-section (e.g., in the line in the middle). Figure 1 (As shown in the plan view).

[0035] Barrier 140 may include any structure capable of preventing stress damage caused by opening 130 in body 102. In some embodiments, barrier 140 includes a plurality of interconnected wire and via layers 142, similar to crack arrester 120. That is, each wall of barrier 140 includes a plurality of interconnected wire and via layers 142. In some embodiments, barrier 140 may simply include a plurality of interconnected wire and via layers 142 arranged to surround opening 130. Here, barrier 140 is structurally similar to crack arrester 120, but is located within active region 104, rather than outside active region 104 as in all conventional crack arresters. Barrier 140 may have any shape in the plane of body 102, configured to surround opening 130. Figure 1 As shown in the phantom view, barrier 140 includes a first wall portion 144 that meets a second wall portion 146 at a corner 148. Barrier 140 can have any polygon containing walls 144, 146. In the specific example shown, barrier 140 is rectangular and includes a pair of first wall portions 144A, 144B and opposing pairs of second wall portions 146A, 146B. Here, the first wall portions 144A, 144B meet with the opposing pairs of second wall portions 146A, 146B to form four corners 148. Similarly, each wall portion 144, 146 includes a plurality of interconnecting lines and via layers 142 ( Figures 2 to 3In this way, barrier 140 can prevent stress damage from propagating to or from opening 130, and prevent the formation of cracks, delamination, and other physical damage. Barrier 140 also hermetically seals dielectric insulation layer 114 to prevent moisture damage to the structure. Barrier 140 also provides additional structural support for dielectric interconnect layer 114.

[0036] In other embodiments, barrier 140 may include the aforementioned wall portions 144, 146 and additional structures. The additional structures improve the barrier performance in relation to opening 130 and optical element 138. Figures 4 to 6 Schematic plan views of various embodiments of the barrier 140 including these additional structures are shown.

[0037] like Figure 4 As shown, in some embodiments, barrier 140 includes one or more first wall portions 144 that meet one or more second wall portions 146 at one or more corners 148, and chamfered wall portions 150 traverse between one or more first wall portions 144 and one or more second wall portions 146 across one or more corners 148. While not required at all corners 148, chamfered wall portions 150 may traverse between each first wall portion 144 and the corresponding second wall portion 146 across each corner 148. In the example shown, one or more first wall portions 144 meet the first or more second wall portions 146 at a vertical angle at one or more corners 148. Therefore, one or more chamfered wall portions 150 traverse between one or more first wall portions 144 and one or more second wall portions 146 across a vertical angle. It will be appreciated that in other embodiments, wall portions 144, 146 may not meet at a vertical angle. Figure 4 A barrier 140 with optical elements 138 is shown. Each wall portion 144, 146, 150 includes a plurality of interconnecting lines and via layers 142. Figures 2 to 3 One or more chamfered wall portions 150 improve the barrier's resistance to stress damage and hermetic seal retention by providing wall portions in the locations of highest stress (i.e., the corner regions of opening 130 and the lower metal layer in the dielectric interconnect layer 114 near the edge of opening 130).

[0038] exist Figure 5In this design, barrier 140 includes one or more first wall portions 144 that meet one or more second wall portions 146 at one or more corners 148, for example, in a rectangular shape. However, instead of chamfered wall portions 150, barrier 140 includes corner buttresses 156 located at one or more corners 148. In some embodiments, as shown, barrier 140 may include corner buttresses 156 located at each corner 148. Corner buttresses 156 may include first support wall portions 160 coupling extensions 162 of the first wall portions 144 and second support wall portions 164 of the first wall portions 144. Corner buttresses 156 also include third support wall portions 168 coupling extensions 162 of the first wall portions 144 and extensions 166 of the second wall portions 146. Each corner buttress 156 includes a plurality of interconnecting lines and via layers 142, i.e., vertically entering the page. In general, the corner support 156 forms three triangular walls 170A-C on the outside of the corner 148. One or more corner supports 156 improve the barrier's resistance to stress damage and its airtightness by providing walls at the location of highest stress and on the outside of the inside of the corner 148 so as not to interfere with the space of the optical element 138. Figure 5 A barrier 140 having an optical element 138 is shown.

[0039] like Figure 6 As shown, in some embodiments, barrier 140 includes Figure 4 and Figure 5 Additional structures. More specifically, barrier 140 includes one or more first wall portions 144 that meet one or more second wall portions 146 at one or more corners 148, and one or more chamfered wall portions 150 that span between one or more first wall portions 144 and one or more second wall portions 146 across one or more corners 148. In the example shown, one or more first wall portions 144 meet one or more second wall portions 146 at a vertical angle at one or more corners 148. Therefore, one or more chamfered wall portions 150 span between one or more first wall portions 144 and one or more second wall portions 146 across a vertical angle. As noted, wall portions 144, 146 may not meet at a vertical angle. Figure 6In some embodiments, barrier 140 may further include corner supports 156 located at one or more corners 148. As indicated, corner supports 156 include a first support wall portion 160 coupling an extension 162 of the first wall portion 144 and a second wall portion 146. Corner supports 156 also include an extension 166 coupling the second wall portion 146 and a second support wall portion 164 coupling the first wall portion 144. Corner supports 156 also include a third support wall portion 168 coupling the extension 162 of the first wall portion 144 and the extension 166 of the second wall portion 146. The first and second wall portions 144, 146, their extensions 162, 166, the chamfered wall portion 150, and the wall portions 160, 164, 168 of corner supports 156 include a plurality of interconnecting lines and via layers 142. The use of chamfered wall portion 150 and one or more corner supports 156 together improves the barrier's resistance to stress damage and maintains its airtight seal by providing barrier wall portions inside and outside the corner 148 at locations of highest stress and strain. Figure 6 A barrier 140 having an optical element 138 is shown.

[0040] In terms of vertical cross-sectional shape, the barrier 140 can have various shapes. For example... Figure 3 As shown, the barrier 140 may have a periphery comprising an inner sidewall 172 and an outer sidewall 174, which are respectively generally vertically aligned. Figure 7 As shown, the barrier 140 may have a periphery comprising an inner wall 172 and an outer wall 174 that are respectively generally stepped. Figure 7 The sidewalls 172 and 174 can be referred to as stepped bidirectional bumpers. Here, barrier 140 narrows as it extends upwards. The outermost layer 178 of barrier 140 can be wider than the layers below it to trap cracks / delamination. Barrier 140 can be approximately symmetrical (see example...). Figure 7 ), but does not need to be perfectly symmetrical (see example) Figure 8 ).like Figure 8 As shown, stepped sidewalls 172, 174 are advantageous because they can redirect the propagation of any crack 176 in a direction that can cause less damage, such as vertically toward the outermost layer 178 of barrier 140. In the case of using stepped bidirectional buffers, stepped bidirectional buffers can redirect cracks or delaminations, whether the cracks or delaminations originate from opening 130 and propagate outwards, or originate from other locations on the body 102 and propagate inwards toward opening 130.

[0041] Regardless of the embodiment, barrier 140 can be positioned above the active layer 108 of the active region 104 of PIC structure 100, similar to crack arrest ring 120. Figure 1 and Figure 2The barrier 140 is formed together with multiple dielectric interconnect layers 114 in a manner that allows it to be constructed. As noted, after fabrication, the barrier 140 surrounds a retention area 134 within the active region 104, and an opening 130 is formed therein. As described above, the barrier 140 can be formed in which one or more first wall portions 144 meet one or more second wall portions 146 at one or more corners 148, and one or more chamfered wall portions 150 traverse across the respective one or more corners 148 between the respective one or more first wall portions 144 and one or more second wall portions 146. In the configuration, the barrier 140 may also include forming corner supports 156, wherein forming corner supports 156 includes forming: extensions 162, 166 of the first and second wall portions 144, 146, and wall portions 160, 164, 168 of the corner support 156. The barrier 140 may include multiple interconnected (metallic) lines and via layers 142. The metal wires and via layers of the crack arrestor ring 120 may comprise the same material as the electrical interconnects (not shown) in the dielectric interconnect layer 114, and may be formed using any thin film technology.

[0042] refer to Figure 9 The barrier 140 may optionally include a plurality of anchors 180 coupled to the lowest layer 182 of the plurality of interconnecting lines and via layers 142. The anchors 180 extend at least into the base substrate 112 to improve the physical coupling of the barrier 140 and increase resistance to stress damage propagating to or from the opening 130. The anchors 180 may be formed during and in a manner similar to that of a through-silicon via (TSV). Since the techniques for forming TSVs are known, further details are unnecessary.

[0043] refer to Figure 10 In some embodiments, opening 130 may include a plurality of openings 130A-H, which are defined within a plurality of dielectric interconnect layers 114 and located within the active region 104. Figure 10 The diagram shows eight (8) openings 130A-H, but it should be recognized that any number can be used. Figure 3As shown, each opening 130A-H extends at least into the active layer 108 and may extend into the base substrate 112. Barriers 140 within a plurality of dielectric interconnect layers 114 surround each opening 130A-H. Optical elements 138 may be located within each opening 130A-H. The openings 130A-H may be formed as described herein and may be defined within a plurality of dielectric interconnect layers 114 and located within the active region 104. Each opening 130A-H extends at least into the active layer 108 and may extend into the buried insulating layer 110 and the substrate 112. Here, barriers 140 within the dielectric interconnect layers 114 surround each opening 130A-H. Thus, the barriers 140 provide walls (like a cage surrounding the elements) between each element 138, preventing interaction between the plurality of adjacent openings 130A-H. While any embodiment of the barrier 140 described herein may be used, Figure 7 The stepped bidirectional buffer embodiment for Figure 10 This embodiment is advantageous because it increases the ability to handle stress propagating from any direction. Optical elements 138 can be coupled within each opening 130A-H. Here, the barrier 140 can resist stress damage propagating to or from the openings 130A-H, and can resist stress damage leading to cracks, delamination, and other physical damage. The barrier 140 also maintains a hermetic seal and provides additional structural support for the dielectric interconnect layer 114.

[0044] Optical element 138 can optically communicate with one or more components of at least one of the dielectric interconnect layer 114, buried insulating layer 110, active layer 108, and base substrate 112. Optical communication can be configured in various ways. In some embodiments, such as... Figure 2 As shown, optical element 138 can directly communicate optically with photodetector 184 facing opening 130 from dielectric interconnect layer 114 adjacent to opening 130. Photodetector 184 can then communicate electrically beneath barrier 140 via electrical interconnects 186 (e.g., doped wells) in dielectric interconnect layer 114, active layer 108, buried insulating layer 110, and / or base substrate 112. In other embodiments, such as... Figure 11 As shown, optical element 138 can directly communicate optically with waveguide 190 facing opening 130 from dielectric interconnect layer 114 adjacent to opening 130. Waveguide 190 can then communicate optically under barrier 140 via optical interconnects 192 (optical tunnels) in dielectric interconnect layer 114, active layer 108, buried insulating layer 110 and / or base substrate 112. In some embodiments, such as Figure 12As shown, optical element 138 can be directly optically connected to waveguide 196 extending from buried insulating layer 110 adjacent to opening 130 towards opening 130. Waveguide 196 can then perform optical communication beneath barrier 140 via buried insulating layer 110. In another embodiment, as... Figure 13 As shown, waveguide 200 can extend laterally through barrier 140. Waveguide 200 can be configured to perform optical communication between components (e.g., photodetectors, waveguides, etc.) and optical elements 138 in a plurality of dielectric interconnect layers 114 and possibly in at least one of buried insulating layer 110, active layer 108, and base substrate 112. The waveguides described herein can include any waveguide structures and materials now known or hereafter developed, such as silicon and / or silicon nitride.

[0045] In the previously described embodiments, the opening 130, optical element 138, and barrier 140 are mostly illustrated as rectangles. Figure 14 As shown, the opening 130, optical element 138, and / or barrier 140 can have other shapes. In the example shown, they have a hammerhead shape. The barrier 140 may include any chamfered wall portion 150 and corner support 156 as needed. Figure 14 It is also shown that the chamfered wall portion 150X can also face outward from the opening 130, wherein the first wall portion 144X and the second wall portion 146X meet in a manner facing outward from the opening 130, thereby creating an outward-facing corner 148X.

[0046] Figure 15 A cross-sectional view of another embodiment of the barrier 140 in the PIC structure 100 is shown. Here, the barrier 140 includes a solid material 202 forming a solid wall around the opening 130. The material 202 may include, for example, a dielectric (e.g., an oxide) or a conductor (e.g., those used for TSVs, such as copper, tungsten, or aluminum).

[0047] Any embodiment of barrier 140 can be used in conjunction with any other embodiment.

[0048] Embodiments of this disclosure provide a PIC structure including a barrier to prevent stress damage, such as cracks and / or delamination, from propagating from or to an opening within the active region of an optical element. In one example, for Figure 5 In one embodiment, data showed that stress and strain at the corner were reduced by up to 32% compared to an opening without a barrier. The barrier also maintains the hermetic seal of the BEOL dielectric interconnect layer, despite the openings formed therein. Barrier 140 also reinforces the dielectric interconnect layer. When providing more than one optical element, the barrier provides a wall between each element, i.e., like a cage surrounding the element.

[0049] The methods and structures described herein are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0051] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0052] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A photonic integrated circuit (PIC) structure, comprising: The active region is located at least in the active layer above the substrate; Multiple dielectric interconnect layers are located above the active region; An opening that extends through the plurality of dielectric interconnect layers and is located within the active region, the opening extending at least into the active layer; as well as A barrier, located within the plurality of dielectric interconnect layers and surrounding the opening, the barrier comprising: The first wall section meets the second wall section at the corner; as well as A first supporting wall portion, which couples an extension of the first wall portion and a second wall portion.

2. The PIC structure according to claim 1, wherein the barrier further includes a chamfered wall spanning across the corner between the first wall and the second wall.

3. The PIC structure according to claim 2, wherein the barrier further comprises: A second supporting wall portion, which couples an extension of the second wall portion and the first wall portion; as well as A third supporting wall portion is coupled to the extension portion of the first wall portion and the extension portion of the second wall portion.

4. The PIC structure of claim 1, wherein the barrier is rectangular, and the first wall portion includes a first wall portion pair, the second wall portion includes an opposing second wall portion pair, the first wall portion pair and the opposing second wall portion pair meeting to form four corners, and wherein a chamfered wall portion spans across each corner between each first wall portion and the corresponding second wall portion.

5. The PIC structure according to claim 1, wherein the barrier further includes a corner support, the corner support comprising: The first supporting wall portion is coupled to the extension portion of the first wall portion and the second wall portion; A second supporting wall portion, which couples an extension of the second wall portion and the first wall portion; as well as A third supporting wall portion is coupled to the extension portion of the first wall portion and the extension portion of the second wall portion.

6. The PIC structure according to claim 5, wherein the barrier is rectangular, and the first wall portion includes a first wall portion pair, the second wall portion includes opposing second wall portion pairs, the first wall portion pair and the opposing second wall portion pair meeting to form four corners, and wherein a corner support is provided at each corner.

7. The PIC structure of claim 1, wherein the opening comprises a plurality of openings defined within the plurality of dielectric interconnect layers and located within the active region, each opening extending at least into the active layer, and wherein the barrier located within the plurality of dielectric interconnect layers surrounds each opening, and The PIC structure further includes optical elements located within each opening.

8. The PIC structure of claim 1, wherein the barrier comprises a plurality of interconnecting lines and via layers; and Multiple anchors are coupled to the lowest layer of the multiple interconnected lines and vias, and extend at least into the substrate.

9. The PIC structure according to claim 1, further comprising: An optical element is located in the opening; as well as A waveguide extending laterally through the barrier, the waveguide being configured to enable optical communication between components in at least one of the plurality of dielectric interconnect layers, the active layer, and the substrate and the optical element.

10. The PIC structure of claim 1, further comprising a crack-stopping ring extending around the outer periphery of the PIC structure, wherein the crack-stopping ring is located outside the active region.

11. A photonic integrated circuit (PIC) structure, comprising: The active region is located at least in the active layer above the substrate; Multiple dielectric interconnect layers are located above the active region; Multiple openings are defined within the multiple dielectric interconnect layers and located within the active region, each opening extending at least into the active layer; Optical elements located within each opening; as well as A barrier is located within the plurality of dielectric interconnect layers and surrounds each opening; in The barrier includes a first wall portion that meets a second wall portion at a corner, an extension of the first wall portion and a first support wall portion that couples the second wall portion, and a chamfered wall portion that spans across the corner between the first wall portion and the second wall portion.

12. The PIC structure of claim 11, wherein the barrier further comprises a corner support, the corner support comprising: The first supporting wall portion is coupled to the extension portion of the first wall portion and the second wall portion; A second supporting wall portion, which couples an extension of the second wall portion and the first wall portion; as well as A third supporting wall portion is coupled to the extension portion of the first wall portion and the extension portion of the second wall portion.

13. The PIC structure of claim 11, wherein the barrier comprises a plurality of interconnecting lines and via layers; and Multiple anchors are coupled to the lowest layer of the multiple interconnected lines and vias, and extend at least into the substrate.

14. The PIC structure of claim 11, further comprising a crack-stopping ring extending around the outer periphery of the PIC structure, the crack-stopping ring being located outside the active region.

15. The PIC structure according to claim 11, further comprising: A waveguide extending laterally through the barrier, the waveguide being configured to enable optical communication between components in at least one of the plurality of dielectric interconnect layers, the active layer, and the substrate and the optical element.

16. A method for forming a photonic integrated circuit (PIC) structure, comprising: A barrier having multiple dielectric interconnect layers is formed above the active layer of the active region of the photonic integrated circuit (PIC) structure, the barrier surrounding the reserved region within the active region; An opening is formed within the reserved area, the opening extending through the plurality of dielectric interconnect layers to at least the active layer of the active region; and The barrier includes a first wall portion that meets a second wall portion at a corner, a first support wall portion that couples the first wall portion and the second wall portion, and a chamfered wall portion that spans across the corner between the first wall portion and the second wall portion.

17. The method of claim 16, wherein forming the barrier further comprises forming a corner support, the forming of the corner support comprising: The first support wall portion is formed, and the first support wall portion is coupled to the extension portion of the first wall portion and the second wall portion; A second support wall portion is formed, and the second support wall portion is coupled to an extension of the second wall portion and the first wall portion; as well as A third support wall portion is formed, wherein the third support wall portion is coupled to the extension portion of the first wall portion and the extension portion of the second wall portion.

18. The method of claim 16, wherein forming the opening comprises forming a plurality of openings defined within the plurality of dielectric interconnect layers and located within the active region, each opening extending at least into the active layer, and wherein the barrier within the plurality of dielectric interconnect layers surrounds each opening, and The method further includes coupling optical elements within each opening.

19. The method of claim 16, further comprising coupling an optical element in the opening.

20. The method of claim 16, further comprising: During the formation of the barrier, a crack arresting ring is formed, which extends along the outer periphery of the PIC structure and is located outside the outer range of the active region.

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