A time-to-digital converter based on pulse stretching

Abstract

The application discloses a time-to-digital converter based on pulse stretching. The time-to-digital converter structure combines frequency multiplication delay locked loop, pulse stretching circuit and calibration circuit, guarantees high resolution, effectively increases the range of the time-to-digital converter, and can reduce the influence of PVT. The calibration circuit has simple structure, low calibration cost, and is suitable for the calibration of the pulse stretching circuit. In addition, the calibration algorithm for the static phase error of the frequency multiplication delay locked loop only needs to increase a 1bit counter, the additional circuit cost is very small, and the influence of the static phase error of the frequency multiplication delay locked loop can be overcome.

Description

Technical Field

[0001] This invention belongs to the field of digital circuits, and specifically relates to a time-to-digital converter based on pulse broadening. Background Technology

[0002] A time-to-digital converter (TDC) converts time intervals into digital signals and is a core component of time quantization systems. TDCs have wide applications, such as lidar ranging, medical imaging, and ultrasonic flow meters. The simplest TDC consists of a delay line and a sampling circuit, quantizing the time interval by recording the number of delay units the signal travels through within the measured time interval. However, the resolution of this TDC cannot be less than the delay of the delay unit, and the measurement range is limited by the number of delay units. Currently, various TDC structures exist that reduce the resolution to less than the delay of the delay unit, such as vernier TDCs, locally passive interpolation TDCs, and pulse contraction TDCs. In a vernier TDC, the start signal propagates in a slow delay chain, and the end signal propagates in a fast delay chain. By counting the number of delay units the end signal catches up with the start signal, the resolution can be reduced to the delay difference between the fast and slow delay units. Local passive interpolation TDC inserts multiple resistors between the beginning and end of delay units, and inserts multiple rising edges between the delay units, thus reducing the resolution to a lower value than the delay time of the delay unit itself. In pulse contraction TDC, the propagation delay of the rising edge of the signal input to the delay unit is greater than the propagation delay of the falling edge. Therefore, a pulse signal, after passing through a certain number of delay units, is eventually contracted to a fixed level. The resolution of pulse contraction TDC is the difference between the propagation delays of the rising and falling edges. To achieve a large measurement range, multi-step measurements are generally adopted. An external clock or a high-resolution TDC (usually in the form of a ring TDC) is used for preliminary quantization, and then a fine TDC is used for fine quantization of the margin.

[0003] A pulse stretching circuit can stretch a narrow pulse into a wide pulse by a certain ratio. The quantization of the wide pulse can be used to quantize the narrow pulse, thereby reducing the resolution. Reference [1] inputs the time interval between the rising edge of the input signal and the rising edge of the clock into the pulse stretching circuit, stretching the pulse by about 240 times. Then, it counts the pulses using an 80MHz clock, thereby achieving a resolution of 50ps. The disadvantage of the TDC in Reference [1] is that it requires an external high-frequency clock input, and the stretching factor of the pulse stretching needs to be calibrated by an external circuit. Reference [2] improves the pulse stretching circuit based on Reference [1], giving it a three-slope stretching. However, it does not solve the disadvantage of Reference [1]. In Reference [3], the pulse stretching circuit acts as a time amplifier, precisely amplifying the time interval by 4 times. However, in Reference [3], the resolution is determined by the vernier-type TDC, which is independent of the stretching factor of the pulse stretching circuit. In addition, the pulse stretching circuit requires precise amplification and needs to be combined with other additional circuits, making the circuit relatively complex.

[0004] References:

[0005] [1]Chen P, Chen CC, Shen Y SA Low-Cost Low-Power CMOS Time-to-DigitalConverter Based on Pulse Stretching[J]. IEEE Transactions on Nuclear Science, 2006, 53(4): 2215-2220.

[0006] [2]Kim M,Lee H,Woo JK,et al.A Low-Cost and Low-Power Time-to-DigitalConverter Using Triple-Slope Time Stretching[J].IEEE Transactions onCircuits&Systems II Express Briefs,2011,58(3):169-173.

[0007] [3] Guo Weiwei, Yin Yongsheng, Gong Hao, Meng Xu, Chen Zhenhai, Deng Honghui. Design of a time-to-digital converter based on time amplification technology [J]. Journal of Electronic Measurement & Instrumentation, 2022, 36(04):98-105. DOI:10.13382 / j.jemi.B2104759.3

[0008] In summary, the shortcomings of the existing technology are as follows: 1. TDC based on pulse widening circuit requires a high-frequency off-chip input clock; 2. The calibration of the pulse widening circuit is performed off-chip; 3. The static phase error of MDLL has a direct impact on the results of TDC. Summary of the Invention

[0009] The main objective of this invention is to overcome the shortcomings of the prior art and to propose a pulse-spanning-based time-to-digital converter, provide a circuit for measuring time intervals, and an algorithm for overcoming MDLL static phase errors.

[0010] The specific technical solution adopted in this invention is as follows:

[0011] A time-to-digital converter based on pulse broadening includes a frequency-doubling delay phase-locked loop, a pulse generation circuit, a calibration circuit, a delay circuit, an encoder, a pulse broadening circuit, a first selector, a first counter, a second counter, and a third counter.

[0012] The input to the frequency multiplication delay phase-locked loop is an external reference clock CLKREF, the first output is the high-frequency clock CLK, and the second output is the multi-phase clock CLK0-CLK. 11 ;

[0013] The first input of the pulse generation circuit is the output CLK of the frequency multiplication delay phase-locked loop, the second input is the signal to be quantized INPUT, the first output signal is P1, and the second output is CEN;

[0014] The first input of the calibration circuit is the output CLK of the frequency doubling delay phase-locked loop, the second input is the enable signal CALIBRATION, the third input is the output DONE of the pulse widening circuit, and the output signal is P2.

[0015] The first input of the delay circuit is the output CLK of the frequency doubling delay phase-locked loop, the second input is the output DONE of the pulse widening circuit, and the output signal is RESET;

[0016] The first input of the encoder is the output CLK0-CLK of the frequency multiplication delay phase-locked loop. 11 The second input is the output DONE of the pulse stretching circuit; the encoder output is PHASE<3:0>, which is part of the fine quantization result.

[0017] The first input of the pulse widening circuit is the output TOUT of the first selector, the second input is the output RESET of the delay circuit, and the output signal is DONE.

[0018] The first input of the first selector is the output signal P1 of the pulse generation circuit, the second input is the output signal P2 of the calibration circuit, the third input is the enable signal CALIBRATION, and the output signal is TOUT.

[0019] The first input of the first counter is the output CEN of the pulse generation circuit, and the second input is the output CLK of the frequency multiplication delay phase-locked loop; the output of the first counter is COARSE<19:0>, which serves as the coarse quantization result.

[0020] The first input of the second counter is the output TOUT of the first selector, the second input is the output CLK of the frequency multiplication delay phase-locked loop, and the third input is the output DONE of the pulse widening circuit; the output of the second counter is FINE<7:0>, which is part of the fine quantization result;

[0021] The first input of the third counter is the output CEN of the pulse generation circuit, and the second input is the external reference clock CLKREF; the output of the third counter is OUTM, which is used to eliminate the influence of the static phase error of the frequency doubling delay phase-locked loop.

[0022] Preferably, the calibration signal generation circuit in the calibration circuit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a second selector, a first AND gate, and an inverter;

[0023] The D terminal of the first D flip-flop is connected to the first D flip-flop. The clock input terminal is connected to CLK, the reset terminal is connected to the reset signal RN, and the Q terminal is connected to the second input of the second selector.

[0024] The first input of the second selector is connected to CLK, and the third input is connected to the selection signal SEL.

[0025] The D terminal of the second D flip-flop is connected to the second D flip-flop. The clock input terminal is connected to the output of the second selector, the reset terminal is connected to the reset signal RN, and the Q terminal is connected to the input of the inverter and the second input of the first AND gate.

[0026] The D terminal of the third D flip-flop is connected to the power supply voltage VDD, the clock input terminal is connected to the output of the inverter, the reset terminal is connected to the reset signal RN, and the Q terminal is left floating. The terminal is connected to the first input of the first AND gate;

[0027] The output of the first AND gate is P2.

[0028] Preferably, during the operation of the calibration signal generation circuit, CLK is divided by two or four according to the selection signal SEL. The inverter on the right, the third D flip-flop, and the first AND gate can convert the divided clock into a one-time pulse. In conjunction with the input reset signal RN, pulses with a width of one clock cycle and two clock cycles are continuously output sequentially.

[0029] Preferably, the calibration circuit, in addition to the calibration signal generation circuit, also includes a logic circuit for generating a selection signal SEL and a reset signal RN, the generation logic being:

[0030] 1. When CALIBRATION is low, RN is low;

[0031] 2. When CALIBRATION changes from low to high, RN changes from low to high.

[0032] 3. When CALIBRATION is high, the following process is continuously executed in a loop:

[0033] First, P2 outputs a pulse;

[0034] Then, after P2 outputs a pulse, RN goes low, and SEL performs a level switch;

[0035] Then, after the pulse widening circuit output signal DONE changes from high to low, RN changes to high.

[0036] Preferably, the pulse generation circuit includes a fourth D flip-flop, a fifth D flip-flop, and a second AND gate;

[0037] The D terminal of the fourth D flip-flop is connected to the power supply voltage VDD, the clock input is connected to CLK, the reset terminal is connected to INPUT, and the Q terminal is connected to the D terminal of the fifth D flip-flop. The end is suspended in the air;

[0038] The clock input of the fifth D flip-flop is connected to CLK, the reset input is connected to the reset signal RST, and the Q input is left floating. The terminal is connected to the first input of the second AND gate;

[0039] The second input of the second AND gate is INPUT, and the output is P1.

[0040] Preferably, the pulse widening circuit includes a first capacitor, a second capacitor, a first current source, a second current source, a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, logic circuitry, and a comparator; the capacitance of the second capacitor is greater than that of the first capacitor.

[0041] One end of the first capacitor is grounded, and the other end is connected to the drain of the first MOSFET, the drain of the third MOSFET, and the positive input of the comparator.

[0042] One end of the second capacitor is grounded, and the other end is connected to the drain of the second MOSFET, the drain of the fourth MOSFET, and the negative input terminal of the comparator.

[0043] The gate of the first MOSFET is connected to the first output T1 of the logic circuit, and the source is connected to the current input terminal of the first current source.

[0044] The gate of the second MOSFET is connected to the second output T2 of the logic circuit, and the source is connected to the current input terminal of the second current source.

[0045] The current output terminals of the first current source and the second current source are grounded;

[0046] The sources of the third and fourth MOSFETs are both connected to the power supply VDD, and their gates are both connected to the reset signal RESET.

[0047] The input to the logic circuit is the output TOUT of the first selector;

[0048] The comparator output is DONE.

[0049] Preferably, during the operation of the pulse widening circuit, after the input pulse signal TOUT, the logic circuit first outputs a pulse signal T1 with the same width as TOUT. At this time, the first MOS transistor turns on, and the first current source discharges the first capacitor, causing the voltage of the first capacitor to drop rapidly. After the pulse signal T1, the output signal T2 of the logic circuit remains at a high level. At this time, the second current source discharges the second capacitor, causing the voltage of the second capacitor to drop slowly. When the voltages of the first capacitor and the second capacitor are equal, the comparator output signal DONE switches to a high level, and after waiting for a period of time, the voltages of the first capacitor and the second capacitor are reset.

[0050] Preferably, in the pulse-span-based time-to-digital converter, the frequency-multiplied delay phase-locked loop (PLL) multiplies the input reference clock CLKREF, generating a high-frequency clock CLK for input to other circuits, and outputting a multi-phase clock CLK0-CLK. 11For fine quantization; the quantization at the rising edge of the input signal INPUT is completed by the first counter, the second counter, the third counter and the encoder. First, the output CLK of the frequency multiplication delay locked loop is used for coarse quantization. When the first rising edge of INPUT arrives, the output CEN of the pulse generation circuit generates a rising edge, and the first counter is enabled. CLK starts to drive CNT1, and at this time, the value of CNT1 is 0. After each subsequent rising edge of INPUT arrives, the output CEN of the pulse generation circuit will generate a rising edge. At this time, record the value COARSE<19:0> of the first counter. Then, take the time interval between the rising edge of INPUT and the next rising edge of CLK as the margin P1 and perform fine quantization on the margin. A complete clock cycle T CLK Subtracting the margin gives the time interval between the rising edge of INPUT and the previous rising edge of the clock; this margin P1 is generated by the pulse generation circuit. After adding an offset of one clock cycle to the margin P1, it is input to the pulse broadening circuit, which extends this time interval proportionally and enables the second counter at the same time. When the output signal DONE of the pulse broadening circuit converts to high level at the end of the extension, record the second counter and the encoder at this time to obtain FINE<7:0> and the phase PHASE<3:0> of the frequency multiplication delay locked loop.

[0051] Preferably, the quantization result of the rising edge of the input signal INPUT is:

[0052]

[0053] In the formula: T REF is the input reference clock period, D C is the result COARSE<19:0> of the first counter, D F is the result FINE<7:0> of the second counter, D P is the phase PHASE<3:0> of the frequency multiplication delay locked loop, M is the frequency multiplication ratio of the frequency multiplication delay locked loop, N is the number of bits of the first counter, and P is the number of phases of the frequency multiplication delay locked loop.

[0054] Preferably, the quantization result of the rising edge of the input signal INPUT is:

[0055]

[0056] In the formula: The coefficients a and b need to satisfy the following three conditions: a mod 2 = OUTM, M * a + b = D C , -M < b < M, and both coefficients are integers; T REF is the input reference clock period, D C is the result COARSE<19:0> of the first counter, D FFor the result of the second counter, FINE<7:0>, D P Let PHASE<3:0> be the phase of the frequency-multiplied delay phase-locked loop (PLL), M be the frequency multiplication ratio of the PLL, N be the number of bits in the first counter, and P be the number of phases in the PLL. Of the M cycles output by the PLL, one cycle has a width of T. M The width of the remaining M-1 periods is

[0057] Compared with the prior art, the present invention has the following advantages:

[0058] Existing technologies require high-frequency input clocks, and the calibration of the pulse stretching circuit requires off-chip circuitry, making real-time calibration difficult. In TDCs with frequency multiplier circuits, some existing solutions employ a PLL+DLL method to avoid the influence of MDLL static phase error, resulting in high circuit costs. The TDC structure proposed in this invention combines MDLL, pulse stretching circuit, and calibration circuit, ensuring high resolution while effectively increasing the TDC range and reducing the influence of PVT. The calibration circuit has a simple structure, low calibration cost, and is suitable for calibrating pulse stretching circuits. Furthermore, the calibration algorithm for MDLL static phase error only requires adding a 1-bit counter, resulting in minimal additional circuit cost, while simultaneously overcoming the influence of MDLL static phase error. Attached Figure Description

[0059] Figure 1 This is a diagram showing the overall structure of a pulse-spanning time-to-digital converter.

[0060] Figure 2 This is the timing diagram of TDC during normal operation.

[0061] Figure 3 This is the calibration signal generation circuit in the calibration circuit.

[0062] Figure 4 This is a pulse generation circuit.

[0063] Figure 5 This is a pulse broadening circuit.

[0064] Figure 6 This is a schematic diagram of the capacitor voltage in a pulse broadening circuit. Detailed Implementation

[0065] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. Technical features in the various embodiments of the present invention can be combined accordingly without mutual conflict.

[0066] In the description of this invention, it should be understood that the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include at least one of those features.

[0067] This invention proposes a time-to-digital converter (TDC) structure based on pulse broadening and a calibration algorithm to address the impact of static phase error in the multiplying delay-locked loop (MDLL). The TDC uses a low-frequency input reference clock with a multiplied delay-locked loop (MDLL), which allows for coarse quantization of the input time. The pulse broadening circuit broadens the margin after coarse quantization by a certain proportion, thereby achieving high-resolution quantization. Through time quantization, this TDC can be applied to scenarios where the input interval is less than the time-of-flight, such as ultrasonic flow meters. The measurement result of the time interval is the difference (t2-t1) between the quantization results t1 and t2 of the two desired times. Subtracting the quantization results effectively avoids errors caused by the fixed propagation delay in the pulse broadening circuit. Furthermore, the MDLL and calibration circuit in this invention can reduce the influence of process, voltage, and temperature (PVT).

[0068] In a preferred embodiment of the present invention, a time-to-digital converter based on pulse broadening is provided, the basic working principle of which is as follows: Figure 1 As shown, the specific circuit structure includes a frequency multiplication delay phase-locked loop (MDLL), a pulse generation circuit (A), a calibration circuit (B), a delay circuit (D), an encoder (E), a pulse widening circuit (F), a first selector (MUX1), a first counter (CNT1), a second counter (CNT2), and a third counter (CNT3). The specific connection methods and signal transmission processes of each circuit module are described in detail below.

[0069] The input to the frequency multiplication delay phase-locked loop (MDLL) is an external reference clock CLKREF, the first output is the high-frequency clock CLK, and the second output is the multiphase clock CLK0-CLK. 11 ;

[0070] The first input of the pulse generation circuit A is the output CLK of the frequency multiplication delay phase-locked loop MDLL, the second input is the signal to be quantized INPUT, the first output signal is P1, and the second output is CEN;

[0071] The first input of calibration circuit B is the output CLK of frequency doubling delay phase-locked loop MDLL, the second input is the enable signal CALIBRATION, the third input is the output DONE of pulse widening circuit F, and the output signal is P2.

[0072] The first input of the delay circuit D is the output CLK of the frequency multiplication delay phase-locked loop MDLL, the second input is the output DONE of the pulse widening circuit F, and the output signal is RESET;

[0073] The first input to encoder E is the output CLK0-CLK of the frequency multiplication delay phase-locked loop (MDLL). 11 The second input is the output DONE of the pulse stretching circuit F; the output of encoder E is PHASE<3:0>, which is part of the fine quantization result.

[0074] The first input of the pulse widening circuit F is the output TOUT of the first selector MUX1, the second input is the output RESET of the delay circuit, and the output signal is DONE;

[0075] The first input of the first selector MUX1 is the output signal P1 of the pulse generation circuit A, the second input is the output signal P2 of the calibration circuit B, the third input is the enable signal CALIBRATION, and the output signal is TOUT.

[0076] The first input of the first counter CNT1 is the output CEN of the pulse generation circuit A, and the second input is the output CLK of the frequency multiplication delay phase-locked loop MDLL; the output of the first counter CNT1 is COARSE<19:0>, which serves as the coarse quantization result;

[0077] The first input of the second counter CNT2 is the output TOUT of the first selector MUX1, the second input is the output CLK of the frequency multiplication delay phase-locked loop MDLL, and the third input is the output DONE of the pulse widening circuit F; the output of the second counter CNT2 is FINE<7:0>, which is part of the fine quantization result;

[0078] The first input of the third counter CNT3 is the output CEN of the pulse generation circuit A, and the second input is the external reference clock CLKREF. The output of the third counter CNT3 is OUTM, which is used to eliminate the influence of the static phase error of the frequency doubling delay phase-locked loop MDLL.

[0079] Figure 2 This is a timing diagram for a rising edge of an INPUT input using a TDC quantization. In this TDC, the frequency-multiplied delay phase-locked loop (MDLL) multiplies the input reference clock CLKREF, generating a higher frequency clock CLK for input to other circuits, and simultaneously outputting a multi-phase clock CLK0-CLK. 11 For fine quantization. Quantization at the rising edge of the input signal INPUT is mainly accomplished by the first counter CNT1, the second counter CNT2, the third counter CNT3, and the encoder E. First, coarse quantization is performed using the output CLK of the frequency multiplication delay phase-locked loop (MDLL). When the first rising edge of INPUT arrives, the output CEN of pulse generation circuit A generates a rising edge, the first counter CNT1 is enabled, and CLK starts driving CNT1. At this time, the value of CNT1 is 0. Afterwards, each time the rising edge of INPUT arrives, the output CEN of pulse generation circuit A generates a rising edge. At this time, the value of the first counter CNT1, COARSE<19:0>, is recorded. Then, the time interval between the rising edge of INPUT and the next rising edge of CLK is used as the margin P1, and fine quantization is performed on the margin. One complete clock cycle T... CLK Subtracting the margin gives the time interval between the rising edge of INPUT and the previous rising edge of the clock. This margin P1 is generated by the pulse generation circuit A. An additional clock cycle offset is added to the margin P1 and then input to the pulse widening circuit F to extend this time interval proportionally. At the same time, the second counter CNT2 is enabled. When the extension ends, the output signal DONE of the pulse widening circuit F is converted to a high level. At this time, the second counter CNT2 and the encoder E are recorded to obtain FINE<7:0> and the phase PHASE<3:0> of the frequency multiplication delay phase-locked loop MDLL.

[0080] In the above process, adding an extra clock cycle offset to the margin is to ensure that the pulse widening circuit still meets the minimum setup time requirement when the input margin is very small, so that the actual input range of the pulse widening circuit is kept within 1 to 2 clock cycles.

[0081] In the embodiments of the present invention, the specific circuit structure principles of the calibration signal generation circuit, pulse generation circuit A, and pulse widening circuit F of the calibration circuit B are further given, and the three are described in detail below.

[0082] like Figure 3 As shown, the calibration signal generation circuit of calibration circuit B includes a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a second selector MUX2, a first AND gate AND1, and an inverter INV. Wherein:

[0083] The D terminal of the first D flip-flop DFF1 is connected to the first D flip-flop DFF1. The clock input terminal is connected to CLK, the reset terminal is connected to the reset signal RN, and the Q terminal is connected to the second input of the second selector MUX2.

[0084] The first input of the second selector MUX2 is connected to CLK, and the third input is connected to the selection signal SEL.

[0085] The D terminal of the second D flip-flop DFF2 is connected to the second D flip-flop DFF2. The clock input terminal is connected to the output of the second selector MUX2, the reset terminal is connected to the reset signal RN, and the Q terminal is connected to the input of the inverter INV and the second input of the first AND gate AND1.

[0086] The D terminal of the third D flip-flop, DFF3, is connected to the power supply voltage VDD. The clock input terminal is connected to the output of the inverter INV. The reset terminal is connected to the reset signal RN. The Q terminal is left floating. The terminal is connected to the first input of the first AND gate AND1;

[0087] The output of the first AND gate, AND1, is P2.

[0088] like Figure 4 As shown, the pulse generation circuit A includes a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, and a second AND gate AND2;

[0089] The D terminal of the fourth D flip-flop, DFF4, is connected to the power supply voltage VDD, the clock input is connected to CLK, the reset terminal is connected to INPUT, and the Q terminal is connected to the D terminal of the fifth D flip-flop, DFF5. End suspended in the air;

[0090] The clock input of the fifth D flip-flop, DFF5, is connected to CLK, the reset input is connected to the reset signal RST, and the Q input is left floating. The terminal is connected to the first input of the second AND gate AND2;

[0091] The second input of the second AND gate AND2 is INPUT, and the output is P1.

[0092] like Figure 5 As shown, the pulse widening circuit F includes a first capacitor C1, a second capacitor C2, a first current source I1, a second current source I2, and a first MOSFET M. N1 Second MOSFET M N2 The third MOSFET M P3 Fourth MOSFET M P4 The logic circuit LOGIC and the comparator COMP; the capacitance of the second capacitor C2 is greater than that of the first capacitor C1;

[0093] One end of the first capacitor C1 is grounded, and the other end is connected to the first MOSFET M. N1 The drain of the third MOSFET M P3 The drain of the comparator and the positive input of the comparator COMP;

[0094] One end of the second capacitor C2 is grounded, and the other end is connected to the second MOSFET M. N2 The drain of the fourth MOSFET M P4 The drain of the comparator and the negative input of the comparator COMP;

[0095] First MOSFET M N1 The gate is connected to the first output T1 of the logic circuit, and the source is connected to the current input terminal of the first current source I1.

[0096] Second MOSFET M N2 The gate of the logic circuit is connected to the second output T2, and the source is connected to the current input terminal of the second current source I2.

[0097] The current output terminals of the first current source I1 and the second current source I2 are ground;

[0098] Third MOSFET M P3 and the fourth MOSFET M P4 The sources of all three are connected to the power supply VDD, and the gates are all connected to the reset signal RESET.

[0099] The input of the logic circuit LOGIC is the output TOUT of the first selector MUX1;

[0100] The output of comparator COMP is DONE.

[0101] The TDC designed in the above embodiment quantizes the input times of the start and end signals separately, and then uses the difference in quantization results as the time interval. This ensures that the start and end signals travel the same path, avoiding the influence of the circuit's own propagation delay on the result. The circuit principle and result quantization process are described in detail below.

[0102] This invention employs a step-by-step quantization approach combining coarse and fine quantization, which effectively increases the range of the TDC while maintaining high resolution. Assume the input reference clock period is T. REF If the frequency multiplication ratio of MDLL is M, and the number of bits of the first counter CNT1 is N, then the range DR of TDC is:

[0103]

[0104] A pulse broadening circuit broadens the input pulse by a certain ratio, similar to amplifying the margin of coarse quantization, thereby improving resolution. Assuming the broadening ratio is K and the MDLL has P phases, the resolution r of the TDC is:

[0105]

[0106] Assume the result of the first counter CNT1 recorded, COARSE<19:0>, is D. C The result of the second counter CNT2, FINE<7:0>, is D. F MDLL phase PHASE<3:0> is D P Then the quantization result Q at the rising edge of INPUT is:

[0107]

[0108] The specific quantization result of the rising edge of the input signal INPUT can be calculated using the above formula (3).

[0109] Of course, this invention also provides an improved algorithm for overcoming MDLL static phase error, which can reduce the impact of MDLL static phase error on quantization results after determining clock deterministic jitter. This will be described in detail below.

[0110] When the CALIBRATION signal is high, the circuit enters calibration mode. In calibration mode, the main functions of each module of the TDC are the same as in normal operation, making TDC calibration convenient and requiring no additional external signals.

[0111] Calibration circuit B is used to generate calibration signals. In addition to the calibration signal generation circuit, calibration circuit B also needs to include logic circuits for generating selection signal SEL and reset signal RN.

[0112] Figure 3 This is the schematic diagram of the calibration signal generation circuit in calibration circuit B. During operation, the calibration signal generation circuit divides CLK by two or four according to the selection signal SEL. The inverter INV on the right, the third D flip-flop DFF3, and the first AND gate AND1 convert the divided clock into a one-time pulse. Combined with the input reset signal RN, it continuously outputs pulses with a width of one clock cycle and two clock cycles. Therefore, the calibration circuit continuously generates two pulses with a pulse width difference of one clock cycle T. CLK The quantization result D of these two pulses in calibration mode. F1 D P1 D F2 D P2 The difference represents the pulse broadening ratio K of the pulse broadening circuit.

[0113]

[0114] In calibration circuit B, in addition to the calibration signal generation circuit, other logic circuits are needed to generate the selection signal SEL and the reset signal RN. The generation logic is as follows:

[0115] 1. When CALIBRATION is low, RN is low;

[0116] 2. When CALIBRATION changes from low to high, RN changes from low to high.

[0117] 3. When CALIBRATION is high, the following process is continuously executed in a loop:

[0118] First, P2 outputs a pulse;

[0119] Then, after P2 outputs a pulse, RN goes low, and SEL performs a level switch;

[0120] Then, after the pulse widening circuit F outputs the signal DONE from high level to low level, RN goes high.

[0121] As long as CALIBRATION remains high, the circuit state will continuously cycle through step 3 above.

[0122] Figure 5 This is the schematic diagram of the pulse widening circuit F. Figure 6 This is a schematic diagram of the capacitor voltages in the pulse widening circuit F, showing the voltage changes across capacitors C1 and C2 when the circuit F is operating. Since the capacitance of the second capacitor C2 is greater than that of the first capacitor C1, C2 is a large capacitor, and C1 is a small capacitor. After the input pulse signal TOUT, the logic circuit LOGIC first outputs a pulse signal T1 with the same width as TOUT. At this time, the first MOSFET M... N1 When the circuit is turned on, the first current source I1 discharges the first capacitor C1, causing its voltage to drop rapidly. After pulse signal T1, the output signal T2 of the logic circuit LOGIC remains high. At this time, the second current source I2 discharges the second capacitor C2, causing its voltage to drop slowly. When the voltages of the first capacitor C1 and the second capacitor C2 are equal, the comparator COMP output signal DONE switches to high. After waiting for a period of time, the voltages of the first capacitor C1 and the second capacitor C2 are reset. Assume I1 / I2 = A, C1 / C2 = 1 / B, T... IN The pulse width is ΔT IN The total propagation delay of the digital logic circuit LOGIC and the comparator COMP is T. d Then T IN The time interval ΔT between the rising edge and the rising edge of COMP is:

[0123] ΔT=(AB+1)·ΔT IN +T d #(5)

[0124] Propagation delay T d Although it affects the magnitude of ΔT, it has different effects on different T values. IN The difference between ΔT and ΔT IN The difference is directly proportional, T d The effect is negligible. Since the time interval is the difference between two quantization results, T... d It has almost no impact on TDC's measurement of time intervals.

[0125] By using the output signal OUTM, the improved algorithm proposed in this invention can overcome the influence of the static phase error of MDLL. Specifically, the improved algorithm is as follows:

[0126] The static phase error of the MDLL will cause the CLK output of the MDLL to have two periods. Assume T REF Given an input reference clock period, a frequency-doubled delay phase-locked loop (MDLL) outputs M cycles, where one of these cycles has a width of T. M The width of the remaining M-1 periods is T. M-1 :

[0127]

[0128] For example, in this embodiment of the invention, the multiplication ratio M of the MDLL is 32. Therefore, within each reference clock cycle, the MDLL will output 32 CLK cycles. Of these, 31 CLK cycles are T. 31 There is one CLK with a period of T. 32 ,T 31 and T 32 The relationship can be represented as:

[0129]

[0130] After measuring T M-1 Subsequently, the algorithm proposed in this invention can be used to overcome the influence of MDLL static phase error. The INPUT signal enables the first counter CNT1 and simultaneously enables a 1-bit third counter CNT3, which is driven by a reference clock. When the rising edge of the subsequent INPUT signal arrives, TDC records the output COARSE<19:0> of CNT1 and the output OUTM of CNT3. When determining T… M-1 When the value is , equation (3) can be improved, and the quantization result Q of the rising edge of the input signal INPUT is:

[0131]

[0132] Where: The coefficients a and b need to satisfy the following three conditions: a mod 2 = OUTM, M*a + b = D C , -M < b < M, and both coefficients are integers; T REF is the input reference clock period, D C is the result COARSE<19:0> of the first counter CNT1, D F is the result FINE<7:0> of the second counter CNT2, D P is the phase PHASE<3:0> of the multiplication frequency delay locked loop MDLL, M is the multiplication frequency ratio of the multiplication frequency delay locked loop MDLL, N is the number of bits of the first counter CNT1, and P is the number of phases of the multiplication frequency delay locked loop MDLL.

[0133] Thus, it can be seen that the above improved algorithm of the present invention converts the calculation of coarse quantization from a simple D C *T CLK to finding the number of Ts in the entire time interval, so that only by adding a 1-bit counter without adding additional circuit costs, the influence of the static phase error of the MDLL can be overcome. During the fine quantization process, T M-1 needs to be divided by the broadening ratio, and the influence of the static phase error is relatively small, so it can be not processed. M CLK

[0134] The above-described embodiments are only a preferred solution of the present invention, but they are not intended to limit the present invention. Those of ordinary skill in the relevant art can still make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all technical solutions obtained by means of equivalent replacement or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A time-to-digital converter based on pulse broadening, characterized in that, It includes a frequency multiplication delay phase-locked loop (MDLL), a pulse generation circuit (A), a calibration circuit (B), a delay circuit (D), an encoder (E), a pulse widening circuit (F), a first selector (MUX1), a first counter (CNT1), a second counter (CNT2), and a third counter (CNT3). The input to the frequency multiplication delay phase-locked loop (MDLL) is an external reference clock CLKREF, the first output is the high-frequency clock CLK, and the second output is the multiphase clock CLK0-CLK. 11 ; The pulse generation circuit (A) has the following inputs: the first input is the output CLK of the frequency multiplication delay phase-locked loop (MDLL), the second input is the signal to be quantized INPUT, the first output signal is P1, and the second output is CEN. The first input of the calibration circuit (B) is the output CLK of the frequency doubling delay phase-locked loop (MDLL), the second input is the enable signal CALIBRATION, the third input is the output DONE of the pulse widening circuit (F), and the output signal is P2. The first input of the delay circuit (D) is the output CLK of the frequency multiplication delay phase-locked loop (MDLL), the second input is the output DONE of the pulse widening circuit (F), and the output signal is RESET; The first input of the encoder (E) is the output CLK0-CLK of the frequency multiplication delay phase-locked loop (MDLL). 11 The second input is the output DONE of the pulse stretching circuit (F); the output of the encoder (E) is PHASE<3:0>, which is part of the fine quantization result. The first input of the pulse widening circuit (F) is the output TOUT of the first selector (MUX1), the second input is the output RESET of the delay circuit, and the output signal is DONE; The first input of the first selector (MUX1) is the output signal P1 of the pulse generation circuit (A), the second input is the output signal P2 of the calibration circuit (B), the third input is the enable signal CALIBRATION, and the output signal is TOUT. The first input of the first counter (CNT1) is the output CEN of the pulse generation circuit (A), and the second input is the output CLK of the frequency multiplication delay phase-locked loop (MDLL); the output of the first counter (CNT1) is COARSE<19:0>, which serves as the coarse quantization result; The first input of the second counter (CNT2) is the output TOUT of the first selector (MUX1), the second input is the output CLK of the frequency multiplication delay phase-locked loop (MDLL), and the third input is the output DONE of the pulse widening circuit (F); the output of the second counter (CNT2) is FINE<7:0>, which is part of the fine quantization result; The first input of the third counter (CNT3) is the output CEN of the pulse generation circuit (A), and the second input is the external reference clock CLKREF; the output of the third counter (CNT3) is OUTM, which is used to eliminate the effect of static phase error of the frequency doubling delay phase-locked loop (MDLL); In the pulse-wide extension time-to-digital converter, the frequency-multiplied delay phase-locked loop (MDLL) multiplies the input reference clock CLKREF. This generates a high-frequency clock CLK for input to other circuits and outputs a multi-phase clock CLK0-CLK. 11 For fine quantization; quantization at the rising edge of the input signal INPUT is performed by the first counter (CNT1), the second counter (CNT2), the third counter (CNT3), and the encoder (E). First, coarse quantization is performed using the output CLK of the frequency multiplication delay phase-locked loop (MDLL). When the first rising edge of INPUT arrives, the output CEN of the pulse generation circuit (A) generates a rising edge, the first counter (CNT1) is enabled, and CLK begins to drive CNT1, at which point the value of CNT1 is 0. Afterwards, each time the rising edge of INPUT arrives, the output CEN of the pulse generation circuit (A) generates a rising edge, and the value of the first counter (CNT1) COARSE<19:0> is recorded. Then, the time interval between the rising edge of INPUT and the next rising edge of CLK is used as the margin P1, and fine quantization is performed on the margin. A complete clock cycle T... CLK Subtracting the margin gives the time interval between the rising edge of INPUT and the previous rising edge of the clock. This margin P1 is generated by the pulse generation circuit (A). An additional clock cycle offset is added to the margin P1 and then input to the pulse widening circuit (F) to extend this time interval proportionally. At the same time, the second counter (CNT2) is enabled. When the extension ends, the output signal DONE of the pulse widening circuit (F) is converted to a high level. At this time, the second counter (CNT2) and the encoder (E) are recorded to obtain FINE<7:0> and the phase PHASE<3:0> of the frequency multiplication delay phase-locked loop (MDLL). The quantization result of the rising edge of the input signal INPUT is: Where: The coefficients a and b need to satisfy the following three conditions: a mod 2 = OUTM, M*a + b = D C , -M < b < M, and both coefficients are integers; T REF For the input reference clock period, D C For the result of the first counter (CNT1), COARSE<19:0>, D F For the result of the second counter (CNT2), FINE<7:0>, D P Here, PHASE<3:0> represents the phase of the frequency-doubling delay phase-locked loop (MDLL), M is the frequency multiplication ratio of the MDLL, P is the number of phases in the MDLL, and K is the pulse broadening ratio of the pulse broadening circuit. Of the M cycles output by the MDLL, one cycle has a width of... The width of the remaining M-1 periods is .

2. The time-to-digital converter based on pulse broadening as described in claim 1, characterized in that, The calibration signal generation circuit in the calibration circuit (B) includes a first D flip-flop (DFF1), a second D flip-flop (DFF2), a third D flip-flop (DFF3), a second selector (MUX2), a first AND gate (AND1), and an inverter (INV). The D terminal of the first D flip-flop (DFF1) is connected to the first D flip-flop (DFF1). The clock input terminal is connected to CLK, the reset terminal is connected to the reset signal RN, and the Q terminal is connected to the second input of the second selector (MUX2). The first input of the second selector (MUX2) is connected to CLK, and the third input is connected to the selection signal SEL; The D terminal of the second D flip-flop (DFF2) is connected to the second D flip-flop (DFF2). The clock input terminal is connected to the output of the second selector (MUX2), the reset terminal is connected to the reset signal RN, and the Q terminal is connected to the input of the inverter (INV) and the second input of the first AND gate (AND1). The D terminal of the third D flip-flop (DFF3) is connected to the power supply voltage VDD, the clock input terminal is connected to the output of the inverter (INV), the reset terminal is connected to the reset signal RN, and the Q terminal is left floating. The terminal is connected to the first input of the first AND gate (AND1); The output of the first AND gate (AND1) is P2.

3. The time-to-digital converter based on pulse broadening as described in claim 2, characterized in that, During the operation of the calibration signal generation circuit, CLK is divided by two or four according to the selection signal SEL. The inverter (INV), the third D flip-flop (DFF3), and the first AND gate (AND1) on the right side can convert the divided clock into a one-time pulse. With the input reset signal RN, pulses with a width of one clock cycle and two clock cycles are continuously output in sequence.

4. The time-to-digital converter based on pulse broadening as described in claim 3, characterized in that, The calibration circuit (B) includes, in addition to the calibration signal generation circuit, a logic circuit for generating a selection signal SEL and a reset signal RN. The generation logic is as follows:

1. When CALIBRATION is low, RN is low; 2. When CALIBRATION changes from low to high, RN changes from low to high.

3. When CALIBRATION is high, the following process is continuously executed in a loop: First, P2 outputs a pulse; Then, after P2 outputs a pulse, RN goes low, and SEL performs a level switch; Then, after the output signal DONE of the pulse widening circuit (F) changes from high to low, RN changes to high.

5. The time-to-digital converter based on pulse broadening as described in claim 1, characterized in that, The pulse generation circuit (A) includes a fourth D flip-flop (DFF4), a fifth D flip-flop (DFF5), and a second AND gate (AND2). The D terminal of the fourth D flip-flop (DFF4) is connected to the power supply voltage VDD, the clock input is connected to CLK, the reset terminal is connected to INPUT, and the Q terminal is connected to the D terminal of the fifth D flip-flop (DFF5). End suspended in the air; The clock input of the fifth D flip-flop (DFF5) is connected to CLK, the reset input is connected to the reset signal RST, and the Q input is left floating. The terminal is connected to the first input of the second AND gate (AND2); The second input of the second AND gate (AND2) is INPUT, and the output is P1.

6. The time-to-digital converter based on pulse broadening as described in claim 1, characterized in that, The pulse broadening circuit (F) includes a first capacitor (C1), a second capacitor (C2), a first current source (I1), a second current source (I2), and a first MOSFET (M). N1 ), second MOS transistor (M) N2 ), third MOS transistor (M) P3 ), fourth MOSFET (M P4 ), logic circuit (LOGIC) and comparator (COMP); the capacitance of the second capacitor (C2) is greater than that of the first capacitor (C1); One end of the first capacitor (C1) is grounded, and the other end is connected to the first MOSFET (M). N1 The drain of the third MOSFET (M) P3 The drain of the comparator and the positive input of the comparator (COMP); One end of the second capacitor (C2) is grounded, and the other end is connected to the second MOSFET (M). N2 The drain of the fourth MOSFET (M) P4 The drain of the comparator and the negative input of the comparator (COMP); First MOSFET (M) N1 The gate of the logic circuit is connected to the first output T1, and the source is connected to the current input terminal of the first current source (I1). Second MOSFET (M) N2 The gate of the logic circuit is connected to the second output T2, and the source is connected to the current input terminal of the second current source (I2). The current output terminals of the first current source (I1) and the second current source (I2) are ground; Third MOSFET (M) P3 ) and the fourth MOSFET (M P4 The sources of all three components are connected to the power supply VDD, and the gates are all connected to the reset signal RESET. The input to the logic circuit (LOGIC) is the output TOUT of the first selector (MUX1); The comparator (COMP) outputs DONE.

7. The time-to-digital converter based on pulse broadening as described in claim 3, characterized in that, During the operation of the pulse widening circuit (F), after the input pulse signal TOUT, the logic circuit (LOGIC) first outputs a pulse signal T1 with the same width as TOUT. At this time, the first MOS transistor (M) N1 When the circuit is turned on, the first current source (I1) discharges the first capacitor (C1), causing the voltage of the first capacitor (C1) to drop rapidly. After the pulse signal T1, the output signal T2 of the logic circuit (LOGIC) remains at a high level. At this time, the second current source (I2) discharges the second capacitor (C2), causing the voltage of the second capacitor (C2) to drop slowly. When the voltages of the first capacitor (C1) and the second capacitor (C2) are equal, the comparator output signal DONE switches to a high level. After waiting for a period of time, the voltages of the first capacitor (C1) and the second capacitor (C2) are reset.

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