A video wall display screen and a control system for the video wall display screen.

Abstract

This disclosure provides a video wall display and a control system for the video wall display. The video wall display includes multiple interconnected displays, multiple control modules, and a communication bus. Each control module is equipped with an image processing algorithm. Each control module is configured to receive video information and send edge signal supplementation requests to other control modules. Based on the address information carried in the edge signal supplementation requests, the control module determines whether the communication bus is occupied by itself. If occupied, the control module acts as the master control module, and the other control modules corresponding to the address information occupying the communication bus act as slave control modules. Upon gaining control of the communication bus, the control module reads at least some edge information from the slave control modules via the communication bus. The received video information and multiple at least some edge information are processed to generate sub-image information to be displayed. The displays are configured to display the received sub-image information.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a splicing display screen and a control system for the splicing display screen. Background Technology

[0002] With the rapid development of display technology, displays are becoming increasingly diversified, among which video wall displays are a relatively new technology in recent years. Typically, several small displays are spliced ​​together to form a single video wall unit, also known as a video wall display. Because of the gaps between the displays, video wall displays inevitably have areas where images cannot be displayed. Traditionally, an external splicing system pre-processes the image information from each small display before sending the processed video signal to the receiving end (the display screen) for display. This method places high demands on the splicing system equipped with image processing algorithms, requiring significant computing power to process the images on each display, thus greatly increasing the processing load on the splicing system. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a video wall display and a control system for the video wall display.

[0004] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a splicing display screen, which includes multiple spliced ​​display screens, multiple control modules, and a communication bus; one display screen corresponds to one control module; each control module is equipped with an image processing algorithm; the control modules are connected to each other through the communication bus.

[0005] The control module is configured to, in response to received video information, send an edge signal supplementation request to other control modules in the splicing display screen; the edge signal supplementation request carries address information of at least some of the other control modules besides itself; based on the address information, determine whether the communication bus is occupied by itself; if it is determined that the communication bus is occupied by itself, designate itself as the master control module and the other control modules corresponding to the address information occupying the communication bus as slave control modules; if it obtains control over the communication bus, read at least some edge information of the video information received by the slave control modules through the communication bus; release control over the communication bus to allow the other control modules to occupy the communication bus for a new round; if multiple pieces of edge information are read from each of the at least some of the other control modules, perform image processing on the received video information and the multiple pieces of edge information to generate sub-image information to be displayed;

[0006] The display screen is configured to display information based on the received sub-image information.

[0007] In some embodiments, when the communication bus is occupied by multiple main control modules at the same time, each main control module is further configured to determine whether it has control over the communication bus;

[0008] The main control module includes a judgment unit and a reading unit;

[0009] The judgment unit is configured to send a pre-configured read code to the slave control module, and determine whether it has control over the communication bus based on the read code.

[0010] The reading unit is configured to, when having control of the communication bus, send a request to the slave control module to read information, and read at least a portion of the edge information fed back by the slave control module through the communication bus; and release control of the communication bus so that the other control modules can occupy the communication bus for a new round of time.

[0011] The control module includes a receiving unit and a transmitting unit;

[0012] The receiving unit is configured to determine, in response to the received read encoding, at least a portion of the edge information of the received video information;

[0013] The sending unit is configured to send at least a portion of the edge information to the reading unit in response to a received request for the read information.

[0014] In some embodiments, the determining unit is specifically configured to sequentially send the read-encoded data bits to the communication bus, and when sending each data bit, determine whether the logic level of the currently sent data bit is consistent with the logic level of the communication bus at the current moment; if the logic level of the currently sent data bit is consistent with the logic level of the communication bus at the current moment, and the logic level of the currently sent data bit is low, then it is determined that it has control over the communication bus.

[0015] In some embodiments, the control module is specifically configured to sequentially send data bits of the address information to the communication bus; and, when the data bit sent at the current moment is at a low level and the logic level of the communication bus is adjusted to a low level, determine that the communication bus is occupied by itself.

[0016] The communication bus is configured to adjust its own logic level to low when the logic level of the data bits of the address information received from any of the control modules is low.

[0017] In some embodiments, the edge signal supplementation request carries at least one data byte, wherein the first bit of the data byte is a data bit used to characterize read control or write control;

[0018] The slave control module is configured to respond to the edge signal supplementation request, and if it determines that the first data bit received is a write control bit, detect whether the received address information is consistent with the preset address information; if the received address information is consistent with the preset address information, it sends a response signal back to the master control module.

[0019] The main control module is configured to receive the response signal from the slave control module, and upon gaining control of the communication bus, read partial edge information of the video information received by the slave control module through the communication bus; and release control of the communication bus.

[0020] In some embodiments, the control module further includes a clock unit, the initial state of which is a high level; the communication bus includes a data signal line and a clock signal line, the initial state of which is a high level.

[0021] The clock unit is configured to detect the logic level on the clock signal line; when it detects a transition from a high level to a low level on the clock signal line, it adjusts the currently high logic level to a low level, maintains the low level for a preset low level period, and then adjusts the currently low logic level to a high level; if the logic level on the clock signal line remains low, it adjusts itself to a high level waiting state; when it detects a transition from a low level to a high level on the clock signal line, it counts its own high level period; if its own high level period is less than the high level period of any other control module's clock unit, it adjusts its own currently high logic level to a low level.

[0022] The clock signal line is configured to detect the logic level of the clock unit of each control module when its own logic level transitions from high to low and remains at a low level; if the logic level of the clock unit of each control module is high, the logic level of the clock signal line is adjusted to high.

[0023] In some embodiments, the low-level period of the clock signal line is greater than the low-level period of any of the clock units.

[0024] Secondly, this disclosure also provides a control system for a video wall display, which includes the video wall display described in the above embodiments.

[0025] In some embodiments, the system further includes a playback control module and a data transmission module;

[0026] The playback control module is configured to send the video stream to the data sending module through the video interface;

[0027] The data sending module is configured to divide each video frame in the video stream into blocks according to the video stream, the video resolution of the video stream, and the number of displays, to obtain video information corresponding to each control module; and to send the video information to the corresponding control module.

[0028] The video display screen is configured to display based on the received video information.

[0029] In some embodiments, the data sending module includes a configuration unit, a segmentation unit, and a sending unit;

[0030] The configuration unit is configured to receive configuration information sent by the user terminal; the configuration information includes the address information of the control module and the number of displays.

[0031] The segmentation unit is configured to divide each video frame in the video stream into blocks according to the video stream, the video resolution of the video stream, and the number of the displays, to obtain video information corresponding to each control module.

[0032] The sending unit is configured to send the video information to the corresponding control module according to the address information of each control module. Attached Figure Description

[0033] Figure 1 A schematic diagram illustrating an exemplary edge information supplementation provided for an embodiment of this disclosure;

[0034] Figure 2 This is a schematic diagram of the structure of a splicing display screen provided in an embodiment of the present disclosure;

[0035] Figure 3 An exemplary priority sorting diagram provided for embodiments of this disclosure;

[0036] Figure 4 A schematic diagram illustrating the specific structure of the master control module and slave control module provided in the embodiments of this disclosure;

[0037] Figure 5a A schematic diagram illustrating a main control module requesting to read edge information, provided in an embodiment of this disclosure;

[0038] Figure 5b for Figure 5aA schematic diagram showing the division of the edge area of ​​display screen No. 1;

[0039] Figure 6 A schematic diagram of an exemplary I2C bus communication signal waveform provided for an embodiment of this disclosure;

[0040] Figure 7 A schematic diagram of an exemplary signal waveform for synchronizing multiple control modules with a communication bus clock, provided for an embodiment of this disclosure;

[0041] Figure 8 This is a schematic diagram of the structure of a splicing display screen control system provided in an embodiment of this disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0044] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0045] In related technologies, the gaps between the individual displays in a video wall result in poor image quality in the spliced ​​area. Therefore, a video wall system incorporating image processing algorithms processes the images displayed on each display and the edge pixel information of surrounding displays to achieve a smoother transition between the spliced ​​screens. However, this approach places high demands on the video wall system equipped with image processing algorithms, requiring it to provide significant computing power (e.g., the unified calculation of the images displayed on each display and the edge pixel information of surrounding displays) to perform image processing on each screen, thus greatly increasing the processing load on the video wall system.

[0046] Based on this, embodiments of this disclosure provide a splicing display screen, which includes multiple spliced ​​display screens and multiple control modules; one display screen corresponds to one control module. The splicing display screen provided by embodiments of this disclosure deploys image processing algorithms within the control modules corresponding to the display screens, thus distributing the burden of image processing algorithms that would otherwise be uniformly processed in traditional technologies. For each control module, it only needs to process the image to be displayed, significantly reducing the computational power of its internal image processing algorithms.

[0047] It should be noted that if the image is simply distributed among the image processing algorithms of each control module, problems such as incomplete pixels at image boundaries and poor display quality due to gaps between spliced ​​displays will occur. Specifically, for example... Figure 1As shown, this is a schematic diagram of an exemplary edge information supplementation provided by an embodiment of this disclosure. The black dashed box represents a 5×5 filter kernel, and the gray dashed box represents a 5×5 filter kernel after a step size. For example, an image processing algorithm uses a 5×5 filter kernel with a step size of 1 to process pixels on the display screen. When processing edge pixels on the display screen, it is inevitable to need edge pixels displayed on other displays. Therefore, to further improve the display effect of the spliced ​​display screen and make the transition between spliced ​​displays smoother, the spliced ​​display screen provided by this disclosure also includes a communication bus, through which control modules communicate. The communication bus provided by this disclosure can be any bus that supports multi-master communication and has an arbitration mechanism, such as the I2C bus. Here, "master" refers to the control module. This disclosure uses the I2C bus as an example. All control modules are connected to a single communication bus. To avoid conflict caused by multiple control modules simultaneously requesting edge information through the communication bus, this disclosure also sets up an "arbitration" mechanism between the control module and the communication bus. See the two arbitration processes described below for details, which will not be elaborated here. The control module utilizes the data transmission function of the communication bus and the logical functions provided by the "arbitration" mechanism to obtain information about the edge pixels of other control modules without conflict, so as to optimize the image it displays and improve the consistency of the display effect of the splicing display screen.

[0048] The following is a detailed explanation of the various structures of the video wall display. Figure 2 This is a schematic diagram of the structure of a splicing display screen provided in an embodiment of the present disclosure, as shown below. Figure 2 As shown, it illustrates a 4×4 display screen, where each row of display screens is connected in series, forming a total of four groups. The connection lines without arrows represent the communication bus. The serpentine wiring method can achieve communication connections between control modules, reduce wiring complexity, and avoid messy wiring between control modules.

[0049] The control module is configured to send an edge signal supplementation request to other control modules in the splicing display in response to received video information. Here, the edge signal supplementation request carries address information of at least some of the other control modules besides itself. The difference between this control module and other control modules is that the other control modules are those other than the control module itself among multiple control modules. The address information of at least some of the other control modules can be the pre-set address information of specific control modules related to this control module, such as the address information of control modules adjacent to this control module. Here, "address information" can be understood as an identifier that can characterize other control modules, such as a pre-configured identity document (ID) for the control module, which can be represented by "1" for high level and "0" for low level in logic. Here, the video information can be information sent to the control module after segmentation of video frames from an external playback source; specifically, it can be a video signal containing partial video frames. The partial video frames can be understood as the sub-image to be displayed on the display screen corresponding to the control module.

[0050] Furthermore, the control module is configured to determine whether it is occupying the communication bus based on the address information. This is the first arbitration. If it is determined that the communication bus is occupied, it becomes the master control module, and other control modules corresponding to the address information occupying the communication bus become slave control modules. Here, before determining whether the communication bus is occupied, the same control module can actively send edge signal supplementation requests and passively receive the address information carried in edge signal supplementation requests sent by other control modules. After determining whether the communication bus is occupied, if it is determined that the communication bus is occupied by itself, it defines itself as the master control module. This master control module can use the communication bus to transmit data, while other non-master control modules cannot use the communication bus to transmit data. It should be noted that each control module in the multiple control modules can simultaneously send edge signal supplementation requests and determine whether the communication bus is occupied by itself based on the address information. Therefore, there is at least one master control module occupying the communication bus among the multiple control modules.

[0051] For example, the communication bus has a "wired-AND" logic function, which means that in logic levels, low level 0 and low level 0 together equals low level 0, low level 0 and high level 1 together equals low level 0, and high level 1 and high level 1 together equals high level 1. That is, as long as one control module sends a low level, the communication bus will behave as a low level. Figure 3 This is an exemplary priority sorting diagram provided in an embodiment of the present disclosure. Assume a tiled display screen comprises 3×2 interconnected display screens, such as... Figure 3As shown, the address information of display screen 1 (i.e., the address information of the control module corresponding to display screen 1) is pre-configured as 0000000, the address information of display screen 2 is 0000001, the address information of display screen 3 is 0000011, the address information of display screen 4 is 0000111, the address information of display screen 5 is 0001111, and the address information of display screen 6 is 0011111. Among them, the control module of display screen 1 has the highest priority, and the priority decreases in a serpentine arrangement. Here, "control module priority" can be understood as the communication bus being able to switch from a high level to a low level first when the address information of the control module is received by the communication bus, compared with other control modules, that is, the communication bus is in an occupied state at this time. The control module of display screen 1 is the slave control module first. The control module that sends the address information 0000000 is the master control module first.

[0052] like Figure 3As shown, taking the control module corresponding to display screen 1 as an example, the edge signal supplementation request issued by the control module corresponding to display screen 1 carries the address information of display screen 2 (0000001), display screen 4 (0000111), and display screen 5 (0001111). Similarly, taking the control module corresponding to display screen 2 as an example, the edge signal supplementation request issued by the control module corresponding to display screen 2 carries the address information of display screen 1 (0000000), display screen 3 (0000011), display screen 4 (0000111), display screen 5 (0001111), and display screen 6 (0011111). And taking the control module corresponding to display screen 3 as an example, the edge signal supplementation request issued by the control module corresponding to display screen 3 carries the address information of display screen 2 (0000001), display screen 5 (0001111), and display screen 6 (0011111). Taking the control module corresponding to display screen 4 as an example, the edge signal supplementation request sent by the control module corresponding to display screen 4 carries the address information of display screen 1 (0000000), display screen 2 (0000001), and display screen 5 (0001111). Similarly, taking the control module corresponding to display screen 5 as an example, the edge signal supplementation request sent by the control module corresponding to display screen 5 carries the address information of display screen 1 (0000000), display screen 2 (0000001), display screen 3 (0000011), display screen 4 (0000111), and display screen 6 (0011111). According to the wired-AND logic of the communication bus, address information 0000000 has the highest priority. This means that the communication bus is preferentially occupied by the control module that sent the address information 0000000. For example, the control module corresponding to display screen 2 determines that the communication bus is occupied based on its address information 0000000; the control module corresponding to display screen 4 determines that the communication bus is occupied based on its address information 0000000; and the control module corresponding to display screen 5 determines that the communication bus is occupied based on its address information 0000000. Therefore, the control modules corresponding to display screens 2, 4, and 5 are designated as master control modules, and the control module of display screen 1 (which occupies the communication bus with address information 0000000) is designated as a slave control module.

[0053] If a control module determines that the communication bus is occupied by itself, it will designate itself as the main control module. Therefore, the execution processes of the following control modules are all performed based on the premise that this control module has been defined as the main control module. Furthermore, the main control module is configured to, upon acquiring control of the communication bus, read at least a portion of the edge information of the video information received from the control module through the communication bus; and release control of the communication bus to allow other control modules to occupy the communication bus for a new round of use.

[0054] Among multiple control modules, there is at least one master control module. If there is only one master control module, it directly gains control of the communication bus. If there are multiple master control modules, they must contend for control of the communication bus (this is a second arbitration process). Ultimately, only one master control module gains control of the communication bus. The master control module that gains control is then configured to read at least a portion of the edge information of the video information received from the control modules via the communication bus, and releases control of the communication bus after reading is complete. At this point, other master control modules can again vie for control of the communication bus, and / or, other control modules can again determine whether the communication bus is occupied by themselves based on the address information.

[0055] Continuing the previous example, the main control modules corresponding to displays 2, 4, and 5 compete for control of the communication bus. Taking the case where the main control module corresponding to display 2 wins control of the communication bus first, the control module corresponding to display 2 can then read at least part of the edge information of the video information received by the control module corresponding to display 1 through the communication bus. Here, "at least part of the edge information" refers to... Figure 3 The edge information A is shown in the diagram. After the control module corresponding to display screen 2 finishes reading, it releases its control over the communication bus. Then, the other main control modules, namely the control modules corresponding to display screens 4 and 5, can continue to compete for control of the communication bus. After the control modules corresponding to display screens 4 and 5 have both released control of the communication bus, the other control modules besides those corresponding to display screens 2, 4, and 5 can continue to determine whether the communication bus is occupied by themselves based on the sent address information, that is, repeat the process of defining main and slave control modules as described above.

[0056] Furthermore, the control module is configured to perform image processing on the received video information and the multiple edge information when it reads multiple edge information from each of the at least some of the other control modules, thereby generating sub-image information to be displayed. The display screen is configured to display the received sub-image information. Here, "at least some of the other control modules" is the same as "at least some of the other control modules" in the "address information of at least some of the other control modules other than itself carried in the edge signal supplement request sent by the control module. Since the main control module can only read the at least some edge information corresponding to one slave control module once it occupies the communication bus, for a control module, when there are multiple "at least some of the other control modules" corresponding to it, it needs to occupy the communication bus multiple times to read the at least some edge information of the video information received by each of the other control modules, thereby obtaining the edge information of the video information received by the control module composed of multiple at least some edge information, for subsequent image processing. Specifically, as Figure 1 As shown, the control module calls the image processing algorithm and uses a 5×5 filter kernel with a step size of 1 to process the received video information and multiple edge information, which can optimize the image it displays, so that the spliced ​​displays show a smoother transition and improve the consistency of the display effect of the spliced ​​displays.

[0057] The splicing display screen provided in this disclosure deploys the image processing algorithm within the corresponding control module of the display screen. Compared to traditional splicing systems that deploy the image processing algorithm outside the splicing display screen and possess superior image processing capabilities, the control module in this disclosure can distribute the image processing load of the image processing algorithm. Specifically, each control module only needs to process the image it needs to display, thus significantly reducing the computational power of the image processing algorithm within the control module. Furthermore, the communication bus provided in this disclosure enables communication between the control modules. Utilizing the data transmission function and the logical functions provided by the "arbitration" mechanism of the communication bus, the main control module can read the edge information from the control modules without conflict. After each control module completes the edge information of the video information it receives, a highly consistent display effect can be achieved during splicing. Furthermore, in traditional technologies, image processing algorithms are deployed on a splicing system external to the video wall display. Therefore, the splicing method of each display in the video wall display will affect the image processing algorithm's processing of the images displayed on each display. For example, changing the splicing method requires adjusting the image engine of the splicing system. However, in this embodiment, because the image processing algorithm is deployed within the control module corresponding to each display, the splicing method between multiple interconnected displays is unlimited, greatly expanding the splicing flexibility between interconnected displays and enabling arbitrary splicing of displays.

[0058] The first arbitration process is described in detail below. In some embodiments, the control module is specifically configured to sequentially send data bits of the address information to the communication bus; and, when the data bit sent at the current moment is low and the logic level of the communication bus is adjusted to low, it determines that the communication bus is occupied by itself. The communication bus is configured to adjust its own logic level to low when the logic level of any data bit of the address information sent by the control module is low. The logic level of the communication bus is initially high.

[0059] Here, the address information data bits can include multiple data bits, and the number of data bits is related to the number of control modules in the splicing display screen. Since this embodiment of the disclosure does not limit the number of displays spliced ​​together in the splicing display screen, this embodiment of the disclosure also does not limit the number of address information data bits. For example, if the splicing display screen is composed of 4×4 spliced ​​displays, the address information can be set to 15 data bits, where the address information of display screen 1 is 000000000000000; the address information of display screen 2 is 000000000000001; ...; the address information of display screen 16 is 111111111111111.

[0060] This embodiment of the disclosure uses a seven-bit address information data bit as an example for illustration. Continuing the above example, the address information of display screen 1 is 7 bits of 0000000; the address information of display screen 2 is 7 bits of 0000001; the address information of display screen 3 is 7 bits of 0000011; the address information of display screen 4 is 7 bits of 0000111; the address information of display screen 5 is 7 bits of 0001111; and the address information of display screen 6 is 7 bits of 0011111.

[0061] Continuing the previous example, the control module sends address information to the communication bus sequentially according to the order of the 7-bit data bits. The control module corresponding to display screen 1 simultaneously sends the first bit of 0000001, 0000111, and 0001111, which are "1", "1", and "1" respectively. The control module corresponding to display screen 2 simultaneously sends the first bit of 0000000, 0000011, 0000111, 0001111, and 0011111, which are "0", "1", "1", "1", and "1" respectively. The control module corresponding to display screen 3 simultaneously sends 0000001, 0001111, and 0011111, which are "1", "1", and "1" respectively. The control module corresponding to display screen 4 simultaneously sends the first bit of 0000000, 0000001, and 0001111, which are "0", "1", and "1" respectively. The control module corresponding to display screen #5 simultaneously sends the first bit of 0000000, 0000001, 0000011, 0000111, and 0011111, which are "0", "1", "1", "1", and "1" respectively. The control module corresponding to display screen #6 simultaneously sends the first bit of 0000001, 0000011, and 0001111, which are "1", "1", and "1" respectively. Because the communication bus has a wired-AND logic function, when it receives a low level (0), it adjusts from its initial high logic level to a low level. When the control modules corresponding to displays screens #2, #4, and #5 send the first data bit of the address information corresponding to other control modules, since the first bit of address information 0000000 is low, and the communication bus also adjusts its logic level to low under the wired-AND function, it is determined that the control modules corresponding to displays screens #2, #4, and #5 occupy the communication bus.

[0062] In the first round of competition for the communication bus among the multiple control modules in the splicing display screen, the control modules corresponding to displays 2, 4, and 5 act as the master control modules, and the control module corresponding to display 1 acts as the slave control module. The control modules corresponding to display 1, 3, and 6 can wait for the next round of competition for the communication bus. Specifically, the next round of competition for the communication bus can begin after the control modules corresponding to displays 2, 4, and 5 have all denied control of the communication bus.

[0063] In this embodiment, the "wired-AND" logic function of the communication bus and the logic level of the data bits sent at the current moment and the logic level of the communication bus are detected by the control module to complete the first arbitration. The master control module and the slave control module are defined from multiple control modules, so that the master control module can read the edge information of the slave control module without conflict through the communication bus. After each control module completes the edge information of the video information it receives, the splicing display screen achieves a highly consistent display effect when splicing.

[0064] In some embodiments, the edge signal supplementation request carries at least one data byte, wherein the first bit of the data byte is a data bit used to characterize read control or write control, denoted as the read / write control bit R / W. If the logic level of this control bit is low (0), it indicates that the master control module is writing data to the slave control module; if the logic level of this control bit is high (1), it indicates that the master control module is reading data from the slave control module.

[0065] For example, the edge signal supplementation request carries a data byte, i.e., 8 bits. The data byte includes seven bits for representing the address information and a first bit for read control or write control.

[0066] The slave control module is configured to respond to the edge signal supplementation request and, when the first data bit is a write control bit, detect whether the received address information is consistent with the preset address information.

[0067] Here, the control module detects that the first data bit is a write control bit, that is, the control module detects that the logic level of the first data bit is low level 0, and then continues to respond to subsequent data bits. According to the timing of each data bit of the received address information, the control module sequentially verifies whether each data bit of the received address information is consistent with each data bit of the pre-set address information.

[0068] Furthermore, the slave control module is configured to send an ACK signal to the master control module when the received address information matches the pre-set address information. Here, the slave control module sends an ACK signal to the master control module, indicating that the master control module can read the edge information of the slave control module during subsequent execution. The pre-set address information is the address information of the slave control module itself, pre-configured by the user and stored in the slave control module. For example, as shown... Figure 6 As shown, the control module sends back the ACK signal from the 9th clock device on the communication bus.

[0069] The aforementioned control module can accurately respond to the main control module through address information verification, avoiding the main control module reading incorrect edge information in the subsequent execution process. This improves the accuracy of image processing in the main control module and thus enhances the display effect of the splicing display screen.

[0070] The main control module is configured to receive the response signal from the slave control module, and upon gaining control of the communication bus, read partial edge information of the video information received by the slave control module through the communication bus; and release control of the communication bus.

[0071] Although the main control module has received the response signal sent from the control module, since there may be multiple main control modules occupying the communication bus, a second arbitration is set up to avoid conflict between the requests of the main control modules, so as to select the main control module with the final control over the communication bus from the multiple main control modules.

[0072] The second arbitration process is described in detail below. In some embodiments, when the communication bus is occupied by multiple main control modules at the same time, each main control module is also configured to determine whether it has control over the communication bus. Figure 4 A schematic diagram of the specific structure of the master control module and slave control module provided in the embodiments of this disclosure is shown below. Figure 4 As shown. The main control module includes a judgment unit and a reading unit.

[0073] The determining unit is configured to send a pre-configured read code to the slave control module and determine whether it has control over the communication bus based on the read code. Here, the pre-configured read code can be at least one pre-configured data character stored in the main control module, capable of representing the location region of at least a portion of the edge information in the video information received by the slave control module that the main control module wants to read. It should be noted that the main control module stores multiple pre-configured read codes, and one pre-configured read code corresponds to one of the "at least some other control modules". Here, "at least some other control modules" is the same as the "at least some other control modules" mentioned in the above embodiment.

[0074] Specifically, after receiving a response signal from the slave control module, the master control module can retrieve the pre-configured read code corresponding to that slave control module based on the response signal. Continuing the previous example, such as... Figure 3As shown, the main control module is the control module corresponding to display screen 2, and the slave control module is the control module corresponding to display screen 1. After receiving the response signal from the control module corresponding to display screen 1, the control module corresponding to display screen 2 retrieves the pre-configured read code corresponding to display screen 1.

[0075] The read encoding can be, for example, an 8-bit digital signal, which can be represented by "1" for high level and "0" for low level in logic level. Figure 5a This is a schematic diagram illustrating a main control module requesting to read edge information, provided in an embodiment of this disclosure. Figure 5b for Figure 5a A schematic diagram showing the division of the edge area of ​​display screen No. 1, as shown below. Figure 5a and Figure 5b As shown. The main control module needs to read at least a portion of the edge information of the video information received from the control module. The reading encoding is configured in a loop order from left to right → top to bottom → right to left → bottom to top. The 8-bit data bits represent the pixels in the upper left, upper right, upper right, right, lower right, lower left, and left regions of the video information, respectively. A reading encoding of 1 indicates that the edge pixels in the region corresponding to the current data bit do not belong to the edge pixels that the main control module needs to read; a reading encoding of 0 indicates that the edge pixels in the region corresponding to the current data bit belong to the edge pixels that the main control module needs to read. Continuing the example above, as... Figure 3 and Figure 5a As shown, the main control module corresponds to the control modules for displays 2, 4, and 5, and the slave control module corresponds to the control module for display 1. The control module for display 2 retrieves the pre-configured read code 11100011 for display 1; the control module for display 4 retrieves the pre-configured read code 10001111 for display 1; and the control module for display 5 retrieves the pre-configured read code 11101111 for display 1.

[0076] The system determines whether it has control over the communication bus. Specifically, the determining unit is configured to sequentially send the read-encoded data bits to the communication bus, and when sending each data bit, determine whether the logic level of the currently sent data bit is consistent with the logic level of the communication bus at the current moment; if the logic level of the currently sent data bit is consistent with the logic level of the communication bus at the current moment, and the logic level of the currently sent data bit is low, then it is determined that it has control over the communication bus.

[0077] Continuing the previous example, the control modules corresponding to displays 2, 4, and 5 all send the first data bit of the read code to the communication bus. Since the first data bit is always 1, the communication bus remains at a high level. At this time, the judgment unit can determine that the logic level of the currently sent data bit is consistent with the current logic level of the communication bus. Therefore, the control modules corresponding to displays 2, 4, and 5 continue to occupy the communication bus. The judgment process for the second data bit of the read code is the same as described above, and the process will not be repeated here. Specifically, for the third data bit of the read encoding, the control module corresponding to display screen 2 sends the third data bit 0 to the communication bus, the control module corresponding to display screen 4 sends the third data bit 1 to the communication bus, and the control module corresponding to display screen 5 sends the third data bit 1 to the communication bus. Based on this, according to the "wired-AND" logic function of the communication bus, the communication bus adjusts from a high-level state to a low-level state. The judgment unit of the control module corresponding to display screen 2 determines that the logic level of the currently sent third data bit (i.e., low level 0) is consistent with the current logic level of the communication bus (i.e., the adjusted low level 0), and both are low. The judgment unit of the control module corresponding to display screen 4 determines that the logic level of the currently sent third data bit (i.e., high level 1) is inconsistent with the current logic level of the communication bus (i.e., the adjusted low level 0). The judgment unit of the control module corresponding to display screen number 5 determines that the logic level (i.e., high level 1) of the currently transmitted third data bit is inconsistent with the current logic level of the communication bus (i.e., the adjusted low level 0). Therefore, the main control module corresponding to display screen number 2 obtains final control of the communication bus.

[0078] The reading unit is configured to, when having control of the communication bus, send a request to the slave control module to read information, and read at least a portion of the edge information fed back by the slave control module through the communication bus; and release control of the communication bus to allow other control modules to occupy the communication bus for a new round. The slave control module includes a receiving unit and a sending unit. The receiving unit is configured to, in response to the received reading encoding, determine the at least a portion of the edge information of the received video information. The sending unit is configured to, in response to the received request to read information, send the at least a portion of the edge information to the reading unit.

[0079] Here, when the determining unit sequentially sends the read-encoded data bits to the communication bus, the receiving unit receives the read-encoded data transmitted from the communication bus and, based on each data bit of the read-encoded data, determines at least one location region of the video information received by the slave control module where the receiving unit is located, and further obtains the edge pixels corresponding to each location region. The sending unit is configured to respond to the received read information request. At this point, it can be determined that the main control module has gained control of the communication bus, so it sends the edge pixels corresponding to each location region as at least part of the edge information to the reading unit of the main control module through the communication bus. Afterwards, the reading unit can read at least part of the edge information fed back by the slave control module through the communication bus; after the reading unit finishes reading, the main control module controls the communication bus to allow other control modules to occupy the communication bus for a new round.

[0080] The following example illustrates the specific processing procedure of a video wall display. After receiving their respective video information, each control module sends an edge signal supplementation request to other control modules. During subsequent execution, there are two arbitration processes between the control modules and the communication bus. The first arbitration process involves selecting at least one master control module and one slave control module from among multiple control modules. The second arbitration process involves at least one master control module competing for control of the communication bus.

[0081] like Figure 3 As shown, requests from control modules 1 through 6 are responded to first by control module 1, then by control module 2, and so on in a serpentine pattern, until all requests from control modules have been responded to. Specifically, Figure 6 A schematic diagram of an exemplary I2C bus communication signal waveform provided for an embodiment of this disclosure, as shown below. Figure 6 As shown, taking the I2C bus as an example, each control module manages the I2C bus using the START signal. After sending the START signal to the communication bus, each control module immediately follows with an edge signal supplement request, addressing the slave control module according to the address information carried in the edge signal supplement request. Here, the clock signal line SCL is held high, and then the data signal line SDA changes from high to low to indicate a start signal. The clock signal line SCL is held high, and then the data line changes from low to high to indicate a stop signal.

[0082] Continuing the previous example, control modules 2, 4, and 5 win the first arbitration contest and gain control of the I2C bus. Control modules 2, 4, and 5 act as master control modules, and control module 1 acts as a slave control module. All master control modules send read codes related to control module 1. Then, master control module 2 wins the second arbitration contest, gaining final control of the I2C bus. Master control module 2 then sends a read information request to slave control module 1, which feeds back at least a portion of the edge information of the received video information determined according to the read codes to master control module 2. Master control module 2 releases the I2C bus with a stop signal (STOP). Figure 6 As shown, each digital byte is transmitted with the most significant bit (MSB) first.

[0083] In the above embodiments, the control module utilizes the logic function provided by the "arbitration" mechanism of the communication bus to ensure that only one of the multiple main control modules has control over the communication bus at any given time. This allows each main control module to read edge information from the slave control module without conflict through the communication bus, thereby improving the efficiency of information reading.

[0084] In some embodiments, the control module further includes a clock unit CLK, whose logic level starts at a high level; the communication bus includes a data signal line SDA and a clock signal line SCL, the clock signal line SCL starting at a high level. Here, the data signal line SDA of the communication bus is used to transmit data signals from the data bytes in the above embodiments. The clock signal line SCL is used to adjust its logic level in response to a clock signal. The clock unit CLK includes the clock interface of the control module. Figure 7 A schematic diagram of the signal waveforms for synchronizing multiple control modules with a communication bus clock, provided as an embodiment of this disclosure, is shown below. Figure 7 As shown.

[0085] The clock unit CLK is configured to detect the logic level on the clock signal line SCL; when it detects a transition from high to low on the clock signal line SCL, it adjusts the currently high logic level to low, maintains the low level for a preset low-level period, and then adjusts the currently low logic level to high; if the logic level of the clock signal line SCL remains low, it adjusts itself into a high-level waiting state; when it detects a transition from low to high on the clock signal line SCL, it determines its own high-level period; if its own high-level period is less than the high-level period of the clock unit CLK of any other control module, it adjusts its own currently high logic level to low. The clock signal line SCL is configured to detect the logic level of the clock units CLK of each control module when its own logic level transitions from high to low and remains low; if the logic levels of the clock units CLK of each control module are all high, it adjusts the logic level of the clock signal line SCL to high.

[0086] For example, such as Figure 7As shown, each clock unit CLK has a wired-AND logic relationship with the I2C clock signal line SCL. When a clock unit CLK detects that the logic level on the clock signal line SCL is low (0), it pulls its own logic level low and begins counting down the duration of its low-level state, i.e., a preset low-level period. Once a preset low-level period ends, it pulls its logic level high. If other clock units CLK remain low at this time, the I2C clock signal line SCL remains low due to the wired-AND logic. When a clock unit CLK detects that the clock signal line SCL is still low, it adjusts itself into a high-level waiting state. Here, the high-level waiting state lasts from the moment it remains high until the clock signal line SCL changes from low to high. When all clock units CLK have completed their low-level period count, the clock signal line SCL is released and becomes high. The logic level state of each clock unit CLK is kept consistent with the logic level state of the clock signal line SCL, both being high. The clock unit CLK constantly monitors the logic level of the clock signal line SCL. If it detects a transition from low to high in the SCL logic level, it calculates its own high-level period. The first clock unit CLK to complete its high-level period pulls its logic level low again, thus generating a synchronized I2C bus clock. In some embodiments, the low-level period of the clock signal line SCL is longer than the low-level period of any of the clock units CLK. The low-level period of the I2C clock signal line SCL is determined by the clock unit CLK with the longest low-level period, and the high-level period of the I2C clock signal line SCL is determined by the clock unit CLK with the shortest high-level period.

[0087] The above embodiments utilize the clock synchronization of the communication bus, enabling each control module to read edge information from the control module without conflict, thereby improving the efficiency of information reading.

[0088] Secondly, this disclosure also provides a control system for a video wall display, which includes the video wall display in any of the embodiments of the first aspect described above. For a detailed description of the video wall display in the control system, please refer to the detailed description of the video wall display in the above embodiments, and it will not be repeated here.

[0089] In some embodiments, Figure 8 This is a schematic diagram of the structure of a control system for a video wall display provided in an embodiment of this disclosure, as shown below. Figure 8As shown, the control system of the video wall display also includes a playback control module and a data transmission module. The playback control module is configured to send the video stream to the data transmission module via a video interface. Specifically, based on a playback plan, the video stream to be played can be determined and sent to the data transmission module via the video interface. Here, the playback plan can be a pre-configured identifier for the target video wall display, playback duration, number of loop playback cycles, etc. The video interface can be a High Definition Multimedia Interface (HDMI) or a DisplayPort (DP), etc.

[0090] The data sending module is configured to divide each video frame in the video stream into blocks according to the video stream, the video resolution of the video stream, and the number of displays, to obtain video information corresponding to each control module; and to send the video information to the corresponding control module.

[0091] Here, video resolution refers to the resolution of each frame in the video stream. One segmentation method involves a video display panel with M×N interconnected display panels. For each frame in the video stream, it is segmented into M×N video information pieces according to the video resolution. Each segmented video information piece corresponds to one control module. Each of the M×N video information pieces is associated with the address information of its corresponding control module, and the corresponding video information is sent to the control module according to the address information.

[0092] Specifically, the data transmission module includes a configuration unit, a segmentation unit, and a transmission unit. The configuration unit is configured to receive configuration information sent by the user terminal; the configuration information includes the address information of the control modules and the number of displays. The segmentation unit is configured to divide each frame of the video stream into blocks based on the video stream, the video resolution of the video stream, and the number of displays, obtaining video information corresponding to each control module. The transmission unit is configured to send the video information to the corresponding control module based on its address information.

[0093] The video wall display is configured to display based on the received video information. For details on the processing and display procedures, please refer to the detailed description of the video wall display in the first aspect; these details will not be repeated here.

[0094] The control system for the splicing display screen provided in this disclosure includes a splicing display screen. The splicing display screen deploys image processing algorithms within the control module corresponding to the display screen, so that the data sending module (such as the splicing system in the conventional technology) does not need to have super strong image processing capabilities. The control module in this disclosure can distribute the image processing pressure of the image processing algorithm. Specifically, for each control module, it only needs to process the image to be displayed, thus greatly reducing the computing power of the image processing algorithm inside the control module.

[0095] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A splicing display screen, comprising multiple spliced ​​display screens, multiple control modules, and a communication bus; one display screen corresponds to one control module; each control module is equipped with an image processing algorithm; the control modules are connected to each other via the communication bus; The control module is configured to send an edge signal supplementation request to other control modules in the splicing display screen in response to received video information; the edge signal supplementation request carries address information of at least some of the other control modules besides itself; based on the address information, it determines whether the communication bus is occupied by itself; if it is determined that the communication bus is occupied by itself, it designates itself as the master control module and the other control modules corresponding to the address information occupying the communication bus as slave control modules; When the communication bus is occupied by multiple master control modules at the same time, each master control module is configured to determine whether it has control over the communication bus. Specifically, this includes: sending a pre-configured read code to the slave control module and determining whether it has control over the communication bus based on the read code; if it has control over the communication bus, reading at least a portion of the edge information of the video information received by the slave control module through the communication bus; releasing control over the communication bus to allow the other control modules to occupy the communication bus for a new round; and if multiple portions of edge information are read from each of the other control modules, performing image processing on the received video information and the multiple portions of edge information to generate sub-image information to be displayed. The display screen is configured to display information based on the received sub-image information.

2. The splicing display screen according to claim 1, wherein, The main control module includes a judgment unit and a reading unit; The judgment unit is configured to send a pre-configured read code to the slave control module, and determine whether it has control over the communication bus based on the read code. The reading unit is configured to, when having control of the communication bus, send a request to the slave control module to read information, and read at least a portion of the edge information fed back by the slave control module through the communication bus; and release control of the communication bus so that the other control modules can occupy the communication bus for a new round of time. The control module includes a receiving unit and a transmitting unit; The receiving unit is configured to determine, in response to the received read encoding, at least a portion of the edge information of the received video information; The sending unit is configured to send at least a portion of the edge information to the reading unit in response to a received request for the read information.

3. The splicing display screen according to claim 2, wherein, The judgment unit is specifically configured to sequentially send the read-encoded data bits to the communication bus, and when sending each data bit, determine whether the logic level of the currently sent data bit is consistent with the logic level of the communication bus at the current moment; If the logic level of the currently transmitted data bit is consistent with the logic level of the communication bus at the current moment, and the logic level of the currently transmitted data bit is low, then it is determined that the user has control over the communication bus.

4. The splicing display screen according to claim 1, wherein, The control module is specifically configured to sequentially send data bits of the address information to the communication bus; and, when the data bit sent at the current moment is at a low level and the logic level of the communication bus is adjusted to a low level, determine that the communication bus is occupied by itself. The communication bus is configured to adjust its own logic level to low when the logic level of the data bits of the address information received from any of the control modules is low.

5. The splicing display screen according to claim 1, wherein, The edge signal supplementation request carries at least one data byte, wherein the first bit of the data byte is a data bit used to characterize read control or write control; The slave control module is configured to respond to the edge signal supplementation request, and if it determines that the first data bit received is a write control bit, detect whether the received address information is consistent with the preset address information; if the received address information is consistent with the preset address information, it sends a response signal back to the master control module. The main control module is configured to receive the response signal from the slave control module, and upon gaining control of the communication bus, read partial edge information of the video information received by the slave control module through the communication bus; and release control of the communication bus.

6. The splicing display screen according to claim 1, wherein, The control module also includes a clock unit, whose logic level starts at a high level; the communication bus includes a data signal line and a clock signal line, the clock signal line's logic level starts at a high level. The clock unit is configured to detect the logic level on the clock signal line; when it detects a transition from a high level to a low level on the clock signal line, it adjusts the currently high logic level to a low level, maintains the low level for a preset low level period, and then adjusts the currently low logic level to a high level; if the logic level on the clock signal line remains low, it adjusts itself to a high level waiting state; when it detects a transition from a low level to a high level on the clock signal line, it counts its own high level period; if its own high level period is less than the high level period of any other control module's clock unit, it adjusts its own currently high logic level to a low level. The clock signal line is configured to detect the logic level of the clock unit of each control module when its own logic level transitions from high to low and remains at a low level; if the logic level of the clock unit of each control module is high, the logic level of the clock signal line is adjusted to high.

7. The splicing display screen according to claim 6, wherein, The low-level period of the clock signal line is greater than the low-level period of any of the clock units.

8. A control system for a video wall display, comprising the video wall display as described in any one of claims 1 to 7.

9. The control system for the splicing display screen according to claim 8, wherein, It also includes a playback control module and a data transmission module; The playback control module is configured to send the video stream to the data sending module through the video interface; The data sending module is configured to divide each video frame in the video stream into blocks according to the video stream, the video resolution of the video stream and the number of the displays, so as to obtain video information corresponding to each control module. The video information is sent to its corresponding control module; The video display screen is configured to display based on the received video information.

10. The control system for the splicing display screen according to claim 9, wherein, The data transmission module includes a configuration unit, a segmentation unit, and a transmission unit; The configuration unit is configured to receive configuration information sent by the user terminal; the configuration information includes the address information of the control module and the number of displays. The segmentation unit is configured to divide each video frame in the video stream into blocks according to the video stream, the video resolution of the video stream, and the number of the displays, to obtain video information corresponding to each control module. The sending unit is configured to send the video information to the corresponding control module according to the address information of each control module.

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