A watchdog monitoring method and device, electronic equipment and storage medium

Abstract

This invention provides a watchdog monitoring method, apparatus, electronic device, and storage medium. The method includes: acquiring a first operating frequency of the processor's operating clock and a second operating frequency of an independent counting clock; calculating the ratio between the first and second operating frequencies; receiving a pulse signal sent by the independent counting clock; performing frequency division processing on the pulse signal according to the ratio; counting the number of processed pulse signals; and monitoring the processor based on the count of processed pulse signals. By applying this invention, the pulse signal sent to the watchdog module by the independent counting clock is frequency divided according to the operating frequencies of the processor's operating clock and the independent counting clock, thereby adjusting the duration for which the watchdog module counts the maximum number of pulse signals, ensuring synchronization between the watchdog's own clock cycle and the processor's running program's watchdog feeding cycle when the processor's operating frequency changes.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a watchdog monitoring method, apparatus, electronic device, and storage medium. Background Technology

[0002] To meet the reliability design requirements of the system, a watchdog module is usually used to monitor the operating status of the MCU (Microcontroller Unit) in real time and generate a reset signal when an anomaly is detected, so that the system can be reset and resume normal operation. This avoids the situation where the program running on the MCU runs out of control or gets stuck in an infinite loop due to some external or internal factors, which would cause the entire system to be paralyzed and unable to recover.

[0003] Currently, watchdog timers are typically triggered by independent control logic and a fixed-frequency counting clock source independent of the MCU system clock, so that the watchdog module can operate independently of the MCU system and monitor the MCU.

[0004] However, because the watchdog timer has a fixed clock frequency, while the MCU system dynamically changes its operating frequency according to its actual application needs, a mismatch can occur between the clock frequency at which the watchdog counts and the operating frequency of the MCU system. For example, when the MCU is running at a slower clock frequency, it takes longer to run a long program segment, and the watchdog timer feeding period becomes longer. However, the watchdog timer itself does not need to be fed, resulting in an abnormal situation where the MCU system is normal but cannot feed the watchdog in time, which in turn affects application development. Summary of the Invention

[0005] This invention provides a watchdog monitoring method and a corresponding watchdog monitoring device, electronic device, and storage medium to overcome the problem that the watchdog clock cycle is out of sync with the watchdog feeding cycle of the MCU program due to the MCU system dynamically changing its operating frequency according to its actual application needs.

[0006] To address the aforementioned problems, this invention discloses a watchdog monitoring method applied to a watchdog module, wherein the watchdog module is connected to a processor and an independent counting clock, and the method includes:

[0007] Obtain the first operating frequency of the processor's operating clock and the second operating frequency of the independent counting clock;

[0008] Calculate the ratio between the first operating frequency and the second operating frequency;

[0009] Receive the pulse signal sent by the independent counting clock, and perform frequency division processing on the pulse signal according to the ratio;

[0010] The number of processed pulse signals is counted, and the processor is monitored based on the counted number of processed pulse signals.

[0011] Optionally, calculating the ratio between the first operating frequency and the second operating frequency includes:

[0012] Obtain the first frequency configuration table and the second frequency configuration table;

[0013] Find the first frequency configuration value corresponding to the first operating frequency from the first frequency configuration table, and find the second frequency configuration value corresponding to the second operating frequency from the second frequency configuration table;

[0014] Calculate the ratio of the first frequency configuration value to the second frequency configuration value.

[0015] Optionally, the watchdog module includes a counter, and the step of counting the number of processed pulse signals further includes:

[0016] The processed pulse signal is input into the counter of the watchdog module;

[0017] The watchdog module uses a counter to count the number of processed pulse signals.

[0018] Optionally, monitoring the processor based on the statistically processed number of pulse signals includes:

[0019] Determine whether the number of pulse signals after statistical processing reaches a preset threshold;

[0020] When the number of processed pulse signals reaches the preset threshold, it is determined that the processor is malfunctioning.

[0021] Optionally, after the number of processed pulse signals reaches the preset threshold, the method further includes:

[0022] A reset signal is sent to the processor, and the processor is reset by means of the reset signal.

[0023] Optionally, it also includes:

[0024] Before the number of processed pulse signals counted by the watchdog module reaches the preset threshold, an interrupt signal sent by the processor is received, the count of processed pulse signals is cleared to zero, and the count of processed pulse signals is recalculated.

[0025] This invention discloses a watchdog monitoring device applied to a watchdog module. The watchdog module is connected to a processor and an independent counting clock. The device includes:

[0026] The frequency acquisition module is used to acquire the first operating frequency of the processor's operating clock and the second operating frequency of the independent counting clock;

[0027] The relationship calculation module is used to calculate the ratio between the first operating frequency and the second operating frequency;

[0028] A frequency processing module is used to receive the pulse signal sent by the independent counting clock and perform frequency division processing on the pulse signal according to the ratio relationship;

[0029] An anomaly monitoring module is used to count the number of processed pulse signals and monitor the processor based on the count of processed pulse signals.

[0030] Optionally, the relationship calculation module includes:

[0031] The configuration table retrieval submodule is used to retrieve the first frequency configuration table and the second frequency configuration table.

[0032] The configuration value lookup submodule is used to look up the first frequency configuration value corresponding to the first operating frequency from the first frequency configuration table, and to look up the second frequency configuration value corresponding to the second operating frequency from the second frequency configuration table.

[0033] The ratio calculation submodule is used to calculate the ratio between the first frequency configuration value and the second frequency configuration value.

[0034] Optionally, the anomaly monitoring module includes:

[0035] The signal input submodule is used to input the processed pulse signal into the counter of the watchdog module;

[0036] The quantity statistics submodule is used to count the number of processed pulse signals using the counter of the watchdog module.

[0037] Optionally, the anomaly monitoring module includes:

[0038] The quantity judgment submodule is used to determine whether the number of the statistically processed pulse signals reaches a preset threshold.

[0039] The anomaly determination submodule is used to determine that the processor has an anomaly when the number of processed pulse signals reaches the preset threshold.

[0040] Optionally, it also includes:

[0041] The signal sending submodule is used to send a reset signal to the processor, and to perform a reset process on the processor through the reset signal.

[0042] Optionally, it also includes:

[0043] The signal receiving submodule is used to receive an interrupt signal sent by the processor before the number of processed pulse signals counted by the watchdog module reaches the preset threshold, clear the count of processed pulse signals to zero, and start counting the number of processed pulse signals again.

[0044] This invention discloses an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, it implements the steps of the watchdog monitoring method described above.

[0045] This invention discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the watchdog monitoring method described above.

[0046] The embodiments of the present invention have the following advantages:

[0047] In this embodiment of the invention, a first operating frequency of the processor's operating clock and a second operating frequency of the independent counting clock are obtained. The ratio between the first and second operating frequencies is calculated. Pulse signals sent by the independent counting clock are received and frequency-divided according to the ratio. The number of processed pulse signals is counted, and the processor is monitored based on the counted number of processed pulse signals. Applying this embodiment, based on the first operating frequency of the operating clock and the second operating frequency of the independent counting clock, the pulse signals sent by the independent counting clock to the watchdog module are frequency-divided. This adjusts the pulse width of the pulse signals sent by the independent counting clock to the watchdog module, thereby adjusting the duration for the watchdog module to count the maximum number of pulse signals. This ensures that when the processor's operating frequency changes, the watchdog module's own clock cycle is synchronized with the processor's running program's watchdog feeding cycle. The watchdog module can accurately determine the occurrence of processor anomalies, avoiding the abnormal situation where the watchdog module's watchdog feeding cycle becomes longer while the watchdog module's own watchdog feeding time remains unchanged, resulting in the processor system being normal but unable to feed the watchdog in time. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of a watchdog monitoring logic in a related technology of the present invention;

[0049] Figure 2 This is a flowchart illustrating the steps of an embodiment of the watchdog monitoring method of the present invention;

[0050] Figure 3 This is a logical schematic diagram of a watchdog monitoring method according to the present invention;

[0051] Figure 4 This is a flowchart illustrating the steps of another embodiment of the watchdog monitoring method of the present invention;

[0052] Figure 5 This is a logic diagram of a watchdog module according to the present invention;

[0053] Figure 6 This is a structural block diagram of an embodiment of the watchdog monitoring device of the present invention. Detailed Implementation

[0054] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] Reference Figure 1 The figure illustrates a watchdog monitoring logic diagram of a related technology of the present invention. As shown in the figure, the operating frequency of the MCU104 (Microcontroller Unit) is determined by the pulse signal provided by the MCU operating clock 103. The watchdog counting is triggered by an independent counting clock 101 with a fixed frequency to realize the independent monitoring of the MCU104 by the watchdog module 102. If the MCU104 software program runs normally, the MCU104 will send an interrupt signal to the watchdog module 102 within a specified time to reset the watchdog module 102's count to zero and restart the counting. If the MCU104 software program runs abnormally, the software program will not perform the watchdog feeding operation within a specified time. After the specified time is reached, the watchdog module 102 will send a reset signal to the MCU104 to reset the MCU104 to avoid failure and achieve a safe state.

[0056] However, the above solution has the following problems: the clock frequency of the watchdog module 102 is fixed, while the MCU 104 system will dynamically change its operating frequency according to its actual application needs. This can lead to a mismatch between the clock frequency of the watchdog module 102 and the operating frequency of the MCU 104 system. For example, when the MCU 104 is running at a slower clock frequency, it takes a long time to run a certain long program, and the time cycle for feeding the watchdog becomes longer. However, the time cycle for feeding the watchdog module 102 itself remains unchanged, resulting in an abnormal situation where the MCU 104 system is normal but cannot feed the watchdog in time, which in turn affects application development.

[0057] This invention provides a watchdog monitoring method. Based on the MCU's operating frequency, the pulse signal sent to the watchdog module via an independent counting clock is adjusted. This dynamically changes the watchdog module's counting frequency in response to changes in the MCU's operating frequency, synchronizing the watchdog module's own clock cycle with the MCU's feeding time cycle. This solves the problem of asynchrony between the watchdog module's clock cycle and the MCU's feeding time cycle caused by the MCU dynamically changing its operating frequency according to its actual application requirements.

[0058] Reference Figure 2 The diagram illustrates a flowchart of an embodiment of a watchdog monitoring method according to the present invention. This embodiment applies to a watchdog module, which operates independently of the processor and is connected to both the processor and an independent counting clock. Specifically, this embodiment may include the following steps:

[0059] Step 201: Obtain the first operating frequency of the processor's operating clock and the second operating frequency of the independent counting clock.

[0060] The processor is a microcontroller unit (MCU). The processor includes a running clock. The pulse signal provided by the running clock is divided to become the processor's internal clock frequency, i.e., the first running frequency. The second running frequency is the fixed clock frequency of the independent counting clock itself.

[0061] Specifically, the watchdog module obtains the first operating frequency of the processor's operating clock and the second operating frequency of the independent counting clock. The first operating frequency will change dynamically according to the processor's actual application requirements, while the second operating frequency of the independent counting clock is a fixed frequency.

[0062] Step 202: Calculate the ratio between the first operating frequency and the second operating frequency.

[0063] Specifically, the watchdog module includes proportional processing logic. After obtaining the first operating frequency and the second operating frequency, the proportional processing logic calculates the proportional relationship between the first operating frequency and the second operating frequency. For example, when the processor runs at 100MHz (the first operating frequency), the corresponding frequency configuration value is 0x1. The clock frequency of the independent counting clock is 1000Hz (the second operating frequency), and the corresponding frequency configuration value is 0x1. After the proportional processing logic processes the above frequency configuration value, it obtains a proportional value K = 1. At this time, the proportional relationship between the first operating frequency and the second operating frequency is 1.

[0064] Step 203: Receive the pulse signal sent by the independent counting clock, and perform frequency division processing on the pulse signal according to the ratio.

[0065] The watchdog module includes dynamic configuration logic. Specifically, after calculating the ratio between the first and second operating frequencies through proportional processing logic, the ratio is sent to the dynamic configuration logic. The dynamic configuration logic determines the third operating frequency (counting frequency) of the watchdog module based on the ratio. Based on the third frequency determined by the dynamic configuration logic, the pulse signal sent to the watchdog module by the independent counting clock is frequency-divided. For example, when the ratio is 10, the dynamic configuration logic determines that the third operating frequency (counting frequency) of the watchdog module is 10 times the second operating frequency of the independent counting clock. The pulse signal sent to the watchdog module by the independent counting clock is then divided by 10. The pulse width (duration of a single pulse signal) of the processed pulse signal is 10 times the original pulse width (duration of a single pulse signal). The third operating frequency corresponding to the processed pulse signal is one-tenth of the second operating frequency of the independent counting clock. For example, if the second operating frequency is 1000Hz, then the third operating frequency is 100Hz.

[0066] Reference Figure 3 The figure shows a logical schematic diagram of a watchdog monitoring method according to an embodiment of the present invention. As can be seen from the figure, the clock configuration value of MCU304 is determined by the pulse signal provided by MCU running clock 303. The watchdog module 302 receives the clock configuration value (the first frequency configuration value corresponding to the first frequency) sent by MCU304 (processor). Based on the clock configuration value, the watchdog feeding cycle is dynamically controlled (the pulse signal sent to the watchdog module 302 by independent counting clock 301 is frequency divided, thereby dynamically controlling the monitoring time interval of watchdog module 302), so as to realize the synchronization of the clock cycle of watchdog module 302 itself with the watchdog feeding cycle of the processor running program, and complete the monitoring of the processor.

[0067] Step 204: Count the number of processed pulse signals and monitor the processor based on the count of processed pulse signals.

[0068] In this process, after the pulse signal is frequency divided, the pulse width of the pulse signal changes, that is, the duration of a single pulse signal changes. As long as the maximum number of pulse signals counted by the watchdog module remains unchanged, the monitoring duration of the watchdog module changes.

[0069] Specifically, the watchdog module counts the number of processed pulse signals and monitors the processor based on this count to determine if the processor is malfunctioning. For example, if the watchdog module receives an interrupt signal (feed signal) from the processor before the count of processed pulse signals reaches its maximum, the processor is operating normally. In this case, the watchdog module resets the count of processed pulse signals to zero and starts counting them again. When the count of processed pulse signals reaches its maximum, it indicates that the processor is malfunctioning.

[0070] In this embodiment of the invention, the pulse signal sent from the independent counter clock to the watchdog module is frequency-divided according to the first operating frequency of the running clock and the second operating frequency of the independent counter. That is, the pulse width of the pulse signal sent from the independent counter clock to the watchdog module is adjusted, thereby adjusting the duration when the number of counted pulse signals by the watchdog module reaches the maximum. This ensures that the clock cycle of the watchdog module itself is synchronized with the watchdog feeding cycle of the processor running program when the processor operating frequency changes. The watchdog module can accurately determine the occurrence of processor abnormalities, avoiding the abnormal situation where the processor system is normal but the watchdog is not fed in time due to the watchdog feeding cycle becoming longer while the watchdog module itself needs to feed the watchdog for the same period of time.

[0071] Reference Figure 4 The diagram illustrates a flowchart of another embodiment of the watchdog monitoring method of the present invention. This embodiment applies to a watchdog module that operates independently of the processor and is connected to both the processor and an independent counting clock. Specifically, this embodiment may include the following steps:

[0072] Step 401: Obtain the first operating frequency of the processor's operating clock and the second operating frequency of the independent counting clock.

[0073] Step 402: Obtain the first frequency configuration table and the second frequency configuration table.

[0074] Step 403: Find the first frequency configuration value corresponding to the first operating frequency from the first frequency configuration table, and find the second frequency configuration value corresponding to the second operating frequency from the second frequency configuration table.

[0075] Step 404: Calculate the ratio of the first frequency configuration value to the second frequency configuration value.

[0076] The processor's operating clock has a first operating frequency and an independent counting clock has a second operating frequency with corresponding first and second frequency configuration value tables. The frequency configuration table contains the correspondence between the operating frequency and the frequency configuration value. For example, in the first frequency configuration table, when the first operating frequency is 100MHz, the corresponding frequency configuration value is 0x1, and when the first operating frequency is 10MHz, the corresponding frequency configuration value is 0xA (A is 10 in hexadecimal). In the second frequency configuration table, when the second operating frequency is 1000Hz, the corresponding frequency configuration value is 0x1.

[0077] Specifically, the first and second frequency configuration values ​​corresponding to the first and second operating frequencies are found according to the first and second frequency configuration tables, respectively. Then, the ratio of the first and second frequency configuration values ​​is calculated through proportional processing logic. The ratio is the proportional relationship between the first and second operating frequencies. For example, when the processor runs at 10MHz (first operating frequency), the corresponding frequency configuration value is 0xA. The clock frequency of the independent counting clock is 1000Hz (second operating frequency), and the corresponding frequency configuration value is 0x1. After the proportional processing logic processes the above frequency configuration values, the ratio value K = 10 is obtained. At this time, the ratio between the first and second operating frequencies is 1.

[0078] Step 405: Receive the pulse signal sent by the independent counting clock, and perform frequency division processing on the pulse signal according to the ratio.

[0079] Step 406: Count the number of processed pulse signals and monitor the processor based on the count of processed pulse signals.

[0080] In one embodiment of the present invention, the step of counting the number of processed pulse signals includes: inputting the processed pulse signals into the counter of the watchdog module; and counting the number of processed pulse signals by the counter of the watchdog module.

[0081] Specifically, after the pulse signal sent to the watchdog module by the independent counting clock is frequency divided according to the proportional relationship, the watchdog module inputs the processed pulse signal into the watchdog module's counter, and the watchdog module's counter counts the number of processed pulse signals.

[0082] Reference Figure 5The figure shows a logic diagram of a watchdog module according to an embodiment of the present invention. As can be seen from the figure, after the watchdog module obtains the MCU (processor) operating frequency configuration value (first frequency configuration value) and the independent counting clock frequency configuration value (second frequency configuration value), it performs proportional processing on the MCU operating frequency configuration value and the independent counting clock frequency configuration value to obtain the ratio value of the MCU operating frequency configuration value and the independent counting clock frequency configuration value. Based on the ratio value, the dynamic configuration value of the watchdog module's counter (counting frequency of the counter) is determined, and the counting frequency of the independent counting clock input to the watchdog module's counter is controlled according to the dynamic configuration value (the pulse signal sent to the watchdog module by the independent counting clock is frequency divided according to the proportional relationship), and then counting is performed by the counter.

[0083] In one embodiment of the present invention, the step of monitoring the processor based on the number of processed pulse signals includes: determining whether the number of processed pulse signals reaches a preset threshold; and determining that the processor is abnormal when the number of processed pulse signals reaches the preset threshold.

[0084] The preset threshold is the maximum value of the pulse signal counted by the pre-set counter. After setting, it is a fixed number. At this time, the monitoring time of the watchdog module counter = preset threshold * duration of a single pulse signal. Therefore, after the pulse signal is frequency divided, the pulse width of the pulse signal changes, that is, the duration of a single pulse signal changes, which causes the monitoring time of the watchdog module to change.

[0085] Specifically, when the number of pulse signals counted by the counter reaches a preset threshold, it indicates that the watchdog monitoring module has not received the interrupt signal (feed signal) sent for processing, indicating that there is an abnormality in the processor's operation.

[0086] In one embodiment of the present invention, after the number of processed pulse signals reaches the preset threshold, the method further includes: sending a reset signal to the processor and resetting the processor through the reset signal.

[0087] The preset threshold is the maximum value of the pulse signal counted by the pre-set counter. After setting, it is a fixed number. At this time, the monitoring time of the watchdog module counter = preset threshold * duration of a single pulse signal. Therefore, after the pulse signal is frequency divided, the pulse width of the pulse signal changes, that is, the duration of a single pulse signal changes, which causes the monitoring time of the watchdog module to change.

[0088] Specifically, when the number of pulse signals counted by the counter reaches a threshold, it indicates that there is an abnormality in the operation of the processor. The watchdog module sends a reset signal to the processor to reset the processor.

[0089] In one embodiment of the present invention, the method further includes: before the number of processed pulse signals counted by the watchdog module reaches the preset threshold, receiving an interrupt signal sent by the processor, clearing the count of processed pulse signals to zero, and starting to recount the number of processed pulse signals.

[0090] Specifically, the watchdog module's counter counts the number of processed pulse signals. Before the count of processed pulse signals reaches a preset threshold, the processor sends an interrupt signal to the watchdog module. This indicates that the processor is operating normally, and the count of processed pulse signals in the watchdog module's counter is reset to zero, and the count of processed pulse signals is restarted.

[0091] In this embodiment of the invention, a ratio of the frequency configuration values ​​corresponding to the first and second operating frequencies is determined based on the first operating frequency of the running clock and the second operating frequency of the independent counting clock. According to this ratio, the pulse signal sent from the independent counting clock to the watchdog module is frequency-divided, that is, the pulse width of the pulse signal sent from the independent counting clock to the watchdog module is adjusted. This adjusts the duration at which the number of pulse signals counted by the watchdog module reaches a preset threshold, ensuring that the watchdog's own clock cycle is synchronized with the processor's running program's watchdog feeding cycle when the processor's operating frequency changes. This allows the watchdog module to accurately determine the occurrence of processor anomalies, avoiding the abnormal situation where the watchdog feeding cycle becomes longer while the watchdog's own feeding time remains unchanged, resulting in the processor system being normal but unable to feed the watchdog in time.

[0092] To better understand the above embodiments of the present invention, a specific embodiment will be described:

[0093] There is a processor with a maximum operating frequency of 100MHz. The processor is connected to an independent watchdog module. The maximum frequency of the independent counting clock connected to the watchdog module is 1000Hz (the duration of a single clock cycle / single pulse signal is 1ms). The watchdog module includes a counter, which counts the pulse signals input to the counter at the independent counting clock frequency. The number of pulse signals counted by the counter is set to 1000 (1000 clock cycles).

[0094] When the processor runs at 100MHz, the corresponding frequency configuration value is 0x1, and the independent counting clock frequency is 1000Hz (the duration of a single clock cycle / single pulse signal is 1ms), with the corresponding frequency configuration value being 0x1. When the watchdog module's proportional processing logic collects the above configuration value, it identifies the proportional relationship K=1. At this time, after the dynamic configuration logic receives the proportional relationship K=1, it determines that the counting frequency of the watchdog module's counter is 1 / 2 of the independent counting clock frequency. That is, the pulse signal input to the counter at the independent counting clock frequency is processed by 1 / 2, and the counting frequency of the counter is 1000Hz (the duration of a single clock cycle / single pulse signal is 1ms). The maximum allowed time interval for the watchdog module to monitor is 1000 clock cycles with a counting frequency of 1 / 2 (single pulse time 1ms*1000), which is 1S.

[0095] When the processor runs at 10MHz, the corresponding frequency configuration value is 0xA, the independent counting clock frequency is 1000Hz (the duration of a single clock cycle / single pulse signal is 1ms), and the corresponding frequency configuration value is 0x1. When the watchdog module's proportional processing logic collects the above configuration values, it identifies the proportional relationship K=10. At this time, after the dynamic configuration logic receives the proportional relationship K=10, it determines that the counting frequency of the watchdog module's counter is 10 times the independent counting clock frequency. That is, the pulse signal input to the counter at the independent counting clock frequency is processed by 10 times, and the counting frequency of the counter is 100Hz (the duration of a single clock cycle / single pulse signal is 10ms). The maximum allowed time interval for the watchdog module to monitor is 1000 clock cycles with a counting frequency of 1 times the clock frequency (single pulse time 10ms*1000), which is 10S.

[0096] The calculation of the ratio K is not limited to the example of 10 times mentioned above; the specific ratio value can be adjusted according to specific needs.

[0097] In this embodiment of the invention, the pulse signal input to the watchdog module counter is adjusted according to the processor's operating frequency and the independent counting clock frequency, thereby adjusting the maximum allowable time interval for watchdog monitoring. This ensures that the watchdog module's own clock cycle is synchronized with the processor's running program's watchdog feeding cycle when the processor's operating frequency changes. This allows for accurate detection of processor anomalies and avoids the abnormal situation where the watchdog module's watchdog feeding cycle becomes longer while the watchdog module's own watchdog feeding time remains unchanged, resulting in the processor system being normal but unable to feed the watchdog in time.

[0098] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0099] Reference Figure 6 The diagram illustrates a structural block diagram of an embodiment of a watchdog monitoring device according to the present invention. The watchdog module is connected to a processor and an independent counting clock. Specifically, this embodiment may include the following modules:

[0100] The frequency acquisition module 601 is used to acquire the first operating frequency of the processor's operating clock and the second operating frequency of the independent counting clock;

[0101] The relationship calculation module 602 is used to calculate the ratio between the first operating frequency and the second operating frequency;

[0102] The frequency processing module 603 is used to receive the pulse signal sent by the independent counting clock and perform frequency division processing on the pulse signal according to the ratio relationship.

[0103] The anomaly monitoring module 604 is used to count the number of processed pulse signals and monitor the processor based on the count of processed pulse signals.

[0104] In one embodiment of the present invention, the relationship calculation module 602 includes:

[0105] The configuration table retrieval submodule is used to retrieve the first frequency configuration table and the second frequency configuration table.

[0106] The configuration value lookup submodule is used to look up the first frequency configuration value corresponding to the first operating frequency from the first frequency configuration table, and to look up the second frequency configuration value corresponding to the second operating frequency from the second frequency configuration table.

[0107] The ratio calculation submodule is used to calculate the ratio between the first frequency configuration value and the second frequency configuration value.

[0108] In one embodiment of the present invention, the anomaly monitoring module 604 includes:

[0109] The signal input submodule is used to input the processed pulse signal into the counter of the watchdog module;

[0110] The quantity statistics submodule is used to count the number of processed pulse signals using the counter of the watchdog module.

[0111] In one embodiment of the present invention, the anomaly monitoring module 604 includes:

[0112] The quantity judgment submodule is used to determine whether the number of the statistically processed pulse signals reaches a preset threshold.

[0113] The anomaly determination submodule is used to determine that the processor has an anomaly when the number of processed pulse signals reaches the preset threshold.

[0114] In one embodiment of the present invention, it further includes:

[0115] The signal sending submodule is used to send a reset signal to the processor, and to perform a reset process on the processor through the reset signal.

[0116] In one embodiment of the present invention, it further includes:

[0117] The signal receiving submodule is used to receive an interrupt signal sent by the processor before the number of processed pulse signals counted by the watchdog module reaches the preset threshold, clear the count of processed pulse signals to zero, and start counting the number of processed pulse signals again.

[0118] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0119] This invention discloses an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, it implements the steps described in the above watchdog monitoring method embodiment.

[0120] This invention discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps described in the above watchdog monitoring method embodiment.

[0121] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0122] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0123] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0124] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0126] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0127] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0128] The watchdog monitoring method, watchdog monitoring device, electronic device, and storage medium provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A watchdog monitoring method, characterized in that, The method, applied to a watchdog module connected to both a processor and an independent counting clock, includes: Obtain the first operating frequency of the processor's operating clock and the second operating frequency of the independent counting clock; Calculate the ratio between the first operating frequency and the second operating frequency; Receive the pulse signal sent by the independent counting clock, and perform frequency division processing on the pulse signal according to the ratio; The number of processed pulse signals is counted, and the processor is monitored based on the count of processed pulse signals. The calculation of the ratio between the first operating frequency and the second operating frequency includes: Obtain the first frequency configuration table and the second frequency configuration table; Find the first frequency configuration value corresponding to the first operating frequency from the first frequency configuration table, and find the second frequency configuration value corresponding to the second operating frequency from the second frequency configuration table; Calculate the ratio between the first frequency configuration value and the second frequency configuration value; The step of frequency division of the pulse signal according to the stated ratio includes: The dynamic configuration value of the watchdog module's counter is determined based on the stated ratio. The counting frequency of the counter input to the watchdog module is controlled according to the dynamic configuration value.

2. The method according to claim 1, characterized in that, The watchdog module includes a counter, and the counting of the number of processed pulse signals includes: The processed pulse signal is input into the counter of the watchdog module; The watchdog module uses a counter to count the number of processed pulse signals.

3. The method according to claim 1 or 2, characterized in that, The step of monitoring the processor based on the number of processed pulse signals includes: Determine whether the number of pulse signals after statistical processing reaches a preset threshold; When the number of processed pulse signals reaches the preset threshold, it is determined that the processor is malfunctioning.

4. The method according to claim 3, characterized in that, After the number of processed pulse signals reaches the preset threshold, the method further includes: A reset signal is sent to the processor, and the processor is reset by means of the reset signal.

5. The method according to claim 3, characterized in that, Also includes: Before the number of processed pulse signals counted by the watchdog module reaches the preset threshold, an interrupt signal sent by the processor is received, the count of processed pulse signals is cleared to zero, and the count of processed pulse signals is recalculated.

6. A watchdog monitoring device, characterized in that, The device is applied to a watchdog module, wherein the watchdog module is connected to both a processor and an independent counting clock, and the device includes: The frequency acquisition module is used to acquire the first operating frequency of the processor's operating clock and the second operating frequency of the independent counting clock; The relationship calculation module is used to calculate the ratio between the first operating frequency and the second operating frequency; A frequency processing module is used to receive the pulse signal sent by the independent counting clock and perform frequency division processing on the pulse signal according to the ratio relationship; An anomaly monitoring module is used to count the number of processed pulse signals and monitor the processor based on the count of processed pulse signals. The relation calculation module includes: The configuration table retrieval submodule is used to retrieve the first frequency configuration table and the second frequency configuration table. The configuration value lookup submodule is used to look up the first frequency configuration value corresponding to the first operating frequency from the first frequency configuration table, and to look up the second frequency configuration value corresponding to the second operating frequency from the second frequency configuration table. The ratio calculation submodule is used to calculate the ratio between the first frequency configuration value and the second frequency configuration value; The frequency processing module is specifically used to determine the dynamic configuration value of the watchdog module's counter based on the proportional value, and to control the counting frequency of the independent counting clock input to the watchdog module's counter based on the dynamic configuration value.

7. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the watchdog monitoring method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the steps of the watchdog monitoring method as described in any one of claims 1 to 5.

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