Pixel circuit and driving method thereof, display substrate, and display device

Abstract

The present invention provides a pixel circuit and a driving method thereof, a display substrate, and a display device, which relate to the field of display technology, and are intended to solve the problems of insufficient data writing on a display screen, requiring a high voltage to display a black screen, and display brightness differences between odd and even rows. In the pixel circuit, a data writing circuit is used to control the connection between a data line and a second end of a driving circuit under the control of a first scanning signal provided by a first scanning line; a compensation control circuit is used to control the connection between a first end of the driving circuit and a connection node under the control of a second scanning signal provided by a second scanning line; and a first control circuit is used to control the connection between a control end of the driving circuit and a connection node under the control of a first scanning signal. The pixel circuit provided by the present invention is used to drive a light-emitting element to emit light.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to application number PCT / CN2021 / 109894 filed on July 30, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0004] With the popularity of active-matrix organic light-emitting diode (AMOLED) displays in the mid-to-high-end market, the quality requirements for AMOLED displays are getting higher and higher, and more refined requirements are also being put forward for the design.

[0005] At present, in the process of writing data and compensating the driving transistor in the AMOLED display, the problem of insufficient data writing is easy to occur. In addition, the display screen also has the problem that a high voltage is required to display a black screen, and there is a difference in display brightness between odd and even rows. Summary of the invention

[0006] The object of the present invention is to provide a pixel circuit and a driving method thereof, a display substrate, and a display device, which are used to solve the problems of insufficient data writing on the display screen, requiring a high voltage to display a black screen, and display brightness differences between odd and even rows.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] A first aspect of the present invention provides a pixel circuit, comprising: a driving circuit, a data writing circuit, a compensation control circuit and a first control circuit;

[0009] The data writing circuit is coupled to the first scan line, the data line, and the second end of the driving circuit respectively, and is used to control the data line to be connected to the second end of the driving circuit under the control of the first scan signal provided by the first scan line;

[0010] The compensation control circuit is coupled to the second scan line, the first end of the drive circuit and the connection node respectively, and is used to control the connection between the first end of the drive circuit and the connection node under the control of the second scan signal provided by the second scan line;

[0011] The first control circuit is coupled to the first scan line, the control end of the drive circuit and the connection node respectively, and is used to control the connection between the control end of the drive circuit and the connection node under the control of the first scan signal.

[0012] Optionally, the pixel circuit further includes:

[0013] A first initialization circuit, wherein the first initialization circuit is coupled to an initialization control line, a first initialization voltage line and a control end of the driving circuit respectively, and is used for controlling the connection between the first initialization voltage line and the control end of the driving circuit under the control of an initialization control signal provided by the initialization control line.

[0014] Optionally, the pixel circuit further includes:

[0015] A first initialization circuit is coupled to the initialization control line, the first initialization voltage line and the connection node respectively, and is used to control the connection between the first initialization voltage line and the connection node under the control of an initialization control signal provided by the initialization control line.

[0016] Optionally, the pixel circuit further includes:

[0017] A reset circuit is respectively coupled to the third scan line, the reset voltage line and the second end of the drive circuit, and is used to control the connection between the reset voltage line and the second end of the drive circuit under the control of a third scan signal provided by the third scan line.

[0018] Optionally, the pixel circuit further includes:

[0019] A reset circuit is coupled to the third scan line, the reset voltage line and the first end of the drive circuit respectively, and is used to control the connection between the reset voltage line and the first end of the drive circuit under the control of a third scan signal provided by the third scan line.

[0020] Optionally, the pixel circuit further includes: a light emitting control circuit, a storage circuit and a light emitting element;

[0021] The light emitting control circuit is coupled to the light emitting control line, the first end of the driving circuit and the light emitting element respectively, and is used to control the connection between the first end of the driving circuit and the light emitting element under the control of the light emitting control signal provided by the light emitting control line;

[0022] The light emitting control circuit is also coupled to the first voltage line and the second end of the driving circuit, and is used to control the first voltage line to be connected to the second end of the driving circuit under the control of the light emitting control signal;

[0023] The energy storage circuit is coupled to the control terminal of the driving circuit and the first voltage line respectively.

[0024] Optionally, the pixel circuit further includes: a second initialization circuit and a light emitting element;

[0025] The second initialization circuit is coupled to the third scan line, the second initialization voltage line and the light emitting element respectively, and is used to control the connection between the second initialization voltage line and the light emitting element under the control of a third scan signal provided by the third scan line.

[0026] Optionally, the pixel circuit further includes a first initialization circuit, wherein the first initialization circuit is coupled to a first initialization voltage line, and the first initialization voltage line is multiplexed as the reset voltage line.

[0027] Optionally, the compensation control circuit includes a first transistor, the driving circuit includes a third transistor, the data writing circuit includes a fourth transistor, and the first control circuit includes a ninth transistor;

[0028] The gate of the first transistor is coupled to the second scan line, the first electrode of the first transistor is coupled to the second electrode of the third transistor, and the second electrode of the first transistor is coupled to the connection node;

[0029] A gate of the fourth transistor is coupled to the first scan line, a first electrode of the fourth transistor is coupled to the data line, and a second electrode of the fourth transistor is coupled to the first electrode of the third transistor;

[0030] A gate of the ninth transistor is coupled to the first scan line, a first electrode of the ninth transistor is coupled to the connection node, and a second electrode of the ninth transistor is coupled to the gate of the third transistor.

[0031] Optionally, the first initialization circuit includes a second transistor, a gate of the second transistor is coupled to the initialization control line, a first electrode of the second transistor is coupled to the first initialization voltage line, and a second electrode of the second transistor is coupled to the control end of the driving circuit.

[0032] Optionally, the first initialization circuit includes a second transistor, a gate of the second transistor is coupled to the initialization control line, a first electrode of the second transistor is coupled to the first initialization voltage line, and a second electrode of the second transistor is coupled to the connection node.

[0033] Optionally, the reset circuit includes an eighth transistor;

[0034] A gate of the eighth transistor is coupled to the third scan line, a first electrode of the eighth transistor is coupled to the reset voltage line, and a second electrode of the eighth transistor is coupled to the second end of the driving circuit.

[0035] Optionally, the reset circuit includes an eighth transistor;

[0036] A gate of the eighth transistor is coupled to the third scan line, a first electrode of the eighth transistor is coupled to the reset voltage line, and a second electrode of the eighth transistor is coupled to the first end of the driving circuit.

[0037] Optionally, the light emitting control circuit includes a fifth transistor and a sixth transistor;

[0038] The gate of the fifth transistor is coupled to the light emitting control line, the first electrode of the fifth transistor is coupled to the first voltage line, and the second electrode of the fifth transistor is coupled to the second end of the driving circuit;

[0039] The gate of the sixth transistor is coupled to the light emitting control line, the first electrode of the sixth transistor is coupled to one end of the driving circuit, and the second electrode of the sixth transistor is coupled to the light emitting element.

[0040] Optionally, the second initialization circuit includes a seventh transistor,

[0041] A gate of the seventh transistor is coupled to the third scan line, a first electrode of the seventh transistor is coupled to the second initialization voltage line, and a second electrode of the seventh transistor is coupled to the light emitting element.

[0042] Based on the technical solution of the above pixel circuit, the second aspect of the present invention provides a driving method, which is applied to the above pixel circuit, wherein the display cycle includes a writing compensation stage, and the writing compensation stage includes: a writing control stage and a non-writing control stage; the driving method includes:

[0043] During the entire write compensation phase, the compensation control circuit controls the first end of the driving circuit to be connected to the connection node under the control of the second scanning signal;

[0044] In the write control stage, the data write circuit controls the data line to be connected to the second end of the drive circuit under the control of the first scan signal; the first control circuit controls the control end of the drive circuit to be connected to the connection node under the control of the first scan signal;

[0045] In the non-write control stage, the data write circuit controls the data line to be disconnected from the second end of the drive circuit under the control of the first scan signal; the first control circuit controls the control end of the drive circuit to be disconnected from the connection node under the control of the first scan signal.

[0046] Optionally, the end time of the write compensation phase is the same as the end time of the write control phase.

[0047] Optionally, the display cycle further includes an initialization phase; and the driving method further includes:

[0048] In the initialization stage, the first initialization circuit in the pixel circuit controls the connection between the first initialization voltage line and the control end of the driving circuit under the control of the initialization control signal;

[0049] Alternatively, in the initialization stage, the first initialization circuit controls the connection between the first initialization voltage line and the connection node under the control of the initialization control signal, and the first control circuit controls the connection between the control end of the drive circuit and the connection node under the control of the first scanning signal.

[0050] Optionally, the display period further includes a bias compensation phase and a light emitting phase, and the driving method includes:

[0051] In the bias compensation stage, the reset circuit controls the reset voltage line to be connected to the second end of the drive circuit under the control of the third scan signal; or the reset circuit controls the reset voltage line to be connected to the first end of the drive circuit under the control of the third scan signal;

[0052] In the light-emitting stage, the light-emitting control circuit in the pixel circuit controls the connection between the first voltage line and the second end of the driving circuit, and controls the connection between the first end of the driving circuit and the light-emitting element under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

[0053] Based on the technical solution of the above pixel circuit, the third aspect of the present invention provides a display substrate, including a substrate and a plurality of sub-pixels arranged on the substrate, wherein the sub-pixels include the above pixel circuit; the sub-pixels also include:

[0054] A data line, a first scan line and a second scan line; the data line includes at least a portion extending along a first direction, the first scan line includes at least a portion extending along a second direction, the third scan line includes at least a portion extending along the second direction, and the second direction intersects the first direction;

[0055] The data writing circuit is coupled to the first scan line, the data line and the second end of the driving circuit respectively, and is used to control the data line to be connected to the second end of the driving circuit under the control of the first scan signal provided by the first scan line;

[0056] The compensation control circuit is coupled to the second scan line, the first end of the drive circuit and the connection node respectively, and is used to control the connection between the first end of the drive circuit and the connection node under the control of the second scan signal provided by the second scan line;

[0057] The first control circuit is coupled to the first scan line, the control end of the drive circuit and the connection node respectively, and is used to control the connection between the control end of the drive circuit and the connection node under the control of the first scan signal.

[0058] Optionally, the first control circuit includes a ninth transistor, the ninth transistor includes a ninth active layer, and the ninth active layer includes at least a portion extending along the first direction;

[0059] The driving circuit comprises a third transistor, and an orthographic projection of a gate of the third transistor on the substrate and an orthographic projection of the ninth active layer on the substrate are arranged along the first direction;

[0060] The sub-pixel further includes a first connection pattern, and the second electrode of the ninth transistor is coupled to the gate electrode of the third transistor through the first connection pattern.

[0061] Optionally, the first initialization circuit in the pixel circuit includes a second transistor, the second transistor includes a second active layer, the second active layer includes at least a portion extending along the first direction; an orthographic projection of a portion of the second active layer on the substrate and an orthographic projection of a portion of the ninth active layer on the substrate are arranged along the second direction;

[0062] The sub-pixel further includes a second connection pattern, the second connection pattern includes a portion extending along the first direction and a portion extending along the second direction; the second electrode of the second transistor is coupled to the first connection pattern through the second connection pattern.

[0063] Optionally, the first initialization circuit in the pixel circuit includes a second transistor, the second transistor includes a second active layer, the second active layer includes at least a portion extending along the first direction; an orthographic projection of a portion of the second active layer on the substrate and an orthographic projection of a portion of the ninth active layer on the substrate are arranged along the second direction;

[0064] The sub-pixel further includes a third connection pattern, wherein the third connection pattern includes at least a portion extending along the second direction; the second electrode of the second transistor is coupled to the first electrode of the ninth transistor through the third connection pattern.

[0065] Optionally, an orthographic projection of the third connection pattern on the substrate at least partially overlaps with an orthographic projection of the first scanning line on the substrate.

[0066] Optionally, the sub-pixel further includes an initialization control line, and an orthographic projection of the third connection pattern on the substrate at least partially overlaps with an orthographic projection of the initialization control line on the substrate.

[0067] Based on the technical solution of the above pixel circuit, the fourth aspect of the present invention provides a display device, including the above display substrate.

[0068] In the technical solution provided by the present invention, by connecting the first control circuit between the N1 node and the compensation control circuit, and the first control circuit and the data writing circuit are both controlled by the first scanning signal, the following beneficial effects are achieved.

[0069] Effect 1: At time tb, the second scan signal written by the second scan line changes from low level to high level, and T1 is turned on. Between time tb and time tc, since the first control circuit controls to disconnect the electrical connection between the N1 node and the connection node, the voltages of the N2 node and the N3 node will no longer flow to the N1 node, so that when the data signal is written at time tc, the potential of the N1 node is still maintained at the low voltage of Vi1, ensuring that the data signal is fully written.

[0070] Effect 2: At the end of the write compensation phase, the second scan signal written by the second scan line changes from a high level to a low level. By adding the first control circuit, at the end of the write compensation phase, the first scan signal written by the first scan line changes from a low level to a high level, so that at the end of the write compensation phase, the N1 node is pulled upward, which is beneficial to reduce the data voltage required when displaying a black screen.

[0071] Effect 3: When one GOA (S2) provides the second scanning signal to the second scanning lines corresponding to two rows of sub-pixels at the same time. At time tb, the second scanning signal written to the second scanning line changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit controls the disconnection of the electrical connection between the N1 node and the connection node, the N1 node will not be discharged between time tb and time tc, thereby ensuring that the initial voltage of the N1 node before the data signal is written is the same.

[0072] Moreover, between time tb and time tc, since the first control circuit controls the disconnection of the electrical connection between the N1 node and the connection node, it ensures that the voltage is given to the N1 nodes in the two rows of sub-pixels at the same time. Therefore, even in the case of row-by-row scanning, the initial voltage of the N1 nodes in the two rows of sub-pixels before the data signal is written is the same.

[0073] Therefore, when the two rows of sub-pixels include odd-numbered rows of sub-pixels and even-numbered rows of sub-pixels, there will be no difference in display brightness between the odd-numbered rows of sub-pixels and the even-numbered rows of sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0075] Figure 1 A first structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0076] Figure 2 A second structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0077] Figure 3 A first circuit diagram of a pixel circuit provided by an embodiment of the present invention;

[0078] Figure 4 A first timing diagram provided for an embodiment of the present invention;

[0079] Figure 5 A third structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0080] Figure 6 A second circuit diagram of a pixel circuit provided by an embodiment of the present invention;

[0081] Figure 7 A second timing diagram provided by an embodiment of the present invention;

[0082] Figure 8 A third circuit diagram of a pixel circuit provided by an embodiment of the present invention;

[0083] Fig. 9 A schematic diagram of the voltage of the N1 node provided in an embodiment of the present invention;

[0084] Fig.10 A current difference diagram of odd-numbered rows and even-numbered rows of sub-pixels provided by an embodiment of the present invention;

[0085] Fig.11 A schematic diagram of the layout of a display substrate provided by an embodiment of the present invention;

[0086] Fig.12A schematic diagram of stacking the second gate metal layer to the third gate metal layer provided in an embodiment of the present invention;

[0087] Fig.13 A schematic cross-sectional view of an eighth transistor provided in an embodiment of the present invention.

[0088] Fig.14 for Figure 3 The corresponding layout diagram;

[0089] Fig.15 for Fig.14 Schematic diagram of the layout of the poly active layer;

[0090] Fig.16 for Fig.14 A schematic diagram of the layout of the first gate metal layer in FIG.

[0091] Fig.17 for Fig.14 A schematic diagram of the layout of the second gate metal layer in FIG.

[0092] Fig.18 for Fig.14 Schematic diagram of the layout of the oxide active layer in FIG.

[0093] Fig.19 for Fig.14 A schematic diagram of the layout of the third gate metal layer in FIG.

[0094] Fig. 20 for Fig.14 A schematic diagram of a first connecting hole in FIG.

[0095] Fig.21 for Fig.14 A schematic diagram of a second connecting hole in FIG.

[0096] Fig. 22 for Fig.14 A schematic diagram of the layout of the first source and drain metal layer in FIG.

[0097] Fig.23 for Fig.14 Schematic diagram of vias formed in the passivation layer;

[0098] Fig.24 for Fig.14 Schematic diagram of vias formed in the first flat layer;

[0099] Fig.25 for Fig.14 A schematic diagram of the layout of the second source and drain metal layer in FIG.

[0100] Fig.26 for Figure 6 a corresponding first layout schematic diagram;

[0101] Fig. 27for Fig.26 A schematic diagram of the layout of the second gate metal layer in FIG.

[0102] Fig.28 for Fig.26 Schematic diagram of the layout of the oxide active layer in FIG.

[0103] Fig.29 for Fig.26 A schematic diagram of the layout of the third gate metal layer in FIG.

[0104] Fig.30 for Fig.26 A schematic diagram of a second connecting hole in FIG.

[0105] Fig.31 for Fig.26 A schematic diagram of the layout of the first source and drain metal layer in FIG.

[0106] Fig.32 for Figure 6 a corresponding second layout schematic diagram;

[0107] Fig.33 for Fig.32 A schematic diagram of the layout of the first source and drain metal layer in FIG.

[0108] Fig.34 for Figure 6 The corresponding third layout schematic diagram;

[0109] Fig.35 for Fig.34 A schematic diagram of the layout of the first source and drain metal layer in FIG.

[0110] Fig.36 A fourth circuit diagram of a pixel circuit provided by an embodiment of the present invention;

[0111] Fig.37 This is a third timing diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0112] In order to further illustrate the pixel circuit and its driving method, display substrate, and display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0113] like Fig.36 and Fig.37 As shown, the present invention provides a pixel circuit, which includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0114] The gate of the first transistor T1 is coupled to the second scan line S2, the first electrode of the first transistor T1 is coupled to the second electrode of the third transistor T3, and the second electrode of the first transistor T1 is coupled to the gate T3-g of the third transistor T3;

[0115] The gate of the second transistor T2 is coupled to the initialization control line R1, the first electrode of the second transistor T2 is coupled to the first initialization voltage line Vinit1, and the second electrode of the second transistor T2 is coupled to the gate of the third transistor T3;

[0116] A gate of the fourth transistor T4 is coupled to the first scan line S1, a first electrode of the fourth transistor T4 is coupled to the data line D1, and a second electrode of the fourth transistor T4 is coupled to a first electrode of the third transistor T3;

[0117] The gate of the fifth transistor T5 is coupled to the light emitting control line E1, the first electrode of the fifth transistor T5 is coupled to the first voltage line, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the third transistor T3;

[0118] A gate of the sixth transistor T6 is coupled to the light emitting control line E1 , a first electrode of the sixth transistor T6 is coupled to a second electrode of the third transistor T3 , and a second electrode of the sixth transistor T6 is coupled to the light emitting element.

[0119] A gate of the seventh transistor T7 is coupled to the third scan line S3 , a first electrode of the seventh transistor T7 is coupled to the second initialization voltage line Vinit2 , and a second electrode of the seventh transistor T7 is coupled to the light emitting element.

[0120] A gate of the eighth transistor T8 is coupled to the third scan line S3 , a first electrode of the eighth transistor T8 is coupled to the reset voltage line DR, and a second electrode of the eighth transistor T8 is coupled to a first electrode of the third transistor T3 .

[0121] The first transistor T1 and the second transistor T2 include N-type oxide transistors, and the first transistor T1 and the second transistor T2 need to be controlled by independent second scan lines S2 and initialization control lines R1.

[0122] In the initialization phase P1, T2 is turned on, and the first initialization voltage line Vinit1 writes a relatively low negative voltage, ie, the first initialization voltage Vi1 (eg, -3v), to the N1 node to initialize the gate of the third transistor T3.

[0123] In the bias compensation phase P2, T8 is turned on, and the reset voltage line DR writes a reset voltage (e.g., 5V) to the N2 node to apply bias stress to the third transistor T3; at the same time, T7 turns on the second initialization voltage line Vinit2 to write the second initialization voltage Vi2 to the anode of the light-emitting element to initialize the anode. It should be noted that the reset voltage can be a reference voltage Vref, which is used to apply bias stress to the third transistor, and is usually a high voltage to achieve the desired effect.

[0124] In the write compensation phase P3, T1 is turned on, and after T4 is turned on, the data signal starts to be written to the N1 node to achieve threshold voltage compensation.

[0125] After the writing compensation stage P3, after a short interval, the light-emitting stage P4 is entered and the screen starts to emit light.

[0126] The above pixel circuit has the following shortcomings:

[0127] The first deficiency is: at time tb, the second scan signal written by the second scan line S2 changes from a low level to a high level, and T1 is turned on. At this time, the Vref voltage on the N2 node and the N3 node will quickly pull up the N1 node. As a result, when the data signal starts to be written at time tc, the initial voltage of the N1 point that controls the opening of T3 is no longer Vi1, but a higher voltage that changes with Vref. The level of the N1 node voltage controls the degree of T3 switching (within a certain range, the lower the N1 node voltage, the better the degree of opening of the T3 switch, and the greater the current flowing), which affects the writing of the data signal Vdata and causes insufficient writing.

[0128] The second shortcoming is that at the end of the write compensation stage P3, the second scan signal written by the second scan line S2 changes from a high level to a low level, which will couple the N1 node down through the parasitic capacitance formed by T1, causing the light-emitting element to become brighter, which in turn will require a higher data voltage to display a black screen.

[0129] The third shortcoming: at the moment tb, since the current timing is that a GOA (S2) provides the second scan signal for the second scan line S2 corresponding to the two rows of sub-pixels at the same time; and the capacitance of the N2 node and the N3 node in the two rows of sub-pixels may be different due to the different layout environments, so at the moment tb, there is a difference in the discharge amount to the N1 node in the two rows of sub-pixels, which causes the initial voltage of the N1 node to be different before the data signal is written. Moreover, since the display substrate is scanned line by line during display, the N1 node is given voltage for a longer time in the first row of sub-pixels scanned, resulting in different initial voltages of the N1 nodes in the two rows of sub-pixels before the data signal is written. Therefore, when the two rows of sub-pixels include odd-numbered rows of sub-pixels and even-numbered rows of sub-pixels, it will cause a difference in display brightness between the odd-numbered and even-numbered rows of sub-pixels.

[0130] Based on the above three deficiencies, the embodiments of the present invention provide the following technical solutions:

[0131] See also Figure 1 , Figure 2 , Figure 5 , an embodiment of the present invention provides a pixel circuit, comprising: a driving circuit 11, a data writing circuit 41, a compensation control circuit 13 and a first control circuit 12;

[0132] The data writing circuit 41 is coupled to the first scan line S1, the data line D1, and the second end of the driving circuit 11, respectively, and is used to control the data line D1 to be connected to the second end of the driving circuit 11 (i.e., the second node N2) under the control of the first scan signal provided by the first scan line S1;

[0133] The compensation control circuit 13 is coupled to the second scan line S2, the first end of the drive circuit 11 (i.e., the third node N3) and the connection node N0 respectively, and is used to control the connection between the first end of the drive circuit 11 and the connection node N0 under the control of the second scan signal provided by the second scan line S2;

[0134] The first control circuit 12 is coupled to the first scan line S1, the control end (first node N1) of the drive circuit 11 and the connection node N0 respectively, and is used to control the connection between the control end of the drive circuit 11 and the connection node N0 under the control of the first scan signal.

[0135] Exemplarily, the first scan line S1 is used to write the first scan signal, the data line D1 is used to write the data signal, and the second scan line S2 is used to write the second scan signal.

[0136] Exemplarily, when the first scan signal is at an effective level, the data write circuit 41 is used to, under the control of the first scan signal provided by the first scan line S1, conduct the electrical connection between the data line D1 and the second end of the drive circuit 11. When the first scan signal is at an ineffective level, the data write circuit 41 is used to, under the control of the first scan signal provided by the first scan line S1, disconnect the electrical connection between the data line D1 and the second end of the drive circuit 11.

[0137] Exemplarily, when the first scan signal is at an effective level, the first control circuit 12 is used to, under the control of the first scan signal, conduct the electrical connection between the control end of the drive circuit 11 and the connection node N0. When the first scan signal is at an ineffective level, the first control circuit 12 is used to, under the control of the first scan signal, disconnect the electrical connection between the control end of the drive circuit 11 and the connection node N0.

[0138] Exemplarily, when the second scanning signal is at a valid level, the compensation control circuit 13 is used to, under the control of the second scanning signal, turn on the electrical connection between the first end of the driving circuit 11 and the connection node N0; when the second scanning signal is at an ineffective level, the compensation control circuit 13 is used to, under the control of the second scanning signal, disconnect the electrical connection between the first end of the driving circuit 11 and the connection node N0.

[0139] Exemplarily, the driving circuit 11 is used to control the connection between the first end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the potential of the control end thereof.

[0140] like Figure 4 and Figure 7 As shown, exemplarily, the display cycle includes a write compensation phase P3, and the write compensation phase P3 includes: a write control phase P32 and a non-write control phase P31; the driving method includes:

[0141] During the entire write compensation phase P3, the compensation control circuit 13 controls the first end of the driving circuit 11 to be connected to the connection node N0 under the control of the second scanning signal;

[0142] In the non-writing control phase P31, the data writing circuit 41 controls the data line D1 to be disconnected from the second end of the driving circuit 11 under the control of the first scanning signal; the first control circuit 12 controls the control end of the driving circuit 11 to be disconnected from the connection node N0 under the control of the first scanning signal;

[0143] In the write control stage P32, the data write circuit 41 controls the data line D1 to be connected to the second end of the drive circuit 11 under the control of the first scan signal; the first control circuit 12 controls the control end of the drive circuit 11 to be connected to the connection node N0 under the control of the first scan signal.

[0144] According to the specific structure of the above-mentioned pixel circuit, it can be known that in the pixel circuit provided in the embodiment of the present invention, by connecting the first control circuit 12 between the N1 node and the compensation control circuit 13, and the first control circuit 12 and the data writing circuit 41 are both controlled by the first scanning signal, the following beneficial effects are achieved.

[0145] Effect 1: At time tb, the second scanning signal written into the second scanning line S2 changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit 12 controls to disconnect the electrical connection between the N1 node and the connection node N0, the voltages of the N2 node and the N3 node will no longer flow to the N1 node, so that when the data signal is written at time tc, the potential of the N1 node is still maintained at the low voltage of Vi1, ensuring that the data signal is fully written.

[0146] Effect 2: At the end of the writing compensation phase P3, the second scanning signal written by the second scanning line S2 changes from a high level to a low level. By adding the first control circuit 12, at the end of the writing compensation phase P3, the first scanning signal written by the first scanning line S1 changes from a low level to a high level, so that at the end of the writing compensation phase P3, the N1 node is pulled upward, which is conducive to reducing the data voltage required when displaying a black screen.

[0147] like Fig. 9 As shown, curve 1 is a potential simulation curve of the N1 node when the first control circuit 12 is set in the pixel circuit. Curve 2 is a potential simulation curve of the N1 node when the first control circuit 12 is not set in the pixel circuit. Comparing curve 1 and curve 2, it is found that when the first control circuit 12 is set, the potential of the N1 node is increased by 0.5v, so it is expected that the corresponding data voltage when displaying a black screen can be reduced by 0.5v, that is, the data voltage required for displaying a black screen is reduced.

[0148] Effect 3: When one GOA (S2) provides the second scanning signal to the second scanning line S2 corresponding to two rows of sub-pixels at the same time. At time tb, the second scanning signal written to the second scanning line S2 changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit 12 controls the disconnection of the electrical connection between the N1 node and the connection node N0, no discharge is made to the N1 node between time tb and time tc, thereby ensuring that the initial voltage of the N1 node before the data signal is written is the same.

[0149] Moreover, between time tb and time tc, since the first control circuit 12 controls the disconnection of the electrical connection between the N1 node and the connection node N0, it ensures that the voltage is given to the N1 nodes in the two rows of sub-pixels at the same time. Therefore, even in the case of row-by-row scanning, the initial voltage of the N1 nodes in the two rows of sub-pixels before the data signal is written is the same.

[0150] Therefore, when the two rows of sub-pixels include odd-numbered rows of sub-pixels and even-numbered rows of sub-pixels, there will be no difference in display brightness between the odd-numbered rows of sub-pixels and the even-numbered rows of sub-pixels.

[0151] like Fig.10 As shown, the driving current difference of the odd and even rows of sub-pixels under a certain data signal is illustrated. It can be seen that the pixel circuit provided by the present invention basically eliminates the driving current difference of the odd and even rows of sub-pixels (the difference is 0.3%). When the sub-pixels use the pixel circuit without the first control circuit 12, the driving current difference of the odd and even rows of sub-pixels will reach 2.5% (the driving current difference of the odd and even rows of sub-pixels in general specifications is required to be less than 2%). It should be noted that Fig. 9 The horizontal axis is time and the vertical axis is current.

[0152] like Figure 2 , Figure 3 and Figure 8 As shown, in some embodiments, the pixel circuit further includes:

[0153] The first initialization circuit 14 is respectively coupled to the initialization control line R1, the first initialization voltage line Vinit1 and the control end of the driving circuit 11, and is used to control the connection between the first initialization voltage line Vinit1 and the control end of the driving circuit 11 under the control of the initialization control signal provided by the initialization control line R1.

[0154] The display cycle also includes an initialization phase; the driving method includes:

[0155] In the initialization stage, the first initialization circuit 14 in the pixel circuit controls the connection between the first initialization voltage line Vinit1 and the control end of the driving circuit 11 under the control of the initialization control signal, so as to initialize the control end of the driving circuit 11 .

[0156] like Figures 5 to 7 As shown, in some embodiments, the pixel circuit further includes:

[0157] The first initialization circuit 14 is coupled to the initialization control line R1, the first initialization voltage line Vinit1 and the connection node N0 respectively, and is used to control the connection between the first initialization voltage line Vinit1 and the connection node N0 under the control of the initialization control signal provided by the initialization control line R1.

[0158] The display cycle also includes an initialization phase; the driving method includes:

[0159] In the initialization stage, the first initialization circuit 14 controls the connection between the first initialization voltage line Vinit1 and the connection node N0 under the control of the initialization control signal, and the first control circuit 12 controls the connection between the control end of the drive circuit 11 and the connection node N0 under the control of the first scanning signal, so as to realize the initialization of the control end of the drive circuit 11.

[0160] The two connection modes of the first initialization circuit 14 and the corresponding specific driving methods can both realize the initialization of the control end of the driving circuit 11 .

[0161] like Figures 2 to 8 As shown, in some embodiments, the pixel circuit further includes:

[0162] The reset circuit 20 is respectively coupled to the third scan line S3, the reset voltage line DR and the second end of the drive circuit 11, and is used to control the connection between the reset voltage line DR and the second end of the drive circuit 11 under the control of the third scan signal provided by the third scan line S3.

[0163] In some embodiments, the pixel circuit further comprises:

[0164] A reset circuit is coupled to the third scan line, the reset voltage line and the first end of the drive circuit respectively, and is used to control the connection between the reset voltage line and the first end of the drive circuit under the control of a third scan signal provided by the third scan line.

[0165] Exemplarily, the reset voltage line DR is used to provide a reset voltage.

[0166] Exemplarily, the data signal is used for normal display. The reset voltage can change with the data signal, and in the bias compensation stage P2, a bias with a sign opposite to that in the light emitting stage P4 is applied to the driving transistor included in the driving circuit 11, for example: the bias voltage Vgs (or Vgd) of the driving transistor in the light emitting stage P4 is 5V, and in the compensation stage, the bias voltage of the driving transistor is -5V through the reset voltage line DR.

[0167] Exemplarily, when the third scan signal is at an effective level, the reset circuit 20 is used to, under the control of the third scan signal, conduct the electrical connection between the reset voltage line DR and the second end of the drive circuit 11 or the first end of the drive circuit 11. When the third scan signal is at an ineffective level, the reset circuit 20 is used to, under the control of the third scan signal, disconnect the electrical connection between the reset voltage line DR and the second end of the drive circuit 11 or the first end of the drive circuit 11.

[0168] Exemplarily, a display cycle of the pixel circuit includes: a writing compensation phase P3 and a bias compensation phase P2.

[0169] In the write compensation phase P3 , the data write circuit 41 controls the data line D1 to be connected to the second end of the drive circuit 11 under the control of the first scan signal, and writes a data signal to the second end of the drive circuit 11 .

[0170] In the bias compensation stage P2, the reset circuit 20 controls the reset voltage line DR to be connected to the second end of the drive circuit 11 under the control of the third scanning signal; or, the reset circuit 20 controls the reset voltage line DR to be connected to the first end of the drive circuit 11 under the control of the third scanning signal, so as to write the reset voltage to the first end or the second end of the drive circuit 11.

[0171] In the pixel circuit provided in the above embodiment, by setting the reset circuit 20, a bias with a sign opposite to that in the light-emitting stage P4 can be applied to the driving circuit 11 in the bias compensation stage P2, thereby compensating for the characteristic deviation of the driving circuit 11 after working at a certain bias for a period of time, improving the undesirable problems such as short-term afterimage and slow response time. Moreover, when driving at a low frequency, the different brightness caused by the characteristic deviation of the driving circuit 11 in the long light-emitting stage can be compensated, and the Flicker phenomenon can be improved.

[0172] In addition, when the pixel circuit provided in the above embodiment is applied to a display substrate, it is possible to perform specific bias compensation on the driving circuit 11 in each pixel circuit in the display substrate, and a good compensation effect is achieved.

[0173] In addition, since the reset voltage provided by the reset voltage line DR can be adjusted independently, a suitable bias voltage can be provided to each pixel circuit in the display substrate as required.

[0174] In the pixel circuit provided in the above embodiment, since the first control circuit 12 is added, at time tb, even if the second scanning signal is at a valid level, it will not affect the potential of the N1 node. Therefore, the tc moment can be moved back and the length between the ta moment and the tc moment can be increased to increase the time for applying bias stress to the driving circuit, which is beneficial to further improve the phenomenon such as afterimage caused by hysteresis.

[0175] like Figures 2 to 8 , Fig.14 and Fig. 22 As shown, in some embodiments, the pixel circuit further includes: a light emitting control circuit 31, a storage circuit 42 and a light emitting element O1;

[0176] The light emitting control circuit 31 is respectively coupled to the light emitting control line E1, the first end of the driving circuit 11 and the light emitting element O1, and is used to control the connection between the first end of the driving circuit 11 and the light emitting element O1 under the control of the light emitting control signal provided by the light emitting control line E1;

[0177] The light emitting control circuit 31 is also coupled to the first voltage line 80 and the second end of the driving circuit 11, and is used to control the first voltage line 80 to be connected to the second end of the driving circuit 11 under the control of the light emitting control signal;

[0178] The energy storage circuit 42 is coupled to the control terminal of the driving circuit 11 and the first voltage line 80 respectively.

[0179] Exemplarily, each display cycle of the pixel circuit includes: an initialization phase P1, a bias compensation phase P2, a writing compensation phase P3 and a light emitting phase P4.

[0180] In more detail, after the write compensation stage P3, the gate potential of the driving transistor becomes Vdata+Vth, where Vdata is the data voltage corresponding to the data signal and Vth is the threshold voltage of the driving transistor. After entering the light-emitting stage P4, the voltage Vgs1 received by the driving transistor is Vdata+Vth-VDD, where VDD is the power supply voltage received by the driving transistor and is provided by the first voltage line.

[0181] In the bias compensation phase P2, the reset circuit 20 writes a reset voltage V1 to the first terminal or the second terminal of the driving circuit 11. The reset voltage causes the bias voltage of the driving transistor to be Vgs2, and Vgs2 satisfies: Vgs2 = -Vgs1.

[0182] That is: Vgs2=Vdata+Vth-V1=-Vgs1=-(Vdata+Vth-VDD)

[0183] It should be noted that when entering the bias compensation phase P2, the gate voltage Vg of the driving transistor remains unchanged.

[0184] V1=2*(Vdata+Vth)-VDD

[0185] Since VDD is a fixed value, Vth can be obtained through testing, so the value relationship between V1 and Vdata can be obtained. Setting V1 according to the above relationship can achieve the best compensation effect.

[0186] In the bias compensation stage P2, the driving transistor is subjected to a bias with the same magnitude and opposite direction as that in the light emitting stage P4, so that bias compensation can be achieved.

[0187] like Figures 2 to 8 As shown, in some embodiments, the pixel circuit further includes: a second initialization circuit 32 and a light emitting element O1;

[0188] The second initialization circuit 32 is coupled to the third scan line S3, the second initialization voltage line Vinit2 and the light emitting element O1 respectively, and is used to control the connection between the second initialization voltage line Vinit2 and the light emitting element O1 under the control of the third scan signal provided by the third scan line S3.

[0189] Exemplarily, the second initialization voltage line Vinit2 is used to provide a second initialization voltage Vi2.

[0190] The second initialization circuit 32 can reset the first electrode of the light emitting element O1 under the control of the third scanning signal.

[0191] It should be noted that the first electrode of the light emitting element O1 includes an anode, and the second electrode (ie, cathode) of the light emitting element O1 receives a negative power signal VSS.

[0192] In some embodiments, the pixel circuit further includes a first initialization circuit 14 , wherein the first initialization circuit 14 is coupled to a first initialization voltage line Vinit1 , and the first initialization voltage line Vinit1 is multiplexed as the reset voltage line DR.

[0193] Exemplarily, the reset circuit 20 is coupled to the first initialization voltage line Vinit1. The first initialization voltage Vi1 provided by the first initialization voltage line Vinit1 is adjustable.

[0194] Exemplarily, the first initialization voltage Vi1 provided by the first initialization voltage line Vinit1 is variable. Exemplarily, when the first initialization voltage Vi1 is used to initialize the gate of the driving transistor, it can be set to -5V, and when the first initialization voltage Vi1 is used for bias compensation, it can be set to 5V.

[0195] Setting the first initialization voltage line Vinit1 to be multiplexed as the reset voltage line DR can simplify the sub-pixel structure, reduce the difficulty of sub-pixel layout, and improve the resolution of the display substrate.

[0196] like Figures 2 to 8 As shown, in some embodiments, the compensation control circuit 13 includes a first transistor T1, the driving circuit 11 includes a third transistor T3 (ie, a driving transistor), the data writing circuit 41 includes a fourth transistor T4, and the first control circuit 12 includes a ninth transistor T9;

[0197] The gate of the first transistor T1 is coupled to the second scan line S2, the first electrode of the first transistor T1 is coupled to the second electrode of the third transistor T3, and the second electrode of the first transistor T1 is coupled to the connection node N0;

[0198] A gate of the fourth transistor T4 is coupled to the first scan line S1, a first electrode of the fourth transistor T4 is coupled to the data line D1, and a second electrode of the fourth transistor T4 is coupled to a first electrode of the third transistor T3;

[0199] A gate of the ninth transistor T9 is coupled to the first scan line S1 , a first electrode of the ninth transistor T9 is coupled to the connection node N0 , and a second electrode of the ninth transistor T9 is coupled to the gate of the third transistor T3 .

[0200] In some embodiments, the first initialization circuit 14 includes a second transistor T2, a gate of the second transistor T2 is coupled to the initialization control line R1, a first electrode of the second transistor T2 is coupled to the first initialization voltage line Vinit1, and a second electrode of the second transistor T2 is coupled to the control end of the driving circuit 11.

[0201] In some embodiments, the first initialization circuit 14 includes a second transistor T2, a gate of the second transistor T2 is coupled to the initialization control line R1, a first electrode of the second transistor T2 is coupled to the first initialization voltage line Vinit1, and a second electrode of the second transistor T2 is coupled to the connection node N0.

[0202] In some embodiments, the reset circuit 20 includes an eighth transistor T8;

[0203] A gate of the eighth transistor T8 is coupled to the third scan line S3 , a first electrode of the eighth transistor T8 is coupled to the reset voltage line DR, and a second electrode of the eighth transistor T8 is coupled to the second end of the driving circuit 11 .

[0204] In some embodiments, the reset circuit 20 includes an eighth transistor T8;

[0205] A gate of the eighth transistor T8 is coupled to the third scan line S3 , a first electrode of the eighth transistor T8 is coupled to the reset voltage line DR, and a second electrode of the eighth transistor T8 is coupled to a first end of the driving circuit 11 .

[0206] In some embodiments, the light emitting control circuit 31 includes a fifth transistor T5 and a sixth transistor T6;

[0207] The gate of the fifth transistor T5 is coupled to the light emitting control line E1, the first electrode of the fifth transistor T5 is coupled to the first voltage line 80, and the second electrode of the fifth transistor T5 is coupled to the second end of the driving circuit 11;

[0208] A gate of the sixth transistor T6 is coupled to the light emitting control line E1 , a first electrode of the sixth transistor T6 is coupled to one end of the driving circuit 11 , and a second electrode of the sixth transistor T6 is coupled to the light emitting element O1 .

[0209] In some embodiments, the second initialization circuit 32 includes a seventh transistor T7,

[0210] A gate of the seventh transistor T7 is coupled to the third scan line S3 , a first electrode of the seventh transistor T7 is coupled to the second initialization voltage line Vinit2 , and a second electrode of the seventh transistor T7 is coupled to the light emitting element O1 .

[0211] In some embodiments, the first transistor T1 and the second transistor T2 are oxide thin film transistors.

[0212] By setting the first transistor T1 and the second transistor T2 as oxide thin film transistors, it is beneficial to reduce the gate leakage of the driving transistor and ensure the stability of the gate potential of the driving transistor.

[0213] Exemplarily, in at least one embodiment of the pixel circuit, T1 and T2 may be oxide thin film transistors, T3, T4, T5, T6, T7, T8 and T9 may all be low-temperature polysilicon thin film transistors, T1 and T2 are n-type transistors, T3, T4, T5, T6, T7, T8 and T9 are p-type transistors, but are not limited thereto.

[0214] Exemplarily, T1 and T2 may be single-gate transistors or double-gate transistors.

[0215] Exemplarily, in the channel width-to-length ratio W / L of T1, the value range of W is between 2 microns and 4 microns, including the endpoint values, and the value range of L is between 3 microns and 6 microns, including the endpoint values.

[0216] Exemplarily, the channel width-to-length ratio of T2 is the same as that of T1.

[0217] Exemplarily, in the channel width-to-length ratio W / L of T8, the value range of W is between 2 microns and 3 microns, including the endpoint values, and the value range of L is between 3.2 microns and 6 microns, including the endpoint values.

[0218] In some embodiments, the compensation control circuit 13 includes a first transistor T1, the first initialization circuit 14 includes a second transistor T2, the driving circuit 11 includes a third transistor T3 (ie, the driving transistor), and the light emitting control circuit 31 includes a fifth transistor T5 and a sixth transistor T6;

[0219] The gate of the first transistor T1 is coupled to the second scan line S2, the first electrode of the first transistor T1 is coupled to the second electrode of the third transistor T3, and the second electrode of the first transistor T1 is coupled to the gate T3-g of the third transistor T3;

[0220] The gate of the second transistor T2 is coupled to the initialization control line R1, the first electrode of the second transistor T2 is coupled to the first initialization voltage line Vinit1, and the second electrode of the second transistor T2 is coupled to the gate T3-g of the third transistor T3;

[0221] The gate of the fifth transistor T5 is coupled to the light emitting control line E1, the first electrode of the fifth transistor T5 is coupled to the first voltage line, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the third transistor T3;

[0222] A gate of the sixth transistor T6 is coupled to the light emitting control line E1 , a first electrode of the sixth transistor T6 is coupled to a second electrode of the third transistor T3 , and a second electrode of the sixth transistor T6 is coupled to the light emitting element O1 .

[0223] In some embodiments, a gate of the seventh transistor T7 is coupled to the third scan line S3 , a first electrode of the seventh transistor T7 is coupled to the second initialization voltage line Vinit2 , and a second electrode of the seventh transistor T7 is coupled to the light emitting element O1 .

[0224] In some embodiments, a gate of the fourth transistor T4 is coupled to the first scan line S1, a first electrode of the fourth transistor T4 is coupled to the data line D1, and a second electrode of the fourth transistor T4 is coupled to a first electrode of the third transistor T3;

[0225] A gate T8 - g of the eighth transistor T8 is coupled to the third scan line S3 , a first electrode of the eighth transistor T8 is coupled to the reset voltage line DR, and a second electrode of the eighth transistor T8 is coupled to the first electrode or the second electrode of the third transistor T3 .

[0226] In some embodiments, the gate of the ninth transistor T9 is coupled to the first scan line S1, the first electrode of the ninth transistor T9 is coupled to the connection node N0, and the second electrode of the ninth transistor T9 is coupled to the gate T3-g of the third transistor T3.

[0227] The specific driving process of the pixel circuit of the above structure includes:

[0228] In the initialization phase P1, R1 provides a high voltage signal, T2 is turned on. S1 provides a high voltage signal, T4 and T9 are turned off. S2 provides a low voltage signal, T1 is turned off. S3 provides a high voltage signal, T7 and T8 are turned off. In the initialization phase P1, the gate of T3 is initialized so that T3 can be turned on when the write compensation phase P3 starts.

[0229] In the bias compensation period P2, R1 provides a low voltage signal, and T2 is turned off. S1 provides a high voltage signal, and T4 and T9 are turned off. S2 provides a low voltage signal, and T1 is turned off. S3 provides a low voltage signal, and T7 and T8 are turned on. In the bias compensation period P2, the reset voltage provided by DR can be written into the first electrode or the second electrode of the third transistor T3, and the second initialization voltage can be written into the anode of O1, so that O1 does not emit light, and the residual charge of the anode of O1 is cleared.

[0230] In the write compensation phase P3, T3 is turned on. R1 provides a low voltage signal, and T2 is turned off. S1 provides a low voltage signal, and T4 and T9 are turned on. S2 provides a high voltage signal, and T1 is turned on. S3 provides a high voltage signal, and T7 and T8 are turned off. The data voltage Vdata on the data line D1 is written into the first electrode of the third transistor T3. In the write compensation phase P3, C is charged through Vdata through the turned-on T4, T3, T1 and T9 to increase the potential of the gate of T3 until T3 is turned off, at which time the potential of the gate of T3 is Vdata+Vth.

[0231] In the light-emitting stage P4, E1 provides a low voltage signal, R1 provides a low voltage signal, S1 provides a high voltage signal, S2 provides a low voltage signal, S3 provides a high voltage signal, T1, T2, T4, T9, T7 and T8 are turned off, T5 and T6 are turned on, and T3 is turned on to drive O1 to emit light.

[0232] By adding T8, a bias voltage is provided to the first or second electrode of T3, which is beneficial to improving the stability of T3; by setting T7, the potential of the anode of O1 is initialized, which is beneficial to the freedom of switching frequency under low-frequency flicker.

[0233] In some embodiments, the pixel circuit needs to turn on T3 during the threshold compensation stage. Therefore, the voltage difference Vi1-V1 between the first initialization voltage Vi1 provided by the first initialization voltage line Vinit1 and the reset voltage V1 provided by the reset voltage line DR needs to be less than the threshold voltage Vth of the driving transistor T3. Wherein, Vi1 can be -2 to -6V, for example, -2V, -3V, -4V, -5V, -6V, etc. Vi1-V1 can be less than a*Vth, a can be 2 to 7, for example, a can be 2, 4, 6, 7; Vth can be -2 to -5V, for example, -2V, -3V, -5V, etc. V1 can be greater than 1.5 times Vth, for example, V1 can be 1.6 times, 1.8 times, 2 times, etc. of Vth.

[0234] Exemplarily, V1 is greater than 0. The value of V1 is between 4V and 10V, including the endpoint value.

[0235] In some embodiments, the width-to-length ratio W / L of T8 may be approximately equal to the width-to-length ratio W / L of T7; for another example, the width-to-length ratio W / L of T8 may be greater than the width-to-length ratio W / L of T7, that is, the width-to-length ratio W / L of T8 may be slightly larger, so that the N2 node can be quickly reset.

[0236] In some embodiments, the channel width W of T8 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of T7 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0237] In some embodiments, the width-to-length ratio W / L of T8 may be substantially equal to the width-to-length ratio W / L of T2; for another example, the width-to-length ratio W / L of T8 may be smaller than the width-to-length ratio W / L of T2, so that the reset capabilities of the N1 node and the N2 node can be balanced.

[0238] In some embodiments, the channel width W of T8 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of T2 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0239] The embodiment of the present invention further provides a driving method, which is applied to the pixel circuit provided in the above embodiment, wherein the display cycle includes a writing compensation phase P3, and the writing compensation phase P3 includes: a writing control phase P32 and a non-writing control phase P31; the driving method includes:

[0240] During the entire write compensation phase P3, the compensation control circuit 13 controls the first end of the driving circuit 11 to be connected to the connection node N0 under the control of the second scanning signal;

[0241] In the non-writing control phase P31, the data writing circuit 41 controls the data line D1 to be disconnected from the second end of the driving circuit 11 under the control of the first scanning signal; the first control circuit 12 controls the control end of the driving circuit 11 to be disconnected from the connection node N0 under the control of the first scanning signal;

[0242] In the write control stage P32, the data write circuit 41 controls the data line D1 to be connected to the second end of the drive circuit 11 under the control of the first scan signal; the first control circuit 12 controls the control end of the drive circuit 11 to be connected to the connection node N0 under the control of the first scan signal.

[0243] When the driving method provided by the embodiment of the present invention is used to drive the above-mentioned pixel circuit, the following beneficial effects are achieved by connecting the first control circuit 12 between the N1 node and the compensation control circuit 13, and the first control circuit 12 and the data writing circuit 41 are both controlled by the first scanning signal.

[0244] Effect 1: At time tb, the second scanning signal written into the second scanning line S2 changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit 12 controls to disconnect the electrical connection between the N1 node and the connection node N0, the voltages of the N2 node and the N3 node will no longer flow to the N1 node, so that when the data signal is written at time tc, the potential of the N1 node is still maintained at the low voltage of Vi1, ensuring that the data signal is fully written.

[0245] Effect 2: At the end of the writing compensation phase P3, the second scanning signal written by the second scanning line S2 changes from a high level to a low level. By adding the first control circuit 12, at the end of the writing compensation phase P3, the first scanning signal written by the first scanning line S1 changes from a low level to a high level, so that at the end of the writing compensation phase P3, the N1 node is pulled upward, which is conducive to reducing the data voltage required when displaying a black screen.

[0246] Effect 3: When one GOA (S2) provides the second scanning signal to the second scanning line S2 corresponding to two rows of sub-pixels at the same time. At time tb, the second scanning signal written to the second scanning line S2 changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit 12 controls the disconnection of the electrical connection between the N1 node and the connection node N0, no discharge is made to the N1 node between time tb and time tc, thereby ensuring that the initial voltage of the N1 node before the data signal is written is the same.

[0247] Moreover, between time tb and time tc, since the first control circuit 12 controls the disconnection of the electrical connection between the N1 node and the connection node N0, it ensures that the voltage is given to the N1 nodes in the two rows of sub-pixels at the same time. Therefore, even in the case of row-by-row scanning, the initial voltage of the N1 nodes in the two rows of sub-pixels before the data signal is written is the same.

[0248] Therefore, when the two rows of sub-pixels include odd-numbered rows of sub-pixels and even-numbered rows of sub-pixels, there will be no difference in display brightness between the odd-numbered rows of sub-pixels and the even-numbered rows of sub-pixels.

[0249] In some embodiments, the end time of the write compensation phase P3 is the same as the end time of the write control phase P2.

[0250] Since the first control circuit 12 is added, at time tb, even if the second scanning signal is at a valid level, it will not affect the potential of the N1 node. Therefore, time tc can be moved back, that is, the end time of the write compensation stage P3 is the same as the end time of the write control stage P2, and the length between time ta and time Tc is increased to increase the time for applying bias stress to the driving circuit, which is beneficial to further improve the phenomenon of afterimage caused by hysteresis.

[0251] Exemplarily, the time of the back shift is between 0.2 microseconds and 0.5 microseconds, including endpoint values.

[0252] In some embodiments, the display cycle further includes an initialization phase; and the driving method further includes:

[0253] The first initialization circuit 14 is coupled to the initialization control line R1, the first initialization voltage line Vinit1 and the control end of the driving circuit 11 respectively, and is used to control the first initialization voltage line Vinit1 and the control end of the driving circuit 11 to be connected under the control of the initialization control signal provided by the initialization control line R1. In the initialization stage, the first initialization circuit 14 in the pixel circuit controls the first initialization voltage line Vinit1 and the control end of the driving circuit 11 to be connected under the control of the initialization control signal;

[0254] Alternatively, the first initialization circuit 14 is coupled to the initialization control line R1, the first initialization voltage line Vinit1 and the connection node N0, respectively, and is used to control the connection between the first initialization voltage line Vinit1 and the connection node N0 under the control of the initialization control signal provided by the initialization control line R1. In the initialization stage, the first initialization circuit 14 controls the connection between the first initialization voltage line Vinit1 and the connection node N0 under the control of the initialization control signal, and the first control circuit 12 controls the connection between the control end of the driving circuit 11 and the connection node N0 under the control of the first scanning signal.

[0255] The two connection modes of the first initialization circuit 14 and the corresponding specific driving methods can both realize the initialization of the control end of the driving circuit 11 .

[0256] In some embodiments, the display cycle further includes a bias compensation phase and a light emitting phase, and the driving method includes:

[0257] In the bias compensation stage, the reset circuit 20 controls the reset voltage line DR to be connected to the second end of the drive circuit 11 under the control of the third scan signal; or, the reset circuit 20 controls the reset voltage line DR to be connected to the first end of the drive circuit 11 under the control of the third scan signal;

[0258] In the light-emitting stage, the light-emitting control circuit 31 in the pixel circuit controls the connection between the first voltage line 80 and the second end of the driving circuit 11, and controls the connection between the first end of the driving circuit 11 and the light-emitting element O1 under the control of the light-emitting control signal, and the driving circuit 11 drives the light-emitting element O1 to emit light.

[0259] When the driving method provided by the embodiment of the present invention is used to drive the above-mentioned pixel circuit, a bias with a sign opposite to that of the light-emitting stage P4 can be applied to the driving circuit 11 in the bias compensation stage P2, thereby compensating for the characteristic deviation of the driving circuit 11 after working at a certain bias for a period of time, and improving the undesirable problems such as short-term residual image and slow response time. Moreover, when driving at a low frequency, the different brightness caused by the characteristic deviation of the driving circuit 11 in the long light-emitting stage can be compensated, and the Flicker phenomenon can be improved. In addition, it is possible to achieve specific bias compensation for the driving circuit 11 in each pixel circuit in the display substrate, with a good compensation effect. In addition, since the reset voltage provided by the reset voltage line DR can be adjusted independently, a suitable bias can be provided to each pixel circuit in the display substrate as needed.

[0260] In more detail, in the initialization stage P1, the first initialization circuit 14 controls the first initialization voltage line Vinit1 to be connected to the control end of the drive circuit 11, and initializes the control end of the drive circuit 11. In the bias compensation stage P2, the reset circuit 20 controls the reset voltage line DR to be connected to the second end of the drive circuit 11, or controls the reset voltage line DR to be connected to the first end of the drive circuit 11. In the light-emitting stage P4, the light-emitting control circuit 31 controls the first voltage line to be connected to the second end of the drive circuit 11, and controls the first end of the drive circuit 11 to be connected to the light-emitting element O1, and the drive circuit 11 drives the light-emitting element O1 to emit light.

[0261] like Figures 3 to 8 , Figures 14 to 35 As shown, an embodiment of the present invention further provides a display substrate, comprising a substrate and a plurality of sub-pixels arranged on the substrate, wherein the sub-pixels include the pixel circuit provided in the above embodiment; the sub-pixels further include:

[0262] A data line D1, a first scan line S1 and a second scan line S2; the data line D1 includes at least a portion extending along a first direction, the first scan line S1 includes at least a portion extending along a second direction, the third scan line S3 includes at least a portion extending along the second direction, and the second direction intersects the first direction;

[0263] The data writing circuit 41 is coupled to the first scan line S1, the data line D1 and the second end of the driving circuit 11 respectively, and is used to control the data line D1 to be connected to the second end of the driving circuit 11 under the control of the first scan signal provided by the first scan line S1;

[0264] The compensation control circuit 13 is coupled to the second scan line S2, the first end of the drive circuit 11 and the connection node N0 respectively, and is used to control the first end of the drive circuit 11 to be connected to the connection node N0 under the control of the second scan signal provided by the second scan line S2;

[0265] The first control circuit 12 is coupled to the first scan line S1 , the control end of the drive circuit 11 and the connection node N0 respectively, and is used to control the connection between the control end of the drive circuit 11 and the connection node N0 under the control of the first scan signal.

[0266] Exemplarily, the display substrate includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes a pixel circuit.

[0267] Exemplarily, in the sub-pixels located in the same column along the first direction, the data lines D1 are coupled in sequence to form an integrated structure.

[0268] Exemplarily, in the sub-pixels in the same row along the second direction, the first scan lines S1 are sequentially coupled to form an integrated structure. Exemplarily, in the sub-pixels in the same row along the second direction, the second scan lines S2 are sequentially coupled to form an integrated structure.

[0269] Exemplarily, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0270] Exemplarily, the display substrate includes: a light-shielding layer, an isolation layer, a first buffer layer, a poly active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a second buffer layer, an oxide active layer (such as IGZO), a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source-drain metal layer, a passivation layer, a first planarizing layer, a second source-drain metal layer, a second planarizing layer, an anode layer, a pixel defining layer, a spacer layer, a light-emitting functional layer, a cathode layer and an encapsulation layer, which are stacked on the substrate in a direction away from the substrate.

[0271] Exemplarily, the data line D1 is made of the second source-drain metal layer, and the first scan line S1 is made of the first gate metal layer.

[0272] Exemplarily, the second scanning line S2 includes a first scanning sub-graph S21 and a third scanning sub-graph S22, and at least a portion of the first scanning sub-graph S21 and at least a portion of the third scanning sub-graph S22 both extend along the second direction. The compensation control circuit 13 includes a first transistor T1, and the first transistor T1 includes a first oxide active layer (such as the first active layer 51); in a direction perpendicular to the substrate, at least a portion of the first oxide active layer is located between the first scanning sub-graph S21 and the third scanning sub-graph S22.

[0273] Exemplarily, the first scanning sub-pattern S21 is made of the second gate metal layer, and the third scanning sub-pattern S22 is made of the third gate metal layer. At least a portion of the first scanning sub-pattern S21 is located between the substrate and the third scanning sub-pattern S22.

[0274] Exemplarily, the data write circuit 41 includes a fourth transistor T4, the fourth transistor T4 includes a fourth active layer, the orthographic projection of the fourth active layer on the substrate at least partially overlaps with the orthographic projection of the data line D1 on the substrate, and the orthographic projection of the fourth active layer on the substrate and the orthographic projection of the first oxide active layer on the substrate are arranged along the second direction.

[0275] In the pixel circuit provided in the above embodiment, by connecting the first control circuit 12 between the N1 node and the compensation control circuit 13, and both the first control circuit 12 and the data writing circuit 41 are controlled by the first scanning signal, the following beneficial effects are achieved.

[0276] Effect 1: At time tb, the second scanning signal written into the second scanning line S2 changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit 12 controls to disconnect the electrical connection between the N1 node and the connection node N0, the voltages of the N2 node and the N3 node will no longer flow to the N1 node, so that when the data signal is written at time tc, the potential of the N1 node is still maintained at the low voltage of Vi1, ensuring that the data signal is fully written.

[0277] Effect 2: At the end of the writing compensation phase P3, the second scanning signal written by the second scanning line S2 changes from a high level to a low level. By adding the first control circuit 12, at the end of the writing compensation phase P3, the first scanning signal written by the first scanning line S1 changes from a low level to a high level, so that at the end of the writing compensation phase P3, the N1 node is pulled upward, which is conducive to reducing the data voltage required when displaying a black screen.

[0278] Effect 3: When one GOA (S2) provides the second scanning signal to the second scanning line S2 corresponding to two rows of sub-pixels at the same time. At time tb, the second scanning signal written to the second scanning line S2 changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit 12 controls the disconnection of the electrical connection between the N1 node and the connection node N0, no discharge is made to the N1 node between time tb and time tc, thereby ensuring that the initial voltage of the N1 node before the data signal is written is the same.

[0279] Moreover, between time tb and time tc, since the first control circuit 12 controls the disconnection of the electrical connection between the N1 node and the connection node N0, it ensures that the voltage is given to the N1 nodes in the two rows of sub-pixels at the same time. Therefore, even in the case of row-by-row scanning, the initial voltage of the N1 nodes in the two rows of sub-pixels before the data signal is written is the same.

[0280] Therefore, when the two rows of sub-pixels include odd-numbered rows of sub-pixels and even-numbered rows of sub-pixels, there will be no difference in display brightness between the odd-numbered rows of sub-pixels and the even-numbered rows of sub-pixels.

[0281] Therefore, the display substrate provided by the embodiment of the present invention also has the above-mentioned beneficial effects when including the above-mentioned pixel circuit, which will not be described in detail here.

[0282] like Figures 3 to 8 , Figures 14 to 35 As shown, in some embodiments, the first control circuit 12 includes a ninth transistor T9, the ninth transistor T9 includes a ninth active layer 59, and the ninth active layer 59 includes at least a portion extending along the first direction;

[0283] The driving circuit 11 comprises a third transistor T3, and the orthographic projection of the gate of the third transistor T3 on the substrate and the orthographic projection of the ninth active layer 59 on the substrate are arranged along the first direction;

[0284] The sub-pixel further includes a first connection pattern 71 , through which the second electrode of the ninth transistor T9 is coupled to the gate of the third transistor T3 .

[0285] Exemplarily, the ninth active layer 59 is made of a poly active layer.

[0286] Exemplarily, the orthographic projection of the ninth active layer 59 on the substrate at least partially overlaps with the orthographic projection of the second scan line S2 on the substrate.

[0287] Exemplarily, at least a portion of the orthographic projection of the ninth active layer 59 on the substrate is located between the orthographic projection of the data line D1 on the substrate and the orthographic projection of the first active layer on the substrate.

[0288] Exemplarily, the orthographic projection of the ninth active layer 59 on the substrate does not overlap with the orthographic projection of the initialization control line R1 on the substrate.

[0289] Exemplarily, the orthographic projection of the ninth active layer 59 on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the initialization control line R1 on the substrate.

[0290] Exemplarily, the first connection pattern 71 is made of a first source-drain metal layer.

[0291] Exemplarily, the first connection pattern 71 includes a portion extending along the first direction and a portion extending along a third direction, and the third direction intersects both the first direction and the second direction.

[0292] Exemplarily, the first connection pattern 71 is coupled to the second electrode of the ninth transistor T9 through a via hole, and the first connection pattern 71 is coupled to the gate of the third transistor T3 through a via hole.

[0293] Exemplarily, the orthographic projection of the first connection pattern 71 on the substrate does not overlap with the orthographic projection of the second scanning line S2 on the substrate.

[0294] The above configuration is conducive to reducing the difficulty of layout of the sub-pixel and reducing the parasitic capacitance generated by the ninth transistor T9.

[0295] like Figures 14 to 25 As shown, in some embodiments, the first initialization circuit 14 in the pixel circuit includes a second transistor T2, the second transistor T2 includes a second active layer, the second active layer includes at least a portion extending along the first direction; the orthographic projection of a portion of the second active layer on the substrate and the orthographic projection of a portion of the ninth active layer on the substrate are arranged along the second direction;

[0296] The sub-pixel further includes a second connection pattern 72 , which includes a portion extending along the first direction and a portion extending along the second direction; the second electrode of the second transistor T2 is coupled to the first connection pattern 71 through the second connection pattern 72 .

[0297] Exemplarily, the sub-pixel further includes an initialization control line R1, the initialization control line R1 includes a first initialization sub-graph R11 and a second initialization sub-graph R12, at least a portion of the first initialization sub-graph R11 and at least a portion of the second initialization sub-graph R12 both extend along the second direction;

[0298] Exemplarily, the first initialization sub-pattern R11 is made of the second gate metal layer, and the second initialization sub-pattern R12 is made of the third gate metal layer. At least a portion of the first initialization sub-pattern R11 is located between the substrate and the second initialization sub-pattern R12.

[0299] Exemplarily, the first initialization circuit 14 includes a second transistor T2, and the second active layer 52 includes a second oxide active layer; in a direction perpendicular to the substrate, at least a portion of the second oxide active layer is located between the first initialization sub-graph R11 and the second initialization sub-graph R12.

[0300] Exemplarily, the first oxide active layer and the second oxide active layer are arranged along the first direction; the first oxide active layer and the second oxide active layer form an integrated structure.

[0301] Exemplarily, the first oxide active layer and the second oxide active layer are staggered along the second direction.

[0302] Exemplarily, an orthographic projection of a portion of the second active layer on the substrate and an orthographic projection of a portion of the ninth active layer on the substrate are arranged along the second direction.

[0303] Exemplarily, the second connection pattern 72 is made of a first source-drain metal layer.

[0304] Exemplarily, an orthographic projection of the second connection pattern 72 on the substrate at least partially overlaps with an orthographic projection of the second scan line S2 on the substrate.

[0305] Exemplarily, the orthographic projection of the second connection pattern 72 on the substrate at least partially overlaps with the orthographic projection of the first scanning sub-pattern S21 on the substrate. The orthographic projection of the second connection pattern 72 on the substrate at least partially overlaps with the orthographic projection of the third scanning sub-pattern S22 on the substrate.

[0306] Exemplarily, the second connection pattern 72 and the first connection pattern 71 form an integral structure.

[0307] Illustratively, an orthographic projection of the second connection pattern 72 on the substrate at least partially overlaps with an orthographic projection of the first active layer 51 on the substrate.

[0308] Exemplarily, the second connection pattern 72 is coupled to the second electrode of the second transistor T2 through a via.

[0309] The above configuration is conducive to reducing the difficulty of layout of the sub-pixel. The above configuration enables the second transistor to directly initialize the gate of the third transistor, and the driving method is simple.

[0310] like Figure 26 to Figure 31 As shown, in some embodiments, the first initialization circuit 14 in the pixel circuit includes a second transistor T2, the second transistor T2 includes a second active layer, the second active layer includes at least a portion extending along the first direction; the orthographic projection of a portion of the second active layer on the substrate and the orthographic projection of a portion of the ninth active layer on the substrate are arranged along the second direction;

[0311] The sub-pixel further includes a third connection pattern 73 , and the third connection pattern 73 includes at least a portion extending along the second direction; the second electrode of the second transistor T2 is coupled to the first electrode of the ninth transistor T9 through the third connection pattern 73 .

[0312] Exemplarily, the third connection pattern 73 is made of the first source-drain metal layer.

[0313] Exemplarily, an orthographic projection of the third connection pattern 73 on the substrate at least partially overlaps with an orthographic projection of the first scanning line S1 on the substrate.

[0314] Exemplarily, the orthographic projection of the third connection pattern 73 on the substrate does not overlap with the orthographic projection of the first scanning sub-pattern S21 on the substrate. The orthographic projection of the third connection pattern 73 on the substrate does not overlap with the orthographic projection of the third scanning sub-pattern S22 on the substrate.

[0315] Exemplarily, the third connection pattern 73 is coupled to the second electrode of the second transistor T2 through a via hole. The third connection pattern 73 is coupled to the first electrode of the ninth transistor T9 through a via hole.

[0316] Exemplarily, the orthographic projection of the third connection pattern 73 on the substrate does not overlap with the orthographic projection of the initialization control line R1 on the substrate.

[0317] Exemplarily, an orthographic projection of the third connection pattern 73 on the substrate at least partially overlaps with an orthographic projection of the initialization control line R1 on the substrate.

[0318] Exemplarily, the orthographic projection of the third connection pattern 73 on the substrate is located between the orthographic projection of the initialization control line R1 on the substrate and the orthographic projection of the second scanning line S2 on the substrate.

[0319] The above configuration is conducive to reducing the difficulty of the layout of the sub-pixel. The above configuration enables the second transistor T2 to initialize the gate T3-g of the third transistor T3 through the ninth transistor T9.

[0320] like Fig.32 and Fig.33 As shown, in some embodiments, the orthographic projection of the third connection pattern 73 on the substrate is set to at least partially overlap with the orthographic projection of the first scanning line S1 on the substrate.

[0321] Exemplarily, the third connection pattern 73 includes a portion extending along the first direction, a portion extending along the second direction, and a portion extending along a fourth direction, wherein the fourth direction intersects both the first direction and the second direction.

[0322] Exemplarily, the orthographic projection of a portion of the third connection pattern 73 on the substrate is located inside the orthographic projection of the first scan line S1 on the substrate. The orthographic projection of another portion of the third connection pattern 73 on the substrate is located inside the orthographic projection of the ninth active layer on the substrate.

[0323] The above configuration is beneficial to increasing the transmittance of the display substrate.

[0324] like Fig.34 and Fig.35 As shown, in some embodiments, setting the sub-pixel further includes an initialization control line R1, and the orthographic projection of the third connection pattern 73 on the substrate at least partially overlaps with the orthographic projection of the initialization control line R1 on the substrate.

[0325] Exemplarily, the initialization control line R1 includes a first initialization sub-pattern R11 and a second initialization sub-pattern R12.

[0326] Exemplarily, the orthographic projection of the third connection pattern 73 on the substrate at least partially overlaps with the orthographic projection of the first initialization sub-pattern R11 on the substrate. The orthographic projection of the third connection pattern 73 on the substrate at least partially overlaps with the orthographic projection of the second initialization sub-pattern R12 on the substrate.

[0327] Exemplarily, the third connection pattern 73 includes a portion extending along the first direction, a portion extending along the second direction, and a portion extending along the third direction.

[0328] The above configuration is beneficial to increasing the transmittance of the display substrate.

[0329] like Figures 14 to 34 As shown, in some embodiments, the sub-pixel further includes:

[0330] A data line D1, a reset voltage line DR, a first scan line S1 and a third scan line S3; the data line D1 includes at least a portion extending along a first direction, the first scan line S1 includes at least a portion extending along a second direction, and the third scan line S3 includes at least a portion extending along the second direction, and the second direction intersects the first direction;

[0331] The data writing circuit 41 is coupled to the first scan line S1, the data line D1 and the second end of the driving circuit 11 respectively, and is used to control the data line D1 to be connected to the second end of the driving circuit 11 under the control of the first scan signal provided by the first scan line S1;

[0332] The reset circuit 20 is coupled to the third scan line S3 and the reset voltage line DR, respectively, and is also coupled to the first end or the second end of the drive circuit 11, and is used to control the connection between the reset voltage line DR and the second end of the drive circuit 11 under the control of the third scan signal provided by the third scan line S3; or to control the connection between the reset voltage line DR and the first end of the drive circuit 11.

[0333] Exemplarily, the reset voltage line DR includes at least a portion extending along the first direction. Exemplarily, the reset voltage line DR is made of a second source-drain metal layer or a first source-drain metal layer. Exemplarily, in sub-pixels located in the same column along the first direction, the reset voltage lines DR are sequentially coupled to form an integrated structure.

[0334] Exemplarily, the reset voltage line DR includes at least a portion extending along the second direction. Exemplarily, the reset voltage line DR is made of a third gate metal layer. Exemplarily, an orthographic projection of the reset voltage line DR on the substrate overlaps at least partially with an orthographic projection of the third scan line S3 on the substrate. Exemplarily, in sub-pixels located in the same row along the second direction, the reset voltage lines DR are sequentially coupled to form an integrated structure.

[0335] Exemplarily, the reset voltage line DR includes a reference signal line.

[0336] Exemplarily, in the sub-pixels located in the same row along the second direction, the third scan lines S3 are sequentially coupled to form an integrated structure. Exemplarily, the first scan line S1 and the third scan line S3 are both made of the first gate metal layer.

[0337] Since the pixel circuit provided in the above embodiment is provided with the reset circuit 20, a bias with a sign opposite to that in the light-emitting stage P4 can be applied to the driving circuit 11 in the bias compensation stage P2, thereby compensating for the characteristic deviation of the driving circuit 11 after working at a certain bias for a period of time, thereby improving the undesirable problems such as short-term afterimage and slow response time. Moreover, when driven at a low frequency, the different brightness caused by the characteristic deviation of the driving circuit 11 in the long light-emitting stage can be compensated, and the Flicker phenomenon can be improved. Therefore, the display substrate provided in the above embodiment also has the above beneficial effects when including the above pixel circuit, which will not be repeated here.

[0338] In addition, when the display substrate provided by the above embodiment includes the above pixel circuit, it is possible to realize specific bias compensation for the driving circuit 11 in each pixel circuit in the display substrate, and has a good compensation effect. In addition, since the reset voltage provided by the reset voltage line DR can be adjusted independently, a suitable bias can be provided to each pixel circuit in the display substrate as needed.

[0339] like Fig.11 As shown, in some embodiments, the display substrate includes a plurality of pixel circuits P distributed in an array, and a plurality of reset voltage lines DR11, DR12, DR21, and DR22. The reset voltage lines DR11, DR12, DR21, and DR22 can all be used to provide a reset voltage.

[0340] like Fig.10 As shown, the reset voltage lines DR11 and DR12 extend in the column direction, the reset voltage lines DR21 and DR22 extend in the row direction, and the pixel circuits in two adjacent rows can be connected to the reset voltage line DR extending in the same row direction. The reset voltage line DR can be located between the above-mentioned two adjacent rows of pixel driving circuits 11, and the reset voltage line DR extending in the column direction can be connected to multiple reset voltage lines DR extending in the row direction that intersect with it, so that multiple reset voltage lines DR can form a grid structure. Among them, the reset voltage line DR extending in the column direction can be located in the area where the red pixel circuit is located. In addition, in the same pixel row, the two pixel circuits in adjacent columns can be mirrored to facilitate wiring.

[0341] like Figures 14 to 34 As shown, in some embodiments, the driving circuit 11 includes a third transistor T3, and the reset circuit 20 includes an eighth transistor T8;

[0342] A gate T8-g of the eighth transistor T8 is coupled to the third scan line S3, a first electrode of the eighth transistor T8 is coupled to the reset voltage line DR, and a second electrode of the eighth transistor T8 is coupled to a first electrode of the third transistor T3;

[0343] The reset voltage line DR includes at least a portion extending along the second direction; an orthographic projection of the reset voltage line DR on the substrate and an orthographic projection of the gate of the driving transistor on the substrate are arranged along the first direction.

[0344] Exemplarily, the gate T3 - g of the third transistor T3 is made of the first gate metal layer. The gate T8 - g of the eighth transistor T8 is formed as an integral structure with the third scan line S3 .

[0345] Exemplarily, the reset voltage line DR is made of a third gate metal layer.

[0346] Exemplarily, the first electrode of the eighth transistor T8 is coupled to the reset voltage line DR through a fourth connection pattern 74. Exemplarily, the fourth connection pattern 74 includes a portion extending along the second direction.

[0347] Need to explain, Fig.15 Schematically shows a third active layer 53 included in T3, a fourth active layer 54 included in T4, a fifth active layer 55 included in T5, a sixth active layer 56 included in T6, and a seventh active layer 57 included in T7. Fig.18 It illustrates a first active layer 51 included in T1 and a second active layer 52 included in T2. Fig.12 Schematically shows a second gate metal layer Gate2, a first interlayer insulating layer ILD1, a second buffer layer Buffer2, an oxide layer (IGZO), a third gate insulating layer GI3, and a third gate metal layer Gate3. Fig.13 FIG. 4 illustrates that the first electrode of the eighth transistor T8 is coupled to the reset voltage line DR through the fourth connection pattern 74 .

[0348] Need to explain, Fig. 20 The first connection hole in the first source-drain metal layer is used to connect the first source-drain metal layer and the corresponding structure thereunder. Fig. 20 The depths of the first connecting holes in the embodiment may be the same or different. Fig.21 The second connection hole in the first source-drain metal layer is used to connect the first source-drain metal layer and the corresponding structure thereunder. Fig.21 The depths of the second connecting holes in the embodiment may be the same or different.

[0349] Need to explain, Fig.26 , Fig.32 and Fig.34 In the corresponding embodiment, some single-layer film layers are not shown, see Fig.14 The corresponding single film layer is sufficient.

[0350] The above configuration method is helpful to reduce the difficulty of layout of the sub-pixels.

[0351] In some embodiments, the eighth transistor T8 includes an eighth active layer 58 , and the eighth active layer 58 includes at least a portion extending along the first direction.

[0352] Exemplarily, an orthographic projection of the eighth active layer 58 on the substrate at least partially overlaps with an orthographic projection of the reset voltage line DR on the substrate.

[0353] Exemplarily, the orthographic projection of the light emitting control line E1 on the substrate is located between the orthographic projection of the eighth active layer 58 on the substrate and the orthographic projection of the gate T3 - g of the third transistor T3 on the substrate.

[0354] Exemplarily, the second electrode of the eighth transistor T8 is coupled to the first electrode of the third transistor T3 via the first conductive connection portion 61. The orthographic projection of the first conductive connection portion 61 on the substrate at least partially overlaps with the orthographic projection of the light emitting control line E1 on the substrate.

[0355] Exemplarily, the first conductive connection portion 61 is made of the first source-drain metal layer.

[0356] Exemplarily, the orthographic projection of the first conductive connection portion 61 on the substrate partially overlaps with the orthographic projection of the data line D1 on the substrate.

[0357] Exemplarily, the orthographic projection of the first conductive connection portion 61 on the substrate does not overlap with the orthographic projection of the data line D1 on the substrate, and does not overlap with the orthographic projection of the reset voltage line DR on the substrate.

[0358] Exemplarily, the orthographic projection of the first conductive connection portion 61 on the substrate does not overlap with the orthographic projection of the second electrode plate C2 of the storage capacitor C on the substrate.

[0359] Exemplarily, the first conductive connection portion 61 is respectively coupled to the second electrode of the eighth transistor T8 and the first electrode of the third transistor T3 through corresponding vias.

[0360] The above configuration method is helpful to reduce the difficulty of layout of the sub-pixels.

[0361] In some embodiments, the second initialization circuit 32 includes a seventh transistor T7 , a gate of the seventh transistor T7 is coupled to the third scan line S3 , and a first electrode of the seventh transistor T7 is coupled to the second initialization voltage line Vinit2 .

[0362] Exemplarily, the seventh transistor T7 includes a seventh active layer, and the eighth active layer 58 is arranged along the second direction with the seventh active layer. The orthographic projection of the eighth active layer 58 on the substrate is located between the orthographic projection of the seventh active layer on the substrate and the orthographic projection of the data line D1 on the substrate.

[0363] In some embodiments, the sub-pixel further includes a light emitting control line E1, and the light emitting control line E1 includes at least a portion extending along the second direction;

[0364] The light emitting control circuit 31 includes a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is coupled to the light emitting control line E1, and the gate of the sixth transistor T6 is coupled to the light emitting control line E1;

[0365] The fifth transistor T5 includes a fifth active pattern, the sixth transistor T6 includes a sixth active pattern, and the fifth active pattern and the sixth active pattern are arranged along the second direction.

[0366] An embodiment of the present invention further provides a display device, comprising the display substrate provided by the above embodiment.

[0367] In the display substrate provided in the above embodiment, by connecting the first control circuit 12 between the N1 node and the compensation control circuit 13, and both the first control circuit 12 and the data writing circuit 41 are controlled by the first scanning signal, the following beneficial effects are achieved.

[0368] Effect 1: At time tb, the second scanning signal written into the second scanning line S2 changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit 12 controls to disconnect the electrical connection between the N1 node and the connection node N0, the voltages of the N2 node and the N3 node will no longer flow to the N1 node, so that when the data signal is written at time tc, the potential of the N1 node is still maintained at the low voltage of Vi1, ensuring that the data signal is fully written.

[0369] Effect 2: At the end of the writing compensation phase P3, the second scanning signal written by the second scanning line S2 changes from a high level to a low level. By adding the first control circuit 12, at the end of the writing compensation phase P3, the first scanning signal written by the first scanning line S1 changes from a low level to a high level, so that at the end of the writing compensation phase P3, the N1 node is pulled upward, which is conducive to reducing the data voltage required when displaying a black screen.

[0370] Effect three: When a GOA (S2) provides a second scan signal to the second scan line S2 corresponding to two rows of sub-pixels at the same time. At time tb, the second scan signal written to the second scan line S2 changes from a low level to a high level, and T1 is turned on. Between time tb and time tc, since the first control circuit 12 controls the disconnection of the electrical connection between the N1 node and the connection node N0, the N1 node will not be discharged between time tb and time tc, thereby ensuring that the initial voltage of the N1 node before the data signal is written is the same. Moreover, between time tb and time tc, since the first control circuit 12 controls the disconnection of the electrical connection between the N1 node and the connection node N0, it is ensured that the time when the voltage is given to the N1 node in the two rows of sub-pixels is the same, so even in the case of row-by-row scanning, the initial voltage of the N1 node in the two rows of sub-pixels before the data signal is written is the same. Therefore, when the two rows of sub-pixels include odd-numbered rows of sub-pixels and even-numbered rows of sub-pixels, it will not cause a difference in display brightness between the odd-numbered and even-numbered rows of sub-pixels.

[0371] Therefore, the display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0372] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0373] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0374] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0375] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0376] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0377] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0378] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0379] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A pixel circuit, It is characterized in that include: A driving circuit, a data writing circuit, a compensation control circuit and a first control circuit; The data writing circuit is coupled to the first scan line, the data line, and the second end of the driving circuit respectively, and is used to control the data line to be connected to the second end of the driving circuit under the control of the first scan signal provided by the first scan line; The compensation control circuit is coupled to the second scan line, the first end of the drive circuit and the connection node respectively, and is used to control the connection between the first end of the drive circuit and the connection node under the control of the second scan signal provided by the second scan line; The first control circuit is coupled to the first scan line, the control end of the drive circuit and the connection node respectively, and is used to control the connection between the control end of the drive circuit and the connection node under the control of the first scan signal; The first control circuit includes a ninth transistor, a gate of the ninth transistor is coupled to the first scan line, a first electrode of the ninth transistor is coupled to the connection node, and a second electrode of the ninth transistor is coupled to the control end of the driving circuit.

2. The pixel circuit according to claim 1, It is characterized in that The pixel circuit further includes: A first initialization circuit, wherein the first initialization circuit is coupled to an initialization control line, a first initialization voltage line and a control end of the driving circuit respectively, and is used for controlling the connection between the first initialization voltage line and the control end of the driving circuit under the control of an initialization control signal provided by the initialization control line.

3. The pixel circuit according to claim 1, It is characterized in that The pixel circuit further includes: A first initialization circuit is coupled to the initialization control line, the first initialization voltage line and the connection node respectively, and is used to control the connection between the first initialization voltage line and the connection node under the control of an initialization control signal provided by the initialization control line.

4. The pixel circuit according to claim 1, It is characterized in that The pixel circuit further includes: A reset circuit is respectively coupled to the third scan line, the reset voltage line and the second end of the drive circuit, and is used to control the connection between the reset voltage line and the second end of the drive circuit under the control of a third scan signal provided by the third scan line.

5. The pixel circuit according to claim 1, It is characterized in that The pixel circuit further includes: A reset circuit is coupled to the third scan line, the reset voltage line and the first end of the drive circuit respectively, and is used to control the connection between the reset voltage line and the first end of the drive circuit under the control of a third scan signal provided by the third scan line.

6. The pixel circuit according to claim 1, It is characterized in that The pixel circuit further includes: a light emitting control circuit, a storage circuit and a light emitting element; The light emitting control circuit is respectively coupled to the light emitting control line, the first end of the driving circuit and the light emitting element, and is used to control the connection between the first end of the driving circuit and the light emitting element under the control of the light emitting control signal provided by the light emitting control line; The light emitting control circuit is also coupled to the first voltage line and the second end of the driving circuit, and is used to control the first voltage line to be connected to the second end of the driving circuit under the control of the light emitting control signal; The energy storage circuit is coupled to the control terminal of the driving circuit and the first voltage line respectively.

7. The pixel circuit according to claim 4 or 5, It is characterized in that The pixel circuit further includes: a second initialization circuit and a light emitting element; The second initialization circuit is coupled to the third scan line, the second initialization voltage line and the light emitting element respectively, and is used to control the connection between the second initialization voltage line and the light emitting element under the control of a third scan signal provided by the third scan line.

8. The pixel circuit according to claim 7, It is characterized in that The pixel circuit further includes a first initialization circuit, wherein the first initialization circuit is coupled to a first initialization voltage line, and the first initialization voltage line is multiplexed as the reset voltage line.

9. The pixel circuit according to claim 1, It is characterized in that The compensation control circuit includes a first transistor, the driving circuit includes a third transistor, and the data writing circuit includes a fourth transistor; The gate of the first transistor is coupled to the second scan line, the first electrode of the first transistor is coupled to the second electrode of the third transistor, and the second electrode of the first transistor is coupled to the connection node; The gate of the fourth transistor is coupled to the first scan line, the first electrode of the fourth transistor is coupled to the data line, the second electrode of the fourth transistor is coupled to the first electrode of the third transistor; the second electrode of the ninth transistor is coupled to the gate of the third transistor.

10. The pixel circuit according to claim 2, It is characterized in that The first initialization circuit includes a second transistor, a gate of the second transistor is coupled to the initialization control line, a first electrode of the second transistor is coupled to the first initialization voltage line, and a second electrode of the second transistor is coupled to the control end of the driving circuit.

11. The pixel circuit according to claim 3, It is characterized in that The first initialization circuit includes a second transistor, a gate of the second transistor is coupled to the initialization control line, a first electrode of the second transistor is coupled to the first initialization voltage line, and a second electrode of the second transistor is coupled to the connection node.

12. The pixel circuit according to claim 4, It is characterized in that The reset circuit includes an eighth transistor; A gate of the eighth transistor is coupled to the third scan line, a first electrode of the eighth transistor is coupled to the reset voltage line, and a second electrode of the eighth transistor is coupled to the second end of the driving circuit.

13. The pixel circuit according to claim 5, It is characterized in that The reset circuit includes an eighth transistor; A gate of the eighth transistor is coupled to the third scan line, a first electrode of the eighth transistor is coupled to the reset voltage line, and a second electrode of the eighth transistor is coupled to the first end of the driving circuit.

14. The pixel circuit according to claim 6, It is characterized in that The light emitting control circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is coupled to the light emitting control line, the first electrode of the fifth transistor is coupled to the first voltage line, and the second electrode of the fifth transistor is coupled to the second end of the driving circuit; The gate of the sixth transistor is coupled to the light emitting control line, the first electrode of the sixth transistor is coupled to one end of the driving circuit, and the second electrode of the sixth transistor is coupled to the light emitting element.

15. The pixel circuit according to claim 7, It is characterized in that The second initialization circuit includes a seventh transistor, A gate of the seventh transistor is coupled to the third scan line, a first electrode of the seventh transistor is coupled to the second initialization voltage line, and a second electrode of the seventh transistor is coupled to the light emitting element.

16. A driving method, It is characterized in that Applied to the pixel circuit according to any one of claims 1 to 15, the display cycle includes a write compensation phase, the write compensation phase includes: a write control phase and a non-write control phase; the driving method includes: During the entire write compensation phase, the compensation control circuit controls the first end of the driving circuit to be connected to the connection node under the control of the second scanning signal; In the write control stage, the data write circuit controls the data line to be connected to the second end of the drive circuit under the control of the first scan signal; the first control circuit controls the control end of the drive circuit to be connected to the connection node under the control of the first scan signal; In the non-write control stage, the data write circuit controls the data line to be disconnected from the second end of the drive circuit under the control of the first scan signal; the first control circuit controls the control end of the drive circuit to be disconnected from the connection node under the control of the first scan signal.

17. The driving method according to claim 16, It is characterized in that The end time of the write compensation phase is the same as the end time of the write control phase.

18. The driving method according to claim 16, It is characterized in that The display cycle also includes an initialization phase; the driving method also includes: In the initialization stage, the first initialization circuit in the pixel circuit controls the connection between the first initialization voltage line and the control end of the driving circuit under the control of the initialization control signal; Alternatively, in the initialization stage, the first initialization circuit controls the connection between the first initialization voltage line and the connection node under the control of the initialization control signal, and the first control circuit controls the connection between the control end of the drive circuit and the connection node under the control of the first scanning signal.

19. The driving method according to claim 16, It is characterized in that The display cycle also includes a bias compensation phase and a light emitting phase, and the driving method includes: In the bias compensation stage, the reset circuit controls the reset voltage line to be connected to the second end of the drive circuit under the control of the third scan signal; or the reset circuit controls the reset voltage line to be connected to the first end of the drive circuit under the control of the third scan signal; In the light-emitting stage, the light-emitting control circuit in the pixel circuit controls the connection between the first voltage line and the second end of the driving circuit, and controls the connection between the first end of the driving circuit and the light-emitting element under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

20. A display substrate, It is characterized in that The invention comprises a substrate and a plurality of sub-pixels arranged on the substrate, wherein the sub-pixels comprise the pixel circuit according to any one of claims 1 to 15; and the sub-pixels further comprise: A data line, a first scan line and a second scan line; the data line includes at least a portion extending along a first direction, the first scan line includes at least a portion extending along a second direction, the second scan line includes at least a portion extending along the second direction, and the second direction intersects the first direction; The data writing circuit is coupled to the first scan line, the data line and the second end of the driving circuit respectively, and is used to control the data line to be connected to the second end of the driving circuit under the control of the first scan signal provided by the first scan line; The compensation control circuit is coupled to the second scan line, the first end of the drive circuit and the connection node respectively, and is used to control the connection between the first end of the drive circuit and the connection node under the control of the second scan signal provided by the second scan line; The first control circuit is coupled to the first scan line, the control end of the drive circuit and the connection node respectively, and is used to control the connection between the control end of the drive circuit and the connection node under the control of the first scan signal.

21. The display substrate according to claim 20, It is characterized in that The first control circuit includes a ninth transistor, the ninth transistor includes a ninth active layer, the ninth active layer includes at least a portion extending along the first direction; The driving circuit comprises a third transistor, and an orthographic projection of a gate of the third transistor on the substrate and an orthographic projection of the ninth active layer on the substrate are arranged along the first direction; The sub-pixel further includes a first connection pattern, and the second electrode of the ninth transistor is coupled to the gate electrode of the third transistor through the first connection pattern.

22. The display substrate according to claim 21, It is characterized in that The first initialization circuit in the pixel circuit includes a second transistor, the second transistor includes a second active layer, and the second active layer includes at least a portion extending along the first direction; An orthographic projection of a portion of the second active layer on the substrate and an orthographic projection of a portion of the ninth active layer on the substrate are arranged along the second direction; The sub-pixel further includes a second connection pattern, the second connection pattern includes a portion extending along the first direction and a portion extending along the second direction; the second electrode of the second transistor is coupled to the first connection pattern through the second connection pattern.

23. The display substrate according to claim 21, It is characterized in that The first initialization circuit in the pixel circuit includes a second transistor, the second transistor includes a second active layer, and the second active layer includes at least a portion extending along the first direction; An orthographic projection of a portion of the second active layer on the substrate and an orthographic projection of a portion of the ninth active layer on the substrate are arranged along the second direction; The sub-pixel further includes a third connection pattern, wherein the third connection pattern includes at least a portion extending along the second direction; the second electrode of the second transistor is coupled to the first electrode of the ninth transistor through the third connection pattern.

24. The display substrate according to claim 23, It is characterized in that An orthographic projection of the third connection pattern on the substrate at least partially overlaps with an orthographic projection of the first scanning line on the substrate.

25. The display substrate according to claim 23, It is characterized in that The sub-pixel further includes an initialization control line, and an orthographic projection of the third connection pattern on the substrate at least partially overlaps with an orthographic projection of the initialization control line on the substrate.

26. A display device, It is characterized in that Comprising the display substrate as claimed in any one of claims 20 to 25.

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