Display driver and display device

Abstract

The object is to provide a display driver and a display device capable of sensing a failure generated on a display panel with high accuracy without increasing an output load. The present invention has: an amplifier circuit that supplies an output voltage to a source line of a display panel by outputting an output current based on a differential signal, which indicates a difference between a gradation voltage corresponding to a video signal and the output voltage, to the source line; an output current detection circuit that generates a mirror current that replicates the output current and outputs an output current detection signal that indicates the mirror current; and a failure determination circuit that determines whether a short-circuit failure or a current leakage failure is generated in the source line by comparing a level of the output current detection signal with a prescribed threshold. The output current detection circuit includes: a transistor that generates the mirror current by receiving the differential signal at a gate; and a variable resistor that generates the output current detection signal by flowing in the generated mirror current.

Description

TECHNICAL FIELD

[0001] The present application relates to a display driver for driving a display panel from a video signal, and a display device having the same. BACKGROUND

[0002] In recent years, there are vehicles in which not only a display panel such as a liquid crystal display panel or an organic EL (Electro Luminescence) display panel is used for a car navigation of a vehicle but also it is mounted on various electronic instruments.

[0003] However, when a display panel fails and displays an error while the vehicle is traveling, it can be a hindrance to driving.

[0004] Therefore, a liquid crystal display device provided with a failure inspection circuit that inspects whether a failure occurs in normal use of the display panel and warns the occupant of the vehicle of the meaning in the case where a failure is sensed (for example, refer to Patent Document 1) has been proposed.

[0005] The failure inspection circuit supplies a monitoring input signal from one end of each of a plurality of source lines of the liquid crystal display panel and compares a monitoring output signal output from the other end of each with a prescribed expected value, thereby detecting a short-circuit abnormality and an open-circuit abnormality of the source lines. Therefore, in such a failure inspection circuit, a monitoring signal line for inputting a monitoring input signal for failure inspection is connected to one end of each source line individually, and a comparison circuit that compares a monitoring output signal output from the other end of each source line with a prescribed expected value is included.

[0006] PRIOR ART DOCUMENTS

[0007] PATENT DOCUMENTS

[0008] Patent Document 1: WO2018 / 079636 SUMMARY

[0009] PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] However, in the failure inspection described in Patent Document 1, whether a short-circuit abnormality or an open-circuit abnormality occurs in the source lines of the display panel is determined by size comparison using the expected value as a threshold value, so it is difficult to detect a failure such as a slight current leakage with high precision. Furthermore, in the failure inspection circuit described in Patent Document 1, a switch for deriving the above-described monitoring output signal is connected to the other end of the source line, so there is a problem that the amount of the switch element increases as the output load of the amplifier that outputs the drive voltage to the source line increases.

[0011] Accordingly, an object of the present application is to provide a display driver and a display device capable of sensing a failure generated on a display panel with high accuracy without increasing an output load.

[0012] Means for solving the problem

[0013] The display driver of the present application has an amplifier circuit that receives a gradation voltage having a voltage value corresponding to a luminance level shown by a video signal, outputs an output current based on the gradation voltage to a source line of a display panel, thereby supplying an output voltage having a voltage value corresponding to the gradation voltage to the source line, an output current detection circuit that generates a mirror current that replicates the output current, and outputs an output current detection signal having a level corresponding to an amount of the mirror current, and a failure determination circuit that determines whether a short-circuit failure or a current leakage failure is generated in the source line by comparing the level of the output current detection signal output from the output current detection circuit with a prescribed threshold value, the amplifier circuit including a differential section that generates a differential signal indicating a difference between the gradation voltage and the output voltage, and a first transistor that receives the differential signal at its own gate, and outputs the output current from a first output node to which its own drain is connected, the output current detection circuit including a second transistor that receives the differential signal at its own gate, and outputs the mirror current from a second output node to which its own drain is connected, and a variable resistor that is connected to the second output node, and generates the output current detection signal at the second output node by the mirror current flowing thereto.

[0014] Further, the display driver of the present application has: first to nth amplifier circuits that receive first to nth gradation voltages each having a voltage value corresponding to a luminance level of each pixel shown by a video signal, generate a current corresponding to a variation amount of the voltage value of the gradation voltage as a first to nth output current in accordance with each of the first to nth gradation voltages, and output the generated first to nth output currents to first to nth source lines of a display panel, respectively, whereby first to nth output voltages having voltage values corresponding to the first to nth gradation voltages, respectively, are supplied to the first to nth source lines, where n is an integer of two or more; first to nth output current detection circuits that generate first to nth mirror currents each of which replicates the first to nth output currents, and output first to nth output current detection signals each having a level corresponding to the amount of the first to nth mirror currents, respectively; and a failure determination circuit that determines a short-circuit failure or a current leakage failure of the first to nth source lines based on the first to nth output current detection signals output from the first to nth output current detection circuits, each of the first to nth amplifier circuits includes: a differential section that generates a differential signal indicating a difference between the gradation voltage and the output voltage; and a first transistor that receives the differential signal at its own gate, and sends out the output current from a first output node to which its own drain is connected, and each of the first to nth output current detection circuits includes: a second transistor that receives the differential signal at its own gate, and sends out the mirror current from a second output node to which its own drain is connected; and a variable resistor that is connected to the second output node, and generates the output current detection signal at the second output node by the mirror current flowing thereto.

[0015] The display device of the present application has a display panel in which display units are arranged in each of intersections of first to nth source lines and a plurality of gate lines, wherein n is an integer of 2 or more, and a display driver that drives the display panel according to a video signal, wherein the display driver has first to nth amplifier circuits that receive first to nth gradation voltages each having a voltage value corresponding to a luminance level of each pixel shown by the video signal, generate a current corresponding to an amount of change in the voltage value of the gradation voltage as first to nth output currents for each of the first to nth gradation voltages, and supply the generated first to nth output voltages to the first to nth source lines, first to nth output current detection circuits that generate first to nth mirror currents each of which replicates the first to nth output currents and output first to nth output current detection signals each having a level corresponding to an amount of the first to nth mirror currents, and a failure determination circuit that individually determines whether a short-circuit failure or a current leakage failure occurs in the first to nth source lines by comparing the levels of the first to nth output current detection signals output from the first to nth output current detection circuits with predetermined threshold values, respectively, each of the first to nth amplifier circuits includes a differential section that generates a differential signal indicating a difference between the gradation voltage and the output voltage, and a first transistor that receives the differential signal at its gate and sends out the output current from a first output node to which its drain is connected, and each of the first to nth output current detection circuits includes a second transistor that receives the differential signal at its gate and sends out the mirror current from a second output node to which its drain is connected, and a variable resistor connected to the second output node that generates the output current detection signal at the second output node by the mirror current flowing thereto.

[0016] Further, the display driver of the present application has: first to nth amplifier circuits that receive first to nth gradation voltages each having a voltage value corresponding to a luminance level of each pixel shown by a video signal, generate a current corresponding to a variation amount of the voltage value of the gradation voltage as a first to nth output current in accordance with each of the first to nth gradation voltages, and output the generated first to nth output currents to first to nth source lines of a display panel, respectively, whereby first to nth output voltages having voltage values corresponding to the first to nth gradation voltages, respectively, are supplied to the first to nth source lines, wherein n is an integer of two or more; a failure determination circuit that determines a short-circuit failure or a current leakage failure of the first to nth source lines; and a common wiring connected to each of the first to nth amplifier circuits, each of which includes: a differential section that generates a differential signal representing a difference between the gradation voltage and the output voltage; a first transistor that receives the differential signal at its own gate and sends out the output current from its own drain; and a second transistor that receives the differential signal at its own gate and sends out a mirror current to the common wiring, the mirror current copying the output current sent out from the first transistor, the failure determination circuit including: a variable resistor connected to the common wiring, which generates an output current detection signal at the common wiring by flowing a current through the common wiring, the current being a synthesis of the mirror currents sent out from the second transistors of the first to nth amplifier circuits, respectively; and a comparator that determines whether a short-circuit failure or a current leakage failure occurs in the first to nth source lines by comparing a level of the output current detection signal with a prescribed threshold value.

[0017] Further, the display driver of the present application has: first to nth amplifier circuits that receive first to nth gradation voltages each having a voltage value corresponding to a luminance level of each pixel shown by a video signal, generate a current corresponding to a variation in the voltage value of the gradation voltage as a first to nth output current in accordance with each of the first to nth gradation voltages, and output the generated first to nth output currents to first to nth source lines of a display panel, respectively, whereby first to nth output voltages having voltage values corresponding to the first to nth gradation voltages, respectively, are supplied to the first to nth source lines, wherein n is an integer of two or more; a failure determination circuit that determines a short-circuit failure or a current leakage failure of the first to nth source lines; and first to kth common wirings that divide the first to nth amplifier circuits into first to kth amplifier circuit groups to which at least one of the amplifier circuits belongs, respectively, and are individually connected to the first to kth amplifier circuit groups, respectively, wherein k is an integer of two or more and less than n, each of the first to nth amplifier circuits includes: a differential section that generates a differential signal indicating a difference between the gradation voltage and the output voltage; a first transistor that receives the differential signal at a gate thereof and sends out the output current from a drain thereof; and a second transistor that receives the differential signal at a gate thereof and sends out a mirror current, which is a copy of the output current sent out from the first transistor, to a common wiring to which the amplifier circuit group to which the second transistor belongs is connected among the first to kth common wirings, the failure determination circuit includes: a multiplexer that selects the first to kth common wirings one by one and connects the selected one common wiring to an output node; a variable resistor connected to the output node that generates an output current detection signal at the output node by flowing a current through the one common wiring, the multiplexer, and the output node, the current being a synthesis of the mirror currents sent out from the second transistors of the amplifier circuits, respectively; and a comparator that determines whether a short-circuit failure or a current leakage failure occurs in the first to nth source lines by comparing a level of the output current detection signal with a prescribed threshold value.

[0018] Effects of the Invention

[0019] The present application provides an output current detection circuit and a failure determination circuit that detect a short-circuit failure or a current leakage failure of a source line of a display panel in a display driver including an amplifier circuit that supplies an output voltage to the source line by outputting an output current based on a gradation voltage corresponding to a luminance level shown by a video signal to the source line of the display panel.

[0020] The output current detection circuit generates a mirror current that replicates an output current outputted from the amplifier circuit to the source line, and obtains an output current detection signal that indicates the mirror current. The failure determination circuit determines whether a short-circuit failure or a current leakage failure occurs in the source line by comparing a level of the output current detection signal with a prescribed threshold value.

[0021] Here, the output current detection circuit includes a transistor that generates the mirror current by receiving a differential signal at a gate, the differential signal being generated by a differential section of the amplifier circuit and indicating a difference between the gradation voltage and the output voltage, and a variable resistor that generates the output current detection signal by flowing the mirror current and adjusts a level of the output current detection signal.

[0022] Therefore, by adjusting the level of the output current detection signal using the variable resistor in accordance with an amount of current leakage assumed in the size of the display panel, the length of each source line, and the material, etc., high-precision failure determination using the prescribed threshold value can be performed regardless of the amount of current leakage.

[0023] Therefore, even if the amount of current leakage occurring in the source line of the display panel is slight, it can be detected as a failure with high precision.

[0024] Further, in the output current detection circuit, a mirror current that replicates an output current outputted from the amplifier circuit is generated based on a differential signal generated by a differential section of the amplifier circuit, and an output current detection signal that indicates a change in the amount of the output current is generated based on the mirror current.

[0025] Thus, since it is not necessary to connect a switch or a resistor or the like for current detection to an output node of the amplifier circuit, a short-circuit failure or a current leakage failure of the source line of the display panel can be detected without increasing an output load. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a block diagram showing a structure of the display device 100;

[0027] Figure 2 is a waveform chart showing an example of waveforms of the data import signal LOAD and the strobe signal STB respectively;

[0028] Figure 3 is a block diagram showing an example of an internal structure of the source driver 13;

[0029] Figure 4 is a circuit diagram showing an internal structure of the amplifier AM1;

[0030] Figure 5is a view showing waveforms within the amplifier AM1 in the case where a short-circuit failure or a current leakage failure occurs in the source line S1 of the display panel 20 and in the case where it does not occur;

[0031] Figure 6 is a circuit diagram showing an example of the internal structure of the failure determination circuit 1330;

[0032] Figure 7 is a block diagram showing another example of the internal structure of the source driver 13;

[0033] Figure 8 is a circuit diagram showing the internal structure of the amplifier AX1;

[0034] Figure 9 is a circuit diagram showing an example of the internal structure of the failure determination circuit 1330A;

[0035] Figure 10 is a block diagram showing still another example of the internal structure of the source driver 10;

[0036] Figure 11 is a circuit diagram showing an example of the internal structure of the failure determination circuit 1330B. DETAILED DESCRIPTION

[0037] Hereinafter, an embodiment of the present application will be described in detail with reference to the drawings.

[0038] Figure 1 is a block diagram showing the structure of a display device 100 including a display driver of the present application.

[0039] The display device 100 has a drive control section 11, a gate driver 12, a source driver 13, and a display panel 20.

[0040] The display panel 20 is, for example, a liquid crystal or an organic EL (electro-luminescence) panel. In the display panel 20, gate lines G1 to Gm (m is an integer of 2 or more) each extending in a horizontal direction of a two-dimensional picture and source lines S1 to Sn (n is an integer of 2 or more) each extending in a vertical direction of the two-dimensional picture are arranged in a cross manner. A display unit PC composed of a liquid crystal or an organic EL element or the like is formed at the intersection of the gate lines and the source lines.

[0041] The drive control section 11 receives a video signal VS, generates a scan signal based on a horizontal synchronization signal included in the video signal VS, and supplies the scan signal to the gate driver 12.

[0042] Further, the drive control section 11 generates a video data signal VPD including a sequence of display data pieces each representing a luminance level of each pixel in 8 bits, for example, and various control signals including a data import signal LOAD, based on the video signal VS, and supplies them to the source driver 13.

[0043] As shown in Figure 2 , the data import signal LOAD is a pulse signal of binary (logic levels 0 and 1) having the same period (1H) as the horizontal synchronization signal.

[0044] Further, the drive control section 11 imports the failure site data signal FLD supplied from the source driver 13 every prescribed period. Further, the failure site data signal FLD is a signal showing a failure site in the case where a failure occurs on the display panel 20. In the case where the failure site data signal FLD shows a failure site, the drive control section 11 performs display control or sound output control to notify the user of the meaning that a failure has occurred at the failure site.

[0045] The gate driver 12 generates scan pulses in accordance with the scan signal supplied from the drive control section 11, and applies them to the gate lines Gl to Gn of the display panel 20 in sequence.

[0046] The source driver 13 imports a sequence of display data pieces included in the video data signal VPD in accordance with the data import signal LOAD. Here, the source driver 13 generates output voltages GVl to GVn having voltage values corresponding to the luminance levels represented by the respective display data pieces every time it imports the amount of n display data pieces of one horizontal scan line. Then, the source driver 13 supplies the output voltages GVl to GVn to the source lines Sl to Sn of the display panel 20.

[0047] Further, the source driver 13 detects a failure occurring on the source lines Sl to Sn of the display panel 20, and supplies a signal showing the failure site as the above-mentioned failure site data signal FLD to the drive control section 11.

[0048] Figure 3 is a block diagram showing an example of the internal structure of the source driver 13.

[0049] As shown in Figure 3 , the source driver 13 includes a data latch section 131, a decoder section 132, and an output amplifier section 133.

[0050] The data latch section 131 imports a sequence of display data pieces corresponding to each pixel included in the video data signal VPD at the timing of, for example, the leading edge portion of the data import signal LOAD.

[0051] Then, each time a quantity of n display data pieces for one horizontal scanning period is imported, the data latch section 131 supplies each display data piece as display data J1 to Jn to the decoder section 132 at the timing of, for example, the leading edge portion of the data import signal LOAD.

[0052] The decoder section 132 selects a gradation voltage corresponding to the luminance level indicated by the display data Jq (q is an integer from 1 to n) from, for example, 256 gradation voltages having mutually different voltage values, in accordance with each display data J1 to Jn. Then, the decoder section 132 supplies n gradation voltages selected based on the display data J1 to Jn as described above as gradation voltages V1 to Vn to the output amplifier section 133.

[0053] The output amplifier section 133 includes amplifiers AM1 to AMn provided in correspondence with the source lines S1 to Sn of the display panel 20, respectively, and a failure determination circuit 1330.

[0054] The amplifiers AM1 to AMn receive the gradation voltages V1 to Vn, and generate output voltages GV1 to GVn having voltage values corresponding to the voltage values of the respective gradation voltages by individually amplifying each gradation voltage. Further, the source lines S1 to Sn of the display panel 20 are connected to external terminals TM1 to TMn, respectively. The amplifiers AM1 to AMn supply the generated output voltages GV1 to GVn to the source lines S1 to Sn via the external terminals TM1 to TMn.

[0055] Further, the amplifiers AM1 to AMn detect an output current sent to each source line S1 to Sn in accordance with each source line S1 to Sn, and supply output current detection signals fl to fn indicating the amount of the output current in accordance with each source line S1 to Sn to the failure determination circuit 1330.

[0056] Further, the amplifiers AM1 to AMn have the same internal structure. Therefore, hereinafter, the internal structure of the amplifier AM1 will be described by extracting the amplifier AM1 from the amplifiers AM1 to AMn.

[0057] Figure 4 is a circuit diagram showing an example of the internal structure of the amplifier AM1.

[0058] As shown in Figure 4 , the amplifier AM1 includes an amplifier circuit 1331 and an output current detection circuit 1332.

[0059] The amplifier circuit 1331 is, for example, an operational amplifier of a voltage follower, and has a differential section DC, a transistor Q1 which is an output transistor of a P-channel MOS type, and a transistor Q2 which is an output transistor of an N-channel MOS type.

[0060] The differential DC unit receives the output voltage GV1 from the amplifier circuit 1331 and the aforementioned grayscale voltage V1, and generates a differential signal PG with a level corresponding to the difference between the two voltage values. The differential DC unit supplies the generated differential signal PG to the gate of transistor Q1, which serves as the positive-side output transistor, and the output current detection circuit 1332 via node nd0. Furthermore, the differential DC unit supplies an inverted differential signal NG, obtained by inverting the phase of the differential signal PG, to the gate of transistor Q2, which serves as the negative-side output transistor.

[0061] That is, the differential DC generation generates a differential signal PG when the grayscale voltage V1 is higher than the output voltage GV1, i.e., the greater the difference between the two as the output voltage rises, the higher the level of the differential signal. Furthermore, the differential DC generation generates an inverted differential signal NG when the grayscale voltage V1 is lower than the output voltage GV1, i.e., the greater the difference between the two as the output voltage decreases, the higher the level of the differential signal.

[0062] A power supply potential is applied to the source of transistor Q1, and the drain of transistor Q2 and the external terminal TM1 are connected to the drain of transistor Q1 via the output node nd1. A ground potential is applied to the source of transistor Q2.

[0063] Transistor Q1 generates an output current Iout corresponding to the differential signal PG received from its gate and sends it to the external terminal TM1 via output node nd1. Transistor Q2 draws a current (called the draw current) from output node nd1 corresponding to the inverted differential signal NG received from its gate. Through this operation, an output voltage GV1 with a voltage value corresponding to the input grayscale voltage V1 is generated at output node nd1 and external terminal TM1.

[0064] For example, such as Figure 4 As shown, the external terminal TM1, which is connected to the amplifier circuit 1331 included in amplifier AM1, is connected to the source line S1 of display panel 20. Therefore, amplifier AM1 supplies the output voltage GV1 generated as described above to the source line S1 of display panel 20. Similarly, the external terminal TMj, which is connected to the amplifier circuit 1331 included in amplifier AMj (j is an integer from 2 to n), is connected to the source line Sj of display panel 20, and supplies the output voltage GVj generated by each amplifier to the source line Sj.

[0065] The output current detection circuit 1332 detects the output current output to the source line connected to the amplifier circuit 1331, and generates an output current detection signal that indicates the amount of the output current with a voltage value. For example, the output current detection circuit 1332 included in the amplifier AM1 detects the output current Iout output to the source line S1 by the amplifier circuit 1331, and generates an output current detection signal fl that indicates the amount of the output current with a voltage value. Likewise, the output current detection circuit 1332 included in the amplifier AMj (j is an integer of 2 to n) detects the output current output to the source line Sj by the amplifier circuit 1331, and generates an output current detection signal fj that indicates the amount of the output current with a voltage value.

[0066] As shown in FIG. 13, the output current detection circuit 1332 includes a P-channel MOS transistor QS, a register RG1, and a variable resistor Rl. Figure 4

[0067] The source of the transistor QS is supplied with a power supply potential, and the differential signal PG is supplied to the gate of the transistor QS via a node ndO. That is, like the transistor Ql, the transistor QS receives the differential signal PG generated by the differential section DC at its own gate. The drain of the transistor QS is connected to one end of the variable resistor Rl via an output node nd2. The other end of the variable resistor Rl is supplied with a ground potential, and the resistance value thereof can be changed according to the adjustment value held in the register RG1.

[0068] With this configuration, the transistor QS generates a current corresponding to the differential signal PG received at its own gate, that is, a mirror current corresponding to the output current output by the transistor Ql of the amplifier circuit 1331, and outputs it to the variable resistor Rl via the output node nd2. Therefore, a voltage signal generated at the output node nd2 due to the mirror current flowing into the variable resistor Rl is generated as the output current detection signal f that indicates the change in the amount of the output current output to the source line with a voltage level. In other words, the mirror current flows into the variable resistor Rl, and an output current detection signal that changes according to the amount of the inflow is generated at the output node nd2.

[0069] Thus, the output current detection circuits 1332 included in the amplifiers AM1 to AMn supply the output current detection signals fl to fn to the failure determination circuit 1330, which individually indicate the amounts of the output currents output to the source lines S1 to Sn, respectively.

[0070] ​Furthermore, the levels of the output current detection signals f1 to fn can be adjusted using the adjustment values ​​held in register RG1 via the variable resistor R1. For example, the aforementioned adjustment values ​​are held in register RG1 in advance so that the increase in output current caused by current leakage under the condition of a short circuit between the source and gate lines of the display panel 20 can be taken into account, and the increase in current can be determined as a fault in the fault determination circuit 1330.

[0071] The fault determination circuit 1330 determines whether a short circuit fault or current leakage fault has occurred in the source lines S1 to Sn of the display panel 20 based on the output current detection signals f1 to fn, and generates a fault location data signal FLD that shows the source line where the fault occurred.

[0072] Specifically, such as Figure 2 As shown, the fault determination circuit 1330 compares the level of the output current detection signal with a predetermined threshold Vth for fault determination at time point t1, which is a predetermined period DL after the leading edge of the data import signal LOAD at time point t0. If the level of the output current detection signal is greater than the threshold Vth, the fault determination circuit 1330 determines that a short circuit fault or current leakage fault has occurred in the source line corresponding to the output current detection signal. Conversely, if the level of the output current detection signal is less than or equal to the threshold Vth, the fault determination circuit 1330 determines that no short circuit fault or current leakage fault has occurred in the source line corresponding to the output current detection signal. Then, the fault determination circuit 1330 generates a fault location data signal FLD, which individually displays the determination result obtained by the above-described determination process for each output current detection signal.

[0073] The following is for reference Figure 4 and Figure 5 This will be used to explain the fault determination operation in the amplifier circuit 1331, output current detection circuit 1332, and fault determination circuit 1330 described above.

[0074] also, Figure 5 It is shown by dividing the situation into cases where a short circuit fault or current leakage fault occurs in the source line S1 of the display panel 20 and cases where no fault occurs. Figure 4 The diagram shows the operating waveforms within amplifier AM1. Furthermore, in... Figure 5 The figure shows the waveform of the gray voltage V1 received by amplifier AM1 when the voltage value changes from 0 to Va at the leading edge of the data import signal LOAD (time point t0).

[0075] [No faults]

[0076] like Figure 5As shown, when the grayscale voltage V1 changes from zero to Va (Va>0) at time t0, the differential section DC of amplifier circuit 1331 sends a differential signal PG to node nd0. This differential signal PG has a difference (0-Va) between the output voltage GV1 and the grayscale voltage V1. Based on this differential signal PG, transistor Q1 becomes on, sending the output current Iout corresponding to the difference (0-Va) to the source line S1. Consequently, the voltage on the source line S1, i.e., the output voltage GV1, gradually increases. As a result, the difference between the grayscale voltage V1 and the output voltage GV1 gradually decreases, and as the voltage value of the differential signal PG gradually returns to the voltage value Vb, the output current Iout decreases. Then, when the output voltage GV1 reaches the grayscale voltage V1 value, i.e., Va, the voltage value of the differential signal PG becomes the voltage value Vb that causes transistor Q1 to become off. Therefore, transistor Q1 becomes off, and thus the output current Iout also becomes 0.

[0077] During this period, transistor QS of the output current detection circuit 1332 sends a mirror current Imr, which replicates the output current Iout, to the variable resistor R1 via output node nd2, as shown below. Figure 5 As shown. Therefore, at the output node nd2, a signal is generated that represents the change in current quantity in the mirrored current Imr as a change in voltage value, i.e., representing... Figure 5 The output current detection signal f1 shows the change in current quantity in the output current Iout.

[0078] Here, assuming no short circuit or current leakage fault occurs in the source line S1 of the display panel 20, such as Figure 5 As shown, at time point t1, after a specified period DL has elapsed from time point t0, the output current Iout becomes zero. At this time, the mirror current Imr, which replicates the output current Iout, also becomes zero at time point t1. Therefore, the output current detection signal f1 corresponding to this mirror current Imr is at the same level at time point t1 as shown in the figure. Figure 5 As shown, this becomes the voltage value Vx representing zero current.

[0079] Therefore, as Figure 5 As shown, since the level of the output current detection signal f1 at time point t1 is the specified threshold Vth (by... Figure 4 (As shown by the dashed line) Below, the fault determination circuit 1330 generates a fault data signal FLD for the source line S1 indicating that there is no short circuit fault or current leakage fault.

[0080] [Faulty situation]

[0081] In the case where a short-circuit failure or a current leakage failure occurs in the source line Sl, when the gradation voltage VI is shifted from the voltage value zero to the voltage value Va at the time point tO, the differential section DC of the amplifier circuit 1331 also sends out a differential signal PG having a difference value (0 - Va) between the output voltage GVl and the gradation voltage VI to the node ndO. According to this differential signal PG, the transistor Ql becomes in the on state, and sends out an output current Iout corresponding to the difference value (0 - Va) to the source line Sl. Thereby, the voltage value of the output voltage GVl, that is, the voltage value on the source line Sl gradually rises. As a result, the above difference value gradually becomes large, and along with this, the voltage value of the differential signal PG also gradually increases, and along with the increase of the voltage value of the differential signal PG, the output current Iout decreases.

[0082] At this time, when the source line Sl is short-circuited to at least one of the gate lines Gl to Gn, for example, to the gate line G2 as shown in FIG. 10, the output current Iout flows not only into the source line Sl but also into the gate line G2. That is, a part of the output current Iout leaks into the gate line G2 as a leakage current. Therefore, not only the source line Sl but also the gate line G2 becomes a charging object of the output current Iout, and therefore, the increase of the output voltage GVl becomes slow compared to the case where no short-circuit failure occurs in the source line Sl. Thereby, as shown in FIG. 11, in the stage of the time point tl, the voltage value of the output voltage GVl does not reach the voltage value Va of the gradation voltage VI but stays at a voltage value Vc lower than the voltage value Va, and therefore, the difference value (Vc - Va) between the output voltage GVl and the gradation voltage VI is not zero. Therefore, as shown in FIG. 12, the voltage value of the differential signal PG corresponding to the difference value does not reach the voltage value Vb that can make the transistor Ql shift to the off state. Therefore, the transistor Ql also maintains the on state in the stage of the time point tl, as shown in FIG. 13, sends out the output current Iout having an amount Ib corresponding to the difference value (Vc - Va) represented by the differential signal PG. Thereby, as shown in FIG. 14, the output current detection signal fl corresponding to the mirror current Imr that copies the output current Iout becomes an amount Vy higher than the voltage value Vx representing an amount zero at the time point tl. Figure 5 Figure 5 Figure 5 Figure 5 Figure 5

[0083] Figure 5 Therefore, as shown in FIG. 15, since the level of the output current detection signal fl at the time point tl is higher than the prescribed threshold value Vth, the failure determination circuit 1330 generates the failure place data signal FLD indicating that there is a short-circuit failure or a current leakage failure in the source line Sl.

[0084] ​​​​​​As detailed above, in the display device 100, an output current detection circuit 1332 and a fault determination circuit 1330 are provided in the source driver 13 as a fault detection device for detecting short circuit faults or current leakage faults of the source lines (S1 to Sn) of the display panel 20.

[0085] The output current detection circuit 1332 is installed in each of the amplifiers AM1 to Amn. For each amplifier AM, it generates a mirror current Imr that replicates the output current Iout output to the source line of that amplifier, and sends it to the variable resistor R1 via the output node nd2. At this time, the mirror current Imr flows through the variable resistor R1, thereby generating an output current detection signal f at the output node nd2 that performs a current-voltage transformation on the mirror current Imr, that is, uses the change in voltage value to represent the change in the current quantity of the mirror current Imr.

[0086] like Figure 6 As shown, the fault determination circuit 1330 determines whether there is a fault if the level of the output current detection signal f is greater than the specified threshold Vth after a specified period DL has elapsed from the time point t0 when the input grayscale voltage value changes, and determines whether there is no fault if the level is below the threshold Vth.

[0087] In this way, when the fault detection device (1332, 1330) uses the operational amplifier (1331) of the voltage follower as the output amplifier of the source driver, it focuses on the fact that when a fault such as a short circuit or current leakage occurs in the source line, the mirror current Imr (=Iout) becomes higher than when no fault occurs, thereby performing fault determination using the threshold Vth.

[0088] Here, in the output current detection circuit 1332, a variable resistor R1 is used as a resistor to obtain the output current detection signal from the mirror current Imr, thereby enabling the adjustment of the level of the output current detection signal.

[0089] Therefore, by adjusting the level of the output current detection signal in accordance with the amount of current leakage assumed in the size of the display panel, the length and material of each source line, etc., high-precision fault determination can be performed using a fixed threshold Vth regardless of the amount of current leakage.

[0090] Therefore, according to the fault detection devices (1332, 1330), even if the amount of current leakage generated in the source line of the display panel 20 is minute, it can be determined as a fault with high accuracy.

[0091] Further, in the output current detection circuit 1332, a transistor QS is provided for detecting the output current Iout output to the source line, which receives a differential signal PG generated by the differential section DC of the amplifier circuit 1331 at the gate similarly to the output transistor (Ql).

[0092] That is, in the output current detection circuit 1332, the output current Iout is copied by the transistor QS, and a mirror current Imr obtained by the copying is sent out to the resistor (Rl), whereby the detection of the output current is performed. Thus, it is not necessary to connect a switch or a resistor or the like for performing the failure (short-circuit, current leakage) detection to the output node ndl of the amplifier circuit 1331, and therefore, it is possible to detect the short-circuit failure or the current leakage failure of the source lines of the display panel 20 without increasing the output load of the amplifier.

[0093] Further, as the above failure determination circuit 1330, it is also possible to perform the failure determination on all the source lines S1-Sn individually (as described above), but to divide all the source lines into a plurality of source line groups, and to perform the failure determination on a representative one source line for each source line group.

[0094] Figure 6 is a block diagram showing an example of the internal structure of the failure determination circuit 1330 completed in view of such an aspect. Further, in Figure 6 In the structure shown in FIG. 13, the source lines S1-Sn are divided into first to rth (r is an integer of 2 or more) source line groups each consisting of, for example, 20 adjacent source lines, and the failure determination is performed on an arbitrary one source line as a representative for each of the first to rth source line groups.

[0095] Figure 2 The failure determination circuit 1330 shown in FIG. 13 includes selectors SL1-SLr (r is an integer of 2 or more), comparators CM1-CMr, a delay circuit DDl, and a register RG2.

[0096] Each of the selectors SL1-SLr receives 20 output current detection signals among the output current detection signals fl-fn. Each selector SL1-SLr selects one output current detection signal indicated by the representative source line designation signal TS from the 20 output current detection signals received by itself, and outputs it as a representative output current detection signal Sf. That is, the selectors SL1-SLr supply the representative output current detection signals Sfl-Sfr, which are selected according to the representative source line designation signal TS, respectively, to the corresponding comparators CM1-CMr, respectively.

[0097] Each of the comparators CM1 to CMr compares the level of the output current detection signal Sf received by itself with the prescribed threshold value Vth for failure determination. At this time, each of the comparators CM1 to CMr generates a pre-failure determination signal that shows a failure in the case where the level of the output current detection signal Sf is greater than the threshold value Vth, and shows no failure in the case where it is equal to or less than the threshold value Vth. Thus, the comparators CM1 to CMr supply the sets of the pre-failure determination signals generated respectively as the pre-failure determination signals el to er to the register RG2.

[0098] The delay circuit DD1 receives the data load signal LOAD, and supplies a signal that is delayed by the prescribed period DL as shown by Figure 2 the strobe signal STB to the register RG2.

[0099] The register RG2 imports the pre-failure determination signals el to er supplied from the comparators CM1 to CMr at the timing of the leading edge of the strobe signal STB as shown by Figure 6 The register RG2 outputs a failure location data signal FLD that includes the imported pre-failure determination signals el to er as the failure determination signals bl to br.

[0100] Here, for example, in the case where the failure determination signal bl shows a failure, it is possible to confirm that a short-circuit failure or a current leakage failure has occurred in the first source line group (S1 to S20) that corresponds to the output current detection signal group (e.g., fl to f20) to which the representative output current detection signal Sfl corresponding to the failure determination signal bl belongs. Further, for example, in the case where the failure determination signal b2 shows a failure, it is possible to confirm that a short-circuit failure or a current leakage failure has occurred in the second source line group (S21 to S40) that corresponds to the output current detection signal group (e.g., f21 to f40) to which the representative output current detection signal Sf2 corresponding to the failure determination signal b2 belongs.

[0101] Thus, in the structure as shown by Figure 7 first, the output current detection signals fl to fn corresponding to the source lines S1 to Sn are divided into first to rth output current detection signal groups that are each composed of, for example, 20 output current detection signals. Then, in each of these first to rth output current detection signal groups, one representative output current detection signal is selected, and the level of the selected output current detection signal is compared with the threshold value Vth. Thereby, in each of the source line groups corresponding to the output current detection signal group to which the selected output current detection signal belongs, a determination is made as to whether a short-circuit failure or a current leakage failure has occurred in the source line group.

[0102] Furthermore, in the above embodiment, in the output current detection circuit 1332 provided in each amplifier AM1 to AMn, the mirror current Imr, which replicates the output current Iout, is converted into a voltage level by a variable resistor R1, thereby generating an output current detection signal f representing the current amount of the output current Iout.

[0103] However, the following structure can also be adopted: In the source driver 13, only the variable resistor R1 and register RG1 included in the system output current detection circuit 1332 are set up, and the drain of the transistor QS included in each of the amplifiers AM1 to AMn and one end of the variable resistor R1 are connected by a single wiring.

[0104] Figure 7 This is a block diagram illustrating another example of the internal structure of the source driver 13 completed in view of such aspects.

[0105] In addition, Figure 3 In the structure shown, except for the fact that the output amplifier section 133 is replaced by the output amplifier section 133A, the other structures, namely the data latch section 131 and the decoder section 132, are... Figure 3 The same applies as shown, therefore the explanation is omitted.

[0106] The output amplifier section 133A uses amplifiers AX1 to AXn instead. Figure 3 The amplifiers AM1 to AMn are shown, and a fault diagnosis circuit 1330A is used instead. Figure 8 The fault determination circuit 1330 shown is shown.

[0107] Amplifiers AX1 to AXn receive grayscale voltages V1 to Vn in the same way as amplifiers AM1 to AMn. They generate output voltages GV1 to GVn by individually amplifying each grayscale voltage, and supply the generated output voltages GV1 to GVn to the source lines S1 to Sn via external terminals TM1 to TMn.

[0108] Furthermore, amplifiers AX1 through AXn have the same internal structure. Therefore, the following explanation of the internal structure of amplifier AX1 will focus on amplifier AX1 from among amplifiers AX1 through AXn.

[0109] Figure 8 This is a circuit diagram showing an example of the internal structure of amplifier AX1.

[0110] like Figure 4 As shown, amplifier AX1, like amplifier AM1, includes amplifier circuit 1331. However, in amplifier AX1, a mirror current generation circuit 1333 is used instead. Figure 8The output current detection circuit 1332 is shown.

[0111] also, Figure 4 The structure and operation of the amplifier circuit 1331 shown are similar to those of the amplifier circuit 1331. Figure 9 The amplifier circuit shown is the same as 1331, so the description is omitted.

[0112] The mirror current generation circuit 1333 includes a P-channel MOS transistor QS that applies a power supply potential to its source. The gate of transistor QS is connected to the gate of transistor Q1 in amplifier circuit 1331 via node nd0, and receives the differential signal PG output from the differential section DC at its gate. The drain of transistor QS is connected to the common wiring LB. Furthermore, the drains of transistors QS included in amplifiers AX2 to AXn are also connected to the common wiring LB.

[0113] With this structure, transistor QS generates a mirror current Imr corresponding to the differential signal PG received from its own gate, that is, the output current output by transistor Q1 of amplifier circuit 1331, and sends it out to the common wiring LB.

[0114] The fault determination circuit 1330A determines, based on the current supplied to the common wiring LB, whether a short circuit fault or current leakage fault has occurred in the source lines S1 to Sn of the display panel 20 at a timing corresponding to the data import signal LOAD. Then, the fault determination circuit 1330A outputs a fault detection signal FLX indicating whether a fault has occurred as its determination result.

[0115] Figure 9 This is a circuit diagram showing an example of the internal structure of the fault determination circuit 1330A.

[0116] like Figure 2 As shown, the fault determination circuit 1330A includes register RG1, variable resistor R1, comparator CM1, register RG3, and delay circuit DD1.

[0117] One end of the variable resistor R1 is connected to the common wiring LB, and a ground potential is applied to the other end. Therefore, a synthesized current flows into the variable resistor R1 via the common wiring LB. This synthesized current is obtained by combining the mirror currents Imr from the transistors QS of each of the amplifiers AX1 to Axn. Thus, the variable resistor R1 converts the synthesized current flowing into it via the common wiring LB into a voltage level corresponding to that current, generating a signal with that voltage level on the common wiring LB as the output current detection signal.

[0118] In the register RG1, an adjustment value indicating the resistance value of the variable resistor R1 is held. The register RG1 sets the resistance value of the variable resistor R1 in accordance with the adjustment value held by itself.

[0119] The comparator CM1 compares the voltage of the common wiring LB, that is, the above-mentioned output current detection signal, with a prescribed threshold value Vth for failure determination, and generates a failure determination signal eX indicating a failure in the case where the voltage level of the voltage output current detection signal is greater than the threshold value Vth, and indicating no failure in the case where it is equal to or less than the threshold value Vth. The comparator CM1 supplies the generated failure determination signal eX to the register RG3.

[0120] The delay circuit DD1 receives the data import signal LOAD, and supplies a signal obtained by delaying the signal by a prescribed period DL as shown in Figure 2 to the register RG3 as the strobe signal STB.

[0121] The register RG3 imports the failure determination signal eX supplied from the comparator CM1 at the timing of the leading edge of the strobe signal STB as shown in Figure 5 . The register RG3 holds a signal indicating the level of the imported failure determination signal eX, and supplies it to the drive control section 11 as a failure detection signal FLX indicating whether or not a short-circuit failure or a current leakage failure has occurred in the source line group (S1 to Sn).

[0122] That is, a synthetic current flows through the common wiring LB, the synthetic current being obtained by synthesizing the mirror currents Imr which are the same as the output currents Iout output from the respective transistors QS of the amplifiers AX1 to AXn. At this time, in the case where a short-circuit failure or a current leakage failure has occurred in at least one of the source lines S1 to Sn, the mirror current Imr (= Iout) at the time point t1 as shown in Figure 7-9 becomes high compared to the case where no short-circuit failure or current leakage failure has occurred in the source lines S1 to Sn.

[0123] Therefore, an adjustment value adjusting the resistance value of the variable resistor R1 is held in the register RG1 so that it is possible to discriminate between the case where a short-circuit failure or a current leakage failure has occurred in one of the source lines S1 to Sn and the case where no short-circuit failure or current leakage failure has occurred in the source lines S1 to Sn by the above-mentioned threshold value Vth.

[0124] Therefore, according to the structure as shown in Figure 7-9 , it is possible to detect a short-circuit failure or a current leakage failure which has occurred in at least one of the source lines S1 to Sn. At this time, in the case where a short-circuit failure or a current leakage failure has occurred in at least one of the source lines S1 to Sn, the mirror current Imr (= Iout) at the time point t1 as shown in Figure 3In the illustrated structure, although the source line that is the source of the failure cannot be determined, compared with the case of the structure illustrated in Figure 4 , Figure 6 and Figure 7-9 , the scale of the device can be suppressed.

[0125] Further, with the structure illustrated in Figure 10 , by using a plurality of common wirings LB, it is possible to determine the failure location in units of source line groups.

[0126] Figure 7-9 is a block diagram of an example of the internal structure of the source driver 10 as an application example of the structure illustrated in Figure 10 .

[0127] Further, in the structure illustrated in Figure 3 , other than the point that the output amplifier section 133B is employed instead of the output amplifier section 133, the other structures, that is, the data latch section 131 and the decoder section 132 are the same as those illustrated in Figure 7 , and therefore the explanation is omitted.

[0128] The output amplifier section 133B includes the amplifiers AX1 to AXn, the common wirings LB1 to LB3, and the failure determination circuit 1330B, which are the same as those illustrated in Figure 7 . Further, the amplifiers AX1 to AXn are the same as those illustrated in Figure 11 , and therefore the explanation thereof is omitted.

[0129] However, the drains of the transistors QS of the respective amplifiers AX1 to AXp (p is an integer of 2 or more) among the amplifiers AX1 to AXn are connected to the common wiring LB1. Further, the drains of the transistors QS of the respective amplifiers AX (p+1) to AXt (t is an integer larger than p) are connected to the common wiring LB2, and the drains of the transistors QS of the respective amplifiers AX (t+1) to AXn are connected to the common wiring LB3.

[0130] The failure determination circuit 1330B determines, based on the currents respectively sent to the common wirings LB1 to LB3, whether a short-circuit failure or a current leakage failure has occurred in the source lines S1 to Sn of the display panel 20 at the timing corresponding to the data import signal LOAD. The failure determination circuit 1330B outputs a failure location data signal FLD that individually indicates whether a failure has occurred in each of a first source line group composed of the source lines S1 to Sp, a second source line group composed of the source lines S (p+1) to St, and a third source line group composed of the source lines S (t+1) to Sn.

[0131] Figure 11 is a circuit diagram showing an example of the internal structure of the failure determination circuit 1330B.

[0132] As shown in FIG. 13B, the failure determination circuit 1330B includes a multiplexer MX, registers RG1 and RG4, a variable resistor R1, a comparator CM1, and a delay circuit DD1. Figure 2

[0133] The multiplexer MX selects the common wirings LB1 to LB3 one by one in order based on the source line designation signal TS, and connects the selected one of the common wirings to the output node nd2.

[0134] One end of the variable resistor R1 is connected to the output node nd2, and the other end is applied with a ground potential. In the register RG1, a shown adjustment value of the resistance value of the variable resistor R1 is held. The register RG1 sets the resistance value of the variable resistor R1 according to the adjustment value held by itself.

[0135] The comparator CM1 compares the voltage of the output node nd2, that is, the voltage of the one common wiring (LB1, LB2, or LB3) selected by the multiplexer MX with a prescribed threshold value Vth for failure determination. Here, the comparator CM1 generates a failure determination signal eX showing a failure in the case where the voltage of the one common wiring is greater than the threshold value Vth, and showing no failure in the case where it is equal to or less than the threshold value Vth. Then, the comparator CM1 supplies the generated failure determination signal eX to the register RG4.

[0136] The delay circuit DD1 receives the data import signal LOAD, and supplies a signal obtained by delaying the signal as shown in FIG. 13B for a prescribed period DL to the register RG4 as the strobe signal STB. Figure 2

[0137] The register RG4 holds the failure determination signal eX supplied from the comparator CM1 in the case where the data import signal LOAD is input, and supplies the held failure determination signal eX to the multiplexer MX in the case where the data import signal LOAD is not input. Figure 10 ​​The timing of the front edge of the selection signal STB shown introduces the failure determination signal eX supplied from the comparator CM1. The register RG4 holds a signal representing the level of the introduced failure determination signal eX. That is, the register RG4 holds a signal representing the level of the failure determination signal eX when the common wiring LB1 is connected to the comparator CM1 by the multiplexer MX as a first failure determination signal representing whether a short-circuit failure or a current leakage failure occurs in the first source line group (S1 ~ Sp). Further, the register RG4 holds a signal representing the level of the failure determination signal eX when the common wiring LB2 is connected to the comparator CM1 by the multiplexer MX as a second failure determination signal representing whether a short-circuit failure or a current leakage failure occurs in the second source line group [S (p+1) ~ St]. Further, the register RG4 holds a signal representing the level of the failure determination signal eX when the common wiring LB3 is connected to the comparator CM1 by the multiplexer MX as a third failure determination signal representing whether a short-circuit failure or a current leakage failure occurs in the third source line group [S (t+1) ~ Sn].

[0138] Then, the register RG4 supplies a failure location data signal FLD to the drive control section 11, which individually represents whether a failure occurs in each of the first to third source line groups.

[0139] Further, in the example shown in Figure 11 and ​ In the example shown, the amplifiers AX1 ~ Axn are divided into three amplifier groups, [AX1 ~ AXp], [AX (p+1) ~ AXt], and [AX (t+1) ~ AXn], and three common wirings LB1 ~ LB3 are used to connect the drains of the transistors QS included in each of the amplifier groups to each other, but the number thereof is not limited to three. In any case, it is sufficient to divide the first to nth amplifier circuits (AX1 ~ AXn) into first to kth (k is an integer of 2 or more and less than n) amplifier circuit groups each including at least one amplifier and individually connect the first to kth common wirings with respect to the first to kth amplifier circuit groups.

[0140] Further, in the above-described embodiment, the delay circuit DD1 generates the selection signal STB from the data introduction signal LOAD, but the drive control section 11 can directly generate the selection signal STB.

[0141] Explanation of Reference Numerals

[0142] 11: Drive control section

[0143] 13: Source driver

[0144] 20: Display panel

[0145] 100: display device

[0146] 1330: failure determination circuit

[0147] 1331: amplifier circuit

[0148] 1332: output current detection circuit

[0149] AM1 to AMn: amplifier

[0150] DC: differential unit

[0151] QS: transistor

[0152] R1: variable resistor

[0153] RG1: register

[0154] S1 to Sn: source line

Claims

1. A display driver, characterized in that, have: An amplifier circuit receives a grayscale voltage having a voltage value corresponding to the brightness level indicated by a video signal, and outputs an output current based on the grayscale voltage to the source line of the display panel, thereby supplying an output voltage having a voltage value corresponding to the grayscale voltage to the source line. The output current detection circuit generates a mirror current that replicates the output current and outputs an output current detection signal with a level corresponding to the current quantity of the mirror current. as well as The fault determination circuit determines whether a short circuit or current leakage fault has occurred in the source line by comparing the level of the output current detection signal output from the output current detection circuit with a predetermined threshold. The amplifier circuit includes: The differential unit generates a differential signal, the differential signal representing the difference between the grayscale voltage and the output voltage; and The first transistor receives the differential signal at its gate and outputs the output current from the first output node connected to its drain. The output current detection circuit includes: The second transistor receives the differential signal at its gate and outputs the mirrored current from the second output node connected to its drain; and A variable resistor, connected to the second output node, generates the output current detection signal at the second output node by the inflow of the mirrored current.

2. The display driver according to claim 1, characterized in that, Including registers that hold the adjustment values, The variable resistor adjusts the level of the output current detection signal according to the adjustment value held in the register.

3. The display driver according to claim 1 or 2, characterized in that, include: The data latch unit imports and outputs display data slices representing the brightness levels of each pixel based on the video signal at predetermined intervals. as well as The decoder unit converts the display data chip output from the data latch unit into a voltage with a voltage value corresponding to the brightness level shown by the display data chip, and supplies this voltage as the grayscale voltage to the output amplifier unit. The fault determination circuit determines whether a short circuit fault or current leakage fault has occurred in the source line based on the result of comparing the level of the output current detection signal with the predetermined threshold at a time point after a predetermined period from the predetermined timing point.

4. The display driver according to claim 3, characterized in that, If the level of the output current detection signal is greater than the specified threshold, the fault determination circuit determines that a short circuit fault or current leakage fault has occurred in the source line.

5. A display driver, characterized in that, have: The first to nth amplifier circuits receive first to nth grayscale voltages, each having a voltage value corresponding to the brightness level of each pixel indicated by the video signal. They generate first to nth output currents corresponding to the change in voltage value of each of the first to nth grayscale voltages, and output these first to nth output currents to the first to nth source lines of the display panel, thereby supplying first to nth output voltages to the first to nth source lines. The first to nth output voltages have voltage values ​​corresponding to the first to nth grayscale voltages, where n is an integer greater than or equal to 2. The first to nth output current detection circuits generate first to nth mirror currents that respectively replicate the first to nth output currents, and output first to nth output current detection signals with levels corresponding to the current quantities of the first to nth mirror currents; and The fault determination circuit determines whether there is a short circuit or current leakage fault in the first to nth source lines based on the first to nth output current detection signals output from the first to nth output current detection circuits. Each of the first to nth amplifier circuits includes: The differential unit generates a differential signal, the differential signal representing the difference between the grayscale voltage and the output voltage; and The first transistor receives the differential signal at its gate and outputs the output current from the first output node connected to its drain. Each of the first to nth output current detection circuits includes: The second transistor receives the differential signal at its gate and outputs the mirrored current from the second output node connected to its drain; and A variable resistor, connected to the second output node, generates the output current detection signal at the second output node by the inflow of the mirrored current.

6. The display driver according to claim 5, characterized in that, The fault determination circuit individually determines whether a short circuit fault or current leakage fault has occurred in the first to nth source lines by comparing the levels of the first to nth output current detection signals output from the first to nth output current detection circuits with a predetermined threshold.

7. The display driver according to claim 5, characterized in that, The fault determination circuit divides the first to nth output current detection signals output from the first to nth output current detection circuits into first to rth output current detection signal groups, each consisting of multiple output current detection signals. For each of the first to rth output current detection signal groups, a representative output current detection signal is selected from the output current detection signal group. The level of the selected output current detection signal is compared with a predetermined threshold. Thus, based on the source line group corresponding to the output current detection signal group to which the output current detection signal belongs, a determination is made as to whether a short circuit fault or current leakage fault has occurred, where r is an integer greater than or equal to 2.

8. A display device comprising: The display panel has display units arranged in each intersection of the first to nth source lines and multiple gate lines, wherein... n is an integer greater than 2; and The display driver drives the display panel based on the video signal. Its features are, The display driver has: The first to nth amplifier circuits receive first to nth grayscale voltages, each having a voltage value corresponding to the brightness level of each pixel indicated by the video signal. They generate first to nth output currents corresponding to the change in voltage value of each of the first to nth grayscale voltages, and output these generated first to nth output currents to the first to nth source lines of the display panel, thereby supplying first to nth output voltages to the first to nth source lines. The first to nth output voltages have voltage values ​​corresponding to the first to nth grayscale voltages, respectively. The first to nth output current detection circuits generate first to nth mirror currents that respectively replicate the first to nth output currents, and output first to nth output current detection signals with levels corresponding to the current quantities of the first to nth mirror currents; and The fault determination circuit individually determines whether a short circuit fault or current leakage fault has occurred in the first to nth source lines by comparing the levels of the first to nth output current detection signals output from the first to nth output current detection circuits with predetermined thresholds. Each of the first to nth amplifier circuits includes: The differential unit generates a differential signal, the differential signal representing the difference between the grayscale voltage and the output voltage; and The first transistor receives the differential signal at its gate and outputs the output current from the first output node connected to its drain. Each of the first to nth output current detection circuits includes: The second transistor receives the differential signal at its gate and outputs the mirrored current from the second output node connected to its drain; and A variable resistor, connected to the second output node, generates the output current detection signal at the second output node by the inflow of the mirrored current.

9. A display driver, characterized in that, have: The first to nth amplifier circuits receive first to nth grayscale voltages, each having a voltage value corresponding to the brightness level of each pixel indicated by the video signal. They generate first to nth output currents corresponding to the change in voltage value of each of the first to nth grayscale voltages, and output these first to nth output currents to the first to nth source lines of the display panel, thereby supplying first to nth output voltages to the first to nth source lines. The first to nth output voltages have voltage values ​​corresponding to the first to nth grayscale voltages, where n is an integer greater than or equal to 2. The fault determination circuit determines whether a short circuit or current leakage fault exists on the first to nth source lines; and A common wiring connection is provided, which is used to connect to each of the first to nth amplifier circuits. Each of the first to nth amplifier circuits includes: The differential unit generates a differential signal, which represents the difference between the grayscale voltage and the output voltage; The first transistor receives the differential signal at its gate and outputs the output current from its drain; and The second transistor receives the differential signal at its gate and sends a mirrored current to the common wiring, the mirrored current replicating the output current from the first transistor. The fault determination circuit includes: A variable resistor, connected to the common wiring, generates an output current detection signal on the common wiring by allowing current to flow through it, the current being synthesized from the mirrored currents delivered from the second transistors of the respective first to nth amplifier circuits; and The comparator determines whether a short circuit or current leakage fault has occurred in the first to nth source lines by comparing the level of the output current detection signal with a predetermined threshold.

10. The display driver according to claim 9, characterized in that, Including registers that hold the adjustment values, The variable resistor adjusts the level of the output current detection signal according to the adjustment value held in the register.

11. The display driver according to claim 9 or 10, characterized in that, include: The data latch unit imports and outputs first to nth display data slices representing the brightness levels of each pixel based on the video signal at predetermined time intervals. as well as The decoder unit converts the first to nth display data slices output from the data latch unit into n voltages, each having a voltage value corresponding to the brightness level indicated by the display data slices, and supplies these n voltages as the first to nth grayscale voltages to the first to nth amplifier circuits. The fault determination circuit determines whether a short circuit fault or current leakage fault has occurred in the source line based on the result of comparing the level of the output current detection signal with the predetermined threshold at a time point after a predetermined period from the predetermined timing point.

12. The display driver according to claim 11, characterized in that, If the level of the output current detection signal is greater than the specified threshold, the fault determination circuit determines that a short circuit fault or current leakage fault has occurred in at least one of the first to nth source lines.

13. A display driver, characterized in that, have: The first to nth amplifier circuits receive first to nth grayscale voltages, each having a voltage value corresponding to the brightness level of each pixel indicated by the video signal. They generate first to nth output currents corresponding to the change in voltage value of each of the first to nth grayscale voltages, and output these first to nth output currents to the first to nth source lines of the display panel, thereby supplying first to nth output voltages to the first to nth source lines. The first to nth output voltages have voltage values ​​corresponding to the first to nth grayscale voltages, where n is an integer greater than or equal to 2. The fault determination circuit determines whether a short circuit or current leakage fault exists on the first to nth source lines; and The first to kth common wiring divides the first to nth amplifier circuits into at least one first to kth amplifier circuit group to which the amplifier circuit belongs, and connects them individually to the first to kth amplifier circuit groups, where k is an integer greater than or equal to 2 and less than n. Each of the first to nth amplifier circuits includes: The differential unit generates a differential signal, which represents the difference between the grayscale voltage and the output voltage; The first transistor receives the differential signal at its gate and outputs the output current from its drain; and The second transistor receives the differential signal at its gate and sends a mirrored current to the common wiring of the amplifier circuit group to which it belongs in the first to kth common wiring. The mirrored current replicates the output current sent from the first transistor. The fault determination circuit includes: The multiplexer selects the first to the kth common wiring one by one and connects the selected common wiring to the output node; A variable resistor, connected to the output node, generates an output current detection signal at the output node by allowing current to flow through the common wiring, the multiplexer, and the output node. This current is synthesized from the mirrored currents from the respective second transistors of the amplifier circuits. The comparator determines whether a short circuit or current leakage fault has occurred in the first to nth source lines by comparing the level of the output current detection signal with a predetermined threshold.

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