Unselected sub-block source lines and bit lines are pre-charged to reduce read disturbance

Abstract

The present disclosure relates to pre-charging of non-selected sub-block source lines and bit lines to reduce read disturbance. A memory device includes a non-selected sub-block including a bit line, a drain select (SGD) transistor coupled with the bit line, a source voltage line, a source select (SGS) transistor coupled with the source voltage, and a word line coupled with a gate of a cell string having a channel coupled between the SGS / SGD transistors. Control logic coupled with the non-selected sub-block operates to turn on the SGD / SGS transistors to prepare for a read operation when a plurality of word lines are ramped from a ground voltage to a pass voltage associated with a non-selected word line, pre-charge the channel by ramping voltages on the bit line and the source voltage line to a target voltage greater than a source read voltage level while the word lines are being ramped, and turn off the SGD transistor and the SGS transistor in response to the word line reaching the pass voltage to cause the channel to be pre-charged to the target voltage during the read operation.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to precharging unselected subblock source lines and bit lines to reduce read interference. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may use the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to an aspect of this application, a memory device is provided. The memory device includes: a non-selected sub-block comprising: a bit line; a drain-select (SGD) transistor coupled to the bit line; a source voltage line; a source-select (SGS) transistor coupled to the source voltage line; and a plurality of word lines coupled to the gates of a string of memory cells, wherein the string of memory cells includes a channel coupled between the SGS transistor and the SGD transistor; and control logic operatively coupled to the non-selected sub-block, the control logic performing operations including: turning on the SGD transistor and the SGS transistor to prepare for a read operation when the plurality of word lines are slew from a ground voltage to a pass voltage associated with the non-selected word lines; pre-charging the channel by slewing the voltages on the bit line and the source voltage line to a target voltage greater than the source read voltage level when the plurality of word lines are slew; and turning off the SGD transistor and the SGS transistor in response to the plurality of word lines reaching the pass voltage, so that the channel is pre-charged to the target voltage during the read operation.

[0004] According to another aspect of this application, a method is provided. The method includes: turning on a bit-line-coupled drain-select (SGD) transistor to prepare for a read operation when a plurality of word lines coupled to the gates of a memory cell string are slopped from a ground voltage to a pass voltage associated with an unselected word line; turning on a source-select (SGS) transistor coupled to a source voltage line when the plurality of word lines are slopped, wherein the memory cell string is coupled between the SGD transistor and the SGS transistor and belongs to an unselected sub-block; pre-charging the channel of the memory cell string by slopping the voltages on the bit lines and the source voltage line to a target voltage greater than the source read voltage level when the plurality of word lines are slopped; and turning off the SGD transistor and the SGS transistor in response to the plurality of word lines reaching the pass voltage, so that the channel is pre-charged to the target voltage during the read operation.

[0005] According to another aspect of this application, a method is provided. The method includes: turning on a bit-line-coupled drain-select (SGD) transistor to prepare for a read operation when a plurality of word lines coupled to the gates of a memory cell string are slopped from a ground voltage to a pass voltage associated with an unselected word line; turning on a source-select (SGS) transistor coupled to a source voltage line when the plurality of word lines are slopped, wherein the memory cell string is coupled between the SGD transistor and the SGS transistor and belongs to an unselected sub-block; pre-charging the channel of the memory cell string by slopping the voltages on the bit lines and the source voltage line to a target voltage greater than a source read voltage level when the plurality of word lines are slopped; and turning off the SGD transistor and the SGS transistor in response to the plurality of word lines reaching the pass voltage to pre-charge the channel to the target voltage during the read operation; and discharging the source voltage line to the source read voltage level after the SGS transistor is turned off. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of some embodiments thereof.

[0007] Figure 1A An example computing system including a memory subsystem is shown according to some embodiments.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller according to an embodiment.

[0009] Figure 2 According to the embodiments, see reference Figure 1B A schematic diagram of a portion of the memory cell array used in the described type of memory.

[0010] Figure 3A This is a schematic diagram of two segments of a memory cell array according to at least some embodiments, wherein selected segments and non-selected segments share word lines.

[0011] Figure 3B for Figure 3A A modified schematic diagram of two sub-blocks, showing read signal sources associated with selecting word lines in the selected sub-block and potential read interference to the non-selected sub-block, according to at least some embodiments.

[0012] Figure 4 The images are a series of side views of a string of memory cells having a common channel within a non-selected sub-block, according to at least some embodiments, illustrating a method for pre-charging the source lines and bit lines of the non-selected sub-block to reduce read interference.

[0013] Figure 5 A graphic illustrating the signal waveforms of various components controlling a non-selected sub-block according to various embodiments.

[0014] Figure 6 A flowchart of an example method for precharging non-selected sub-block source lines and bit lines to reduce read interference according to at least some embodiments.

[0015] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0016] Embodiments of this disclosure relate to pre-charging the source lines and bit lines of unselected subblocks to reduce read interference. In some memory devices, a segmented select-gate-source (SGS) architecture is employed, allowing physical segments of a subblock to be selected individually for programming or reading data from it. Initially, this segmented SGS (or SSGS) architecture was used to mitigate field-assisted (Fowler-Nordheim) (FN) tunneling read interference. However, read interference can still occur in unprogrammed or erased cells connected to unselected word lines of the same physical block, but this read interference is more likely to occur in cells of unselected subblocks sharing word lines with selected subblocks. Here, it can be understood that unselected subblocks are located in different physical segments than selected subblocks. When a voltage applied to the bit line (e.g., a data line) ramps up while the drain-select transistor and source-select transistor are turned on, the subblock is "selected" so that the memory cell at the selected word line can be read.

[0017] During a read operation, the voltage of the unselected word line can be skewed or even higher than that of the selected word line, resulting in a high electric field across the tunnel oxide layer. This can cause electrons to tunnel from the substrate channel of the unselected word line to the gate of the memory cell. The threshold voltage of the erased cell increases, and in severe cases, the cell is unintentionally programmed due to interference caused by the read operation.

[0018] Regarding read operations within a sub-block in the SSGS architecture, the word line of the sub-block is boosted during the voltage ramp-up (Vpass) after the channel is floated, for example, to further boost the channel and prevent FN tunneling. For example, the channel could be a common channel shared with the string of memory cells within the sub-block. The channel potential (Vpass) of the sub-block within the SSGS... channelThe channel potential can be modulated by timing the signals sent to the source select line and drain select line (SGS / SGD), which are coupled to the SGS / SGD transistor. However, the challenge lies in the difficulty of accurately controlling the channel potential due to variations in word line resistivity (RC), differences in the SGS / SGD transistor threshold voltage (Vt), and variations in the SGS / SGD resistivity. Inability to control the channel potential can lead to hot carrier injection into the channel (or "hot-e"), causing specific problems in unselected subblocks, for example, due to localized potential differences around selected word lines. For this reason, SSGS is typically disabled on these memory devices to prevent hot carrier injection problems. For large memory layers, full block read interference (FBRD) can be a reliability limiter.

[0019] As described above, aspects of this disclosure address the aforementioned and other drawbacks by reducing the bias difference between the word line and the channel of memory cells in unselected subblocks, thereby reducing FN tunneling read interference without raising the channel potential. More specifically, the control logic of the memory device can turn on the SGD transistor and SGS transistor to prepare for a read operation as the word line is slopped from ground voltage to an intermediate voltage and finally to the pass voltage (Vpass) associated with the unselected word line. During word line slopping, the control logic can further precharge the channel by slopping the voltages on the bit line and source voltage line to a target voltage greater than the source read voltage level (e.g., approximately 0.5V to 2.0V higher). This is understood to mean the default source read voltage level typically supplied to the source voltage line during a read operation. The control logic can then turn off the SGD transistor and SGS transistor in response to the word line reaching the pass voltage, so that the channel is precharged to the target voltage during the read operation. In this way, by pre-charging the channels of the memory cell strings in the unselected sub-blocks, the channel potential is higher, and the aforementioned bias difference between the word lines of the memory cells and the channels is minimized. The control logic can selectively control the target pre-charge voltage level of the channels to minimize this bias.

[0020] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, maintaining the ability to enable SSGS on a memory device while precisely controlling the channel potential through the pre-charge described above. Precise channel potential control means that hot electron problems can be mitigated, for example, by small changes in the control waveform. Furthermore, since pre-charging can be performed in parallel with other read-related operations, there is no anticipated performance impact. Those skilled in the art will appreciate other advantages of the read command processing optimization within the memory device discussed below.

[0021] Figure 1AExample computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. Memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0022] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory units (“units”). The unit is an electronic circuit for storing information. Depending on the unit type, a unit may store one or more bits of binary information and has various logic states associated with the number of bits being stored. The logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0023] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device supporting Internet of Things (IoT) functionality, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0026] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A An example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 can provide data to be stored at the memory subsystem 110 and can request data to be retrieved from the memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0027] Host system 120 may include a processor chipset and software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0028] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can also utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A Memory subsystem 110 is shown as an example. Typically, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0029] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on variations in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, crosspoint non-volatile memory allows for in-place write operations, unlike many flash-based memories, where non-volatile memory cells can be programmed without prior erasing. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0032] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0033] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1A The example memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0036] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] In some embodiments, memory device 130 includes page buffer 152, which provides circuitry for programming data into and reading data from memory cells of memory device 130. As will be explained in detail, the control logic of local media controller 135 may be adapted to coordinate the timing of precharging the channel potential of unselected subblocks.

[0040] Figure 1BA first device in the form of a presenting memory device 130 according to an embodiment and a presenting memory subsystem (e.g., Figure 1A A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0041] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells arranged in logical rows are typically connected to the same access line (e.g., a word line), while memory cells arranged in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown in the image) can be programmed to one of at least two target data states.

[0042] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 104. The memory device 130 also includes an input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to the memory device 130, as well as outputs of data and status information from the memory device 130. An address register 114 communicates with the I / O control circuitry 112, as well as the row decoding circuitry 108 and column decoding circuitry 111, to latch the address signal before decoding. A command register 124 communicates with the I / O control circuitry 112 and the local media controller 135 to latch incoming commands.

[0043] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control them in response to addresses.

[0044] The local media controller 135 also communicates with cache register 118 and data register 121. Cache register 118 latches incoming or outgoing data, such as that initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be transferred from cache register 118 to data register 121 for transmission to the memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During a read operation, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer 152 of memory device 130 (e.g., at least a portion thereof). Page buffer 152 may further include sensing devices (e.g., a sensing amplifier) ​​to sense the data status of the memory cells of memory cell array 104, for example by sensing the status of data lines connected to the memory cells. Status register 122 may communicate with I / O control circuitry system 112 and local memory controller 135 to latch status information for output to memory subsystem controller 115.

[0045] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0046] For example, commands can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. Addresses can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data can then be written to data register 121 for programming memory cell array 104.

[0047] In this embodiment, the cache register 118 may be omitted, and data may be written directly to the data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0048] Those skilled in the art will understand that additional circuitry and signals can be provided, and the process has been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device can be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0049] Figure 2 For example, it can be included as part of memory cell array 104 according to an embodiment in reference. Figure 1B A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the type of memory described. The memory array 200A includes, for example, word lines 2020 to 202. N Access lines such as bit lines 2040 to 204M Such data cables. The word line 202 can be connected in a many-to-one relationship to... Figure 2 Global access lines (e.g., global word lines) not shown. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0050] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 208 in each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as the select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). M Between one of them (for example, it could be a drain-select transistor, often referred to as the select gate drain). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as the source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent multiple select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0051] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 in the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0052] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the selected gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0053] Figure 2 The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2 The memory array 200A in the memory array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, which may be substantially parallel to the plane containing the common source 216.

[0054] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as... Figure 2 As shown. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases, forms) a word line 202.

[0055] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given positioning line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202 NFurthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, memory cells 208 selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cell 208 (e.g., odd memory cell).

[0056] Although Figure 2 Bit lines 2043-2045 are not explicitly depicted in the figure, but it is evident from the figure that bit line 204 of the memory cell array 200A can be connected from bit line 2040 to bit line 204. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, references to memory cell pages herein refer to the memory cells of the logical pages of the memory cells. This is in conjunction with the discussion of NAND flash memory. Figure 2 Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0057] Figure 3A This is a schematic diagram of two segments of a memory cell array 300A according to at least some embodiments, wherein selected and non-selected segments share word lines. For example, in an SSGS architecture, a string of memory cells may be divided into sub-blocks, wherein in some embodiments, each SGS segment contains two sub-blocks. A first (e.g., selected) SGS segment may include a first sub-block 3050 and a second sub-block 3051. A second (e.g., non-selected) SGS segment may include a third sub-block 3052 and a fourth sub-block 3053. In other embodiments, a segment may contain other numbers of sub-blocks.

[0058] Specifically, in at least some embodiments, Figure 3AThe memory cell array 300A includes bit lines 304, with each sub-block coupled to bit lines 304. A first sub-block 3050 (assumed to be a selected sub-block for ease of explanation) may include a first drain-select (SGD) transistor 3120, a first source-select (SGS) transistor 3100, and a first memory cell string 3060 coupled therebetween. A second sub-block 3051 may include a second SGD transistor 3121, a second SGS transistor 3101, and a second memory cell string 3061 coupled therebetween. A third sub-block 3052 may include a third SGD transistor 3122, a third SGS transistor 3102, and a third memory cell string 3062 coupled therebetween. A fourth sub-block 3053 may include a fourth SGD transistor 3123, a fourth SGS transistor 3103, and a fourth memory cell string 3063 coupled therebetween. For example, a third memory cell string 3062 contained in a non-selected SGS segment may contain multiple memory cells 3080…308… N Each SGS transistor can be connected to a common source (SRC), such as a source voltage line, to supply power to multiple memory cells 3080…308. N The source provides a voltage. In some embodiments, the source voltage line includes a source plate that provides the source voltage. In at least some embodiments, a plurality of word lines (WL) are coupled to the gate of the memory cell of each memory cell string 3060…3063. Each memory cell string includes a channel 316 coupled between the SGS transistor and the SGD transistor of the sub-block, wherein the channel 316 in… Figure 4 The clearest one.

[0059] In these embodiments, a first drain-select gate line (SGD0) can be connected to the gate of a first SGD transistor 3120, a second drain-select gate line (SGD1) can be connected to the gate of a second SGD transistor 3121, a third drain-select gate line (SGD2) can be connected to the gate of a third SGD transistor 3122, and a fourth drain-select gate line (SGD3) can be connected to the gate of a fourth SGD transistor 3123. Furthermore, a first source-select gate line (SGS0) can be connected to the gates of a first SGS transistor 3100 and a second SGS transistor 3101. Additionally, a second source-select gate line (SGS1) can be connected to the gates of a third SGS transistor 3102 and a fourth SGS transistor 3103. Therefore, the source voltage of each memory cell string can be jointly controlled by the source select gate line (SGS0 or SGS1) for individual segments, thereby creating an SSGS architecture, where the first segment is a combination of the first sub-block 3050 and the second sub-block 3051, and the second segment is a combination of the third sub-block 3052 and the fourth sub-block 3053.

[0060] Figure 3B for Figure 3A A modified schematic diagram of two sub-blocks is shown, illustrating read signal sources associated with word lines in the selected sub-block according to at least some embodiments, and potential read interference to non-selected sub-blocks. For ease of explanation, it is assumed that the first sub-block 3050 is the selected sub-block, and the third sub-block 3052 is the non-selected sub-block. Read interference can occur on memory cells connected to non-selected word lines located within either the selected sub-block 3050 or the non-selected sub-block 3052. The fact that the SGD line has turned off the third SGD transistor 3122 indicates, for example, that the third sub-block 3052 is non-selected.

[0061] In various embodiments, read interference can be caused by a voltage bias between the pass voltage (Vpass) applied to the unselected word line and the source voltage (V_source) applied to the common source (SRC) terminal of the channel. Therefore, one way to reduce this bias to mitigate (and potentially eliminate) FN tunneling read interference is to reduce the voltage between the gate / WL of the memory cell in the unselected subblock 3122 and the channel of the memory cell, wherein bit line 304 is disconnected by turning off the second SGD transistor 3121. One way to reduce this bias is to precharge the channel after the Vpass ramp-up, thereby turning off the second SGD transistor 3122 and the second SGS transistor 3102 in the unselected subblock (e.g., the third subblock 3052). This thereby avoids the need to boost the channel during the Vpass ramp-up, which could potentially lead to anomalies in the uncontrollable channel potential.

[0062] Figure 4 The image shows a series of side views of a string of memory cells, such as a third memory cell string 3062, having a common channel 316 within a non-selected sub-block according to at least some embodiments. It illustrates a method 400 for pre-charging the source lines and bit lines of the non-selected sub-block to reduce read interference. This method 400 can typically be used with non-selected sub-blocks (e.g., ... Figures 3A-3B The method 400 is executed in three different phases of the read operation associated with the third sub-block 3052. The method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, by Figure 1A-1B The control logic of the local media controller 135 executes the method 400.

[0063] Figure 5 To illustrate the signal waveforms of various components controlling non-selected sub-blocks (and selected sub-blocks) according to various embodiments, in Figure 4This figure will also be referenced in the discussion. The waveform from top to bottom includes the bit line (BL), the selected SGD signal (selected SGD), the non-selected SGD signal (non-selected SGD), the non-selected word line signal (non-selected WL), the selected SGS segment signal (selected SGS segment), the non-selected SGS segment signal (non-selected SGS segment), and the common source (SRC), which is also referred to as the source voltage line in this article for clarity.

[0064] In at least some embodiments, and with reference to Figure 4-5 The first stage 410 of method 400 includes control logic that activates (e.g., turns on) SGD transistor 3122 and SGS transistor 3102 to prepare for a read operation when the word line (WL) is ramped from ground voltage to an intermediate voltage and finally ramped to a pass voltage (Vpass) associated with the unselected word line. This first stage 410 can generally be understood as... Figure 5 Before the "pre-charge" phase in the curve. In addition, the source read voltage (on the source voltage line or SRC) and the voltage on the bit line (at BL) can be scaled toward a target voltage (about Vh) that is higher than the normal voltage level of these lines.

[0065] In these embodiments, the second stage 420 of method 400 includes control logic that, when the word line is slopped, precharges channel 316 by sloping the voltages on the bit line (BL) and the source voltage line (SRC) to a target voltage (approximately Vh) greater than the source read voltage level. In various embodiments, the target voltage (approximately Vh) is approximately 0.5V to 2.0V higher than the source read voltage level, where the target voltages on the bit line and the source voltage line can vary within approximately 10% of each other, thus Vh indicates an approximation. In one embodiment, the target voltage is between 0.8 volts (V) and 1.5 volts (V), or approximately twice the through voltage Vpass. The actual value of the target voltage may depend on the value of the source read voltage level typically supplied to the unselected subblock. While the SGD transistor 3122 is typically turned off, keeping the SGD transistor 3122 and the SGS transistor 3102 active allows the source voltage line and bit line to continue sloping so that channel 316 is fully precharged.

[0066] In some embodiments, pre-charging the channel 316 involves a voltage ramp on the bit line (BL) followed by a voltage ramp on the source voltage line (SRC), and this ramp on the source voltage line can be delayed until... Figure 5 The pre-charge phase is indicated by the dashed line. In another embodiment, pre-charging the channel involves ramping the voltage on the source voltage line (SRC) followed by ramping the voltage on the bit line (BL), and thereby delaying the ramp of the BL voltage until... Figure 5The pre-charge phase is indicated by the dashed line. Furthermore, in some embodiments, the pre-charge phase may include a voltage ramp of one or both of the source voltage line (SRC) or bit line (BL) after the word line voltage ramps. In some embodiments, the source voltage line (SRC) ramps to a target voltage (e.g., about Vh), and after the SGS transistor is turned off, the source voltage line discharges to the source read voltage level. Similarly, in these embodiments, after the bit line (BL) voltage ramps to approximately the target voltage (about Vh), the bit line voltage is discharged until the default drain read voltage level (shown by the dashed line) is reached, which is typically used in read operations.

[0067] In at least some embodiments, the third stage 430 of method 400 includes control logic deactivating (e.g., turning off) SGD transistor 3122 and SGS transistor 3102 in response to a word line reaching the pass voltage (Vpass) to precharge channel 316 to a target voltage (approximately Vh) during a read operation. Turning off the SGD and SGS transistors can occur before discharging the source voltage lines, e.g., discharging to the read source voltage level. In some embodiments, the control logic implements a delay before turning off SGD transistor 3122 and SGS transistor 3102 to ensure the channel is fully precharged to the target voltage. In these embodiments, the potential (e.g., voltage level) of channel 316 can be precisely controlled by precharging channel 316 from the SRC and BL lines at the start of a read operation. Precise channel potential means that hot electron problems can be mitigated. For example, only small changes in the waveform may be required (see...). Figure 5 This can avoid the hot electron problem.

[0068] In some embodiments, in response to a word line reaching a pass voltage, method 400 further includes control logic to maintain the bit line voltage at a target voltage and to discharge the source voltage line to a read voltage level, for example, approximately half the target voltage or approximately Vh / 2, said read voltage level may be approximately 0.5V to 2.0V lower than Vh. Furthermore, method 400 may also include control logic to select a word line from a second set of word lines from a selected subblock, wherein data is read from a memory cell coupled to the selected word line in response to a read operation.

[0069] Figure 6 This is a flowchart of an example method 600 for precharging non-selected sub-block source lines and bit lines to reduce read interference according to at least some embodiments. Method 600 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, it is performed by… Figure 1A-1BThe local media controller 135 executes the method 600. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0070] At operation 610, the SGD transistor is turned on. For example, when the processing logic slews multiple word lines coupled to the gates of the memory cell string from ground voltage to a pass voltage associated with an unselected word line, it activates (i.e., turns on) the drain-select (SGD) transistor coupled to the bit line to prepare for a read operation.

[0071] At operation 620, the SGS transistor is turned on. For example, when the processing logic skews multiple word lines, it activates (i.e., turns on) the source selection (SGS) transistor coupled to the source voltage line, where the memory cell string is coupled between the SGD transistor and the SGS transistor and belongs to the unselected sub-block.

[0072] At operation 630, the channel is pre-charged. For example, when the processing logic skews multiple word lines, it pre-charges the channel of the memory cell string by skewing the voltages on the bit lines and source voltage lines to a target voltage greater than the source read voltage level.

[0073] At operation 640, the SGD transistor and SGS transistor are turned off. For example, in response to multiple word lines reaching through voltage, the processing logic deactivates (i.e., turns off) the SGD transistor and SGS transistor to precharge the channel to the target voltage during a read operation.

[0074] At operation 650, in some embodiments, the SGS transistor is turned off. For example, in these embodiments, in response to multiple word lines reaching a pass voltage, the processing logic causes the source voltage line to discharge to the source read voltage level after the SGS transistor is turned off. Additionally, the voltage on the bit line may also discharge to the drain read voltage level.

[0075] Figure 7 An example machine of computer system 700 is shown, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1A (Operation of the memory subsystem controller 115). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0076] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is shown, it should also be understood that the term "machine" includes any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0077] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0078] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 728 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0079] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 728 or software embodying any one or more of the methods or functions described herein are stored. Data storage system 718 may further include the previously discussed local media controller 135 and page buffer 152. Instructions 728 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1A The memory subsystem 110.

[0080] In one embodiment, instruction 726 includes instructions for implementing a controller (e.g., Figure 1A The memory subsystem controller 115) provides functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0081] Some parts of the previously described description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. Algorithms here are generally considered as self-consistent sequences of operations that produce desired results. These operations are those requiring physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0082] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0083] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0085] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0086] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A memory device comprising: The non-selected sub-blocks include: Bit line; A drain-select (SGD) transistor coupled to the bit line; Source voltage line; A source-select (SGS) transistor coupled to the source voltage line; and Multiple word lines coupled to the gates of memory cell strings, wherein the memory cell strings include channels coupled between the SGS transistor and the SGD transistor; and Control logic, which is operatively coupled to the non-selected sub-block, performs operations including the following: When the plurality of word lines are slew from ground voltage to pass voltage associated with the non-selected word line, the SGD transistor and the SGS transistor are turned on to prepare for a read operation. When skewing the plurality of word lines, the channel is pre-charged by skewing the voltages on the bit lines and the source voltage lines to a target voltage greater than the source read voltage level; and In response to the plurality of word lines reaching the pass voltage, the SGD transistor and the SGS transistor are turned off so that the channel is precharged to the target voltage during the read operation.

2. The memory device of claim 1, wherein the target voltage is approximately 0.5 V to 2.0 V higher than the source read voltage level.

3. The memory device of claim 1, wherein the target voltage is approximately 0.8 V to 1.5 V higher than the source read voltage level.

4. The memory device of claim 1, wherein, In response to the plurality of word lines reaching the through voltage, the operation further includes: Maintain the voltage of the bit line at the target voltage; and Discharge the source voltage line to the source to read the voltage level.

5. The memory device of claim 4, wherein turning off the SGD transistor and the SGS transistor occurs before discharging the source voltage line.

6. The memory device of claim 1, wherein precharging the channel comprises scaling the voltage of the bit line after scaling the source voltage line.

7. The memory device of claim 1, wherein precharging the channel comprises sloping the voltage on the bit line after sloping the voltage on the bit line.

8. A method of operating a memory device, the method comprising: When multiple word lines coupled to the gate of the memory cell string are slew from ground voltage to pass voltage associated with an unselected word line, the drain select (SGD) transistor coupled to the bit line is turned on to prepare for a read operation. When the plurality of word lines are skewed, the source selection (SGS) transistor coupled to the source voltage line is turned on, wherein the memory cell string is coupled between the SGD transistor and the SGS transistor and belongs to the unselected sub-block; When the plurality of word lines are skewed, the channels of the memory cell string are precharged by skewing the voltages on the bit lines and the source voltage lines to a target voltage greater than the source read voltage level. as well as In response to the plurality of word lines reaching the pass voltage, the SGD transistor and the SGS transistor are turned off so that the channel is precharged to the target voltage during the read operation.

9. The method of claim 8, wherein the target voltage is approximately 0.5V to 2.0V higher than the source read voltage level.

10. The method of claim 8, wherein the target voltage is approximately 0.8 V to 1.5 V higher than the source read voltage level.

11. The method of claim 8, wherein, In response to the plurality of word lines reaching the through voltage, the method further includes: Maintain the voltage of the bit line at the target voltage; and Discharge the source voltage line to the source read voltage level.

12. The method of claim 11, wherein turning off the SGD transistor and the SGS transistor occurs before discharging the source voltage line.

13. The method of claim 8, further comprising pre-charging the channel by sloping the voltage of one of the source voltage lines or the bit lines after sloping the voltage on the plurality of word lines.

14. The method of claim 8, wherein precharging the channel comprises sloping the voltage on the bit line after sloping the voltage on the bit line.

15. A method of operating a memory device, the method comprising: When multiple word lines coupled to the gate of the memory cell string are slew from ground voltage to pass voltage associated with an unselected word line, the drain select (SGD) transistor coupled to the bit line is turned on to prepare for a read operation. When the plurality of word lines are skewed, the source selection (SGS) transistor coupled to the source voltage line is turned on, wherein the memory cell string is coupled between the SGD transistor and the SGS transistor and belongs to the unselected sub-block; When the plurality of word lines are skewed, the channels of the memory cell string are precharged by skewing the voltages on the bit lines and the source voltage lines to a target voltage greater than the source read voltage level. as well as In response to the plurality of word lines reaching the pass voltage: Turn off the SGD transistor and the SGS transistor to precharge the channel to the target voltage during the read operation; and After turning off the SGS transistor, the source voltage line is discharged to the source read voltage level.

16. The method of claim 15, wherein the target voltage is approximately 0.5 V to 2.0 V higher than the source read voltage level.

17. The method of claim 15, wherein, In response to the plurality of word lines reaching the through voltage, the method further includes maintaining the voltage of the bit lines at the target voltage.

18. The method of claim 15, wherein after turning off the SGD transistor, the source voltage line is discharged to the source read voltage level.

19. The method of claim 15, wherein precharging the channel comprises sloping the voltage of the bit line after sloping the voltage of the source voltage line.

20. The method of claim 15, wherein pre-charging the trench includes ramping the voltage of the source voltage line after ramping the voltage on the bit line.

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