Method for testing electrical properties of a semiconductor device

Abstract

The application discloses a method for testing the electrical performance of a semiconductor device, which comprises the following steps: forming a first circuit layer on a first surface of a first substrate; forming a first test pad on the side of the first circuit layer away from the first substrate, the first test pad being electrically connected with part of the circuit layer; obtaining the electrical performance of the first circuit layer through the first test pad; and removing the first test pad. In this way, the first test pad can be used as a temporary pinning pad, and the electrical performance of each structure layer can be tested in real time in the front process or the intermediate process of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a method for testing the electrical performance of semiconductor devices. Background Technology

[0002] Integrated circuit manufacturing has a long cycle time and the value of a single wafer is high, making in-circuit testing of wafers particularly important. Currently, wafer electrical performance testing is mostly concentrated at fixed testing stations such as M1-WAT, M2-WAT, and Final-WAT, requiring large test pads to facilitate probe insertion. Probe penetration testing can determine whether wafer products meet the electrical specifications of the process technology platform, and the test data can serve as quality documentation for wafer product delivery.

[0003] However, there is currently a lack of effective and timely electrical testing methods for abnormalities occurring in the preceding or intermediate processes, which is detrimental to product yield. Summary of the Invention

[0004] The main technical problem solved by this application is to provide a method for testing the electrical performance of semiconductor devices, which can use the first test pad as a temporary pin pad to realize real-time detection of the electrical performance of each structural layer in the front-end or intermediate process of semiconductor device processing.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a method for testing the electrical performance of a semiconductor device, comprising: forming a first circuit layer on a first surface of a first substrate; forming a first test pad on a side of the first circuit layer away from the first substrate, wherein the first test pad is electrically connected to a portion of the circuits in the first circuit layer; obtaining the electrical performance of the first circuit layer through the first test pad; and removing the first test pad.

[0006] Unlike existing technologies, the beneficial effects of this application are as follows: The electrical performance testing method for semiconductor devices provided in this application includes: forming a first circuit layer on a first surface of a first substrate; forming a first test pad on the side of the first circuit layer away from the first substrate, wherein the first test pad is electrically connected to a portion of the circuits in the first circuit layer; obtaining the electrical performance of the first circuit layer through the first test pad; and removing the first test pad. Through this method, the first test pad can be used as a temporary pin pad, enabling real-time detection of the electrical performance of each circuit layer in the front-end or intermediate stages of semiconductor device processing. This solves the problem of the limitation that semiconductor devices can only be tested for electrical performance at fixed points. Removing the temporary pin pad after testing avoids any impact on the metal circuits in the subsequently formed structural layers. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0008] Figure 1 This is a flowchart illustrating the first embodiment of the electrical performance testing method for semiconductor devices according to this application;

[0009] Figure 2 yes Figure 1 A schematic diagram of the structure of an embodiment of step S101;

[0010] Figure 3 yes Figure 1 A schematic diagram of the structure of an embodiment of step S102;

[0011] Figure 4 yes Figure 3 Partial top view;

[0012] Figure 5 yes Figure 1 A schematic diagram of another embodiment of step S102;

[0013] Figure 6 yes Figure 1 A schematic diagram of the structure of an embodiment of step S104;

[0014] Figure 7 This is a flowchart illustrating the second embodiment of the electrical performance testing method for semiconductor devices according to this application;

[0015] Figure 8 yes Figure 7 A schematic diagram of the structure of an embodiment of step S201;

[0016] Figure 9 It is formed Figure 8 After the structure in the middle, proceed to step S102 - a structural schematic diagram of an embodiment;

[0017] Figure 10 It is formed Figure 9 After the structure in the middle, proceed to step S201 - a structural diagram of an embodiment;

[0018] Figure 11 It is formed Figure 10 After the structure in the middle, proceed to step S102 - a structural schematic diagram of an embodiment;

[0019] Figure 12 yes Figure 1 A schematic diagram of the structure forming the second test pad after step S104;

[0020] Figure 13 This is a flowchart illustrating the third embodiment of the electrical performance testing method for semiconductor devices according to this application;

[0021] Figure 14 yes Figure 13 A schematic diagram of the structure of one embodiment of steps S101 and S102;

[0022] Figure 15 yes Figure 13 A schematic diagram of the structure of an embodiment of step S301;

[0023] Figure 16 It is formed Figure 15 After the structure in the middle, proceed to step S102 - a structural diagram of an embodiment. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the electrical performance testing method for semiconductor devices according to this application. The electrical performance testing method for semiconductor devices according to this application may include the following steps S101-S104:

[0026] S101: A first circuit layer L1 is formed on the first surface a1 of the first substrate 1.

[0027] Please refer to the following: Figure 2 , Figure 2 for Figure 1The schematic diagram of the structure of one embodiment of step S101 shows that the first substrate 1 can be a substrate including, but not limited to, a single crystal, polycrystalline, or amorphous structure applied to semiconductors. It can be an intermediate product in the intermediate stage of wafer, ingot, or chip processing. It can be doped or undoped. Its material can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. It also includes multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), etc.

[0028] The first circuit layer L1 may include one or more overlapping patterned circuit layers (where multiple layers include two or more layers), which may be active or passive structures known to those skilled in the art for electrical connection, such as hybrid bonding structures, metal bumps, through-silicon via structures, redistribution layers, metal layers, etc. The circuit V in the first circuit layer L1 may be exposed from the surface a1 on the side of the first circuit layer L1 facing away from the first substrate 1, facilitating subsequent connection to the first test pad for electrical performance testing. The circuit structure of the circuit V can be designed according to actual process and product requirements. The first circuit layer L1 may include a chip area G1 and a test area G2, wherein the chip area G1 may include chip circuit V1 with a specific circuit structure for subsequent processing to form a chip; the test area G2 may be located in the dicing area adjacent to the chip area G1 and may include test circuit V2. By testing the electrical performance of the test circuit V2, it is possible to indirectly analyze whether the chip circuit V1 may have open circuits, short circuits, or leakage, determine whether the product meets the electrical specifications of the process technology platform, and evaluate the quality and stability of the semiconductor manufacturing process.

[0029] S102: A first test pad 2 is formed on the side of the first circuit layer L1 away from the first substrate 1, and the first test pad 2 is electrically connected to a portion of the circuit V in the first circuit layer L1.

[0030] Please refer to the following: Figures 3-5 , Figure 3 yes Figure 1 A schematic diagram of the structure of an embodiment in step S102. Figure 4 yes Figure 3 Partial top view in the image, with the top view direction being... Figure 3 In the direction D, Figure 5 yes Figure 1A schematic diagram of another embodiment of step S102.

[0031] In one embodiment, please refer to Figure 3 and Figure 4 Step S102 may include: forming a first test pad 2 on the side of the first circuit layer L1 located in the test area G2 away from the first substrate 1, wherein the number of first test pads 2 may be one or more. Figure 4 The top view shown only includes the portion between the dashed lines; the actual number of first test pads 2 could be greater than [a certain number]. Figure 4 As shown in the diagram (3), different first test pads 2 and their underlying lines V can form different conductive loops, thereby enabling comprehensive analysis of the electrical performance of line V. In this embodiment, the first test pad 2 can serve as a temporary pad electrically connected to the test line V2 in the test area G2. The electrical performance of the chip line V1 in the chip area G1 can be indirectly tested through the test area G2, avoiding damage to the chip line V1 in the chip area G1 during test pin insertion or subsequent removal of the first test pad 2. The first test pad 2 can be a continuous structure or can be made into a specific pattern to accommodate the test line V2. It can cover all the exposed lines of the test line V2 on the side facing away from the first substrate 1, or only cover the exposed portion of the test line V2 on the side facing away from the first substrate 1. Its shape, thickness, position, and quantity can all be selected based on the actual circuit structure of the test line V2 and the chip line V1. Figure 4 The test line V2 is covered by the first test pad 2, which is not shown in the figure.

[0032] In another embodiment, please refer to Figure 5 Step S102 may include: forming a first test pad 2 on the side of the first circuit layer L1 located in the chip region G1 away from the first substrate 1. The number of first test pads 2 can be one or more. The first test pad 2 is electrically connected to the chip circuit V1 in the chip region G1. This embodiment can directly test the electrical performance of the circuit V in the chip region G1, reducing the error of electrical performance testing. The first test pad 2 can be a continuous structure, or it can be adapted to the chip circuit V1 printed as a specific pattern. It can cover all the circuits exposed on the side of the chip circuit V1 away from the first substrate 1, or it can only cover the part of the circuits exposed on the side of the chip circuit V1 away from the first substrate 1. Its shape, thickness, position, number, etc. can all be selected according to the actual circuit structure of the chip circuit V1 and the test circuit V2.

[0033] Of course, in another embodiment, the first test pad 2 can also cover both chip line V1 and test line V2 at the same time.

[0034] The step of forming the first test pad 2 on the side of the first circuit layer L1 opposite to the first substrate 1 can be achieved by inkjet printing or screen printing. Inkjet printing or screen printing processes can form the first test pad 2 of any shape at any location as needed. By selecting materials, controlling the concentration, and adjusting the thickness and shape of the first test pad 2 during the inkjet / screen printing process, the resistance of the first test pad 2 can be effectively and freely controlled. Inkjet printing or screen printing offers high adaptability and flexibility, and is simple and efficient. Furthermore, in existing processes, the method of forming test pads typically involves magnetron sputtering metal onto the surface of the circuit layer using a mask to form metal pads, which are then removed by photolithography. Metal pads formed in this way have a tight contact with the underlying circuitry, making them difficult to remove. Residual metal pads can affect the metal circuitry structure, and even complete removal can easily damage the circuitry itself. In this application, the first test pad 2 is formed by inkjet printing or screen printing. Compared to the existing magnetron sputtering method, the bonding force between the first test pad 2 and the first circuit layer L1 is weaker. Therefore, under the same removal process (e.g., CMP polishing), the removal of the first test pad 2 formed by inkjet printing or screen printing has a relatively smaller impact on the surface of the circuit layer attached to the first test pad 2. In particular, when the first test pad 2 is an organic conductive material, it can also be removed directly by an asher (oxygen plasma etching) process, resulting in less damage to the surface of the circuit layer attached to the first test pad 2. Furthermore, if the first test pad 2 is formed by magnetron sputtering metal, a separate mask needs to be designed to accommodate the position and shape of the temporary pad, increasing preparation time and process costs. However, by using inkjet printing or screen printing to fabricate the first test pad 2 (the material can be metal, conductive organic material, or conductive inorganic material, etc.), temporary pads of any shape can be formed according to product characteristics, eliminating the need for a separate mask design, simplifying the process and reducing costs.

[0035] Semiconductor manufacturing processes include front-end, intermediate, and back-end processes. The front-end process fabricates various circuit components on a substrate without using metal materials. If the first test pad 2 uses a metal material, for example, by screen printing metal onto the surface of the first circuit layer L1 facing away from the first substrate 1, it may disrupt the metal-free environment, contaminate the processed surface, affect the bonding strength between the layers, and ultimately compromise the electrical performance of the final device. Therefore, in the front-end process, the material of the first test pad 2 can preferably be conductive organic or conductive inorganic materials. Furthermore, metal pads generally require photolithography for removal, which can leave residues, and photolithography can easily damage the metal lines in the substrate. Even with CMP polishing, a custom-made protective template is needed to protect the area without the first test pad 2, increasing process costs. Compared to metallic materials, conductive organic and inorganic materials do not excessively bond with the metal circuitry under the first test pad 2, and are easily removed by CMP (chemical mechanical polishing). This removal method is simple, highly efficient, and unlikely to damage the metal circuitry or contaminate the metal-free environment. Furthermore, the material of the first test pad 2 can preferably be a conductive organic material, as it can be efficiently and completely removed by an asher process, ensuring the cleanliness of the processed layer without damaging the substrate or the circuitry structure within it, thus guaranteeing the electrical performance of the final device. Since metallic materials such as solder joints have already been introduced in intermediate and subsequent processes, even if the first test pad 2 is made of metal, it still meets the process requirements for cleanliness in these two processes.

[0036] In some applications, the first test pad 2 can be an organic conductive material containing polar groups. Before step S102, the first circuit layer L1 can be surface-treated to contain functional groups on its surface that can react with the polar groups of the aforementioned organic conductive material. For example, in one embodiment, the material of the first test pad 2 can be a conductive organic material containing hydroxyl groups, such as aluminum octahydroxyquinoline. Before step S102, the side of the first circuit layer L1 facing away from the first substrate 1 can be hydroxylated. This forms hydroxyl groups on the surface of the first circuit layer L1 facing away from the first substrate 1. The organic conductive material and the hydroxyl groups on this surface can dehydrate and bond, thereby increasing the bonding force between the organic conductive material and the surface, improving the bonding strength between the first test pad 2 and the first circuit layer L1, and improving the accuracy of electrical performance testing. In another embodiment, the material of the first test pad 2 can be a conductive organic material containing carboxyl groups, such as a conductive polymer like poly(6-carboxylic acid indole). Before step S102, the side of the first circuit layer L1 facing away from the first substrate 1 can be hydroxylated. The carboxyl and hydroxyl groups can undergo dehydration condensation, thereby increasing the bonding force between the first test pad 2 and the first circuit layer L1. In one embodiment, the surface of the first circuit layer L1 facing away from the first substrate 1 can have an oxide layer. This oxide layer can be an ultrathin native oxide layer formed on the insulating matrix of the first circuit layer L1 other than line V. This oxide layer affects the bonding strength between the first test pad 2 and the first circuit layer L1. Therefore, after the hydroxylation treatment, the oxide layer on the surface of the first circuit layer L1 facing away from the first substrate 1 can be removed, thereby improving the bonding strength between the first test pad 2 and the first circuit layer L1 and improving the accuracy of electrical performance testing. The ultrathin native oxide layer can be removed by polishing using a CMP process.

[0037] S103: Obtain the electrical performance of the first circuit layer L1 through the first test pad 2.

[0038] First, the first contact resistance R1 between the first test pad 2 and the line V, the second contact resistance R2 between the first test pad 2 and the test probe, and the resistance R3 of the first test pad 2 can be obtained.

[0039] The difference in resistance measured between the existing pre-reserved test pad and the first test pad 2 in this application can be determined by the following factors: the difference in contact resistance between line V and the test pad, the difference in contact resistance between the test probe and the test pad, and the difference in resistance of the test pad itself. The difference in resistance of the test pad itself is easily determined by an electrical performance testing device. Alternatively, the resistance of the first test pad 2 can be effectively controlled by adjusting the material selection, concentration control, and the thickness and shape of the first test pad 2 during the inkjet / screen printing process, thus obtaining resistance R3. Of course, the resistance of the first test pad 2 itself can also be designed to be the same as that of the existing pre-reserved test pad, thereby eliminating the resistance difference of the test pad itself. Then, by constructing a two-variable linear inequality for the contact resistance between line V and the test pad, and the contact resistance between the test probe and the test pad, and after multiple measurements, the aforementioned first contact resistance R1 and second contact resistance R2 can be calculated.

[0040] After obtaining the resistance values ​​mentioned above, the total resistance of R1, R2, R3, and the line V electrically connected to the first test pad 2 can be obtained by contacting the test probe with the first test pad 2. For example, please refer to... Figure 4 Multiple pin puncture tests can be performed on any two of the multiple (including two or more) first test pads (for example, first perform pin puncture tests on two square first test pads 2, and then perform pin puncture tests on one square first test pad 2 and one round first test pad 2). Each test can yield a sum as described above. Based on the sums and the differences between R1, R2 and R3 corresponding to each first test pad 2, the resistance of the line V electrically connected to different first test pads 2 can be obtained, thereby enabling a comprehensive analysis of the line connection of the chip line V1.

[0041] This allows the first contact resistance R1 between the first test pad 2 and line V, the second contact resistance R2 between the first test pad 2 and the test probe, and the resistance R3 of the first test pad 2 to be included in the range of electrical performance measurement error, thereby improving the accuracy of electrical performance testing.

[0042] S104: Remove the first test pad 2.

[0043] Please refer to the following: Figure 6 , Figure 6 for Figure 1A schematic diagram of an embodiment of step S104 is shown (at this point, the first test pad 2 no longer exists on the first circuit layer L1; the dashed line in the figure only indicates the position of the first test pad 2 before removal). Preferably, the first test pad 2 can be chemically mechanically polished until the circuit V in the first circuit layer L1 is exposed. Chemical mechanical polishing can form a relatively flat surface and is less likely to cause serious mechanical damage to the metal circuit. In addition to CMP polishing of the first test pad 2, when the first test pad 2 is a conductive organic material, it can also be quickly removed by an asher process, and the asher process will not damage the substrate. When the first test pad 2 is an inorganic conductive material, the adhesive that binds the inorganic conductive organic material can also be dissolved by solvent corrosion, thereby removing the inorganic conductive organic material. When the first test pad 2 is metal, it can also be removed by photolithography.

[0044] In one application scenario, please refer to Figure 7 , Figure 7 This is a flowchart illustrating a second embodiment of the electrical performance testing method for semiconductor devices according to this application. This method can be used to test the electrical performance of different circuit layers sequentially formed in a semiconductor device. After removing the first test pad 2, the method may further include step S201: forming a second circuit layer L2 on the side of the first circuit layer L1 away from the first substrate 1; using the second circuit layer L2 as the first circuit layer L1, and returning to step S102. The second circuit layer L2 may include one or more overlapping patterned circuit layers (where multiple layers include two or more layers), and may be an active or passive structure known to those skilled in the art that provides electrical connection, such as a hybrid bonding structure, metal bump, through-silicon via structure, redistribution layer, metal layer, etc. Its circuit structure may be the same as or different from the first circuit layer L1.

[0045] For example, please refer to Figures 1-11 , Figure 8 yes Figure 7 A schematic diagram of the structure of an embodiment in step S201. Figure 9 It is formed Figure 8 Following the structure in step S102, we proceed to step S102, which is a structural diagram of an embodiment. Figure 10 It is formed Figure 9 Following the structure in step S201, we proceed to step S201, which presents a structural diagram of an embodiment. Figure 11 It is formed Figure 10 Following the structure in step S102, a structural schematic diagram of an embodiment is provided. In one embodiment, the electrical performance testing method for the semiconductor device may include the following steps: forming a first circuit layer L1 on the first surface a1 of the first substrate 1 (refer to...). Figure 2A first test pad 2 is formed on the side of the first circuit layer L1 away from the first substrate 1, and the first test pad 2 is electrically connected to a portion of the circuit V in the first circuit layer L1 (see reference). Figure 3 or Figure 5 ); Obtain the electrical performance of the first circuit layer L1 through the first test pad 2; Remove the first test pad 2 (refer to...) Figure 6 A second circuit layer L2 is formed on the side of the first circuit layer L1 away from the first substrate 1 (see reference). Figure 8 The second circuit layer L2 is used as the first circuit layer, and a first test pad 2 is formed on the side of the second circuit layer L2 away from the first substrate 1. The first test pad 2 is electrically connected to a portion of the circuit V in the first circuit layer L1. The first test pad 2 can be formed in the chip area G1 and / or the test area G2 (see reference). Figure 9 The electrical properties of the second circuit layer L2 are obtained through the first test pad 2; the first test pad 2 is removed; a third circuit layer L3 is formed on the side of the second circuit layer L2 away from the first substrate 1 (see reference). Figure 10 The second circuit layer L2 is used as the first circuit layer, and the third circuit layer L3 is used as the second circuit layer. A first test pad 2 is formed on the side of the third circuit layer L3 away from the first substrate 1. The first test pad 2 can be formed in the chip area G1 and / or the test area G2 (see reference). Figure 11 The electrical performance of the third circuit layer L3 is obtained through the first test pad 2; the first test pad 2 is then removed. The third circuit layer L3 may include one or more overlapping patterned circuit layers (where multiple layers include two or more layers), which can be active or passive structures known to those skilled in the art for electrical connection, such as hybrid bonding structures, metal bumps, through-silicon vias, redistribution layers, metal layers, etc. Its circuit structure may be the same as or different from the first circuit layer L1 and / or the second circuit layer L2. Using the above method, the electrical performance of each circuit layer can be tested promptly after the formation of the first circuit layer L1, the second circuit layer L2, and the third circuit layer L3. Of course, in other embodiments, one or more circuit layers can be formed on the third circuit layer L3 according to the above steps, and the first test pad 2 can be formed for testing. The number of circuit layers formed and on which circuit layer the first test pad 2 is formed can be adjusted according to actual process and product requirements.

[0046] Please refer to Figure 12 , Figure 12 yes Figure 1The schematic diagram of the structure of the second test pad formed after step S104 shows that, upon reaching the fixed testing stations such as M1-WAT, M2-WAT, and Final-WAT in semiconductor device processing, to avoid the influence of the first test pad 2 on subsequent processing steps, after removing the first test pad 2, the process may further include: electroplating metal on the surface of the second circuit layer L2 away from the substrate 1, and performing photolithography on the metal using a mask until the second test pad 3 is formed on the side of the test area G2 away from the substrate 1. The second test pad 3 can be electrically connected to the test line V2 in the test area G2. The second test pad 3 is more stable than the first test pad 2 and can be directly retained in the test area G2, which can avoid deformation of the test pad or impact on the electrical performance of the semiconductor device during subsequent processing.

[0047] In another application scenario, the electrical performance testing method of this semiconductor device can be used to test the electrical performance of the circuit layer located on the bonding surface of the bonding substrate. After removing the first test pad 2, the method may further include step S301: bonding the first substrate 1 to the second substrate 4 (the second substrate 4 may provide at least a circuit layer bonded to the first substrate 1; the second substrate 4 may be a substrate containing, but not limited to, a single crystal, polycrystalline, or amorphous structure applicable to semiconductors; it may be an intermediate product in the intermediate stage of wafer, ingot, or chip processing; it may be doped or undoped; and its material may be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compounds). The semiconductor material includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. The second substrate 4 may be the same as or different from the first substrate 1 in terms of material and / or structure. The line V on the side of the first circuit layer L1 away from the first substrate 1 is electrically connected to the line on the side of the second substrate 4 close to the first substrate 1; wherein, a second circuit layer L2 is provided on the side of the second substrate 4 away from the first substrate 1; then the second circuit layer L2 is used as the first circuit layer, and the process returns to step S102 to form the first test pad 2. Afterwards, the steps following S102 can continue. Please refer to [link / reference]. Figure 13 , Figure 13 This is a flowchart illustrating the third embodiment of the electrical performance testing method for semiconductor devices according to this application.

[0048] The circuit structure and number of circuit layers of the first circuit layer L1, the second circuit layer L2, and the circuit layer bonded to the first circuit layer L1 in the second substrate 4 can be designed according to actual process requirements.

[0049] For example, in one embodiment, please refer to Figures 14-16 , Figure 14 yes Figure 13 A schematic diagram of the structure of one embodiment of steps S101 and S102. Figure 15 yes Figure 13 A schematic diagram of the structure of an embodiment in step S301. Figure 16 It is formed Figure 15 Following the structure described in step S102, a schematic diagram of an embodiment is presented. The electrical performance testing method for the semiconductor device of this application may include the following steps: forming a first circuit layer L1 above a first substrate 1; forming a first test pad 2 on the side of the first circuit layer L1 facing away from the first substrate 1; and electrically connecting the first test pad 2 to a portion of the circuit V in the first circuit layer L1 (see reference). Figure 14 The first circuit layer L1 may include only the chip area G1, or it may include both the chip area G1 and the test area G2, which are not shown in the figure. The electrical performance of the first circuit layer L1 is obtained through the first test pad 2. The first test pad 2 is removed. The first substrate 1 is bonded to the second substrate 4, wherein the second substrate 4 may include one or more overlapping bonded wafers (where multiple refers to two or more). The second substrate 4 containing the second circuit layer L2 is bonded to the side of the first circuit layer L1 away from the first substrate 1, and the second circuit layer L2 is formed on the side of the first circuit layer L1 away from the first substrate 1 (see reference). Figure 15 The second circuit layer L2 is used as the first circuit layer, and a first test pad 2 is formed on the side of the second circuit layer L2 away from the first substrate 1. The first test pad 2 is electrically connected to a portion of the circuit V in the first circuit layer L1 (see reference). Figure 16 The electrical performance of the second circuit layer L2 is obtained through the first test pad 2; the first test pad 2 is removed; then, the aforementioned substrate bonding and electrical performance testing steps can continue on the side of the second circuit layer L2 away from the first substrate 1. The circuit structure of the above circuit V can be designed according to actual process and product requirements. The number of bonding substrates and the position of forming the first test pad 2 can be adjusted according to actual process and product requirements. This allows for timely testing of the electrical performance of the current wafer circuit layer before each wafer bonding, which is beneficial to improving product yield.

[0050] Through steps S101-S104, the first test pad 2 can be used as a temporary pin pad to realize real-time detection of the electrical performance of each structural layer during semiconductor device processing; after using the temporary pin pad for detection, removing the temporary pin pad can avoid the temporary pin pad from affecting the metal lines in the subsequently formed structural layers.

[0051] As can be seen from the above, the semiconductor device electrical performance testing method of the present invention may include: forming a first circuit layer on a first surface of a first substrate; forming a first test pad on the side of the first circuit layer away from the first substrate, wherein the first test pad is electrically connected to a portion of the circuits in the first circuit layer; obtaining the electrical performance of the first circuit layer through the first test pad; and removing the first test pad. Through the above method, the first test pad can be used as a temporary pin pad, enabling real-time detection of the electrical performance of each structural layer in the front-end or intermediate processes of semiconductor device fabrication.

[0052] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A method for testing the electrical performance of a semiconductor device, characterized in that, include: A first circuit layer is formed on the first surface of the first substrate; The side of the first circuit layer opposite to the first substrate is subjected to hydroxylation treatment; Remove the oxide layer on the side of the first circuit layer facing away from the first substrate after hydroxylation treatment; A first test pad is formed on the side of the first circuit layer away from the first substrate, and the first test pad is electrically connected to a portion of the circuit in the first circuit layer. The electrical performance of the first circuit layer is obtained through the first test pad; Remove the first test pad; The step of removing the first test pad includes: A second circuit layer is formed on the side of the first circuit layer away from the first substrate; The second circuit layer is used as the first circuit layer, and the process returns to the step of forming the first test pad on the side of the first circuit layer away from the first substrate; The first substrate includes a chip region and a test region; The step of forming a first test pad on the side of the first circuit layer away from the first substrate, and the first test pad being electrically connected to a portion of the circuits in the first circuit layer, includes: forming the first test pad on the side of the first circuit layer located in the test area away from the first substrate, the first test pad being electrically connected to the circuits in the test area; and forming the first test pad on the side of the first circuit layer located in the chip area away from the first substrate, the first test pad being electrically connected to the circuits in the chip area. And, after the step of removing the first test pad, the method includes: electroplating metal on the surface of the first circuit layer away from the substrate, photolithographically processing the metal until a second test pad is formed on the side of the test area away from the substrate, the second test pad being electrically connected to the circuit in the test area, wherein the second test pad is ultimately retained in the test area.

2. The test method according to claim 1, characterized in that, The step of forming a first test pad on the side of the first circuit layer away from the first substrate may include: inkjet printing or screen printing the first test pad on the side of the first circuit layer away from the first substrate.

3. The test method according to claim 2, characterized in that, The material of the first test pad includes at least one of conductive organic materials or conductive inorganic materials.

4. The test method according to claim 1, characterized in that, The step of removing the first test pad may include: chemically and mechanically polishing the first test pad until the circuitry in the first circuit layer is exposed.

5. The test method according to claim 1, characterized in that, After the step of removing the first test pad, the method further includes: The first substrate and the second substrate are bonded together, and the lines on the side of the first circuit layer away from the first substrate are electrically connected to the lines on the side of the second substrate close to the first substrate; wherein, the second substrate is provided with a second circuit layer on the side away from the first substrate. The second circuit layer is used as the first circuit layer, and the process returns to the step of forming a first test pad on the side of the first circuit layer away from the first substrate.

6. The test method according to claim 1, characterized in that, The step of obtaining the electrical performance of the first circuit layer through the first test pad includes: The first contact resistance between the first test pad and the line, the second contact resistance between the first test pad and the test probe, and the resistance of the first test pad are obtained. The resistance of the first contact pad, the resistance of the second contact pad, the resistance of the first test pad, and the resistance of the line electrically connected to the first test pad are obtained through the first test pad. The resistance of the line electrically connected to the first test pad is obtained based on the sum, the first contact resistance, the second contact resistance, and the resistance of the first test pad.

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