Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a first transistor structure, the first transistor structure comprising a first channel layer, a first gate electrode layer and a first source-drain doped layer, the first channel layer extending along a first direction, the first gate electrode layer extending along a second direction, and the first direction and the second direction having a first included angle, the first transistor structure having a bonding surface located at one side of the first gate electrode layer; a bonding layer located on the bonding surface of the first transistor structure; and a second transistor structure located on the bonding layer, the second transistor structure comprising a second channel layer, a second gate electrode layer and a second source-drain doped layer, the second channel layer extending along a third direction, the second gate electrode layer extending along a fourth direction, and the third direction and the fourth direction having a second included angle, the second included angle being different from the first included angle. The first gate electrode layer and the first source-drain doped layer in the first transistor structure are less likely to be completely shielded by the second transistor structure, which is conducive to saving the occupied area of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the shrinking feature size, the channel length of MOSFETs is also continuously shortening. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, thus reducing the gate's control over the channel and making it increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency.

[0004] Among them, the vertically stacked complementary field-effect transistor (CFET) is a revolutionary three-dimensional transistor. In the CFET structure, PMOS transistors and NMOS transistors stacked vertically to each other form complementary devices, but further improvements are needed in terms of saving area and increasing transistor integration density. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to saving the area occupied by the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a first transistor structure, including a substrate, a first channel layer on the substrate, a first gate dielectric layer covering the first channel layer, a first gate electrode layer covering the first gate dielectric layer, and first source / drain doped layers on the substrate located on both sides of the first gate electrode layer. The first source / drain doped layers are in contact with the end of the first channel layer located below the first gate electrode layer. The first channel layer extends along a first direction, and the first gate electrode layer extends along a second direction, with the first and second directions forming a first angle. The first transistor structure has a layer located on one side of the first gate electrode layer. The bonding surface; the bonding layer, located on the bonding surface of the first transistor structure; the second transistor structure, located on the bonding layer, the second transistor structure including a second channel layer, a second gate dielectric layer covering the second channel layer, a second gate electrode layer covering the second gate dielectric layer, and a second source / drain doped layer on the bonding layer located on both sides of the second gate electrode layer, the second source / drain doped layer being in contact with the end of the second channel layer located below the second gate electrode layer, the second channel layer extending along a third direction, the second gate electrode layer extending along a fourth direction, and the third direction and the fourth direction having a second included angle, the second included angle being unequal to the first included angle.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: forming a first transistor structure, the first transistor structure including a first substrate, a first channel layer on the first substrate, a first gate dielectric layer covering the first channel layer, a first gate electrode layer covering the first gate dielectric layer, and a first source / drain doped layer on a first substrate located on both sides of the first gate electrode layer, the first source / drain doped layer being in contact with an end of the first channel layer located below the first gate electrode layer, the first transistor structure having a bonding surface located on one side of the first gate electrode layer, wherein the first channel layer extends along a first direction, the first gate electrode layer extends along a second direction, and the first direction and the second direction have a first included angle; A second substrate is bonded to the bonding surface using a bonding layer; the second substrate is patterned to form a second channel layer extending along the third direction; a second gate dielectric layer covering the second channel layer, a second gate electrode layer spanning the second channel layer and covering the second gate dielectric layer, and second source / drain doped layers located on the bonding layers on both sides of the second gate electrode layer are formed, the second gate electrode layer extending along the fourth direction having a second angle with the third direction, the second source / drain doped layer contacting the end of the second channel layer located below the second gate electrode layer, the second gate electrode layer, the second gate dielectric layer, the second source / drain doped layer, and the second channel layer are used to constitute a second transistor structure, wherein the second angle is not equal to the first angle.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by this invention, for the first transistor structure, the first channel layer extends along a first direction, the first gate electrode layer extends along a second direction, and the first and second directions have a first angle. For the second transistor structure, the second channel layer extends along a third direction, the second gate electrode layer extends along a fourth direction, and the third and fourth directions have a second angle. The second angle is not equal to the first angle, which makes it easier to horizontally offset the first channel layer in the first transistor structure and the second channel layer and the second gate electrode layer in the second transistor structure. Furthermore, even if the first channel layer in the first transistor structure coincides with the second channel layer or the second gate electrode layer in the second transistor structure, because the second angle is not equal to the first angle, it can still be ensured that the first gate electrode layer in the first transistor structure is not completely blocked by the second transistor structure. Similarly, even if the first gate electrode layer in the first transistor structure coincides with the second gate electrode layer in the second transistor structure, the second gate electrode layer in the first transistor structure is not completely blocked by the second transistor structure. In the transistor structure, the second channel layer or the second gate electrode layer overlaps in the horizontal direction. Since the second included angle is not equal to the first included angle, it can still be ensured that the first channel layer in the first transistor structure is not completely blocked by the second transistor structure in the horizontal direction. That is to say, the probability that the first gate electrode layer and the first source / drain doped layer in the first transistor structure are completely blocked by the second transistor structure is low. Correspondingly, when it is necessary to bring out the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, for example, when it is necessary to form a source / drain plug (contact, CT) electrically connected to the first source / drain doped layer, or a gate plug electrically connected to the first gate electrode layer, the probability that the plug formation process is blocked by the second transistor structure can be reduced. This makes it easier to bring out the electrical properties of the first gate electrode layer or the first source / drain doped layer in the first transistor structure. Furthermore, when bringing out the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, it is not necessary to extend the length of the first source / drain doped layer and the first gate electrode layer too much to form the corresponding source / drain plug and gate plug, thereby saving the area occupied by the semiconductor structure.

[0010] In the semiconductor structure formation method provided by the embodiments of the present invention, when forming the first transistor structure, the first channel layer extends along a first direction, the first gate electrode layer extends along a second direction, and the first direction and the second direction have a first angle. When forming the second transistor structure, the second substrate is patterned, and a second channel layer extending along a third direction is formed. The second gate electrode layer extends along a fourth direction, and the fourth direction and the third direction have a second angle. The second angle is not equal to the first angle, which makes it easier to make the first channel layer in the first transistor structure and the second channel layer and the second gate electrode layer in the second transistor structure horizontally offset. This makes the first gate electrode layer in the first transistor structure and the second channel layer and the second gate electrode layer in the second transistor structure horizontally offset. Even if the first channel layer in the first transistor structure coincides with the second channel layer or the second gate electrode layer in the second transistor structure in the horizontal direction, since the second angle is not equal to the first angle, it can still be ensured that the first gate electrode layer in the first transistor structure is not completely blocked by the second transistor structure. Similarly, even if the first channel layer in the first transistor structure coincides with the second channel layer or the second gate electrode layer in the second transistor structure, the second gate electrode layer in the first transistor structure is not completely blocked by the second transistor structure. A gate electrode layer coincides with the second channel layer or the second gate electrode layer in the second transistor structure in the horizontal direction. Since the second included angle is not equal to the first included angle, it can still be ensured that the first channel layer in the first transistor structure is not completely blocked by the second transistor structure in the horizontal direction. That is to say, the probability that both the first gate electrode layer and the first source / drain doped layer in the first transistor structure are completely blocked by the second transistor structure is low. Correspondingly, when it is necessary to bring out the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, for example, when it is necessary to form a connection with the first source / drain doped layer... When forming a source / drain plug (CT) electrically connected to the first gate electrode layer, or a gate plug electrically connected to the first gate electrode layer, the probability of the plug formation process being blocked by the second transistor structure can be reduced. This makes it easier to extract the electrical properties of the first gate electrode layer or the first source / drain doped layer in the first transistor structure. Furthermore, when extracting the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, it is not necessary to excessively extend the length of the first source / drain doped layer or the first gate electrode layer to form the corresponding source / drain plug and gate plug, thereby helping to save the area occupied by the semiconductor structure.

[0011] The first transistor structure includes a first channel layer, a first gate electrode layer, and a first source / drain doped layer. The first channel layer extends along a first direction, and the first gate electrode layer extends along a second direction, with the first and second directions forming a first angle. The first transistor structure has a bonding surface located on one side of the first gate electrode layer. A bonding layer is located on the bonding surface of the first transistor structure. A second transistor structure is located on the bonding layer. The second transistor structure includes a second channel layer, a second gate electrode layer, and a second source / drain doped layer. The second channel layer extends along a third direction, and the second gate electrode layer extends along a fourth direction, with the third and fourth directions forming a second angle, which is not equal to the first angle. The probability that the first gate electrode layer and the first source / drain doped layer in the first transistor structure are completely blocked by the second transistor structure is low, which is beneficial for saving the area occupied by the semiconductor structure. Attached Figure Description

[0012] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure;

[0013] Figures 3 to 8 This is a schematic diagram of an embodiment of the semiconductor structure of the present invention;

[0014] Figures 9 to 28 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] As is known from the background art, the CFET structure includes PMOS transistors and NMOS transistors stacked vertically on top of each other. However, it is currently difficult to save the area occupied by the CFET structure.

[0016] We will now analyze the reasons why it is difficult to save the area occupied by a CFET structure, using a semiconductor structure as an example.

[0017] Reference Figure 1 and Figure 2 , Figure 1 To illustrate the three-dimensional structure of the channel and gate, for ease of illustration, Figure 1 The source and drain doped layers are not shown. Figure 2 for Figure 1 A cross-sectional view along the direction of the channel's extension.

[0018] The semiconductor structure includes: a first transistor structure 10, including a substrate 11, a first channel layer 12 on the substrate 11, a first gate structure 13 spanning the first channel layer 12, and a first source / drain doped layer 14 located in the first channel layer 12 on both sides of the first gate structure 13, the first transistor structure 10 having a bonding surface (not shown) on one side of the first gate structure 13; a bonding layer 30 located on the bonding surface; and a second transistor structure 20 located on the bonding layer 30, the second transistor structure 20 including a second channel layer 22, a second gate structure 23 covering the second channel layer 22, and a second source / drain doped layer 24 located in the second channel layer 22 on both sides of the second gate structure 23.

[0019] The semiconductor structure is a sequential CFET structure. Specifically, a first transistor structure 10 and a second transistor structure 20 are fabricated using separate silicon wafers, and the first transistor structure 10 and the second transistor structure 20 are bonded together.

[0020] The first source / drain doped layer 14 and the second source / drain doped layer 24 are formed independently. The second channel layer 22 is located directly above the first channel layer 12, and the second gate structure 23 is located directly above the first gate structure 13. Therefore, in the direction from the second transistor structure 20 to the first transistor structure 10, the second channel layer 22 completely blocks the first channel layer 12, and the second gate structure 23 completely blocks the first gate structure 13. For example, the projection of the first channel layer 12 on the substrate 11 lies within the projection of the second channel layer 22 on the substrate 11, and the projections of the second gate structure 23 and the first gate structure 13 on the substrate 11 coincide.

[0021] The semiconductor structure needs to simultaneously achieve vertical integration and electrical isolation between the first transistor structure 10 and the second transistor structure 20. However, since the second channel layer 22 completely blocks the first channel layer 12 and the second gate structure 23 completely blocks the first gate structure 13, the second transistor structure 20 completely blocks the first source / drain doped layer 14 and the first gate structure 13 in the first transistor structure 10, which makes it difficult to electrically bring out the first source / drain doped layer 14 and the first gate structure 13.

[0022] Specifically, refer to Figure 2 The semiconductor structure further includes a bottom source / drain plug 90, located on top of the first source / drain doped layer 14 and electrically connected to the first source / drain doped layer 14.

[0023] To form the bottom source / drain plug 90, the length of the first source / drain doped layer 14 needs to be extended so that a portion of the first source / drain doped layer 14 is not completely blocked by the second source / drain doped layer 24. This allows the bottom source / drain plug 90 to be formed on top of the first source / drain doped layer 14, bringing out the electrical conductivity of the first source / drain doped layer 14. Therefore, the first source / drain doped layer 14 occupies a larger area. Similarly, forming the gate plug for the first gate structure 13 also requires increasing the area occupied by the first gate structure 13, for the same reason as the first source / drain doped layer 14. Therefore, the CFET structure occupies a large area in semiconductor devices, making it difficult to cope with the increasing density of semiconductor devices.

[0024] To solve the aforementioned technical problem, in the semiconductor structure provided by the embodiments of the present invention, for the first transistor structure, the first channel layer extends along a first direction, the first gate electrode layer extends along a second direction, and the first and second directions have a first angle; for the second transistor structure, the second channel layer extends along a third direction, the second gate electrode layer extends along a fourth direction, and the third and fourth directions have a second angle. Since the second angle is not equal to the first angle, it is easy to horizontally offset the first channel layer in the first transistor structure and the second channel layer and second gate electrode layer in the second transistor structure. Furthermore, even if the first channel layer in the first transistor structure coincides with the second channel layer or the second gate electrode layer in the second transistor structure in the horizontal direction, because the second angle is not equal to the first angle, it can still be ensured that the first gate electrode layer in the first transistor structure is not completely blocked by the second transistor structure. Similarly, even if the first gate electrode layer in the first transistor structure coincides with the second channel layer or the second gate electrode layer in the second transistor structure in the horizontal direction, the first gate electrode layer in the first transistor structure is not completely blocked by the second transistor structure. In the second transistor structure, the second channel layer or the second gate electrode layer overlaps in the horizontal direction. Since the second included angle is not equal to the first included angle, it can still be ensured that the first channel layer in the first transistor structure is not completely blocked by the second transistor structure in the horizontal direction. That is to say, the probability that the first gate electrode layer and the first source / drain doped layer in the first transistor structure are completely blocked by the second transistor structure is low. Correspondingly, when it is necessary to bring out the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, for example, when it is necessary to form an electrical connection with the first source / drain doped layer... When forming a contact (CT) plug, or a gate plug electrically connected to the first gate electrode layer, the probability of the plug formation process being blocked by the second transistor structure can be reduced. This makes it easier to extract the electrical properties of the first gate electrode layer or the first source / drain doped layer in the first transistor structure. Furthermore, when extracting the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, it is not necessary to excessively extend the length of the first source / drain doped layer and the first gate electrode layer to form the corresponding source / drain plug and gate plug, thereby helping to save the area occupied by the semiconductor structure.

[0025] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Reference Figures 3 to 8 , Figure 3 This is a perspective view of an embodiment of the semiconductor structure of the present invention. Figure 4This is a schematic diagram of the projection pattern of the first channel layer, the first gate electrode layer, the first source / drain doped layer, the second channel layer, the second gate electrode layer, and the second source / drain doped layer on the substrate in one embodiment of the semiconductor structure of the present invention. Figure 5 This is a cross-sectional view along the second direction in one embodiment of the semiconductor structure of the present invention. Figure 6 This is a cross-sectional view along the first direction in one embodiment of the semiconductor structure of the present invention. For ease of illustration, Figure 5 and Figure 6 The structure of the second transistor is not shown. Figure 7 This is a cross-sectional view along the fourth direction in one embodiment of the semiconductor structure of the present invention. Figure 8 This is a cross-sectional view along a third direction in one embodiment of the semiconductor structure of the present invention. For ease of illustration, Figure 7 and Figure 8 The structure of the first transistor is not shown.

[0027] For ease of illustration, Figure 3 The diagram only shows the substrate, the first gate electrode layer, the first source / drain doped layer, the bonding layer, the second gate electrode layer, the second source / drain doped layer, the bottom source / drain plug, and the bottom gate plug.

[0028] The semiconductor structure includes: a first transistor structure 401, comprising a substrate 101, a first channel layer 291 on the substrate 101, a first gate dielectric layer 421 covering the first channel layer 291, a first gate electrode layer 431 covering the first gate dielectric layer 421, and first source / drain doped layers 301 on the substrate 101 on both sides of the first gate electrode layer 431. The first source / drain doped layers 301 are in contact with the ends of the first channel layer 291 located below the first gate electrode layer 411. The first channel layer 291 is oriented along a first direction (e.g., ...). Figure 4 The first gate electrode layer 411 extends along the second direction (as shown in direction A). Figure 4 Extending in the direction shown in the middle B direction, and with the first direction and the second direction having a first included angle α, the first transistor structure 401 has a bonding surface 402 located on one side of the first gate electrode layer 411; a bonding layer 501 is located on the bonding surface 402 of the first transistor structure 401; a second transistor structure 801 is located on the bonding layer 501, the second transistor structure 801 includes a second channel layer 601, a second gate dielectric layer 821 covering the second channel layer 601, a second gate electrode layer 831 covering the second gate dielectric layer 821, and a second source / drain doped layer 701 located on the bonding layer 501 on both sides of the second gate electrode layer 831, the second source / drain doped layer 701 being in contact with the end of the second channel layer 601 located below the second gate electrode layer 831, the second channel layer 601 extending along a third direction (e.g., in the middle B direction) and having a first included angle α between the first direction and the second direction. Figure 4The second gate electrode layer 831 extends along the fourth direction (as shown in the C direction), and extends along the fourth direction (as shown in the C direction). Figure 4 The direction (as shown in the middle D direction) extends, and the third direction and the fourth direction have a second included angle β, which is not equal to the first included angle α.

[0029] In the semiconductor structure provided in this embodiment, for the first transistor structure 401, the first channel layer 201 extends along a first direction, and the first gate electrode layer 431 extends along a second direction, with the first direction and the second direction having a first included angle α. For the second transistor structure 801, the second channel layer 601 extends along a third direction, and the second gate electrode layer 831 extends along a fourth direction, with the third direction and the fourth direction having a second included angle β. The second included angle β is not equal to the first included angle α, which makes it easier to make the first channel layer 201 in the first transistor structure 401 and the second channel layer 601 and the second gate electrode layer 831 in the second transistor structure 801... The layers are horizontally offset, so that the first gate electrode layer 431 in the first transistor structure 401 and the second channel layer 601 and the second gate electrode layer 831 in the second transistor structure 801 are horizontally offset. Even if the first channel layer 201 in the first transistor structure 401 coincides with the second channel layer 601 or the second gate electrode layer 831 in the second transistor structure 801 in the horizontal direction, because the second included angle β is not equal to the first included angle α, it can still be ensured that the first gate electrode layer 431 in the first transistor structure 401 is not completely blocked by the second transistor structure 801. Similarly, even if the first channel layer 201 in the first transistor structure 401 coincides with the second channel layer 601 or the second gate electrode layer 831 in the second transistor structure 801, the second included angle β is not equal to the first included angle α. The first gate electrode layer 431 coincides with the second channel layer 601 or the second gate electrode layer 831 in the second transistor structure 801 in the horizontal direction. Since the second included angle β is not equal to the first included angle α, it can still be ensured that the first channel layer 201 in the first transistor structure 401 is not completely blocked by the second transistor structure 801 in the horizontal direction. That is to say, the probability that the first gate electrode layer 431 and the first source / drain doped layer 301 in the first transistor structure 401 are completely blocked by the second transistor structure 801 is low. Correspondingly, when it is necessary to bring out the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, for example, when it is necessary to bring out the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, for example, when it is necessary to bring out the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure, When forming a source / drain plug electrically connected to the first source / drain doped layer, or a gate plug electrically connected to the first gate electrode layer 431, the probability of the plug formation process being blocked by the second transistor structure 801 can be reduced. This makes it easier to bring out the electrical properties of the first gate electrode layer 431 or the first source / drain doped layer 301 in the first transistor structure 401. Furthermore, when bringing out the electrical properties of the first source / drain doped layer 301 or the first gate electrode layer 431 in the first transistor structure 401, it is not necessary to excessively extend the length of the first source / drain doped layer 301 and the first gate electrode layer 431 to form the corresponding source / drain plug and gate plug, thereby helping to save the occupied area of ​​the semiconductor structure.

[0030] The semiconductor structure is a CFET structure, and the first transistor structure 401 includes a first transistor, which is the bottom transistor in the CFET structure. The first transistor includes a first channel layer 201, a first gate dielectric layer 421, a first gate electrode layer 431, and a first source / drain doped layer 301, thereby realizing the normal function of the first transistor. In the CFET structure, PMOS transistors and NMOS transistors stacked perpendicularly to each other constitute complementary devices; therefore, depending on the channel conductivity type of the first transistor in the first transistor structure 401, the first transistor can be an NMOS transistor or a PMOS transistor.

[0031] As an example, the first transistor in the first transistor structure 401 is an NMOS transistor. Depending on the structure type of the first transistor structure 401, it may include a FinFET or a Gate-All-Around (GAA) transistor. Specifically, the GAA transistor may be a Horizontal Nanosheet transistor. This embodiment uses a GAA transistor as an example.

[0032] The substrate 101 is used to provide a process platform for the formation of semiconductor structures. In this embodiment, taking the first transistor as a GAA transistor as an example, the substrate 101 includes a substrate 111, a fin 131 protruding on the substrate 111, and an isolation layer 121 located on the substrate 111, the isolation layer 121 covering the sidewall of the fin 131.

[0033] In this embodiment, the substrate 111 is made of silicon. In other embodiments, the substrate 111 may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate 111 may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. As an example, the fin 131 and the substrate 111 are an integral structure.

[0034] In this embodiment, the isolation layer 121 can be a shallow trench isolation structure (STI). The material of the isolation layer 121 is an insulating material. As an example, the material of the isolation layer 121 is silicon oxide.

[0035] The first channel layer 201 is used to provide a channel for the first transistor. In this embodiment, taking a GAA transistor as an example, the first channel layer 201 is located on the substrate 101 and spaced apart from the substrate 101. Specifically, the first channel layer 201 is located on the fin 131 and spaced apart from the fin 131. The first channel layer 201 includes one or more spaced first sub-channel layers 211. It should be noted that this embodiment only illustrates one first sub-channel layer 211, but the number of first sub-channel layers 211 is not limited to one. In other embodiments, when the first transistor is a FinFET, the first channel layer is a first fin protruding from the substrate.

[0036] The material of the first channel layer 201 includes silicon, silicon germanide, germanium, or a group III-V semiconductor material. The material of the first channel layer 201 is determined according to the channel conductivity type and performance requirements of the first transistor. As an example, the material of the first channel layer 201 is silicon.

[0037] The first gate electrode layer 431 is used to control the opening or closing of the channel of the first transistor. In this embodiment, the first gate electrode layer 431 surrounds and covers the first gate dielectric layer 421 on the first channel layer 201. In other embodiments, when the first channel layer is a first fin protruding from the substrate, the first gate electrode layer correspondingly spans the first fin and covers a portion of the top and a portion of the sidewalls of the first fin with the first gate dielectric layer.

[0038] refer to Figure 4 , Figure 4 (a) is a schematic diagram of the projection pattern of the first channel layer 201, the first gate electrode layer 431, the first source / drain doped layer 301, the second channel layer 601, the second gate electrode layer 831, and the second source / drain doped layer 701 onto the substrate 101. Figure 4 (b) is a schematic diagram of the projection pattern of the first channel layer 201, the first gate electrode layer 431, and the first source / drain doped layer 301 on the substrate 101. The first channel layer 201 extends along a first direction, the first gate electrode layer 431 extends along a second direction, and the first direction and the second direction have a first included angle α.

[0039] Wherein, the first included angle α is the angle through which the first direction rotates clockwise until it first coincides with the second direction.

[0040] It should be noted that the first included angle α should not be too small or too large. If the first included angle α is too small, the extension direction of the first gate electrode layer 431 will be too close to the extension direction of the first channel layer 201, causing unnecessary difficulties in forming the first source / drain doped layer 301 and affecting the performance of the CFET structure. If the first included angle α is too large, it will still cause the extension direction of the first gate electrode layer 431 to be too close to the extension direction of the first channel layer 201, thus causing unnecessary difficulties in forming the first source / drain doped layer 301 and affecting the performance of the CFET structure. Therefore, in this embodiment, the first included angle α is 45° to 135°.

[0041] In this embodiment, the first gate electrode layer 431 is a metal gate electrode layer. The material of the first gate electrode layer 431 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the first gate electrode layer 431 includes a first work function layer (not shown) and a first electrode layer (not shown) covering the first work function layer. The first work function layer is used to adjust the threshold voltage of the first transistor, and the first electrode layer is used to bring out the electrical properties of the first gate electrode layer 431.

[0042] In this embodiment, the first gate dielectric layer 421 is located between the first gate electrode layer 431 and the first channel layer 201. The first gate dielectric layer 421 is used to isolate the first gate electrode layer 431 and the first channel layer 201. The material of the first gate dielectric layer 421 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the first gate dielectric layer 421 includes a first gate oxide layer (not shown) and a first high-k gate dielectric layer (not shown) covering the first gate oxide layer.

[0043] In this embodiment, the material of the first gate oxide layer is silicon oxide, and the material of the first high-k gate dielectric layer is a high-k dielectric material. A high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the first high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the first high-k gate dielectric layer is HfO2.

[0044] It should be noted that the first gate dielectric layer 421 and the first gate electrode layer 431 are formed by forming a high k last metal gate last after forming a high k last gate dielectric layer. Therefore, the first gate dielectric layer 421 is also located between the bottom of the first gate electrode layer 431 and the substrate 101, and extends to cover the sidewall of the first gate electrode layer 431.

[0045] It should also be noted that, in other embodiments, depending on process requirements, the first gate electrode layer may also be a polysilicon gate layer or other types of device gate layers.

[0046] The first source / drain doped layer 301 is used as the source or drain of the first transistor. In this embodiment, the first source / drain doped layer 301 includes a first epitaxial layer doped with ions, and the conductivity type of the doped ions in the first epitaxial layer is the same as the channel conductivity type of the first transistor. That is, when the first transistor is an NMOS transistor, the conductivity type of the doped ions in the first epitaxial layer is N-type, and N-type ions include one or more of As, P, and Sb; when the first transistor is a PMOS transistor, the conductivity type of the doped ions in the first epitaxial layer is P-type, and P-type ions include one or more of B, Ga, and In. The material of the epitaxial layer in the first epitaxial layer includes Si, SiGe, or SiP. A detailed description of the first source / drain doped layer 301 is omitted here.

[0047] In this embodiment, the first transistor structure 401 further includes a first gate sidewall 441 covering the sidewall of the first gate electrode layer 431. Specifically, the first gate sidewall 441 covers the first gate dielectric layer 421 located on the sidewall of the first gate electrode layer 431. The first gate sidewall 441 is used to protect the sidewalls of the first gate electrode layer 431 and the first gate dielectric layer 421, and also to define the location of the first source / drain doped layer 301. The first gate sidewall 441 can be a single-layer structure or a stacked structure, and the material of the first gate sidewall 441 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the first gate sidewall 441 is a single-layer structure, and the material of the first gate sidewall 441 is silicon nitride.

[0048] like Figure 6 As shown, taking a GAA transistor as an example, the first transistor structure 401 may further include: a first inner wall (not shown), along the normal direction of the surface of the substrate 101 (e.g., Figure 3 (As shown in the Z direction), the first inner sidewall is located between adjacent first sub-channel layers 211, or between the first sub-channel layer 211 and the substrate 101, and along the first direction, the first inner sidewall is located between the sidewall of the first gate dielectric layer 421 and the first source / drain doped layer 301.

[0049] The first inner wall serves to isolate the first gate electrode layer 431 and the first source / drain doped layer 301, thereby reducing the parasitic capacitance between them. The first inner wall is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the first inner wall is made of silicon nitride.

[0050] In this embodiment, the first transistor structure 401 further includes a first interlayer dielectric layer 221, which is located on the substrate 101 on the side of the first gate electrode layer 431 and covers the sidewall of the first gate electrode layer 431.

[0051] The first interlayer dielectric layer 221 is used to isolate adjacent transistors in the first transistor structure 401. The material of the first interlayer dielectric layer 221 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first interlayer dielectric layer 221 is silicon oxide. Correspondingly, the first gate dielectric layer 421 is located between the bottom of the first gate electrode layer 431 and the substrate 101, and between the sidewall of the first gate electrode layer 431 and the first interlayer dielectric layer 221.

[0052] In this embodiment, the first transistor structure 401 has a bonding surface 402 located on one side of the first gate electrode layer 431. The bonding surface 402 is the front side of the first transistor structure 401. During the fabrication of the semiconductor structure, the bonding surface 402 is used as a process platform to fabricate the second transistor structure 801 above the bonding surface 402.

[0053] The bonding layer 501 is located on the bonding surface 402. During the fabrication of the second transistor structure 801, the substrate required for forming the second transistor structure 801 is bonded to the bonding surface 401 via the bonding layer 501. This allows for the independent fabrication of the first transistor structure 401 and the second transistor structure 801, ensuring electrical isolation between them. The bonding layer 501 also enhances the bonding strength between the first transistor structure 401 and the second transistor structure 801, thereby improving the reliability of the semiconductor structure. Furthermore, during the fabrication of the second transistor structure 801, the bonding layer 501 also protects the first transistor structure 401.

[0054] In this embodiment, the bonding layer 501 is made of a dielectric material, which provides electrical isolation between the second transistor structure 801 and the first transistor structure 401, and makes the bonding layer 501 compatible with semiconductor processes.

[0055] The bonding layer 501 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the bonding layer 501 is made of silicon oxide. By using silicon oxide, bonding can be achieved through fusion bonding, which is beneficial for improving bonding efficiency and bonding strength. Moreover, it is also beneficial for further improving the electrical isolation effect between the second transistor structure 801 and the first transistor structure 401. In addition, by using silicon oxide, the bonding temperature is lower, thereby reducing the impact on the performance of the first transistor in the first transistor structure 401.

[0056] It should be noted that in other embodiments, a conductive layer may also be provided in the bonding layer, thereby realizing the redistribution of the circuit through the conductive layer to meet the design requirements.

[0057] It should also be noted that the bonding layer 501 is located on the bonding surface 401. The bonding layer 501 not only covers the top of the first gate electrode layer 431, but also covers the top of the first interlayer dielectric layer 221.

[0058] The second transistor structure 801 is located on the bonding layer 501. The second transistor structure 801 includes a second transistor, which is the top transistor in the CFET structure. The second transistor includes a second channel layer 601, a second gate dielectric layer 821, a second gate electrode layer 831, and a second source / drain doped layer 701, thereby realizing the normal function of the second transistor.

[0059] Therefore, the second transistor in the second transistor structure 801 can be an NMOS transistor or a PMOS transistor, and the channel conductivity type of the second transistor is different from that of the first transistor. In this embodiment, the first transistor is an NMOS transistor, therefore, the second transistor is a PMOS transistor. In other embodiments, when the first transistor is a PMOS transistor, the second transistor is correspondingly an NMOS transistor.

[0060] Depending on the structural type of the second transistor structure 801, the second transistor structure 801 includes a fin field-effect transistor or a GAA transistor. Specifically, the GAA transistor can be a horizontal nanosheet transistor.

[0061] The second channel layer 601 is used to provide the channel for the second transistor. In this embodiment, taking a GAA transistor as an example, the second channel layer 601 is located on and spaced apart from the bonding layer 501, and the second channel layer 601 includes one or more spaced second sub-channel layers 611. It should be noted that... Figure 7Only one second sub-channel layer 611 is shown in the figure, but the number of second sub-channel layers 611 is not limited to one.

[0062] In other embodiments, when the second transistor is a FinFET, the second channel layer is a second fin protruding from the bonding layer.

[0063] It should be noted that, in this embodiment, during the fabrication of the second transistor structure 801, the substrate bonded to the bonding surface 402 is directly patterned as the second channel layer 601. Therefore, the second transistor structure 801 does not contain an additional substrate (e.g., a substrate). Correspondingly, when the second channel layer is a second fin protruding from the bonding layer, the second fin is in contact with the bonding layer.

[0064] The material of the second channel layer 601 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials. The material of the second channel layer 601 is determined according to the channel conductivity type and performance requirements of the second transistor. As an example, the material of the second channel layer 601 is silicon.

[0065] The second gate electrode layer 831 is used to control the opening or closing of the channel of the second transistor. In this embodiment, the second gate electrode layer 831 surrounds the second gate dielectric layer 821 covering the second channel layer 601. In other embodiments, when the second channel layer is a second fin protruding from the bonding layer, the second gate electrode layer correspondingly spans the second fin and covers a portion of the top and sidewalls of the second fin of the second gate dielectric layer.

[0066] refer to Figure 4 , Figure 4 (a) is a schematic diagram of the projection pattern of the first channel layer 201, the first gate electrode layer 431, the first source / drain doped layer 301, the second channel layer 601, the second gate electrode layer 831, and the second source / drain doped layer 701 onto the substrate 101. Figure 4 (c) is a schematic diagram of the projection pattern of the second channel layer 601, the second gate electrode layer 831, and the second source / drain doped layer 701 on the substrate 101. The second channel layer 601 extends along a third direction, the second gate electrode layer 831 extends along a fourth direction, and the third and fourth directions have a second included angle β.

[0067] Wherein, the second included angle β is the angle through which the third direction rotates clockwise until it first coincides with the fourth direction.

[0068] It should be noted that the second included angle β should not be too small or too large. If the second included angle β is too small, the extension direction of the second gate electrode layer 831 will be too close to the extension direction of the second channel layer 601, causing unnecessary difficulties in forming the second source / drain doped layer 701 and affecting the performance of the CFET structure. If the second included angle β is too large, it will still cause the extension direction of the second gate electrode layer 831 to be too close to the extension direction of the second channel layer 601, thus causing unnecessary difficulties in forming the second source / drain doped layer 701 and affecting the performance of the CFET structure. Therefore, in this embodiment, the second included angle β is 45° to 135°.

[0069] In this embodiment, the first included angle α and the second included angle β are not equal. Specifically, the first direction is parallel to the third direction, and the second direction has an angle with the fourth direction; or, the first direction has an angle with the third direction, and the second direction is parallel to the fourth direction; or, the first direction has an angle with the third direction, and the second direction has an angle with the fourth direction. In this embodiment, taking the first direction having an angle with the third direction and the second direction having an angle with the fourth direction as an example, it is beneficial to ensure that the first channel layer 201 and the first gate electrode layer 431 in the first transistor structure 401 are not completely blocked by the second channel layer 601 or the second gate electrode layer 831 in the second transistor structure 801, thereby facilitating the simultaneous extraction of the electrical properties of the first channel layer 201 and the first gate electrode layer 431 in the first transistor structure 401 in a smaller area.

[0070] It should be noted that the difference in degree between the first included angle α and the second included angle β should not be too small. If the difference in degree between the first included angle α and the second included angle β is too small, when the first channel layer 201 in the first transistor structure 401 coincides with the second channel layer 601 or the second gate electrode layer 831 in the second transistor structure 801 in the horizontal direction, the first gate electrode layer 431 in the first transistor structure 401 is easily completely blocked by the second channel layer 601 or the second gate electrode layer 831 in the second transistor structure 801 because the first included angle α and the second included angle β are too close, thus making it difficult to completely block the first gate electrode layer 431. Similarly, when the first gate electrode layer 431 in the first transistor structure 401 coincides with the second channel layer 601 or the second gate electrode layer 831 in the second transistor structure 801 in the horizontal direction, the first channel layer 201 in the first transistor structure 401 is easily completely blocked by the second channel layer 601 or the second gate electrode layer 831 in the second transistor structure 801, making it difficult to bring out the electrical properties of the first source / drain doped layer 301, thus affecting the performance of the CFET structure. Therefore, in this embodiment, the difference in degree between the first included angle α and the second included angle β is greater than 5°.

[0071] In this embodiment, the second gate electrode layer 831 is a metal gate electrode layer, and the material of the second gate electrode layer 831 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the second gate electrode layer 831 includes a second work function layer (not shown) and a second electrode layer (not shown) covering the second work function layer. For a detailed description of the second work function layer and the second electrode layer and their materials, please refer to the foregoing descriptions of the first work function layer and the first electrode layer, respectively, which will not be repeated here.

[0072] In this embodiment, the second gate dielectric layer 821 is located between the second gate electrode layer 831 and the second channel layer 601, and is also located between the second gate electrode layer 831 and the bonding layer 501.

[0073] The second gate dielectric layer 821 is used to isolate the second gate electrode layer 831 and the second channel layer 601. The material of the second gate dielectric layer 821 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. As an example, the second gate dielectric layer 821 includes a second gate oxide layer and a second high-k gate dielectric layer covering the second gate oxide layer. For a detailed description of the second gate dielectric layer 821, please refer to the foregoing description of the first gate dielectric layer 421, which will not be repeated here.

[0074] In this embodiment, the second transistor structure 801 does not contain an additional substrate (e.g., a substrate), therefore, the second gate dielectric layer 821 is in contact with the top of the bonding layer 501.

[0075] It should be noted that the second gate dielectric layer 821 and the second gate electrode layer 831 are formed by forming the gate electrode layer after forming the high-k gate dielectric layer. Therefore, the second gate dielectric layer 821 also conformally covers the bottom and sidewalls of the second gate electrode layer 831. That is, the second gate dielectric layer 821 is located between the second gate electrode layer 831 and the bonding layer 501, and extends to cover the sidewalls of the second gate electrode layer 831.

[0076] It should also be noted that, in other embodiments, depending on process requirements, the second gate electrode layer may also be a polysilicon gate layer or other types of device gate layers.

[0077] The second source / drain doped layer 601 is used as the source or drain of the second transistor. In this embodiment, the second source / drain doped layer 601 includes a second epitaxial layer doped with ions, and the conductivity type of the doped ions in the second epitaxial layer is the same as the channel conductivity type of the second transistor. For a detailed description of the second source / drain doped layer 601, please refer to the aforementioned description of the first source / drain doped layer 301, which will not be repeated here.

[0078] In this embodiment, the second transistor structure 801 further includes a second gate sidewall 841, covering the sidewalls of the second gate electrode layer 831 and the second gate dielectric layer 821. The second gate sidewall 841 is used to protect the sidewalls of the second gate electrode layer 831 and the second gate dielectric layer 821, and also to define the position of the second source / drain doped layer 601. A detailed description of the material of the second gate sidewall 841 can be found in the foregoing description of the first gate sidewall 441, and will not be repeated here.

[0079] like Figure 8 As shown, it should be noted that, taking the second transistor as a GAA transistor as an example, the second transistor structure 801 may also include: a second inner sidewall (not shown), located between adjacent second channel layers 601 along the normal direction of the surface of the substrate 101, or located between the second channel layer 601 and the bonding layer 501, and along the first direction, the second inner sidewall is located between the sidewall of the second gate dielectric layer 821 and the second source / drain doped layer 601.

[0080] The second inner wall serves to isolate the second gate electrode layer 831 and the second source / drain doped layer 601, thereby reducing the parasitic capacitance between the second gate electrode layer 831 and the second source / drain doped layer 601. A detailed description of the material of the second inner wall can be found in the foregoing description of the first inner wall, and will not be repeated here.

[0081] In this embodiment, the second transistor structure 801 further includes a second interlayer dielectric layer 621, located on the bonding layer 501 and covering the second source / drain doped layer 601 and the second gate electrode layer 831. The second interlayer dielectric layer 621 is used to isolate adjacent transistors in the second transistor structure.

[0082] The material of the second interlayer dielectric layer 621 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 621 is silicon oxide.

[0083] refer to Figure 5 In this embodiment, the semiconductor structure further includes: a bottom gate plug 911 and a bonding layer 501 that penetrates the second channel layer 601 and the side of the second gate electrode layer 831. The bottom gate plug 911 is located on top of the first gate electrode layer 431 and is electrically connected to the first gate electrode layer 431.

[0084] In this embodiment, the bottom gate plug 911 electrically connected to the first gate electrode layer 431 can be formed without extending the first gate electrode layer 431, thus saving the area occupied by the CFET structure.

[0085] The bottom gate plug 911 is used to realize the electrical connection between the first gate electrode layer 431 and the external circuit structure.

[0086] Specifically, the bottom gate plug 911 penetrates the second interlayer dielectric layer 621, the bonding layer 501, and the first interlayer dielectric layer 221 at the top of the first gate electrode layer 431. In this embodiment, the first interlayer dielectric layer 221 only covers the sidewall of the first gate electrode layer 431, exposing the top of the first gate electrode layer 431. Therefore, in this embodiment, the bottom gate plug 911 penetrates the second interlayer dielectric layer 621 and the bonding layer 501 at the top of the first gate electrode layer 431.

[0087] In this embodiment, the bottom gate plug 911 is an integral structure to reduce the process difficulty of forming the bottom gate plug 911 (e.g., the alignment difficulty in the photolithography process). In this embodiment, the material of the bottom gate plug 911 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN, and TiAlC, and the above materials have good conductivity.

[0088] refer to Figure 6In this embodiment, the semiconductor structure further includes: a bottom source / drain plug 901 and a bonding layer 501 that penetrates the second channel layer 601 and the side of the second gate electrode layer 831. The bottom source / drain plug 901 is located on top of the first source / drain doped layer 301 and is electrically connected to the first source / drain doped layer 301.

[0089] In this embodiment, the bottom source / drain plug 901 electrically connected to the first source / drain doped layer 301 can be formed without extending the first source / drain doped layer 301, thus saving the area occupied by the CFET structure.

[0090] The bottom source / drain plug 901 is used to realize the electrical connection between the first source / drain doped layer 301 and the external circuit structure.

[0091] Specifically, the bottom source / drain plug 901 penetrates the second interlayer dielectric layer 621, the bonding layer 501, and the first interlayer dielectric layer 221 at the top of the first source / drain doped layer 301.

[0092] In this embodiment, the bottom source / drain plug 901 is an integral structure to reduce the process difficulty of forming the bottom source / drain plug 901 (e.g., alignment difficulty in photolithography). In this embodiment, the material of the bottom source / drain plug 901 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN, and TiAlC, and the above materials have good conductivity.

[0093] Figures 9 to 28 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0094] Reference Figures 9 to 12 , Figure 9 This is a perspective view of an embodiment of the first transistor structure of the present invention. Figure 10 This is a schematic diagram of the projection pattern of the first channel layer, the first gate electrode layer, and the first source / drain doped layer on a first substrate in one embodiment of the first transistor structure of the present invention. Figure 11 yes Figure 9 A cross-sectional view along the second direction. Figure 12 yes Figure 9A cross-sectional view along a first direction shows a first transistor structure 400, including a first substrate 100, a first channel layer 200 on the first substrate 100, a first gate dielectric layer 420 covering the first channel layer 200, a first gate electrode layer 430 covering the first gate dielectric layer 420, and first source / drain doped layers 300 on the first substrate 100 on both sides of the first gate electrode layer 430. The first source / drain doped layers 300 are in contact with the ends of the first channel layer 200 located below the first gate electrode layer 430. The first transistor structure 400 has a bonding surface 403 on one side of the first gate electrode layer 430. The first channel layer 200 is located along a first direction (e.g., ...). Figure 10 The first gate electrode layer 430 extends along the second direction (as shown in direction A), and extends along the second direction (as shown in direction A). Figure 10 The first direction (as shown in direction B) extends, and the first direction and the second direction have a first included angle α. For ease of illustration, Figure 9 Only the first substrate, the first gate electrode layer, and the first source / drain doped layer are shown in the diagram.

[0095] The formation method is used to form a CFET structure. The first transistor structure 400 includes a first transistor, which is the bottom transistor in the CFET structure. The first transistor includes a first channel layer 200, a first gate dielectric layer 420, a first gate electrode layer 430, and a first source / drain doped layer 300, thereby realizing the normal function of the first transistor. The first transistor in the first transistor structure 400 can be an NMOS transistor or a PMOS transistor. Depending on the structural type of the first transistor structure 400, the first transistor structure 400 includes a FinFET or a GAA transistor. This embodiment uses a GAA transistor as an example.

[0096] The first substrate 100 is used to provide a process platform for the formation of a semiconductor structure. In this embodiment, the first substrate 100 includes a substrate 110, a fin 130 protruding from the substrate 110, and an isolation layer 120 located on the substrate 110, the isolation layer 120 covering the sidewalls of the fin 130.

[0097] In this embodiment, the first channel layer 200 is located on and spaced apart from the fin 130. The first channel layer 200 includes one or more spaced-apart first sub-channel layers 210. It should be noted that this embodiment only illustrates one first sub-channel layer 210, but the number of first sub-channel layers 210 is not limited to one. In other embodiments, when the first transistor is a FinFET, the first channel layer is a first fin protruding from the substrate.

[0098] In this embodiment, the first gate electrode layer 430 surrounds and covers the first gate dielectric layer 420 on the first channel layer 200. In other embodiments, when the first channel layer is a first fin protruding from the substrate, the first gate electrode layer correspondingly spans the first fin and covers a portion of the top and a portion of the sidewalls of the first fin of the first gate dielectric layer.

[0099] refer to Figure 10 The first channel layer 200 extends along a first direction, the first gate electrode layer 430 extends along a second direction, and the first direction and the second direction have a first included angle α.

[0100] Wherein, the first included angle α is the angle through which the first direction rotates clockwise until it first coincides with the second direction.

[0101] It should be noted that the first included angle α should not be too small or too large. If the first included angle α is too small, the extension direction of the first gate electrode layer 430 will be too close to the extension direction of the first channel layer 200, causing unnecessary difficulties in forming the first source / drain doped layer 300 and affecting the performance of the CFET structure. If the first included angle α is too large, it will still cause the extension direction of the first gate electrode layer 430 to be too close to the extension direction of the first channel layer 200, thus causing unnecessary difficulties in forming the first source / drain doped layer 300 and affecting the performance of the CFET structure. Therefore, in this embodiment, the first included angle α is 45° to 135°.

[0102] As an example, the first gate electrode layer 430 includes a first work function layer (not shown) and a first electrode layer (not shown) covering the first work function layer.

[0103] In this embodiment, the first gate dielectric layer 420 is located between the first gate electrode layer 430 and the first channel layer 200. Specifically, the first gate dielectric layer 420 includes a first gate oxide layer and a first high-k gate dielectric layer covering the first gate oxide layer. It should be noted that the first gate dielectric layer 420 and the first gate electrode layer 430 are formed using a process that forms the high-k gate dielectric layer first and then the gate electrode layer. Therefore, the first gate dielectric layer 420 also covers the bottom and sidewalls of the first gate electrode layer 430.

[0104] It should also be noted that, in other embodiments, depending on process requirements, the first gate electrode layer may also be a polysilicon gate layer or other types of device gate layers.

[0105] The first source / drain doped layer 300 includes a first epitaxial layer doped with ions, and the conductivity type of the doped ions in the first epitaxial layer is the same as the channel conductivity type of the first transistor.

[0106] refer to Figure 12In this embodiment, the first transistor structure 400 further includes a first gate sidewall 440 covering the sidewall of the first gate electrode layer 430. Specifically, the first gate sidewall 440 covers the first gate dielectric layer 420 located on the sidewall of the first gate electrode layer 430.

[0107] In this embodiment, the first transistor structure 400 may further include: a first inner wall (not shown), along the normal direction of the surface of the first substrate 100 (e.g., Figure 9 (As shown in the Z direction), it is located between adjacent first sub-channel layers 210, or between the first sub-channel layer 210 and the first substrate 100, and along the first direction, the first inner sidewall is located between the sidewall of the first gate dielectric layer 420 and the first source / drain doped layer 300.

[0108] In this embodiment, the first transistor structure 400 further includes a first interlayer dielectric layer 220, which is located on the first substrate 100 on the side of the first gate electrode layer 430 and covers the sidewall of the first gate electrode layer 430.

[0109] For a detailed description of the first transistor structure 400, please refer to the corresponding description in the foregoing embodiments, and it will not be repeated here.

[0110] In this embodiment, the first transistor structure 400 has a bonding surface 403. The bonding surface 403 is the front side of the first transistor structure 400. Subsequently, using the bonding surface 403 as a process platform, a second transistor structure is fabricated on top of the bonding surface 403, thereby forming a sequential CFET structure.

[0111] refer to Figure 13 and Figure 14 , Figure 13 It is a cross-sectional view along the second direction. Figure 14 It is a cross-sectional view along the first direction, showing that the second substrate 630 is bonded to the bonding surface 403 using the bonding layer 500.

[0112] The second substrate 630 is used to form the second channel layer in the second transistor structure.

[0113] Subsequently, a second transistor structure is formed on the bonding layer 500. The second transistor structure includes a second transistor, which is the top transistor in the CFET structure. The second transistor in the second transistor structure can be an NMOS transistor or a PMOS transistor, and the channel conductivity type of the second transistor is different from that of the first transistor.

[0114] In this embodiment, the second substrate 630 is bonded to the bonding surface 403 by bonding. That is to say, after the fabrication process of the first transistor structure 400 is completed, the fabrication process of the second transistor structure can be completed independently. This reduces the difficulty of the subsequent fabrication process of the second transistor structure and the impact of the fabrication process of the second transistor structure on the first transistor structure 400.

[0115] The bonding layer 500 enhances the bonding strength between the first transistor structure 400 and the second substrate 630, thereby improving the reliability of the semiconductor structure. Furthermore, the bonding layer 500 also protects the first transistor structure 400 during the subsequent fabrication of the second transistor structure.

[0116] In this embodiment, the bonding layer 500 is made of a dielectric material, thereby providing electrical isolation between the first transistor structure 400 and the subsequently formed second transistor structure, and making the bonding layer 500 compatible with semiconductor processes. The bonding layer 500 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the bonding layer 500 is made of silicon oxide. By using silicon oxide, bonding can be achieved through melt bonding, which is beneficial for improving bonding efficiency and bonding strength; moreover, it is also beneficial for further improving the electrical isolation effect of the bonding layer 500; in addition, by using silicon oxide, the bonding temperature is lower, thereby reducing the impact on the performance of the first transistor in the first transistor structure 400.

[0117] It should be noted that in other embodiments, a conductive layer may also be provided in the bonding layer, thereby realizing the redistribution of the circuit through the conductive layer to meet the design requirements.

[0118] In this embodiment, the bonding layer 500 is located between the second substrate 630 and the first transistor structure 400, and the bonding layer 500 covers the top of the first gate electrode layer 430 and the top of the first interlayer dielectric layer 220.

[0119] As an example, taking the bonding surface 403 of the first transistor structure 400 as the first bonding surface (not shown), and the second substrate 630 including a second bonding surface (not shown), the step of bonding the second substrate 630 to the bonding surface 403 using the bonding layer 500 includes: forming a first sub-bonding layer (not shown) on the first bonding surface, forming a second sub-bonding layer (not shown) on the second bonding surface; and placing the first sub-bonding layer and the second sub-bonding layer opposite to each other and bonding them together to bond the second substrate 630 to the bonding surface 403. Accordingly, the first sub-bonding layer and the second sub-bonding layer constitute a stacked bonding layer 500. In this embodiment, the materials of both the first sub-bonding layer and the second sub-bonding layer are silicon oxide, thereby achieving silicon oxide-silicon oxide fusion bonding.

[0120] It should be noted that in other embodiments, the second substrate may be bonded to the bonding surface only on one of the first bonding surface and the second bonding surface after the bonding layer is formed on one of the two bonding surfaces.

[0121] In this embodiment, a deposition process (e.g., chemical vapor deposition) is used to form the bonding layer 500.

[0122] In this embodiment, taking the subsequently formed second transistor as a GAA transistor as an example, in the step of bonding the second substrate 630 to the bonding surface 403 using the bonding layer 500, the second substrate 630 includes one or more stacked channel material stacks 640. The channel material stack 640 includes a sacrificial material layer 650 and a channel material layer 660 located on the sacrificial material layer 650. In the same channel material stack 640, the sacrificial material layer 650 is closer to the bonding layer 500 than the channel material layer 660.

[0123] The sacrificial material layer 650 is used to prepare for the subsequent formation of the sacrificial layer, and the channel material layer 660 is used to prepare for the subsequent formation of the second channel layer. In this embodiment, only one channel material stack 640 is illustrated. However, the number of channel material stacks 640 is not limited to one.

[0124] Specifically, taking the second substrate 630 including a channel material stack 640 as an example, the steps of forming the second substrate 630 and the second sub-bonding layer include: providing an initial substrate, the material of which is the same as the material of the channel material layer 660; forming a sacrificial material layer 650 on the channel material layer 660, the sacrificial material layer 650 and the channel material layer 660 constituting a channel material stack 640; and forming the second sub-bonding layer on the sacrificial material layer 650 after forming the channel material stack 640.

[0125] In this embodiment, after the second substrate 630 is bonded to the bonding surface 403 using the bonding layer 500, the initial substrate is thinned until the remaining initial substrate reaches the target thickness. The target thickness of the remaining initial substrate is equal to the target thickness of the channel material layer 660.

[0126] Accordingly, when the second substrate 630 includes a plurality of stacked channel material stacks 640, after the formation of the first channel material stack 640 and before the formation of the second sub-bonding layer, the method further includes: alternately forming a channel material layer 660 and a sacrificial material layer 650 on the first channel material stack 640 until the total number of channel material stacks 660 reaches the target number.

[0127] Therefore, in this embodiment, after the second transistor structure is subsequently formed, the second transistor structure does not contain an additional substrate (e.g., a base).

[0128] The channel material layer 660 may be made of silicon, silicon germanide, germanium, or a group III-V semiconductor material. The material of the channel material layer 660 is determined based on the channel conductivity type and performance requirements of the second transistor. As an example, the channel material layer 660 may be made of silicon.

[0129] Based on the material of the channel material layer 660, the sacrificial material layer 650 is selected from materials with an etch selectivity ratio that is similar to that of the channel material layer 660. In this embodiment, the channel material layer 660 is made of silicon; therefore, the sacrificial material layer 650 is made of silicon germanide. Silicon germanide has a high etch selectivity ratio with silicon, making it easier to remove the sacrificial material layer 650 subsequently and reducing damage to the channel material layer 660 during the removal process.

[0130] It should be noted that in other embodiments, when the subsequently formed second transistor is a FinFET, in the step of bonding the second substrate to the bonding surface using a bonding layer, the second substrate is a fin material layer. Correspondingly, the initial substrate contains the same material layer as the fin material layer, and after bonding, the initial substrate is thinned until the target thickness of the fin material layer is reached.

[0131] Reference Figure 15 and Figure 16 , Figure 15 This is a schematic diagram of the projection patterns of the first channel layer, the first gate electrode layer, the first source / drain doped layer, and the second channel layer on the first substrate. Figure 16 It is a cross-sectional view along a direction perpendicular to the third direction, graphically representing the second base 630, forming along the third direction (e.g. Figure 15 (As shown in the C direction) Extend the second channel layer by 600.

[0132] For ease of illustration, Figure 16 The first transistor structure 400 is not shown.

[0133] The second channel layer 600 is used to provide the channel for the second transistor. As an example, the material of the second channel layer 600 is silicon.

[0134] Specifically, in the step of patterning the second substrate 630, the channel material stack 640 is patterned as one or more stacked channel stacks 670 protruding from the bonding layer 500. The channel stack 670 includes a sacrificial layer 680 and a sub-channel layer 610 located on the sacrificial layer 680. The one or more sub-channel layers 610 constitute the second channel layer 600.

[0135] It should be noted that the first channel layer 200 includes one or more spaced-apart first sub-channel layers 210. Therefore, in the step of patterning the second substrate 630, the sub-channel layer 610 in the channel stack 670 is defined as the second sub-channel layer 610, and the one or more second sub-channel layers 610 constitute the second channel layer 600. In other embodiments, when the second substrate is a fin material layer, the second channel layer in the step of patterning the second substrate is a fin (specifically a second fin) protruding from the bonding layer.

[0136] In this embodiment, after the second substrate 630 is bonded to the bonding surface 403 using the bonding layer 500, the second substrate 630 is patterned. During the patterning of the second substrate 630, the structure in the first transistor 400 can be used as an alignment mark, which facilitates precise control of the relative positional relationship between the second channel layer 600 and the first channel layer 200. Correspondingly, when the second gate electrode layer is subsequently formed, the structure in the first transistor 400 can also be used as an alignment mark, which facilitates precise control of the relative positional relationship between the second gate electrode layer and the first gate electrode layer 430.

[0137] Reference Figures 17 to 25 A second gate dielectric layer 820 covering the second channel layer 600, a second gate electrode layer 830 spanning the second channel layer 600 and covering the second gate dielectric layer 820, and a second source / drain doped layer 700 located on bonding layers 500 on both sides of the second gate electrode layer 830 are formed, the second gate electrode layer 830 being along the fourth direction (e.g., Figure 23 Extending in the direction shown in the middle D direction, the fourth direction has a second included angle β with the third direction (as shown in the middle D direction). Figure 23 As shown), the second source / drain doped layer 700 is in contact with the end of the second channel layer 600 located below the second gate electrode layer 830. The second gate electrode layer 830, the second gate dielectric layer 820, the second source / drain doped layer 700, and the second channel layer 600 are used to form the second transistor structure 800, wherein the second included angle β is not equal to the first included angle α.

[0138] In the semiconductor structure formation method provided in this embodiment, when forming the first transistor structure 400, the first channel layer 200 extends along a first direction, the first gate electrode layer 430 extends along a second direction, and the first direction and the second direction have a first included angle α. When forming the second transistor structure 800, the second substrate 630 is patterned, a second channel layer 600 extending along a third direction is formed, and the second gate electrode layer 830 extends along a fourth direction, the fourth direction and the third direction having a second included angle β. Since the second included angle β is not equal to the first included angle α, it is easier to ensure that the first channel layer 200 in the first transistor structure 400 and the second transistor structure 800... The second channel layer 600 and the second gate electrode layer 830 are horizontally offset, so that the first gate electrode layer 430 in the first transistor structure 400 and the second channel layer 600 and the second gate electrode layer 830 in the second transistor structure 800 are horizontally offset. Furthermore, even if the first channel layer 200 in the first transistor structure 400 coincides with the second channel layer 600 or the second gate electrode layer 830 in the second transistor structure 800 in the horizontal direction, since the second included angle β is not equal to the first included angle α, it can still be ensured that the first gate electrode layer 430 in the first transistor structure 400 is not completely blocked by the second transistor structure 800. Similarly, even if... The first gate electrode layer 430 in the first transistor structure 400 coincides with the second channel layer 600 or the second gate electrode layer 830 in the second transistor structure 800 in the horizontal direction. Since the second included angle β is not equal to the first included angle α, it can still be ensured that the first channel layer 200 in the first transistor structure 400 is not completely blocked by the second transistor structure 800 in the horizontal direction. That is to say, the probability that the first gate electrode layer 430 and the first source / drain doped layer 300 in the first transistor structure 400 are completely blocked by the second transistor structure 800 is low. Correspondingly, when it is necessary to bring out the electrical properties of the first source / drain doped layer or the first gate electrode layer in the first transistor structure... For example, when it is necessary to form a source / drain plug electrically connected to the first source / drain doped layer, or a gate plug electrically connected to the first gate electrode layer 430, the probability of the plug formation process being blocked by the second transistor structure 800 can be reduced. This makes it easier to bring out the electrical properties of the first gate electrode layer 430 or the first source / drain doped layer 300 in the first transistor structure 400. Furthermore, when bringing out the electrical properties of the first source / drain doped layer 300 or the first gate electrode layer 430 in the first transistor structure 400, it is not necessary to extend the length of the first source / drain doped layer 300 and the first gate electrode layer 430 excessively to form the corresponding source / drain plug and gate plug, thereby saving the area occupied by the semiconductor structure.

[0139] refer to Figure 23 , Figure 23(a) is a schematic diagram of the projection pattern of the first channel layer 200, the first gate electrode layer 430, the first source / drain doped layer 300, the second channel layer 600, the second gate electrode layer 830, and the second source / drain doped layer 700 onto the substrate 100. Figure 4 (b) is a schematic diagram of the projection pattern of the second channel layer 600, the second gate electrode layer 830, and the second source / drain doped layer 700 on the substrate 100. The second channel layer 600 extends along a third direction, the second gate electrode layer 830 extends along a fourth direction, and the third and fourth directions have a second included angle β.

[0140] Wherein, the second included angle β is the angle through which the third direction rotates clockwise until it first coincides with the fourth direction.

[0141] It should be noted that the second included angle β should not be too small or too large. If the second included angle β is too small, the extension direction of the second gate electrode layer 830 will be too close to the extension direction of the second channel layer 600, causing unnecessary difficulties in forming the second source / drain doped layer 700 and affecting the performance of the CFET structure. If the second included angle β is too large, it will still cause the extension direction of the second gate electrode layer 831 to be too close to the extension direction of the second channel layer 600, thus causing unnecessary difficulties in forming the second source / drain doped layer 700 and affecting the performance of the CFET structure. Therefore, in this embodiment, the second included angle β is 45° to 135°.

[0142] In this embodiment, the first included angle α and the second included angle β are not equal. Specifically, the first direction is parallel to the third direction, and the second direction has an angle with the fourth direction; or, the first direction has an angle with the third direction, and the second direction is parallel to the fourth direction; or, the first direction has an angle with the third direction, and the second direction has an angle with the fourth direction. In this embodiment, taking the first direction having an angle with the third direction and the second direction having an angle with the fourth direction as an example, it is beneficial to ensure that the first channel layer 200 and the first gate electrode layer 430 in the first transistor structure 400 are not completely blocked by the second channel layer 600 or the second gate electrode layer 830 in the second transistor structure 800, thereby facilitating the simultaneous extraction of the electrical properties of the first channel layer 200 and the first gate electrode layer 430 in the first transistor structure 400 in a smaller area.

[0143] It should be noted that the difference in degree between the first included angle α and the second included angle β should not be too small. If the difference in degree between the first included angle α and the second included angle β is too small, when the first channel layer 200 in the first transistor structure 400 coincides with the second channel layer 600 or the second gate electrode layer 830 in the second transistor structure 800 in the horizontal direction, because the first included angle α and the second included angle β are too close, the first gate electrode layer 430 in the first transistor structure 400 is easily completely blocked by the second channel layer 600 or the second gate electrode layer 830 in the second transistor structure 800, thus making it difficult to block the first... Similarly, when the first gate electrode layer 430 in the first transistor structure 400 coincides with the second channel layer 600 or the second gate electrode layer 830 in the second transistor structure 800 in the horizontal direction, the first channel layer 200 in the first transistor structure 400 is easily completely blocked by the second channel layer 600 or the second gate electrode layer 830 in the second transistor structure 800, making it difficult to electrically expose the first source / drain doped layer 300 and affecting the performance of the CFET structure. Therefore, in this embodiment, the difference in degree between the first included angle α and the second included angle β is greater than 5°.

[0144] In this embodiment, the second gate dielectric layer 820 and the second gate electrode layer 830 are formed by forming a high k last metal gate last layer. Therefore, before forming the second gate dielectric layer 820, the second gate electrode layer 830 and the second source / drain doped layer 700, a step of forming a pseudo gate structure is also included.

[0145] Accordingly, before forming the bottom source / drain plugs and the bottom gate plugs, the formation method further includes forming a second interlayer dielectric layer 620 on the bonding layer 500. In this embodiment, the second interlayer dielectric layer 620 covers the top of the second source / drain doped layer 700 and the sidewalls of the second gate electrode layer 830.

[0146] The steps for forming the second transistor structure 800 are described in detail below with reference to the accompanying drawings.

[0147] Reference Figures 17 to 19 , Figure 17 This is a schematic diagram of the projection pattern of the first channel layer, the first gate electrode layer, the first source / drain doped layer, the second channel layer, and the dummy gate structure on the first substrate. Figure 18 It is a cross-sectional view along the fourth direction. Figure 19It is a cross-sectional view along the third direction, on which a pseudo-gate structure 850 extending along the second direction is formed on the bonding layer 500. The pseudo-gate structure 850 spans the second channel layer 600 and covers part of the top and part of the sidewalls of the second channel layer 600. The pseudo-gate structure 850 extends along the fourth direction.

[0148] For ease of illustration, Figure 18 and Figure 19 The first transistor structure 400 is not shown.

[0149] The pseudo-gate structure 850 is used to occupy space for the subsequent formation of the second gate electrode layer 830.

[0150] Specifically, the pseudo-gate structure 850 spans the channel stack 670 and covers part of the top and part of the sidewalls of the channel stack 670.

[0151] In this embodiment, the dummy gate structure 850 includes a dummy gate oxide layer (not shown) covering the channel stack 670, and a dummy gate layer (not shown) covering the dummy gate oxide layer. As an example, the material of the dummy gate oxide layer is silicon oxide or silicon oxynitride, and the material of the dummy gate layer is polycrystalline silicon, amorphous silicon, or amorphous carbon.

[0152] In other embodiments, when the second channel layer is a second fin protruding from the bonding layer, the pseudo-gate structure correspondingly spans the second fin and covers part of the top and part of the sidewalls of the second fin.

[0153] Continue to refer to Figures 17 to 19 After forming the dummy gate structure 850, the method further includes: forming a second gate sidewall 840 on the sidewall of the dummy gate structure 850; after forming the second gate sidewall 840, forming a second source / drain doped layer 700 in the second channel layer 600 on both sides of the dummy gate structure 850, wherein the second source / drain doped layer 700 is in contact with the end of the second channel layer 600 located below the dummy gate structure 850.

[0154] The second source / drain doped layer 700 is used as the source or drain of the second transistor. In this embodiment, the second source / drain doped layer 700 includes a second epitaxial layer doped with ions, and the conductivity type of the doped ions in the second epitaxial layer is the same as the channel conductivity type of the second transistor. Specifically, after removing the second channel layer 600 on both sides of the dummy gate structure 850, the second source / drain doped layer 700 is formed using an epitaxial process.

[0155] It should be noted that, after removing the second channel layer 600 on both sides of the pseudo-gate structure 850 and before forming the second source / drain doped layer 700, the process also includes: laterally etching out a portion of the exposed sacrificial layer 680 to form a trench surrounded by adjacent second channel layers 600 and sacrificial layer 680, or a trench surrounded by second channel layer 600, bonding layer 500 and sacrificial layer 680; and forming a second inner sidewall (not shown) in the trench.

[0156] For a detailed description of the second gate sidewall 840, the second source / drain doped layer 700, and the second inner sidewall, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0157] Continue to refer to Figures 17 to 19 After forming the second source / drain doped layer 700, a second interlayer dielectric layer 620 is formed on the bonding layer 500 on the side of the dummy gate structure 850. The second interlayer dielectric layer 620 covers the sidewall of the dummy gate structure 850 and exposes the top of the dummy gate structure 850.

[0158] The second interlayer dielectric layer 620 is used to isolate adjacent transistors in the subsequent second transistor structure, and also to provide a process basis for the subsequent formation of the second gate dielectric layer 820 and the second gate electrode layer 830. The material of the second interlayer dielectric layer 620 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 620 is silicon oxide.

[0159] Reference Figure 20 and Figure 21 , Figure 20 It is a cross-sectional view along the fourth direction. Figure 21 This is a cross-sectional view along a third direction, after removing the pseudo-gate structure 850 (e.g.) Figure 19 As shown), a gate opening 860 is formed in the second interlayer dielectric layer 620.

[0160] For ease of illustration, Figure 20 and Figure 21 The first transistor structure 400 is not shown.

[0161] The gate opening 860 provides space for the subsequent formation of the second gate dielectric layer and the second gate electrode layer. In this embodiment, after forming the gate opening 860, the method further includes: removing the sacrificial layer 680 exposed by the gate opening 860 to form a through-slot 870 communicating with the gate opening 860. The through-slot 870 also provides space for the subsequent formation of the second gate dielectric layer and the second gate electrode layer.

[0162] Reference Figures 22 to 25 , Figure 22This is a perspective view of an embodiment of the first transistor structure and the second transistor structure of the present invention. Figure 23 It is a schematic diagram of the projection pattern of the first channel layer, the first gate electrode layer, the first source / drain doped layer, the second channel layer, the second source / drain doped layer, and the second gate electrode layer on the first substrate. Figure 24 It is a cross-sectional view along the fourth direction. Figure 25 The diagram is a cross-sectional view along a third direction, showing a second gate dielectric layer 820 covering the bottom and sidewalls of the gate opening 860. The second gate dielectric layer 820 also covers the top and sidewalls of the second channel layer 220 in the gate opening 860. A second gate electrode layer 830 is formed in the gate opening 860. The second gate electrode layer 830, the second gate dielectric layer 820, the second source / drain doped layer 201, and the second channel layer 220 are used to constitute a second transistor structure 700.

[0163] For ease of illustration, Figure 22 The diagram only shows the first substrate, the first gate electrode layer, the first source / drain doped layer, the bonding layer, the second gate electrode layer, and the second source / drain doped layer. Figure 24 and Figure 25 The structure of the first transistor is not shown.

[0164] In this embodiment, the second gate dielectric layer 820 is used to isolate the second gate electrode layer 830 and the second channel layer 600. In this embodiment, the second gate dielectric layer 820 includes a second gate oxide layer and a second high-k gate dielectric layer covering the second gate oxide layer. The second gate oxide layer conformally covers each surface of the second channel layer 600; the second high-k gate dielectric layer conformally covers the gate oxide layer and also conformally covers the bottom and sidewalls of the gate opening 860. For a detailed description of the second gate dielectric layer 820, please refer to the foregoing description of the first gate dielectric layer 420, which will not be repeated here.

[0165] It should be noted that in the step of forming the second gate dielectric layer 820, the second gate dielectric layer 820 will also cover the top of the second interlayer dielectric layer 620.

[0166] The second gate electrode layer 830 is used to control the opening or closing of the channel of the second transistor. In this embodiment, the second gate electrode layer 830 surrounds the second gate dielectric layer 820 covering the second channel layer 600. In other embodiments, when the second channel layer is a second fin, the second gate electrode layer correspondingly spans the second fin and covers a portion of the top and a portion of the sidewalls of the second fin's second gate dielectric layer. In this embodiment, the second gate electrode layer 830 is a metal gate electrode layer, and the material of the second gate electrode layer 830 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the second gate electrode layer 830 includes a second work function layer (not shown) and a second electrode layer (not shown) covering the second work function layer. For a detailed description of the second work function layer and the second electrode layer, please refer to the foregoing descriptions of the first work function layer and the first electrode layer, respectively, which will not be repeated here.

[0167] Specifically, a second gate electrode layer 830 is formed in the gate opening 860 through a deposition step and a planarization step performed sequentially. During the planarization process, the second gate dielectric layer 820 located on top of the second interlayer dielectric layer 620 is also removed.

[0168] Reference Figures 26 to 28 , Figure 26 It's a 3D image. Figure 27 yes Figure 26 A cross-sectional view along the second direction. Figure 28 yes Figure 26 A cross-sectional view along the first direction, specifically, refer to... Figure 27 The forming method further includes: forming a bottom gate plug 910 through the bonding layer 500 that penetrates the second channel layer 600 and the side of the second gate electrode layer 830, the bottom gate plug 910 being located on top of the first gate electrode layer 430 and electrically connected to the first gate electrode layer 430.

[0169] For ease of illustration, Figure 26 The diagram only shows the first substrate, the first gate electrode layer, the first source / drain doped layer, the bonding layer, the second gate electrode layer, the second source / drain doped layer, the bottom source / drain plug, and the top source / drain plug. Figure 27 and Figure 28 The structure of the second transistor is not shown.

[0170] The bottom gate plug 910 is used to realize the electrical connection between the first gate electrode layer 430 and the external circuit structure.

[0171] In this embodiment, the step of forming the bottom gate plug 910 includes: forming a second contact hole that penetrates the top of the first gate electrode layer 430 through the second interlayer dielectric layer 620 and the bonding layer 500, with the second contact hole exposing the first gate electrode layer 430; filling the second contact hole with conductive material to form the bottom gate plug 910 located in the second contact hole.

[0172] In this embodiment, in the same step, a second contact hole is formed through the second interlayer dielectric layer 620 and the bonding layer 500 at the top of the first gate electrode layer 430. Therefore, in the process of forming the bottom gate plug 910, only one photolithography process is required, and the bottom gate plug 910 is an integral structure, thereby reducing the process difficulty of forming the bottom gate plug 910 (e.g., the alignment difficulty in the photolithography process).

[0173] refer to Figure 28 The forming method further includes: forming a bottom source / drain plug 900 through the bonding layer 500 that penetrates the second channel layer 600 and the side of the second gate electrode layer 830. The bottom source / drain plug 900 is located on top of the first source / drain doped layer 300 and is electrically connected to the first source / drain doped layer 300.

[0174] The bottom source / drain plug 900 is used to realize the electrical connection between the first source / drain doped layer 300 and the external circuit structure.

[0175] In this embodiment, the step of forming the bottom source / drain plug 900 includes: forming a first contact hole that penetrates the top of the first source / drain doped layer 300, the second interlayer dielectric layer 620, the bonding layer 500, and the first interlayer dielectric layer 220, with the first contact hole exposing the first source / drain doped layer 300; filling the first contact hole with conductive material to form the bottom source / drain plug 900 located in the first contact hole.

[0176] Similarly, in the same step, a first contact hole is formed through the second interlayer dielectric layer 620, the bonding layer 500, and the first interlayer dielectric layer 220, which penetrate the top of the first source / drain doped layer 300. Therefore, in the process of forming the bottom source / drain plug 900, only one photolithography process is required, and the bottom source / drain plug 900 is an integral structure, thereby reducing the process difficulty of forming the bottom source / drain plug 900.

[0177] Specifically, a conductive material is filled using a deposition process, and the conductive material is planarized to form a bottom source / drain plug 900 located in a first contact hole and a bottom gate plug 910 located in a second contact hole. As an example, the bottom source / drain plug 900 and the bottom gate plug 910 can be formed in the same step.

[0178] In this embodiment, the bottom source / drain plug 900 is made of one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN, and TiAlC, and the bottom gate plug 910 is made of one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN, and TiAlC. These materials have good conductivity.

[0179] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first transistor structure includes a substrate, a first channel layer on the substrate, a first gate dielectric layer covering the first channel layer, a first gate electrode layer covering the first gate dielectric layer, and first source / drain doped layers on the substrate on both sides of the first gate electrode layer. The first source / drain doped layers are in contact with the end of the first channel layer located below the first gate electrode layer. The first channel layer extends along a first direction, and the first gate electrode layer extends along a second direction. The first direction and the second direction have a first angle. The first transistor structure has a bonding surface located on one side of the first gate electrode layer. A bonding layer is located on the bonding surface of the first transistor structure; A second transistor structure is located on the bonding layer. The second transistor structure includes a second channel layer, a second gate dielectric layer covering the second channel layer, a second gate electrode layer covering the second gate dielectric layer, and second source / drain doped layers located on the bonding layers on both sides of the second gate electrode layer. The second source / drain doped layers are in contact with the end of the second channel layer located below the second gate electrode layer. The second channel layer extends along a third direction, and the second gate electrode layer extends along a fourth direction. The third direction and the fourth direction have a second included angle, which is not equal to the first included angle.

2. The semiconductor structure as described in claim 1, characterized in that, The first included angle is between 45° and 135°; the second included angle is between 45° and 135°.

3. The semiconductor structure as described in claim 1, characterized in that, The difference in degree between the first included angle and the second included angle is greater than 5°.

4. The semiconductor structure as described in claim 1, characterized in that, The first direction is parallel to the third direction, and the second direction forms an angle with the fourth direction; Alternatively, the first direction forms an angle with the third direction, and the second direction is parallel to the fourth direction; Alternatively, the first direction forms an angle with the third direction, and the second direction forms an angle with the fourth direction.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a bottom source / drain plug, a bonding layer penetrating the side of the second channel layer and the second gate electrode layer, the bottom source / drain plug being located on top of the first source / drain doped layer and electrically connected to the first source / drain doped layer.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a bottom gate plug, a bonding layer penetrating the second channel layer and the side of the second gate electrode layer, the bottom gate plug being located on top of the first gate electrode layer and electrically connected to the first gate electrode layer.

7. The semiconductor structure as described in claim 5, characterized in that, The first transistor structure further includes: a first interlayer dielectric layer, located on a substrate on the side of the first gate electrode layer, and covering the sidewall of the first gate electrode layer; The second transistor structure further includes: a second interlayer dielectric layer, located on the bonding layer and covering the second source / drain doped layer and the second gate electrode layer; The bottom source / drain plug penetrates the second interlayer dielectric layer, the bonding layer, and the first interlayer dielectric layer at the top of the first source / drain doped layer.

8. The semiconductor structure as described in claim 6, characterized in that, The first transistor structure further includes: a first interlayer dielectric layer, located on a substrate on the side of the first gate electrode layer, and covering the sidewall of the first gate electrode layer; The second transistor structure further includes: a second interlayer dielectric layer, located on the bonding layer and covering the second source / drain doped layer and the second gate electrode layer; The bottom gate plug penetrates the second interlayer dielectric layer, the bonding layer, and the first interlayer dielectric layer at the top of the first gate electrode layer.

9. The semiconductor structure as described in claim 5, characterized in that, The material of the bottom source / drain plug includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN, and TiAlC.

10. The semiconductor structure as described in claim 6, characterized in that, The bottom gate plug is made of one or more of the following materials: W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, Al, TiSiN, and TiAlC.

11. The semiconductor structure as claimed in claim 1, characterized in that, The first channel layer is a first fin protruding from the substrate; the first gate electrode layer spans the first fin and covers a portion of the top and a portion of the sidewalls of the first fin, forming a first gate dielectric layer. Alternatively, the first channel layer is located on the substrate and spaced apart from the substrate, and the first channel layer includes one or more spaced first sub-channel layers; the first gate electrode layer surrounds and covers the first gate dielectric layer on the first channel layer.

12. The semiconductor structure as claimed in claim 1, characterized in that, The second channel layer is a second fin protruding from the bonding layer; the second gate electrode layer spans the second fin and covers part of the top and part of the sidewalls of the second fin, and the second gate dielectric layer thereon. Alternatively, the second channel layer is located on the bonding layer and spaced apart from the bonding layer, and the second channel layer includes one or more spaced second sub-channel layers; the second gate electrode layer surrounds and covers the second gate dielectric layer on the second channel layer.

13. The semiconductor structure as claimed in claim 1, characterized in that, The first transistor structure includes an NMOS transistor, and the second transistor structure includes a PMOS transistor; Alternatively, the first transistor structure may include a PMOS transistor, and the second transistor structure may include an NMOS transistor.

14. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first channel layer includes silicon, silicon germanide, germanium, or a group III-V semiconductor material; the material of the second channel layer includes silicon, silicon germanide, germanium, or a group III-V semiconductor material.

15. The semiconductor structure as claimed in claim 1, characterized in that, The bonding layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide.

16. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; the material of the second gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

17. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC; the material of the second gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

18. A method for forming a semiconductor structure, characterized in that, include: A first transistor structure is formed, the first transistor structure including a first substrate, a first channel layer on the first substrate, a first gate dielectric layer covering the first channel layer, a first gate electrode layer covering the first gate dielectric layer, and a first source / drain doped layer on the first substrate on both sides of the first gate electrode layer, the first source / drain doped layer being in contact with the end of the first channel layer located below the first gate electrode layer, the first transistor structure having a bonding surface on one side of the first gate electrode layer, wherein the first channel layer extends along a first direction, the first gate electrode layer extends along a second direction, and the first direction and the second direction have a first included angle; The second substrate is bonded to the bonding surface using a bonding layer; The second substrate is graphically represented to form a second channel layer extending along a third direction; A second gate dielectric layer covering the second channel layer, a second gate electrode layer spanning the second channel layer and covering the second gate dielectric layer, and a second source / drain doped layer on bonding layers located on both sides of the second gate electrode layer are formed. The second gate electrode layer extends along a fourth direction, which has a second angle with a third direction. The second source / drain doped layer contacts the end of the second channel layer located below the second gate electrode layer. The second gate electrode layer, the second gate dielectric layer, the second source / drain doped layer, and the second channel layer are used to form a second transistor structure, wherein the second angle is not equal to the first angle.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The first direction is parallel to the third direction, and the second direction forms an angle with the fourth direction; Alternatively, the first direction forms an angle with the third direction, and the second direction is parallel to the fourth direction; Alternatively, the first direction forms an angle with the third direction, and the second direction forms an angle with the fourth direction.

20. The method for forming a semiconductor structure according to claim 18, characterized in that, The formation method further includes: forming a bottom source / drain plug of a bonding layer penetrating the side portion of the second channel layer and the second gate electrode layer, wherein the bottom source / drain plug is located at the top of the first source / drain doped layer and is electrically connected to the first source / drain doped layer.

21. The method for forming a semiconductor structure according to claim 18, characterized in that, The forming method further includes: forming a bottom gate plug of a bonding layer penetrating the side portion of the second channel layer and the second gate electrode layer, wherein the bottom gate plug is located at the top of the first gate electrode layer and is electrically connected to the first gate electrode layer.

22. The method for forming a semiconductor structure as described in claim 20, characterized in that, In the step of forming the first transistor structure, the first transistor structure further includes a first interlayer dielectric layer, which is located on a first substrate on the side of the first gate electrode layer and covers the sidewall of the first gate electrode layer. Before forming the bottom source / drain plug, the forming method further includes: forming a second interlayer dielectric layer on the bonding layer, wherein the second interlayer dielectric layer covers the top of the second source / drain doped layer and the sidewall of the second gate electrode layer; The step of forming the bottom source / drain plug includes: forming a first contact hole that penetrates the top of the first source / drain doped layer, the second interlayer dielectric layer, the bonding layer and the first interlayer dielectric layer, the first contact hole exposing the first source / drain doped layer; filling the first contact hole with conductive material to form a bottom source / drain plug located in the first contact hole.

23. The method for forming a semiconductor structure as described in claim 21, characterized in that, In the step of forming the first transistor structure, the first transistor structure further includes a first interlayer dielectric layer, which is located on a first substrate on the side of the first gate electrode layer and covers the sidewall of the first gate electrode layer. Before forming the bottom gate plug, the forming method further includes: forming a second interlayer dielectric layer on the bonding layer, wherein the second interlayer dielectric layer covers the top of the second source / drain doped layer and the sidewall of the second gate electrode layer; The step of forming the bottom gate plug includes: forming a second contact hole that penetrates the top of the first gate electrode layer, the second interlayer dielectric layer, the bonding layer and the first interlayer dielectric layer, the second contact hole exposing the first gate electrode layer; filling the second contact hole with a conductive material to form a bottom gate plug located in the second contact hole.

24. The method for forming a semiconductor structure as described in claim 18, characterized in that, In the step of forming the first transistor structure, the first channel layer is a first fin protruding from the substrate; the first gate electrode layer spans the first fin and covers a portion of the top and a portion of the sidewalls of the first fin, forming a first gate dielectric layer. Alternatively, the first channel layer is located on the substrate and spaced apart from the substrate, and the first channel layer includes one or more spaced first sub-channel layers; the first gate electrode layer surrounds and covers the first gate dielectric layer on the first channel layer.

25. The method for forming a semiconductor structure as described in claim 18, characterized in that, In the step of bonding the second substrate to the bonding surface using a bonding layer, the second substrate is a fin material layer; In the step of graphically representing the second substrate, the second channel layer is a fin protruding from the bonding layer; In the step of forming the second gate electrode layer, the second gate electrode layer spans the fin and covers a portion of the top and a portion of the sidewalls of the fin, where a second gate dielectric layer is located. Alternatively, in the step of bonding a second substrate to the bonding surface using a bonding layer, the second substrate includes one or more stacked channel material stacks, the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer, and in the same channel material stack, the sacrificial material layer is closer to the bonding layer than the channel material layer; In the step of patterning the second substrate, the channel material stack is patterned as one or more stacked channel stacks protruding from the bonding layer, the channel stack including a sacrificial layer and a second sub-channel layer located on the sacrificial layer, the one or more second sub-channel layers constituting the second channel layer; Before forming the second gate dielectric layer covering the second channel layer, the sacrificial layer is removed to expose the various surfaces of the second sub-channel layer; In the step of forming the second gate electrode layer, the second gate electrode layer spans the second channel layer and surrounds the second gate dielectric layer covering the second channel layer.

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