Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The structure includes: a substrate, the substrate having a fin on it, the fin including a plurality of device regions and isolation regions; a first gate structure and a first conductive structure, the first gate structure and the first conductive structure having a first isolation opening therebetween; a second isolation opening located in the isolation region; a dielectric structure and a second conductive structure, the second conductive structure located in the dielectric structure, and the dielectric structure enclosing the first isolation opening and the second isolation opening, the first isolation opening and the second isolation opening having an air cavity therein. Since the first isolation opening is not formed by removing the first gate structure, the first isolation opening occupies less space. In addition, when the dielectric structure encloses the first isolation opening and the second isolation opening, the air cavity is easily formed, and the isolation structure having the air cavity moderately generates stress on the channel region, which can improve the mobility of the carriers in the channel region, and thus improve the performance of the semiconductor structure finally formed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the improvement of the integration of semiconductor devices, the critical dimension of transistors is continuously reduced. However, with the sharp reduction of the size of transistors, the difficulty of inhibiting short channel effect is increased due to the unchangeable thickness of the first gate dielectric layer and the working voltage, and the channel leakage current of the transistor is increased.

[0003] The gate of a fin field-effect transistor (FinFET) has a fork-shaped 3D architecture similar to a fish fin. The channel of the FinFET protrudes from the substrate surface to form a fin, and the gate covers the top surface and the sidewall of the fin, so that the inversion layer is formed on each side of the channel, and the on and off of the circuit can be controlled on both sides of the fin. This design can increase the control of the gate on the channel region, thereby effectively inhibiting the short channel effect of the transistor. However, the fin field-effect transistor still has a short channel effect.

[0004] In addition, in order to further reduce the influence of the short channel effect on the semiconductor device and reduce the channel leakage current, a strained silicon technology is introduced in the technical field of semiconductor. The method of the strained silicon technology includes: forming a groove in the fin on both sides of the gate structure; and forming a source-drain doped layer in the groove by an epitaxial growth process.

[0005] In order to prevent the source-drain doped layers of different transistors from being connected to each other, an isolation layer needs to be formed in the fin, and at the same time, in order to reduce the area of the isolation layer and improve the integration of the formed semiconductor structure, the SDB (Single Diffusion Break) technology is introduced in the prior art.

[0006] However, the existing method still has many problems in the process of forming the semiconductor structure. SUMMARY

[0007] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor structure.

[0008] To solve the above problems, the application provides a semiconductor structure, comprising: a substrate, the substrate has a fin on it, the fin extends along a first direction, the fin comprises a plurality of device regions and isolation regions between adjacent device regions, the device regions and the isolation regions are arranged along the first direction; an isolation layer on the substrate, the isolation layer covers part of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin; a first gate structure on the isolation layer, the first gate structure is across the isolation regions; a plurality of source-drain doped layers in the device regions on both sides of the first gate structure; a first conductive structure on the source-drain doped layers, the first gate structure and the first conductive structure have a first isolation opening; a second isolation opening in the isolation regions, the first isolation opening exposes the second isolation opening, and the top surface of the second isolation opening is flush with the bottom surface of the first gate structure, and the bottom surface of the second isolation opening is flush with or lower than the bottom surface of the isolation layer; a dielectric structure and a second conductive structure, the second conductive structure is in the dielectric structure, and the dielectric structure encloses the first isolation opening and the second isolation opening, and the first isolation opening and the second isolation opening have an air cavity.

[0009] Optionally, it further comprises: a first isolation sidewall on the sidewall of the first gate structure.

[0010] Optionally, it further comprises: a second isolation sidewall on the sidewall of the first conductive structure.

[0011] Optionally, the material of the first isolation sidewall is the same as that of the second isolation sidewall; the material of the first isolation sidewall and the second isolation sidewall comprises silicon nitride, silicon oxynitride or silicon carbon nitride.

[0012] Optionally, the dielectric structure comprises a first dielectric layer.

[0013] Optionally, the second conductive structure is in the first dielectric layer, and the first dielectric layer encloses the first isolation opening and the second isolation opening, and the first isolation opening and the second isolation opening have an air cavity.

[0014] Optionally, the dielectric structure comprises a first dielectric layer and a second dielectric layer.

[0015] Optionally, the second conductive structure is in the first dielectric layer, and the second dielectric layer encloses the first isolation opening and the second isolation opening, and the first isolation opening and the second isolation opening have an air cavity.

[0016] Optionally, further comprising: a plurality of second gate structures and a plurality of second sidewall structures on the substrate, the second gate structures spanning over the device regions, the second sidewall structures on sidewalls of the second gate structures, the source-drain doped layers being between adjacent first gate structures and second gate structures, or between adjacent second gate structures.

[0017] Optionally, further comprising: a dielectric layer on the substrate, the dielectric layer covering sidewalls of the first gate structures and the second gate structures.

[0018] Optionally, the dielectric layer further covers sidewalls of the first conductive structures.

[0019] Correspondingly, the technical solution of the present application further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a fin portion thereon, the fin portion extending along a first direction, the fin portion comprising a plurality of device regions and a plurality of isolation regions between adjacent device regions, the device regions and the isolation regions being arranged along the first direction; forming an isolation layer on the substrate, the isolation layer covering part of sidewalls of the fin portion, and a top surface of the isolation layer being lower than a top surface of the fin portion; forming a first gate structure, a first conductive structure and a plurality of source-drain doped layers, the first gate structure being on the isolation layer and spanning over the isolation regions, the plurality of source-drain doped layers being in the device regions on two sides of the first gate structure, the first conductive structure being on the source-drain doped layers, and the first gate structure and the first conductive structure having a first isolation opening therebetween; etching the isolation regions exposed by the first isolation opening to form a second isolation opening in the isolation regions, a top surface of the second isolation opening being flush with a bottom surface of the first gate structure, and a bottom surface of the second isolation opening being flush with or lower than a bottom surface of the isolation layer; forming a dielectric structure and a second conductive structure, the second conductive structure being in the dielectric structure, and the dielectric structure enclosing the first isolation opening and the second isolation opening to form air cavities in the first isolation opening and the second isolation opening.

[0020] Optionally, in the process of forming the first gate structure and the first conductive structure, further comprising: forming a first sidewall structure between the first gate structure and the first conductive structure.

[0021] Optionally, the first sidewall structure comprises: a first isolation sidewall on sidewalls of the first gate structure, and a sacrificial sidewall on sidewalls of the first isolation sidewall.

[0022] Optionally, the dielectric structure comprises: a first dielectric layer.

[0023] Optionally, the method for forming the first isolation gap, the dielectric structure and the second conductive structure comprises: removing the sacrificial sidewall to form the first isolation gap between the first gate structure and the first conductive structure; forming the first dielectric layer on the first gate structure and the first conductive structure, the first dielectric layer enclosing the first isolation gap and the second isolation gap to form air cavities in the first isolation gap and the second isolation gap; and forming the second conductive structure in the first dielectric layer.

[0024] Optionally, the forming process of the first dielectric layer comprises a chemical vapor deposition process.

[0025] Optionally, the dielectric structure comprises: a first dielectric layer and a second dielectric layer.

[0026] Optionally, the method for forming the first isolation gap, the dielectric structure and the second conductive structure comprises: forming the first dielectric layer on the first gate structure and the first conductive structure; forming the second conductive structure in the first dielectric layer; removing part of the first dielectric layer and the sacrificial sidewall to form the first isolation gap between the first gate structure and the first conductive structure; and forming the second dielectric layer to enclose the first isolation gap and the second isolation gap to form air cavities in the first isolation gap and the second isolation gap.

[0027] Optionally, the forming process of the second dielectric layer comprises a chemical vapor deposition process.

[0028] Optionally, the material of the sacrificial sidewall is different from the material of the first isolation sidewall.

[0029] Optionally, the material of the sacrificial sidewall comprises: silicon oxide, silicon carbide or silicon boron carbon nitride; and the material of the first isolation sidewall comprises: silicon nitride, silicon oxynitride or silicon carbon nitride.

[0030] Optionally, the first sidewall structure further comprises: a second isolation sidewall located on the sidewall of the sacrificial sidewall, the material of the second isolation sidewall being the same as the material of the first isolation sidewall.

[0031] Optionally, in the process of forming the first gate structure and the first sidewall structure, the method further comprises: forming a plurality of second gate structures and a plurality of second sidewall structures on the substrate, the second gate structures being transverse to the device region, the second sidewall structures being located on the sidewalls of the second gate structures, the source / drain doped layer being located between adjacent first gate structures and second gate structures, or between adjacent second gate structures.

[0032] Optionally, before forming the first gate structure and the second gate structure, the method further comprises: forming a dielectric layer on the substrate, the dielectric layer covering sidewalls of the first gate structure and the second gate structure.

[0033] Optionally, before forming the first gate structure and the second gate structure, the method further comprises: forming a first dummy gate structure and a plurality of second dummy gate structures on the substrate, the first dummy gate structure spanning over the isolation region, the first sidewall structure being located on a sidewall of the first dummy gate structure, the second dummy gate structure spanning over the device region, the second sidewall structure being located on a sidewall of the second dummy gate structure.

[0034] Optionally, the method for forming the source-drain doped layer comprises: etching the fin portion with the first dummy gate structure, the first sidewall structure, the second dummy gate structure and the second sidewall structure as a mask to form a plurality of source-drain openings in the device region; and forming the source-drain doped layer in the source-drain openings.

[0035] Optionally, after forming the source-drain doped layer, the dielectric layer is formed, the dielectric layer covering sidewalls of the first dummy gate structure, the first sidewall structure, the second dummy gate structure and the second sidewall structure.

[0036] Optionally, the method for forming the first gate structure and the second gate structure comprises: removing the first dummy gate structure, forming a first gate opening in the dielectric layer, and removing the second dummy gate structure, forming a second gate opening in the dielectric layer; forming the first gate structure in the first opening, and forming the second gate structure in the second gate opening.

[0037] Optionally, the method for forming the first conductive structure comprises: forming a first conductive opening in the dielectric layer, the first conductive opening exposing the source-drain doped layer; and forming the first conductive structure in the first conductive opening, the first conductive structure being electrically connected with the source-drain doped layer.

[0038] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0039] The technical scheme of the present application comprises: the first conductive structure is located on the device region, and the first isolation opening is between the first gate structure and the first conductive structure; the second isolation opening is located in the isolation region, and the first isolation opening exposes the second isolation opening; the dielectric structure and the second conductive structure, the second conductive structure is located in the dielectric structure, and the dielectric structure seals the first isolation opening and the second isolation opening, and the first isolation opening and the second isolation opening have air cavities. Since the first isolation opening is not formed by removing the first gate structure, the first isolation opening occupies a smaller space, which can effectively improve the integration of the finally formed semiconductor structure.

[0040] In addition, since the first isolation opening and the second isolation opening occupy a smaller space, the dielectric structure can easily form air cavities when sealing the first isolation opening and the second isolation opening, and the isolation effect of the isolation structure with the air cavities is better. The stress generated by the isolation structure with the air cavities on the channel region is moderate, which can improve the mobility of carriers in the channel region, thereby improving the performance of the finally formed semiconductor structure.

[0041] The forming method of the technical scheme of the present application comprises: forming the first gate structure and the first conductive structure, the first gate structure spans the isolation region, the first conductive structure is located on the device region, and the first isolation opening is between the first gate structure and the first conductive structure; etching the isolation region exposed by the first isolation opening to form the second isolation opening in the isolation region; forming the dielectric structure and the second conductive structure, the second conductive structure is located in the dielectric structure, and the dielectric structure seals the first isolation opening and the second isolation opening to form air cavities in the first isolation opening and the second isolation opening. Since the first isolation opening is not formed by removing the first gate structure, the first isolation opening occupies a smaller space, which can effectively improve the integration of the finally formed semiconductor structure.

[0042] In addition, since the first isolation opening and the second isolation opening occupy a smaller space, the dielectric structure can easily form air cavities when sealing the first isolation opening and the second isolation opening, and the isolation effect of the isolation structure with the air cavities is better. The stress generated by the isolation structure with the air cavities on the channel region is moderate, which can improve the mobility of carriers in the channel region, thereby improving the performance of the finally formed semiconductor structure.

[0043] Further, the material of the sacrificial side wall is different from the material of the first isolation side wall. By using the different materials of the sacrificial side wall and the first isolation side wall, the sacrificial side wall can be removed by a self-aligned etching process, which can reduce the process difficulty. Attached Figure Description

[0044] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.

[0045] Figures 3 to 14 This is a schematic diagram of the steps in a semiconductor structure formation method according to an embodiment of the present invention;

[0046] Figures 15 to 18 This is a schematic diagram of the steps in a semiconductor structure formation method according to another embodiment of the present invention. Detailed Implementation

[0047] As described in the background section, existing methods still have many problems in the process of forming semiconductor structures. These will be explained in detail below with reference to the accompanying drawings.

[0048] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 having fins 101 extending along a first direction X, the fins 101 including a plurality of device regions A1 and an isolation region B1 located between adjacent device regions A1, the device regions A1 and the isolation region B1 being arranged along the first direction X; a first gate structure 102, a sidewall 103 and a first dielectric layer 104 are formed on the substrate 100, the first gate structure 102 spanning the isolation region along a second direction Y, the first direction X being perpendicular to the second direction Y, the sidewall 103 being located on the sidewall of the first gate structure 102, and the first dielectric layer 104 covering the sidewall of the first gate structure 102 and the sidewall of the sidewall 103.

[0049] Please refer to Figure 2 Remove the first gate structure 102, form a first isolation opening (not shown) in the first dielectric layer 104; etch the isolation region B1 exposed by the first isolation opening, form a second isolation opening (not shown) in the isolation region B1; form an isolation structure 105 in the first isolation opening and the second isolation opening.

[0050] In this embodiment, by forming the isolation structure 105, the source and drain doped layers of different transistors can be effectively prevented from interconnecting.

[0051] In the embodiment, the first gate structure 102 and the isolation region B1 are removed, and the isolation structure 105 formed has a large volume, so as to improve the isolation effect of the isolation structure. However, when the isolation structure 105 has a large volume, the stress generated on the channel region is also large, and when the stress generated on the channel region is too large, the mobility of the carriers in the channel region is reduced, and the performance of the semiconductor structure formed finally is affected.

[0052] On this basis, the application provides a semiconductor structure and a forming method thereof. The first gate structure and the first conductive structure are formed, and the first isolation opening is arranged between the first gate structure and the first conductive structure. Since the first isolation opening is not formed by removing the first gate structure, the first isolation opening occupies a small space, and the integration of the semiconductor structure formed finally can be effectively improved. In addition, the isolation effect of the isolation structure with the air cavity is good, and the stress generated on the channel region by the isolation structure with the air cavity is moderate, so as to improve the mobility of the carriers in the channel region, and the performance of the semiconductor structure formed finally is improved.

[0053] In order to make the above-mentioned objects, characteristics and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0054] Figures 3 to 14 is a structure schematic diagram of a forming process of a semiconductor structure in an embodiment of the application.

[0055] Please refer to Figure 3 and Figure 4 , Figure 3 is a semiconductor structure perspective view, Figure 4 is Figure 3 A-A line section view in the semiconductor structure, a substrate 200 is provided, the substrate 200 has a fin 201, the fin 201 extends along a first direction X, the fin 201 includes a plurality of device regions A1 and isolation regions B1 arranged between adjacent device regions A1, and the device regions A1 and the isolation regions B1 are arranged along the first direction X.

[0056] In the embodiment, the forming method of the substrate 200 and the fin 201 includes: providing an initial substrate (not shown) having a mask layer (not shown) exposing part of the top surface of the initial substrate; and etching the initial substrate with the mask layer as a mask to form the substrate 200 and the fin 201 on the substrate 200.

[0057] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0058] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the fin can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0059] Please refer to Figure 5 An isolation layer 202 is formed on the substrate 200, the isolation layer 202 covers part of the sidewall of the fin 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0060] In this embodiment, the forming method of the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200; etching to remove part of the initial isolation layer to form the isolation layer 202, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0061] The material of the isolation layer 202 is an insulating material, which includes silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 202 is silicon oxide.

[0062] After the isolation layer 202 is formed, a first gate structure, a first conductive structure and a plurality of source / drain doped layers are further formed, the first gate structure is located on the isolation layer 202 and across the isolation region B1, the plurality of source / drain doped layers are located in the device region A1 on both sides of the first gate structure, the first conductive structure is located on the source / drain doped layers, and the first gate structure and the first conductive structure have a first isolation opening therebetween. For specific forming process, please refer to Figures 6 to 12 .

[0063] Please refer to Figure 6 A first dummy gate structure 203 is formed on the substrate 200, and the first dummy gate structure 203 crosses the isolation region B1.

[0064] In this embodiment, in the process of forming the first dummy gate structure 203, a plurality of second dummy gate structures 204 are further formed on the substrate 200, and the second dummy gate structures 204 cross the device region A1.

[0065] In this embodiment, the first dummy gate structure 203 includes a first dummy gate dielectric layer and a first dummy gate layer (not labeled) located on the first dummy gate dielectric layer; and the second dummy gate structure 204 includes a second dummy gate dielectric layer and a second dummy gate layer (not labeled) located on the second dummy gate dielectric layer.

[0066] In the embodiment, the material of the first gate dielectric layer and the second dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first gate dielectric layer and the second dummy gate dielectric layer can also be silicon oxynitride.

[0067] In the embodiment, the material of the first dummy gate layer and the second dummy gate layer is polysilicon.

[0068] Please refer to Figure 7 The first sidewall structure is formed on the sidewall of the first dummy gate structure 203.

[0069] In the embodiment, in the process of forming the first sidewall structure, a second sidewall structure 205 is also formed on the sidewall of the second dummy gate structure 204.

[0070] In the embodiment, the first sidewall structure includes a first isolation sidewall 206 on the sidewall of the first gate structure 203, a sacrificial sidewall 207 on the sidewall of the first isolation sidewall 206, and a second isolation sidewall 208 on the sidewall of the sacrificial sidewall 207. In other embodiments, the second isolation sidewall can also be not provided.

[0071] In the embodiment, the material of the first isolation sidewall 206 and the second isolation sidewall 208 is the same, and the material of the first isolation sidewall 206 and the sacrificial sidewall 207 is different. By making the material of the first isolation sidewall 206 and the sacrificial sidewall 207 different, the etching damage to the first isolation sidewall 206 and the second isolation sidewall 208 can be reduced when the sacrificial sidewall 207 is removed subsequently. At the same time, by making the material of the sacrificial sidewall 207 and the material of the first isolation sidewall 206 different, the sacrificial sidewall 207 can be removed by a self-aligned etching process, which can reduce the process difficulty.

[0072] In the embodiment, the material of the sacrificial sidewall 207 is silicon oxide, and the material of the first isolation sidewall 206 and the second isolation sidewall 208 is silicon nitride.

[0073] In other embodiments, the material of the sacrificial sidewall can also be silicon carbide or silicon boron carbon nitride, and the material of the first isolation sidewall and the second isolation sidewall can also be silicon oxynitride or silicon boron carbon nitride.

[0074] In the embodiment, the second sidewall structure 205 and the first sidewall structure are the same in structure, and the first sidewall structure and the second sidewall structure 205 are formed simultaneously.

[0075] Please refer to Figure 8 A plurality of source-drain doped layers 209 are formed in the device area A1.

[0076] In the embodiment, the forming method of the source-drain doped layer 209 includes: taking the first dummy gate structure 203, the first sidewall structure, the second dummy gate structure 205 and the second sidewall structure 205 as a mask to etch the device region A1, and forming a plurality of source-drain openings (not shown) in the device region A1; forming the source-drain doped layer 209 in the source-drain openings, the source-drain doped layer 209 is located between adjacent first dummy gate structures 203 and second dummy gate structures 204, or between adjacent second dummy gate structures 204.

[0077] Please refer to Figure 9 After forming the source-drain doped layer 209, a dielectric layer 210 is formed on the substrate 200, and the dielectric layer 210 covers the first dummy gate structure 203.

[0078] In the embodiment, the dielectric layer 210 also covers the sidewall of the second dummy gate structure 204.

[0079] In the embodiment, the material of the dielectric layer 210 is silicon oxide; in other embodiments, the material of the dielectric layer can also be low-K dielectric material (referring to dielectric material with relative dielectric constant less than 3.9) or ultra-low-K dielectric material (referring to dielectric material with relative dielectric constant less than 2.5).

[0080] Please refer to Figure 10 After forming the dielectric layer 210, the first conductive structure 211 is formed in the dielectric layer 210.

[0081] In the embodiment, the forming method of the first conductive structure 211 includes: forming a first conductive opening (not shown) in the dielectric layer 210, the first conductive opening exposes the source-drain doped layer 209; forming the first conductive structure 211 in the first conductive opening, the first conductive structure 211 is electrically connected with the source-drain doped layer 209.

[0082] In the embodiment, the top surface of the first conductive structure 211 is lower than the top surface of the dielectric layer 210. Therefore, after forming the first conductive structure 211, a covering layer 219 is also formed in the first conductive opening, the covering layer 219 is located on the first conductive structure 211, and the top surface of the covering layer 219 is flush with the top surface of the dielectric layer 210.

[0083] Please refer to Figure 11 After forming the first conductive structure 211, the first gate structure 212 is formed.

[0084] In the embodiment, in the process of forming the first gate structure 212, a second gate structure 213 is also formed.

[0085] In the embodiment, the forming method of the first gate structure 212 and the second gate structure 213 includes: removing the first dummy gate structure 203, forming a first gate opening (not shown) in the dielectric layer 210, and removing the second dummy gate structure 213, forming a second gate opening (not shown) in the dielectric layer 210; forming the first gate structure 212 in the first opening, and forming the second gate structure 213 in the second gate opening.

[0086] In the embodiment, the first gate structure 212 includes a first metal gate layer and a first high-K dielectric layer (not shown); the second gate structure 213 includes a second metal gate layer and a second high-K dielectric layer (not shown).

[0087] The material of the first metal gate layer and the second metal gate layer includes metal, and the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In the embodiment, the material of the first metal gate layer and the second metal gate layer is tungsten.

[0088] Please refer to Figure 12 , removing the sacrificial side wall 207, and forming the first isolation opening 214 between the first gate structure 212 and the first conductive structure 211.

[0089] In the embodiment, the method of removing the sacrificial side wall 207 includes: forming a patterned layer (not shown) on the dielectric layer 210, the patterned layer exposes the top surface of the sacrificial side wall 207; etching the sacrificial side wall 207 with the patterned layer as a mask, and forming the first isolation opening 214 between the first gate structure 212 and the first conductive structure 211.

[0090] In the embodiment, the process of removing the sacrificial side wall 207 adopts a wet etching process; in other embodiments, the process of removing the sacrificial side wall can also adopt a dry etching process.

[0091] Please refer to Figure 13 , etching the isolation region B1 exposed by the first isolation opening 214, and forming a second isolation opening 215 in the isolation region.

[0092] In the embodiment, since the first isolation opening 214 is not formed by removing the first gate structure 212, the occupation space of the first isolation opening 214 is smaller, which can effectively improve the integration of the finally formed semiconductor structure.

[0093] In addition, since the first isolation opening 214 and the second isolation opening 215 have small occupied spaces, when the medium structure formed subsequently encloses the first isolation opening 214 and the second isolation opening 215, an air cavity is easily formed, the isolation effect of the isolation structure with the air cavity is better, and the stress generated by the isolation structure with the air cavity on the channel region is moderate, which can improve the mobility of the carriers in the channel region, and further improve the performance of the semiconductor structure formed finally.

[0094] Please refer to Figure 14 , a medium structure and a second conductive structure 216 are formed, the second conductive structure 216 is located in the medium structure, and the medium structure encloses the first isolation opening 214 and the second isolation opening 215 to form an air cavity 217 in the first isolation opening 214 and the second isolation opening 215.

[0095] In the embodiment, the medium structure includes a first medium layer 218.

[0096] In the embodiment, the forming method of the medium structure and the second conductive structure 216 includes: forming the first medium layer 218 on the first gate structure 212 and the first conductive structure 211, the first medium layer 218 enclosing the first isolation opening 214 and the second isolation opening 215 to form the air cavity 217 in the first isolation opening 214 and the second isolation opening 215; and forming the second conductive structure 216 in the first medium layer 218.

[0097] In the embodiment, the forming process of the first medium layer 218 adopts a chemical vapor deposition process. By forming the first medium layer 218 through the chemical vapor deposition process, the air cavity 217 is more easily formed in the first isolation opening 214 and the second isolation opening 215.

[0098] Figures 15 to 18 is a structural schematic diagram of a semiconductor structure forming process of another embodiment of the present application.

[0099] The embodiment is based on the above-mentioned embodiments and continues to describe the forming method of the semiconductor structure. The difference between the embodiment and the above-mentioned embodiments is that: after the first gate structure (as shown in Figure 11 ) is formed, the medium structure and the second conductive structure are formed first, and then the first isolation opening is formed, and the medium structure includes a first medium layer and a second medium layer. The following will be specifically described with reference to the accompanying drawings.

[0100] Please refer to Figure 15After the first gate structure 212 is formed, the first dielectric layer 218 is formed on the first gate structure 212 and the first conductive structure 211; and the second conductive structure 216 is formed in the first dielectric layer 218.

[0101] The formation of the first dielectric layer 218 and the second conductive structure 216 will be described in detail in the following Figure 14 The related descriptions are not repeated here.

[0102] The first dielectric layer 218 and the second conductive structure 216 will be described in detail in the following Figure 16 The first dielectric layer 218 and the second conductive structure 216 will be described in detail in the following

[0103] The process of removing the sacrificial sidewall 207 will be described in detail in the following Figure 12 The related descriptions are not repeated here.

[0104] The first dielectric layer 218 and the second conductive structure 216 will be described in detail in the following Figure 17 The first dielectric layer 218 and the second conductive structure 216 will be described in detail in the following

[0105] The process of forming the second isolation opening 215 will be described in detail in the following Figure 13 The related descriptions are not repeated here.

[0106] The first dielectric layer 218 and the second conductive structure 216 will be described in detail in the following Figure 18 The first dielectric layer 218 and the second conductive structure 216 will be described in detail in the following

[0107] In the embodiment, the second dielectric layer 220 is formed by using a chemical vapor deposition process. By forming the second dielectric layer 220 by using the chemical vapor deposition process, it is easier to form the air cavity 217 in the first isolation opening 214 and the second isolation opening 215.

[0108] Correspondingly, the embodiment of the present application further provides a semiconductor structure, which will be described in the following Figure 14The semiconductor structure includes: a substrate 200, the substrate 200 has a fin 201 on the substrate 200, the fin 201 extends along a first direction X, the fin 201 includes a plurality of device regions A1 and isolation regions B1 located between adjacent device regions A1, the device regions A1 and the isolation regions B1 are arranged along the first direction X; an isolation layer 202 located on the substrate 200, the isolation layer 202 covers part of the sidewall of the fin 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201; a first gate structure 212 located on the isolation layer 202, the first gate structure 212 is located on the isolation regions B1; a plurality of source-drain doped layers 209 located in the device regions B1 on both sides of the first gate structure 212; a first conductive structure 211 located on the source-drain doped layers 209, the first gate structure 212 and the first conductive structure 211 have a first isolation opening 214 therebetween; a second isolation opening 215 located in the isolation regions B1, the first isolation opening 214 exposes the second isolation opening 215, and the top surface of the second isolation opening 215 is flush with the bottom surface of the first gate structure 212, and the bottom surface of the second isolation opening 215 is flush with or lower than the bottom surface of the isolation layer 202; a dielectric structure and a second conductive structure 216, the second conductive structure 216 is located in the dielectric structure, and the dielectric structure encloses the first isolation opening 214 and the second isolation opening 215, and the first isolation opening 214 and the second isolation opening 215 have an air cavity 217 therebetween.

[0109] In the embodiment, since the first isolation opening 214 is not formed by removing the first gate structure 212, the first isolation opening 214 has a small occupied space, and the integration of the finally formed semiconductor structure can be effectively improved.

[0110] In addition, since the first isolation opening 214 and the second isolation opening 215 have small occupied spaces, the dielectric structure enclosing the first isolation opening 214 and the second isolation opening 215 is easy to form the air cavity 217, the isolation effect of the isolation structure with the air cavity 217 is good, and the stress generated by the isolation structure with the air cavity 217 on the channel region is moderate, which can improve the mobility of the carriers in the channel region, and further improve the performance of the finally formed semiconductor structure.

[0111] In the embodiment, the first isolation sidewall 206 located on the sidewall of the first gate structure 212 is further included.

[0112] In the embodiment, the second isolation sidewall 208 located on the sidewall of the first conductive structure 211 is further included.

[0113] In the embodiment, the material of the first isolation spacer 206 is the same as the material of the second isolation spacer 208; the material of the first isolation spacer 206 and the second isolation spacer 208 is silicon nitride.

[0114] In other embodiments, the material of the first isolation spacer and the second isolation spacer can also be silicon oxynitride or silicon carbon nitride.

[0115] In the embodiment, the dielectric structure includes a first dielectric layer 218; the second conductive structure 216 is located in the first dielectric layer 218, and the first dielectric layer 218 encloses the first isolation opening 214 and the second isolation opening 215, which have air cavities 217 therein.

[0116] In other embodiments, the dielectric structure includes a first dielectric layer and a second dielectric layer; the second conductive structure is located in the first dielectric layer, and the second dielectric layer encloses the first isolation opening and the second isolation opening, which have air cavities therein.

[0117] In the embodiment, it further includes a plurality of second gate structures 213 and a plurality of second spacer structures 205 located on the substrate 200, the second gate structures 213 span over the device region A1, and the second spacer structures 205 are located on the sidewalls of the second gate structures 213; the source / drain doped layer 209 is located between adjacent first gate structures 212 and second gate structures 213, or between adjacent second gate structures 213.

[0118] In the embodiment, it further includes a dielectric layer 210 located on the substrate 200, which covers the sidewalls of the first gate structures 212 and the second gate structures 213.

[0119] In the embodiment, the dielectric layer 210 also covers the sidewalls of the first conductive structure 211, and the first conductive structure 210 is electrically connected with the source / drain doped layer 209.

[0120] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate having a fin on the substrate, the fin extending along a first direction, the fin comprising a plurality of device regions and isolation regions between adjacent device regions, the device regions and the isolation regions arranged along the first direction; an isolation layer on the substrate, the isolation layer covering part of sidewalls of the fin, and a top surface of the isolation layer being lower than a top surface of the fin; a first gate structure on the isolation layer, the first gate structure spanning over the isolation regions; a plurality of source-drain doped layers in device regions on both sides of the first gate structure; a first conductive structure on the source-drain doped layers, the first gate structure and the first conductive structure having a first isolation opening therebetween; a second isolation opening in the isolation regions, the first isolation opening exposing the second isolation opening, and a top surface of the second isolation opening being flush with a bottom surface of the first gate structure, and a bottom surface of the second isolation opening being flush with or lower than a bottom surface of the isolation layer; a dielectric structure and a second conductive structure in the dielectric structure, the dielectric structure enclosing the first isolation opening and the second isolation opening, the first isolation opening and the second isolation opening having an air cavity therein; wherein, the air cavity is used as an SDB structure for the device regions.

2. The semiconductor structure of claim 1, wherein, Further comprising: a first isolation sidewall on sidewalls of the first gate structure.

3. The semiconductor structure of claim 2, wherein, Further comprising: a second isolation sidewall on sidewalls of the first conductive structure.

4. The semiconductor structure of claim 3, wherein, The material of the first isolation sidewall is the same as the material of the second isolation sidewall; the material of the first isolation sidewall and the second isolation sidewall comprises silicon nitride, silicon oxynitride, or silicon carbon nitride.

5. The semiconductor structure of claim 1, wherein, The dielectric structure comprises a first dielectric layer.

6. The semiconductor structure of claim 5, wherein, The second conductive structure is in the first dielectric layer, and the first dielectric layer encloses the first isolation opening and the second isolation opening, the first isolation opening and the second isolation opening having an air cavity therein.

7. The semiconductor structure of claim 1, wherein, The dielectric structure comprises a first dielectric layer and a second dielectric layer.

8. The semiconductor structure of claim 7, wherein the first and second semiconductor layers are formed of a same material. The second conductive structure is in the first dielectric layer, and the second dielectric layer encloses the first isolation opening and the second isolation opening, the first isolation opening and the second isolation opening having an air cavity therein.

9. The semiconductor structure of claim 1, wherein, Further comprising: a plurality of second gate structures on the substrate, the second gate structures spanning over the device regions, and a plurality of second sidewall structures on sidewalls of the second gate structures, the source-drain doped layers being between adjacent first gate structures and second gate structures, or between adjacent second gate structures.

10. The semiconductor structure of claim 9, wherein the first and second semiconductor layers are formed of a same material. Further comprising: a dielectric layer on the substrate, the dielectric layer covering sidewalls of the first gate structures and the second gate structures.

11. The semiconductor structure of claim 10, wherein, The dielectric layer also covers sidewalls of the first conductive structure.

12. A method of forming a semiconductor structure, comprising: Comprising: providing a substrate having a fin on the substrate, the fin extending along a first direction, the fin comprising a plurality of device regions and isolation regions between adjacent device regions, the device regions and the isolation regions arranged along the first direction; forming an isolation layer on the substrate, the isolation layer covering part of sidewalls of the fin, and a top surface of the isolation layer being lower than a top surface of the fin; forming a first gate structure, a first conductive structure and a plurality of source-drain doped layers, the first gate structure being on the isolation layer and across the isolation region, the plurality of source-drain doped layers being in the device region on both sides of the first gate structure, the first conductive structure being on the source-drain doped layers, and a first isolation opening being between the first gate structure and the first conductive structure; etching the isolation region exposed by the first isolation opening to form a second isolation opening in the isolation region, a top surface of the second isolation opening being flush with a bottom surface of the first gate structure, and a bottom surface of the second isolation opening being flush with or lower than a bottom surface of the isolation layer; forming a dielectric structure and a second conductive structure, the second conductive structure being in the dielectric structure, and the dielectric structure enclosing the first isolation opening and the second isolation opening to form an air cavity in the first isolation opening and the second isolation opening; and the air cavity is used as an SDB structure of the device region.

13. The method of forming a semiconductor structure of claim 12, wherein In the process of forming the first gate structure and the first conductive structure, a first sidewall structure is formed between the first gate structure and the first conductive structure.

14. The method of forming a semiconductor structure of claim 13, wherein The first sidewall structure includes a first isolation sidewall on sidewalls of the first gate structure, and a sacrificial sidewall on sidewalls of the first isolation sidewall.

15. The method of forming a semiconductor structure of claim 14, wherein The dielectric structure includes a first dielectric layer.

16. The method of forming a semiconductor structure of claim 15, wherein The method for forming the first isolation opening, the dielectric structure and the second conductive structure includes removing the sacrificial sidewall to form the first isolation opening between the first gate structure and the first conductive structure, forming the first dielectric layer on the first gate structure and the first conductive structure, the first dielectric layer enclosing the first isolation opening and the second isolation opening to form the air cavity in the first isolation opening and the second isolation opening, and forming the second conductive structure in the first dielectric layer.

17. The method of forming a semiconductor structure of claim 15, wherein The forming process of the first dielectric layer includes a chemical vapor deposition process.

18. The method of forming a semiconductor structure of claim 14, wherein, The dielectric structure includes a first dielectric layer and a second dielectric layer.

19. The method of forming a semiconductor structure of claim 18, wherein, The method for forming the first isolation opening, the dielectric structure and the second conductive structure includes forming the first dielectric layer on the first gate structure and the first conductive structure, forming the second conductive structure in the first dielectric layer, removing part of the first dielectric layer and the sacrificial sidewall to form the first isolation opening between the first gate structure and the first conductive structure, and forming the second dielectric layer to enclose the first isolation opening and the second isolation opening to form the air cavity in the first isolation opening and the second isolation opening.

20. The method of forming a semiconductor structure of claim 18, wherein, The forming process of the second dielectric layer includes a chemical vapor deposition process.

21. The method of forming a semiconductor structure of claim 14, wherein, The material of the sacrificial sidewall is different from the material of the first isolation sidewall.

22. The method of forming a semiconductor structure of claim 21, wherein, The material of the sacrificial sidewall includes silicon oxide, silicon carbide or silicon boron carbon nitride, and the material of the first isolation sidewall includes silicon nitride, silicon oxynitride or silicon carbon nitride.

23. The method of forming a semiconductor structure of claim 14, wherein The first side wall structure further comprises a second isolation side wall located at the side wall of the sacrificial side wall, and the material of the second isolation side wall is the same as that of the first isolation side wall.

24. The method of forming a semiconductor structure of claim 13, wherein In the process of forming the first gate structure and the first side wall structure, further comprising: forming a plurality of second gate structures and a plurality of second side wall structures on the substrate, the second gate structures span the device regions, and the second side wall structures are located at the side walls of the second gate structures, and the source-drain doped layers are located between adjacent first gate structures and second gate structures or between adjacent second gate structures.

25. The method of forming a semiconductor structure of claim 24, wherein Before forming the first gate structure and the second gate structure, further comprising: forming a dielectric layer on the substrate, the dielectric layer covering the side walls of the first gate structure and the second gate structure.

26. The method of forming a semiconductor structure of claim 25, wherein Before forming the first gate structure and the second gate structure, further comprising: forming a first dummy gate structure and a plurality of second dummy gate structures on the substrate, the first dummy gate structure spanning the isolation regions, and the first side wall structure being located at the side wall of the first dummy gate structure, and the second dummy gate structure spanning the device regions, and the second side wall structure being located at the side wall of the second dummy gate structure.

27. The method of forming a semiconductor structure of claim 26, wherein The method for forming the source-drain doped layer comprises: etching the fin portion with the first dummy gate structure, the first side wall structure, the second dummy gate structure, and the second side wall structure as masks to form a plurality of source-drain openings in the device regions; and forming the source-drain doped layer in the source-drain openings.

28. The method of forming a semiconductor structure of claim 26, wherein After forming the source-drain doped layer, the dielectric layer is formed, which covers the side walls of the first dummy gate structure, the first side wall structure, the second dummy gate structure, and the second side wall structure.

29. The method of forming a semiconductor structure of claim 28, wherein The method for forming the first gate structure and the second gate structure comprises: removing the first dummy gate structure to form a first gate opening in the dielectric layer, and removing the second dummy gate structure to form a second gate opening in the dielectric layer; forming the first gate structure in the first gate opening, and forming the second gate structure in the second gate opening.

30. The method of forming a semiconductor structure of claim 25, wherein The method for forming the first conductive structure comprises: forming a first conductive opening in the dielectric layer, the first conductive opening exposing the source-drain doped layer; and forming the first conductive structure in the first conductive opening, the first conductive structure being electrically connected with the source-drain doped layer.

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