An SOI power semiconductor device

Abstract

The present application provides a SOI power semiconductor device, which sets a region with opposite type doping to the drift region as a back gate on the substrate, sets a gate material above the SOI layer, and the two together form a gate electrode of the power semiconductor device to realize the control of the device switch. Meanwhile, the present application provides a different voltage level expansion scheme according to the power semiconductor device, sets a well region with opposite doping type on the substrate. The present application provides a power semiconductor device with pinch-off voltage independent of process deviation and without sacrificing the conductive path area characteristic for the SOI device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductors, and more specifically, relates to power semiconductor devices based on SOI technology. Background Technology

[0002] With the increasing demands of the energy industry, the demand for power integrated circuits is also growing. Power semiconductor devices are crucial components of power integrated circuits, and their performance directly affects the efficiency of the chip. In the field of power semiconductors, energy dissipation inevitably leads to poor temperature characteristics, resulting in low energy conversion efficiency of power integrated circuits. The emergence of SOI (Silicon On Insulator) technology effectively improves the power dissipation problem caused by leakage current in the chip substrate, making the device performance more stable. SOI combined with dielectric isolation technologies, such as deep trench isolation (DTI), can achieve efficient isolation of the device. SIMOX (Separation by IMplantation of OXygen) technology is one method to realize SOI technology. SIMOX technology can achieve thin buried oxide layers and thin SOI layers, and the process flow is simpler compared to silicon wafer bonding. Currently, power chips based on SIMOX SOI technology have appeared on the power integrated circuit market.

[0003] The advancement of SOI technology led to Partial SOI (PSOI). This technology allows the substrate of SOI devices to participate in voltage withstand, preventing excessively high electric fields in the buried oxide layer beneath the high-voltage electrodes, which could lead to dielectric breakdown. Dielectric breakdown is detrimental to device reliability, and the damage is usually irreversible. PSOI technology allows the depletion layer to extend within the substrate. By utilizing the substrate's voltage withstand ring, it mitigates the high electric field caused by potential line concentration in the buried oxide layer, thus improving device reliability to some extent.

[0004] In power integrated circuits, depletion-type devices have many applications, such as bootstrap circuit modules, which can integrate junction field-effect transistors (JFETs) or depletion-type LDMOS; and in startup circuit modules, they can be used to charge capacitors. However, for depletion-type devices, the most critical electrical parameters are the pinch-off voltage and saturation current under the required breakdown voltage, both of which are related to the design of the pinch-off voltage. The pinch-off of a depletion-type device is achieved by setting a gate electrode, typically by forming a PN junction in the conductive path with opposite doping types, which serves as the gate to control the channel's on / off state. However, in actual manufacturing, this opposite-doped region requires ion implantation, high-temperature junction pushing, and other processes. Achieving high precision in these processes is challenging, resulting in inconsistent pinch-off voltage uniformity in the manufactured depletion-type device. Furthermore, the opposite-doped region occupies area in the conductive path, thus limiting the overall current of the depletion-type device.

[0005] Therefore, to solve the above problems, this invention provides an SOI power semiconductor device, more specifically a depletion-type power semiconductor device. By providing gate electrodes on both the upper and lower sides of the conductive path, it serves as a switch for the gate control device and does not occupy the area of ​​the conductive path, thus reducing the current required by the original conductive path design. Summary of the Invention

[0006] This invention, based on SOI technology, and more specifically involving thin SOI technology using SIMOX, provides a power semiconductor device, which is a depletion-type power semiconductor device. Unlike JFETs, this device does not form a direct PN junction contact; similar to junctionless field-effect transistors (JLTs), the device has the same doping type from source to drain. The device utilizes a contrasting type of doped silicon beneath the buried oxide layer (BOX) and a MIS structure above the silicon-on-insulator (SI), together forming the gate that controls the device's on / off state. The technical solution provided by this invention, compared to directly setting a PN structure in the carrier conduction path to form a JFET, has a more stable pinch-off voltage (Vp). In manufacturing processes, opposite types of doping in the conduction path are usually formed through ion implantation and high-temperature push junction. The pinch-off voltage of a JFET is limited by the manufacturing process, resulting in insufficient uniformity of the threshold voltage of the manufactured device. In contrast, this invention utilizes ion implantation and high-temperature push junction to form one of the gates. This gate is not affected by process deviations leading to inaccurate pinch-off voltage. The pinch-off voltage of this depletion-formed power semiconductor device depends only on the doping of the conduction path and the relative positional relationship between the upper and lower gates and the SOI. Furthermore, compared to bulk silicon power semiconductor devices, this invention uses SOI technology, resulting in better temperature characteristics and substrate leakage current characteristics.

[0007] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0008] An SOI power semiconductor device includes a substrate 5 of a first doped type, a buried oxide layer 6 disposed above the substrate 5 and in contact with it, and a buried layer 9 of a second doped type disposed on the surface of the substrate 5 and in contact with the buried oxide layer 6; an SOI layer 15 is disposed above the buried oxide layer 6, and the SOI layer 15 is composed of a source region 1 of the first doped type at both ends, a drain region 2 of the first doped type, and a drift region 3 of the first doped type between the source region 1 and the drain region 2 of the first doped type; the buried layer 9 of the second doped type is located below the buried oxide layer 6 and close to the first doped type. On one side of source region 1, the first-doped source region 1 and the first-doped drain region 2 are connected to potentials via source metal 10 and drain metal 11, respectively. A dielectric layer 8 is disposed above SOI layer 15, and a gate electrode 7 is disposed above dielectric layer 8, with the gate electrode 7 located close to the first-doped source region 1. Simultaneously, a field oxide layer 12 is disposed around the perimeter of SOI layer 15. The gate electrode 7 and the second-doped buried layer 9 are connected via a deep trench gate electrode 16 disposed within the field oxide layer 12. The field oxide layer 12 and the buried oxide layer 6 together isolate SOI layer 15 from the first-doped substrate 5. This design is for low-voltage applications.

[0009] As a preferred embodiment, a second-doped contact region 13 is provided between the deep trench gate electrode 16 and the second-doped buried layer 9, wherein the doping concentration of the second-doped contact region is higher than that of the second-doped buried layer 9.

[0010] As a preferred embodiment, a second-doped well region 4 is disposed within the first-doped substrate 5 below the buried oxide layer 6, corresponding to the drain region 2 of the first-doped type. Its top end is connected to the buried oxide layer 6. A drain deep trench electrode 17 is disposed through the field oxide layer 12 and connected to the second-doped well region 4. This design is intended for medium voltage applications.

[0011] As a preferred embodiment, a second-doped floating well region 14 is provided between the second-doped buried layer 9 and the second-doped well region 4. The number of second-doped floating well regions 14 can be one or more, in order to extend the voltage rating of the device. This scheme is designed for high-voltage applications.

[0012] As a preferred embodiment, a second-doped contact region 13 is provided between the deep trench gate electrode 16 and the second-doped buried layer 9, and a second-doped contact region 13 is provided between the drain deep trench electrode 17 and the second-doped well region 4, wherein the doping concentration of the second-doped buried layer 9 is higher than that of the second-doped buried layer 9.

[0013] As a preferred embodiment, the first type of doping is N-type doping and the second type of doping is P-type doping; or the first type of doping is P-type doping and the second type of doping is N-type doping.

[0014] The beneficial effects of this invention are as follows: It provides a power semiconductor device, specifically an SOI depletion-type power semiconductor device, on the SOI process platform with excellent isolation characteristics. By placing a gate electrode above the SOI layer and a second-doped buried layer below the buried oxide layer, the two together constitute the gate of this depletion-type power semiconductor device. This device is compatible with SOI technology, and its pinch-off voltage characteristics are not affected by process deviations such as ion implantation and high-temperature push-junction, exhibiting excellent stability. Based on the basic structure, this invention also extends the device design for medium and high voltage applications. Attached Figure Description

[0015] Figure 1 This is a layout structure of an SOI power semiconductor device provided in Embodiment 1 of the present invention.

[0016] Figure 2(a) shows the cross-section of an SOI power semiconductor device structure corresponding to A1-A1' provided in Embodiment 1 of the present invention.

[0017] Figure 2(b) shows the cross-section of an SOI power semiconductor device structure corresponding to B1-B1' provided in Embodiment 1 of the present invention.

[0018] Figure 2(c) shows the C1-C1' cross-section of an SOI power semiconductor device structure provided in Embodiment 1 of the present invention.

[0019] Figure 3 This is a layout structure of an SOI power semiconductor device provided in Embodiment 2 of the present invention.

[0020] Figure 4(a) shows the cross-section of an SOI power semiconductor device structure along line A2-A2' provided in Embodiment 2 of the present invention.

[0021] Figure 4(b) shows the cross-section of an SOI power semiconductor device structure corresponding to B2-B2' provided in Embodiment 2 of the present invention.

[0022] Figure 4(c) shows the C2-C2' cross-section of an SOI power semiconductor device structure provided in Embodiment 2 of the present invention.

[0023] Figure 5 This is a layout structure of an SOI power semiconductor device provided in Embodiment 3 of the present invention.

[0024] Figure 6(a) shows the cross-section A3-A3' of an SOI power semiconductor device structure provided in Embodiment 3 of the present invention.

[0025] Figure 6(b) shows the cross-section of an SOI power semiconductor device structure corresponding to B3-B3' provided in Embodiment 3 of the present invention.

[0026] Figure 6(c) shows the C3-C3' cross-section of an SOI power semiconductor device structure provided in Embodiment 3 of the present invention.

[0027] Figure 7 The layout structure of an SOI power semiconductor device provided in Embodiment 4 of the present invention

[0028] Figure 8(a) shows the cross-section A4-A4' of an SOI power semiconductor device structure provided in Embodiment 4 of the present invention.

[0029] Figure 8(b) shows the cross-section of an SOI power semiconductor device structure corresponding to B4-B4' provided in Embodiment 4 of the invention.

[0030] Figure 8(c) shows the C4-C4' cross-section of an SOI power semiconductor device structure provided in Embodiment 4 of the present invention.

[0031] Figure 9 This is a layout structure of an SOI power semiconductor device provided in Embodiment 5 of the present invention.

[0032] Figure 10(a) shows the cross-section A5-A5' of an SOI power semiconductor device structure provided in Embodiment 5 of the present invention.

[0033] Figure 10(b) shows the cross-section of an SOI power semiconductor device structure corresponding to B5-B5' provided in Embodiment 5 of the present invention.

[0034] Figure 10(c) shows the C5-C5' cross-section of an SOI power semiconductor device structure provided in Embodiment 5 of the present invention.

[0035] Figure 11 This is a layout structure of an SOI power semiconductor device provided in Embodiment 6 of the present invention.

[0036] Figure 12(a) shows the cross-section A6-A6' of an SOI power semiconductor device structure provided in Embodiment 6 of the present invention.

[0037] Figure 12(b) shows the cross-section of an SOI power semiconductor device structure corresponding to B6-B6' provided in Embodiment 6 of the present invention.

[0038] Figure 12(c) shows the C6-C6' cross-section of an SOI power semiconductor device structure provided in Embodiment 6 of the present invention.

[0039] 1 is the source region of the first doping type, 2 is the drain region of the first doping type, 3 is the drift region of the first doping type, 4 is the well region of the second doping type, 5 is the substrate of the first doping type, 6 is the buried oxide layer, 7 is the gate electrode, 8 is the dielectric layer, 9 is the buried layer of the second doping type, 10 is the source metal, 11 is the drain metal, 12 is the field oxide layer, 13 is the contact region of the second doping type, 14 is the floating well region of the second doping type, 15 is the SOI layer, 16 is the deep trench gate electrode, and 17 is the drain deep trench electrode. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] In the following embodiments, the gate electrode 7 can be either a metal electrode or a polycrystalline silicon electrode.

[0042] SOI can be implemented using SIMOX technology, silicon wafer bonding technology, or Smart Cut SOI technology that combines bonding and implantation.

[0043] The dielectric layer 8 can be made of silicon oxide or a high-k material.

[0044] The deep trench gate electrode 16 can be a metal electrode or a polycrystalline silicon electrode.

[0045] The drain deep trench electrode 17 can be a metal electrode or a polycrystalline silicon electrode.

[0046] The first type of doping is N-type doping, and the second type of doping is P-type doping; or the first type of doping is P-type doping, and the second type of doping is N-type doping. The following examples are all described with the first type of doping being N-type doping and the second type of doping being P-type doping.

[0047] Example 1

[0048] Example 1 corresponds to an SOI power semiconductor device, or more precisely, a depletion-type power semiconductor device. Figure 1 This is the layout structure corresponding to the depletion-mode power semiconductor device. To better illustrate the structural design at various points in the device, in Figure 1 The substrate 5, buried oxide layer 6, dielectric layer 8, source metal 10, and drain metal 11 of the first doped type are not shown in Figure 2(a). Figure 1 The cross-sectional structure diagram corresponding to A1-A1' in Figure 2 mainly shows the interconnection relationship between the gate electrode 7 and the second-doped buried layer 9 of this device; Figure 2(b) is... Figure 1 The cross-sectional structure diagram corresponding to B1-B1' in Figure 2 mainly illustrates the design of the conductive path and gate control structure of the device. Figure 2(c) is... Figure 1 The cross-sectional structural diagram corresponding to C1-C1' mainly shows the positional relationship of the gate control structure, buried oxide layer 6, and SOI layer 15 in the width direction. The positional relationship of each region in Embodiment 1 provided by the present invention is as follows.

[0049] The SOI power semiconductor device corresponding to Example 1 includes: a substrate 5 having a first doping type; a buried oxide layer 6 disposed above the first doped substrate 5 and in contact with the substrate; a buried layer 9 of a second doping type disposed on the surface of the first doped substrate 5 and in contact with the buried oxide layer 6; an SOI layer 15 disposed above the buried oxide layer 6; the SOI layer 15 is composed of a source region 1 of the first doping type at both ends, a drain region 2 of the first doping type, and a drift region 3 of the first doping type between the source region 1 and the drain region 2 of the first doping type; the buried layer 9 of the second doping type is located below the buried oxide layer 6 and close to the first doped layer 6. On one side of the source region 1 of the first doped type, the source region 1 and the drain region 2 of the first doped type are connected to potentials through the source metal 10 and the drain metal 11, respectively. A dielectric layer 8 is disposed above the SOI layer 15, and a gate electrode 7 is disposed above the dielectric layer 8. The gate electrode 7 is located close to the source region 1 of the first doped type. At the same time, a field oxide layer 12 is disposed around the perimeter of the SOI layer 15. The gate electrode 7 and the buried layer 9 of the second doped type are connected through a deep trench gate electrode 16 disposed inside the field oxide layer 12. The field oxide layer 12 and the buried oxide layer 6 together isolate the SOI layer 15 from the substrate 5 of the first doped type.

[0050] In this technical solution, the substrate 5 of the first doping type is connected to a high potential, and the gate electrode 7 and the buried layer 9 of the second doping type are connected to a low potential. The conductive path of the device consists of the source region 1 of the first doping type, the drift region 3 of the first doping type, and the drain region 2 of the first doping type. When there is a potential difference between the source and drain of the device, charge carriers form a current through the conductive path. The overlapping region between the gate electrode 7 and the buried layer 9 of the second doping type can be regarded as the "channel" of the depletion-type device. The two together constitute the gate of the device and affect the depletion line distribution of the conductive path. When the source and drain voltages of the device are higher than the gate potential by a certain value, the depletion lines generated by the two gates above and below the "channel" continuously approach each other until they overlap and "pinch off" the conductive path of the device, thereby turning off the device. The "pinch-off voltage" of the device is determined by the thickness of the buried oxide layer 6, the thickness of the dielectric layer 8, the thickness of the SOI layer 15, the concentration of the drift region 3 of the first doping type, and the relative positions of the gate electrode 7 and the buried layer 9 of the second doping type. These parameters are almost unaffected by manufacturing process deviations, and the uniformity of the "pinch-off voltage" is good. This SOI-based depletion-mode power semiconductor device has electrical characteristics almost identical to those of devices such as JFET and depletion MOSFET, and therefore can be used in circuit startup, high-voltage bootstrapping, level shifting, and other modules.

[0051] Furthermore, the technical solution provided in Example 1 is suitable for low-voltage design requirements. By using the deep trench electrode 16 to achieve voltage consistency between the gate electrode 7 and the second-doped buried layer 9, the distribution of voltage equipotential lines is also introduced into the first-doped substrate 5, solving the problem that the substrate hardly participates in the breakdown voltage under traditional SOI processes. The principle of this method is consistent with PSOI (Partial SOI). However, since only the second-doped buried layer 9 modulates the potential distribution of the first-doped substrate 5, when the length of the first-doped drift region 3 is sufficiently long, the first-doped substrate 5 below the buried oxide layer 6 corresponding to the drain 2 of the first-doped type cannot be depleted and does not participate in the breakdown voltage. Breakdown is still limited by the high electric field between the SOI layer 15 and the buried oxide layer 6. Therefore, this technical solution is only suitable for low-voltage applications; its application in medium and high voltage levels will be described in the following examples.

[0052] Example 2

[0053] Example 2 corresponds to an SOI power semiconductor device, or more precisely, a depletion-type power semiconductor device. Figure 3 This is the layout structure corresponding to the depletion-mode power semiconductor device. To better illustrate the structural design at various points in the device, in Figure 3 The substrate 5, buried oxide layer 6, dielectric layer 8, source metal 10, and drain metal 11 of the first doped type are not shown in Figure 4(a). Figure 3 The cross-sectional structure diagram corresponding to A2-A2' in Figure 4 mainly shows the interconnection relationship between the gate electrode 7 and the second-doped buried layer 9 of this device; Figure 4(b) is... Figure 3 The cross-sectional structure diagram corresponding to B21-B2' in Figure 4(c) mainly illustrates the design of the conductive path and gate control structure of the device. Figure 3 The cross-sectional structure diagram corresponding to C2-C2' mainly shows the positional relationship between the gate control structure, buried oxide layer 6, and SOI layer 15 in the width direction.

[0054] The present invention provides an SOI power semiconductor device. In embodiment 2, based on embodiment 1, a second doped contact region 13 is provided between the deep trench gate electrode 16 and the second doped buried layer 9. The doping concentration of the second doped contact region 13 is higher than that of the second doped buried layer 9.

[0055] In this technical solution, by setting a second doped contact region 13, the contact resistance between the deep trench gate electrode 16 and the second doped buried layer 9 is reduced, ensuring that the gate electrode 7 and the second doped buried layer 9 are at the same potential, which helps to generate depletion lines simultaneously, pinching off the "channel" corresponding to the SOI layer 15 between them, and realizing the device turn-off.

[0056] Example 3

[0057] Example 3 corresponds to an SOI power semiconductor device, or more precisely, a depletion-type power semiconductor device. Figure 5 This is the layout structure corresponding to this power semiconductor device. To better illustrate the structural design of various parts of the device, in Figure 5 The substrate 5, buried oxide layer 6, dielectric layer 8, source metal 10, and drain metal 11 of the first doped type are not shown in Figure 6(a). Figure 5 The cross-sectional structure diagram corresponding to A3-A3' in Figure 6 mainly shows the interconnection relationship between the gate electrode 7 and the second-doped buried layer 9 of this device; Figure 6(b) is... Figure 5 The cross-sectional structure diagram corresponding to B3-B3' in Figure 6(c) mainly illustrates the design of the conductive path and gate control structure of the device. Figure 5 The cross-sectional structure diagram corresponding to C3-C3' mainly reflects the positional relationship of the gate control structure, buried oxide layer 6, and SOI layer 15 in the width direction.

[0058] This invention provides an SOI power semiconductor device. In Embodiment 3, based on Embodiment 1, a second-doped well region 4 is formed within a first-doped substrate 5 below the buried oxide layer 6, corresponding to the drain region 2 of the first-doped type. Its top end is connected to the buried oxide layer 6. A drain deep trench electrode 17 is provided, passing through the field oxide layer 12 and connecting to the second-doped well region 4. The width and number of drain deep trench electrodes 17 depend on design requirements and compatibility with external circuitry. Figure 5 In the corresponding schematic diagram, only three drain deep trench electrodes 17 are shown.

[0059] The depletion-type power semiconductor device provided in this technical solution is suitable for medium-voltage designs. By setting a deep drain electrode 17 and a second-doped well region 4, a voltage is applied to the side of the first-doped substrate 5 near the first-doped drain 2. This voltage can be equal to or different from the drain metal 11. By setting a reverse-voltage-resistant PN junction near the first-doped drain region 2 in the first-doped well region 4, the voltage distribution in the first-doped substrate 5 below the first-doped drain region 2 is optimized when the power device is designed at medium voltage levels, making full use of the area of ​​this region and enabling the extension of the potential lines. At the same time, in the device corresponding to Embodiment 3, when the first-doped drain region 2 is connected to a high voltage, there is no concentration of equipotential lines in the buried oxide layer 6 below, avoiding irreversible damage to the device performance caused by dielectric breakdown in the buried oxide layer 6. This reduces the electric field strength at the interface between the buried oxide layer 6 and the SOI layer 15, and therefore improves the on-state breakdown voltage of the device compared to the case without the second-doped well region 4.

[0060] Example 4

[0061] Example 4 corresponds to an SOI power semiconductor device, or more precisely, a depletion-type power semiconductor device. Figure 7 This is the layout structure corresponding to the depletion-mode power semiconductor device. To better illustrate the structural design at various points in the device, in Figure 7 The substrate 5, buried oxide layer 6, dielectric layer 8, source metal 10, and drain metal 11 of the first doped type are not shown in Figure 8(a). Figure 7 The cross-sectional structure diagram corresponding to A4-A4' in Figure 8 mainly shows the interconnection relationship between the gate electrode 7 and the second-doped buried layer 9 of this device; Figure 8(b) is... Figure 7 The cross-sectional structure diagram corresponding to B4-B4' in Figure 8 mainly illustrates the design of the conductive path and gate control structure of the device. Figure 8(c) is... Figure 7 The cross-sectional structure diagram corresponding to C4-C4' mainly shows the positional relationship of the gate control structure, buried oxide layer 6, and SOI layer 15 in the width direction.

[0062] The present invention provides an SOI power semiconductor device. In embodiment 4, based on embodiment 3, a second doped contact region 13 is provided between the deep trench gate electrode 16 and the second doped buried layer 9, and a second doped contact region 13 is provided between the deep trench drain electrode 17 and the second doped well region 4. The doping concentration of the second doped contact region 13 is higher than that of the second doped buried layer 9.

[0063] In this technical solution, by setting a contact region 13 of the second doping type, the contact resistance between the deep trench gate electrode 16 and the second doped buried layer 9 is reduced, ensuring that the gate electrode 7 and the second doped buried layer 9 are at the same potential. This helps to generate a depletion line simultaneously, pinching off the "channel" corresponding to the SOI layer 15 between them, thus achieving device turn-off. Setting the contact region 13 of the second doping type between the drain deep trench electrode 17 and the second doped well region 4 can ensure that the contact between the drain deep trench electrode 17 and the second doped well region 4 is an ohmic contact, reducing contact resistance.

[0064] Example 5

[0065] Example 5 corresponds to an SOI power semiconductor device, or more precisely, a depletion-type power semiconductor device. Figure 9 This is the layout structure corresponding to the depletion-mode power semiconductor device. To better illustrate the structural design at various points in the device, in Figure 9 The substrate 5, buried oxide layer 6, dielectric layer 8, source metal 10, and drain metal 11 of the first doped type are not shown in Figure 10(a). Figure 9The cross-sectional structure diagram corresponding to A5-A5' in Figure 10 mainly shows the interconnection relationship between the gate electrode 7 and the second-doped buried layer 9 of this device; Figure 10(b) is... Figure 9 The cross-sectional structure diagram corresponding to B5-B5' mainly illustrates the design of the conductive path and gate control structure of the device. Figure 10(c) is... Figure 9 The cross-sectional structure diagram corresponding to C5-C5' mainly shows the positional relationship of the gate control structure, buried oxide layer 6, and SOI layer 15 in the width direction.

[0066] This invention provides an SOI power semiconductor device. In embodiment 5, based on embodiment 3, a second-doped type floating well region 14 is provided between the second-doped buried layer 9 and the second-doped well region 4. The number of such regions can be one or more, and the specific number is determined according to the voltage level requirements.

[0067] In this technical solution, the floating well region 14 of the second doped type acts as a field limiting loop, and this region is not externally connected to a potential. When the device needs to meet the design requirements of a higher voltage level, the depletion region of the substrate of the first doped type can be expanded by simply introducing the second doped type well region 4 as in embodiment 3. However, if the distance between the second doped type well region 4 and the second doped type buried layer 9 is too large, the depletion line will widen to the point that the peak electric field of the lateral PN junction between the second doped type well region 4 and the first doped type substrate 5 reaches its maximum, and there is still an undepleted area between the second doped type well region 4 and the second doped type buried layer 9. This situation will limit the use of higher voltage levels of the device and also cause a waste of area. When the floating well region 14 of the second doped type is introduced, the depletion region can be expanded, improving the breakdown voltage of the substrate of the first doped type 5. In addition, while modulating the depletion region distribution of the substrate of the first doped type 5, it can also affect the potential distribution in the SOI layer 15, making its electric field more uniform and preventing the device from breaking down in the SOI layer 15.

[0068] Meanwhile, if the buried oxide layer 6 is thin enough during device design, the second doped floating well region 14 can mutually deplete with the first doped drift region 3 in the SOI layer 15, i.e., it can act as a RESURF. In this case, a higher conduction current can be achieved by increasing the doping concentration of the first doped drift region 3.

[0069] Example 6

[0070] Example 6 corresponds to an SOI power semiconductor device, or more precisely, a depletion-type power semiconductor device. Figure 11 This is the layout structure corresponding to the depletion-mode power semiconductor device. To better illustrate the structural design at various points in the device, in Figure 11The substrate 5, buried oxide layer 6, dielectric layer 8, source metal 10, and drain metal 11 of the first doped type are not shown; Figure 12(a) is... Figure 11 The cross-sectional structure diagram corresponding to A6-A6' in Figure 12 mainly shows the interconnection relationship between the gate electrode 7 and the second-doped buried layer 9 of this device; Figure 12(b) is... Figure 11 The cross-sectional structure diagram corresponding to B6-B6' in Figure 12 mainly illustrates the design of the conductive path and gate control structure of the device. Figure 12(c) is... Figure 11 The cross-sectional structure diagram corresponding to C6-C6' mainly shows the positional relationship of the gate control structure, buried oxide layer 6, and SOI layer 15 in the width direction.

[0071] This invention provides an SOI power semiconductor device. In embodiment 6, based on embodiment 5, a second-doped contact region 13 is provided between the deep trench gate electrode 16 and the second-doped buried layer 9, and a second-doped contact region 13 is provided between the drain deep trench electrode 17 and the second-doped well region 4. The doping concentration of the second-doped contact region 13 is the same as that of the second-doped buried layer 9.

[0072] In this technical solution, for the gate of the device, by setting a second-doped contact region 13, the contact resistance between the deep trench gate electrode 16 and the second-doped buried layer 9 is reduced, ensuring that the gate electrode 7 and the second-doped buried layer 9 are at the same potential, which helps to generate depletion lines simultaneously, pinching off the "channel" corresponding to the SOI layer 15 between them, and realizing the device turn-off; for the drain of the device, by setting a second-doped contact region 13 between the drain deep trench electrode 17 and the second-doped well region 4, the contact resistance is reduced.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An SOI power semiconductor device, characterized in that; A substrate (5) having a first doping type is provided above the substrate (5) and connected to it by a buried oxide layer (6). A buried layer (9) of a second doping type is provided on the surface of the substrate (5) and connected to the buried oxide layer (6). An SOI layer (15) is provided above the buried oxide layer (6). The SOI layer (15) is composed of a source region (1) of the first doping type at both ends, a drain region (2) of the first doping type, and a drift region (3) of the first doping type between the source region (1) and the drain region (2) of the first doping type. The buried layer (9) of the second doping type is located below the buried oxide layer (6) and close to the source region (1) of the first doping type. The source region (1) of type 1 and the drain region (2) of type 1 doping are connected to potentials through source metal (10) and drain metal (11), respectively. A dielectric layer (8) is provided above the SOI layer (15), and a gate electrode (7) is provided above the dielectric layer (8). The gate electrode (7) is located on the side close to the source region (1) of type 1 doping. Meanwhile, a field oxide layer (12) is provided around the perimeter of the SOI layer (15). The gate electrode (7) and the buried layer (9) of type 2 doping are connected through a deep trench gate electrode (16) provided inside the field oxide layer (12). The field oxide layer (12) and the buried oxide layer (6) together isolate the SOI layer (15) from the substrate (5) of type 1 doping. A second-doped contact region (13) is provided between the deep trench gate electrode (16) and the second-doped buried layer (9), the doping concentration of which is higher than that of the second-doped buried layer (9). A second-doped type well region (4) is provided in the first-doped type substrate (5) below the buried oxide layer (6), corresponding to the drain region (2) of the first-doped type. Its top end is connected to the buried oxide layer (6), and a drain deep trench electrode (17) is provided to pass through the field oxide layer (12) and connect to the second-doped type well region (4). A second-doped floating well region (14) is provided between the second-doped buried layer (9) and the second-doped well region (4), and the number of second-doped floating well regions (14) is one or more, in order to extend the voltage level of the device.

2. The SOI power semiconductor device according to claim 1, characterized in that: A second-doped contact region (13) is provided between the deep trench gate electrode (16) and the second-doped buried layer (9), and a second-doped contact region (13) is provided between the drain deep trench electrode (17) and the second-doped well region (4), wherein the doping concentration of the region is higher than that of the second-doped buried layer (9).

3. The SOI power semiconductor device according to any one of claims 1 to 2, characterized in that: The first type of doping is N-type doping, and the second type of doping is P-type doping; or the first type of doping is P-type doping, and the second type of doping is N-type doping.

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