Vertical transistor and method of manufacturing the same

Abstract

Embodiments of the present application relate to a vertical transistor and a preparation method thereof, wherein the vertical transistor comprises: a semiconductor substrate comprising a first surface and a second surface opposite to each other, the semiconductor substrate having a first conductivity type; a plurality of second-conductivity-type body regions extending from the first surface to the interior of the semiconductor substrate; wherein the second conductivity type is different from the first conductivity type; a source region located in the second-conductivity-type body region; a drain located on the second surface; a groove located between two adjacent second-conductivity-type body regions and extending from the first surface to the interior of the semiconductor substrate; a gate dielectric layer extending from the groove to above the first surface and covering part of the second-conductivity-type body region; and a gate located on the gate dielectric layer. Thus, the Cgd at low voltage can be reduced, while the Cgd at high voltage remains basically unchanged, thereby reducing the Qg and driving loss, and the process is simple and easy to implement.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a vertical transistor and a preparation method thereof. BACKGROUND

[0002] The gate charge Qg and the gate-source capacitance Cgs / gate-drain capacitance Cgd of the vertical transistor are closely related, and generally, the purpose of reducing the loss is achieved by adjusting the capacitance to reduce Qg. In the case of a fixed Cgs, the purpose of reducing Qg is usually achieved by reducing Cgd at low voltage (low Vds). In the conventional structure, the reduction of Cgd at low voltage usually leads to the reduction of Cgd at high voltage, and the reduction of Cgd at high voltage will bring many adverse effects to the device. Especially for super-junction VDMOS (Vertical Double-diffused MOSFET, vertical double-diffused transistor), the reduction of Cgd at high voltage will lead to a series of problems such as too fast switching, severe oscillation, voltage overshoot, too fast reverse recovery, large dv / dt, and easy to die in reverse recovery.

[0003] Therefore, how to reduce Cgd at low voltage while keeping Cgd at high voltage basically unchanged is an important technical problem to be solved in the current field. SUMMARY

[0004] In view of this, the embodiments of the present application provide a vertical transistor and a preparation method thereof to solve at least one problem in the background art.

[0005] In a first aspect, the embodiments of the present application provide a vertical transistor, comprising:

[0006] a semiconductor substrate comprising a first surface and a second surface opposite to each other, the semiconductor substrate having a first conductivity type;

[0007] a plurality of second-conductivity-type body regions extending from the first surface to the interior of the semiconductor substrate; wherein the second conductivity type is different from the first conductivity type;

[0008] a source region located in the second-conductivity-type body region,

[0009] a drain located on the second surface;

[0010] a groove located between two adjacent second-conductivity-type body regions and extending from the first surface to the interior of the semiconductor substrate;

[0011] a gate dielectric layer extending from the groove to above the first surface and covering part of the second-conductivity-type body region;

[0012] a gate electrode on the gate dielectric layer.

[0013] In combination with the first aspect of the present application, in an optional implementation, the method further comprises:

[0014] a plurality of second-conductivity-type pillars are arranged in the semiconductor substrate at intervals to form first-conductivity-type pillars between two adjacent second-conductivity-type pillars; the second-conductivity-type pillars and the first-conductivity-type pillars are arranged alternately to form a super-junction structure;

[0015] a plurality of the second-conductivity-type body regions are respectively above a plurality of the second-conductivity-type pillars.

[0016] In combination with the first aspect of the present application, in an optional implementation, a line width of the groove is in a range of greater than or equal to 1 / 3 of a distance between two adjacent second-conductivity-type body regions and less than or equal to 1 / 2 of the distance between the two adjacent second-conductivity-type body regions.

[0017] In combination with the first aspect of the present application, in an optional implementation, a depth of the groove is in a range of greater than or equal to 1 / 3 of a distance between two adjacent second-conductivity-type body regions and less than or equal to 1 / 2 of the distance between the two adjacent second-conductivity-type body regions.

[0018] In combination with the first aspect of the present application, in an optional implementation, a material of a portion of the gate dielectric layer in the groove is different from a material of a portion of the gate dielectric layer on the second-conductivity-type body region.

[0019] In a second aspect, embodiments of the present application provide a method for manufacturing a vertical transistor, the method comprising:

[0020] providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the semiconductor substrate having a first conductivity type;

[0021] forming a plurality of second-conductivity-type body regions extending from the first surface to an interior of the semiconductor substrate; wherein the second conductivity type is different from the first conductivity type;

[0022] forming a groove extending from the groove to above the first surface, the groove being between two adjacent second-conductivity-type body regions;

[0023] forming a gate dielectric layer extending from the groove to above the first surface, the gate dielectric layer covering a portion of the second-conductivity-type body region;

[0024] forming a gate electrode on the gate dielectric layer.

[0025] forming a source region in the second-conductivity-type body region;

[0026] forming a drain on the second surface.

[0027] In combination with the second aspect of the present application, in an optional implementation, before forming the plurality of second-conductivity-type body regions, the method further comprises: forming a plurality of second-conductivity-type pillars, the plurality of second-conductivity-type pillars being spaced apart within the semiconductor substrate to leave a first-conductivity-type pillar between any two adjacent second-conductivity-type pillars; the second-conductivity-type pillars and the first-conductivity-type pillars being arranged alternately to form a super-junction structure.

[0028] forming the plurality of second-conductivity-type body regions comprises: forming the plurality of second-conductivity-type body regions respectively above the plurality of second-conductivity-type pillars.

[0029] In combination with the second aspect of the present application, in an optional implementation, the line width of the recess and / or the depth of the recess is in a range of: greater than or equal to 1 / 3 of the spacing between any two adjacent second-conductivity-type body regions, and less than or equal to 1 / 2 of the spacing between any two adjacent second-conductivity-type body regions.

[0030] In combination with the second aspect of the present application, in an optional implementation, forming the gate dielectric layer comprises:

[0031] depositing a first dielectric material within the recess by a first deposition process;

[0032] depositing a second dielectric material on the first surface by a second deposition process, the second dielectric material covering at least a portion of the second-conductivity-type body regions;

[0033] wherein the first dielectric material is different from the second dielectric material.

[0034] In combination with the second aspect of the present application, in an optional implementation, forming the gate dielectric layer comprises:

[0035] depositing a gate dielectric material within the recess;

[0036] removing part of the gate dielectric material deposited at the upper opening of the recess;

[0037] depositing the gate dielectric material within the recess again;

[0038] the gate dielectric material not removed forms part of the gate dielectric layer.

[0039] The vertical transistor and the preparation method thereof provided by the embodiment of the present application comprise: a semiconductor substrate comprising a first surface and a second surface opposite to each other, wherein the semiconductor substrate has a first conductive type; a plurality of second conductive type body regions extending from the first surface to the interior of the semiconductor substrate; wherein the second conductive type is different from the first conductive type; a source region located in the second conductive type body region; a drain located on the second surface; a groove located between two adjacent second conductive type body regions and extending from the first surface to the interior of the semiconductor substrate; a gate dielectric layer extending from the groove to above the first surface and covering part of the second conductive type body region; and a gate located on the gate dielectric layer. Thus, the purpose of reducing Cgd at low voltage and keeping Cgd unchanged at high voltage can be achieved, thereby reducing Qg and driving loss, and the process is simple and easy to implement.

[0040] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0041] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0042] Figure 1 A schematic diagram of a cross-sectional structure of a super-junction VDMOS;

[0043] Figure 2 A schematic diagram of a cross-sectional structure of a vertical transistor provided by the embodiment of the present application;

[0044] Figure 3 A schematic diagram of a flow of a preparation method of a vertical transistor provided by the embodiment of the present application;

[0045] Figures 4 to 9 A schematic diagram of a cross-sectional structure of a vertical transistor in a preparation process provided by the embodiment of the present application;

[0046] Figure 10 A schematic diagram of a simulation structure of a vertical transistor provided by the embodiment of the present application;

[0047] Figure 11 A schematic diagram of a simulation structure of a vertical transistor in a comparative example;

[0048] Figure 12 A schematic diagram of a simulation structure of a vertical transistor in a comparative example; Figure 10 A schematic diagram of a simulation structure of a vertical transistor in a comparative example; Figure 11 A comparison diagram of gate-drain capacitance curves of the embodiment and the comparative example;

[0049] Figure 13 A comparison diagram of gate-drain capacitance curves of the embodiment and the comparative example; Figure 12An enlarged schematic view of the low-voltage portion;

[0050] Figure 14 For Figure 10 A comparison of the gate charge curves for the embodiments shown in Figure 11 A comparison of the gate charge curves for the embodiments shown in

[0051] Figure 15 A cross-sectional view of a gate dielectric during formation. DETAILED DESCRIPTION

[0052] Example embodiments of the present application will now be described in detail with reference to the accompanying drawings. Although example embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited to specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0053] In the following description, numerous specific details are given to provide a thorough understanding of the present application. However, it will be apparent that the present application can be practiced without one or more of these specific details. In other instances, well-known structures are not shown in detail in order not to obscure the present application. That is, well-known functions or constructions are not described in detail because they would be

[0054] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.

[0055] It should be understood that when an element or layer is referred to as being "on" or "over" another element or layer, it can be directly on or over the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element or layer, there are no intervening elements or layers present. It will also be appreciated by those of skill in the art that references to a structure or feature that is positioned "adjacent" to another feature can have the structure or feature positioned directly adjacent to the other feature or intervening structures or features can also be present. In addition, it should be understood that references to various features of structures generally having the same relative positions relative to one another can be interpreted differently depending on the specific structure being referred to. For example, a first feature can be described as being "above" a second feature, and a third feature can be described as being "above" the first feature. In some cases, the first feature can be directly above the second feature, and the third feature can be directly above the first feature. In other cases, however, the first feature can be indirectly above the second feature, and the third feature can be indirectly above the first feature. That is, one or more intervening features can be present between the first and second features, and one or more intervening features can be present between the first and third features.

[0056] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] For a thorough understanding of the present application, reference will be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0059] Figure 1 A cross-sectional structure of a super-junction VDMOS is shown in the figure. As shown, in the semiconductor substrate 100, especially the epitaxial layer 120, there are a plurality of second-conductivity-type pillars 220 arranged at intervals, thereby forming a super-junction structure (or "super-junction cell structure") with NPNP repeating arrangement; the gate 320 above the semiconductor substrate 100 is connected to the gate terminal (not shown in the figure); the conductive connection layer on one side of the semiconductor substrate 100 is the source 400; and the conductive connection layer on the other side of the semiconductor substrate 100 is the drain 500. In order to reduce Qg, it is generally necessary to reduce Cgd at low voltage. However, the reduction of Cgd at low voltage usually leads to the reduction of Cgd at high voltage as well, and the Cgd at high voltage being too low will lead to a series of problems as described above, which requires the skilled person in the art to make a balance and selection.

[0060] To solve the above technical problems, the embodiments of the present application provide a vertical transistor. Please refer to Figure 2 The vertical transistor comprises: a semiconductor substrate 100 comprising a first surface 101 and a second surface 102 opposite to each other, the semiconductor substrate 100 having a first conductive type; a plurality of second conductive type body regions 230 extending from the first surface 101 to the interior of the semiconductor substrate 100; wherein the second conductive type is different from the first conductive type; a source region 240 located in the second conductive type body region 230; a drain 500 located on the second surface 102; a groove 103 located between two adjacent second conductive type body regions 230 and extending from the first surface 101 to the interior of the semiconductor substrate 100; a gate dielectric layer 310 extending from the groove 103 to above the first surface 101 and covering part of the second conductive type body region 230; and a gate 320 located on the gate dielectric layer 310.

[0061] In the embodiments of the present application, the term "substrate" refers to a carrier on which subsequent material layers are added, which can be a growth substrate or can include an epitaxial layer. In the case of ignoring the flatness of the first surface 101 and the second surface 102, the plane on which the first surface 101 and the second surface 102 of the semiconductor substrate 100 are located, or strictly speaking, the central plane in the thickness direction of the semiconductor substrate 100, is determined as the substrate plane; the direction parallel to the substrate plane is the in-plane direction along the substrate. The direction perpendicular to the substrate plane is the thickness direction of the semiconductor substrate 100, or the height direction of the device, the depth direction of each region; the thickness direction of the semiconductor substrate 100 is also the layer stacking direction of the subsequent deposition of each material layer on the semiconductor substrate 100.

[0062] To better meet the formation requirements of the transistor, the material of the semiconductor substrate 100 can be selected as a single crystal semiconductor material; specifically, for example, single crystal silicon. Of course, the present application does not exclude the semiconductor substrate made of single crystal germanium and the like.

[0063] As an optional implementation, the semiconductor substrate 100 comprises: a semiconductor base 110 and an epitaxial layer 120 epitaxially grown on the semiconductor base 110. Wherein, the first surface 101 is specifically the upper surface of the epitaxial layer 120, and the second surface 102 is specifically the lower surface of the semiconductor base 110. Taking an N-type VDMOS as an example, the first conductive type is N-type; thus, the semiconductor substrate 100 comprises an N-type heavily doped (n+) semiconductor base 110 and an N-type doped epitaxial layer 120.

[0064] It can be understood that the material of the epitaxial layer 120 is also a single crystal semiconductor material; specifically, for example, single crystal silicon.

[0065] The second-conductivity-type body region 230 can be formed by an ion implantation process. Specifically, as one optional embodiment, the gate structure 300 is formed first, and then the ion implantation is performed in a self-alignment manner with the opening between two adjacent gate structures 300 as an implantation window, where the semiconductor substrate 100 is exposed. As another optional embodiment, a patterned mask layer is formed on the first surface 101 by a photolithography process, thereby defining the implantation window; specifically, the semiconductor substrate 100 is exposed through the pattern of the mask layer, and then the ion implantation is performed on the exposed semiconductor substrate 100. After the ion implantation, a high-temperature annealing process can be further included to promote the lateral diffusion of the second-conductivity-type impurities in the first-conductivity-type region, thereby forming the body region of the transistor. At least a portion of the second-conductivity-type body region 230 forms the channel of the transistor.

[0066] The second-conductivity-type is different from the first-conductivity-type. For example, the first-conductivity-type is N-type, and the second-conductivity-type is P-type; or conversely, the first-conductivity-type is P-type, and the second-conductivity-type is N-type.

[0067] The source region 240 can be formed by an ion implantation process. In actual fabrication, the implantation window can be defined by a photolithography process. Exemplarily, N+ type ion implantation is performed to form the source region 240.

[0068] As a vertical device, the source region 240 is close to the first surface 101 of the semiconductor substrate 100. Thus, the source electrode 400 is located on the first surface 101 and is in electrical connection with the source region 240. The drain electrode 500 is located on the second surface 102. In actual fabrication, the source electrode 400 and the drain electrode 500 can be formed by depositing a metal material.

[0069] The recess 103 can be formed by etching the first surface 101 of the semiconductor substrate 100. By digging the recess 103 under the gate dielectric layer in the conventional structure, the subsequently deposited gate dielectric layer 310 has an increased thickness at the position where the recess 103 is located. In this way, a certain degree of reduction of the Cgd is achieved when the Vds starts to rise. The material of the gate dielectric layer 310 is usually oxide (e.g., silicon oxide), and thus it is often referred to as gate oxide layer, or simply gate oxide, in the art. It should be understood that even if the gate dielectric layer 310 is referred to as gate oxide layer and the capacitance formed by the gate dielectric layer 310 is referred to as gate oxide capacitance in the following, this does not mean that the material selection of the gate dielectric layer 310 in the embodiments of the present application is limited, and any material suitable for the gate dielectric layer can be used to form the gate dielectric layer 310.

[0070] It can be understood that the gate-drain capacitance Cgd is formed by the gate oxide capacitance and the depletion junction capacitance in series, and according to the formula 1 / C 总= 1 / C1+1 / C2, it can be known that total capacitance C 总 is determined by the minimum one of C1 and C2. Wherein, one of C1 and C2 represents a gate oxide capacitance, and the other represents a depletion junction capacitance, then C 总 is a gate-drain capacitance Cgd.

[0071] At the beginning of the increase of Vds, the depletion line just starts to extend, and the depletion junction capacitance is large; at this time, Cgd is determined by the gate oxide capacitance. In the embodiment of the present application, the thickness of the partial gate dielectric layer 310 at the position where the groove 103 is located is increased. According to the capacitance formula C = ε / tox, wherein tox represents the thickness of the gate dielectric layer, and the partial increase of tox causes the gate oxide capacitance to decrease to a certain extent, thus Cgd is reduced at the beginning of the increase of Vds. Since the Cgd capacitance decreases with the increase of Vds, Qgd is mainly determined by Cgd at low Vds, thus Qgd is reduced to a certain extent.

[0072] And at high voltage, since the depletion junction capacitance is small, Cgd is mainly determined by the depletion junction capacitance. Therefore, at high voltage, the influence of the gate oxide capacitance on the total capacitance can be basically ignored, and the Cgd at high voltage of this structure is basically unchanged, and the influence on the dynamic performance of the device is small.

[0073] In this way, the effects of reducing Cgd at low voltage (low Vds) and stabilizing Cgd at high voltage are achieved, and the process is simple and easy to implement. By adjusting the capacitance, the Qg of the device is reduced, thereby reducing the driving loss of the opening process of the device. The groove 103 is located in the JFET region under the gate 320, compared with the traditional technology, the groove 103 is additionally arranged in the region and filled with gate dielectric material, which reduces the driving loss of the device without any influence on the overall process flow and thermal process of the device, and thus the influence on other static parameters of the device is negligible.

[0074] In the embodiment of the present application, the gate dielectric layer 310 only has an increased thickness at the position of the groove 103, and the thickness is unchanged at the position of the partial region covering the second conductive type body region 230, thereby avoiding the influence on the threshold voltage Vt. Specifically, please continue to refer to Figure 2 The thickness of the gate dielectric layer 310 at the position of the groove 103 is greater than the thickness at the position of the partial region covering the second conductive type body region 230.

[0075] The recess 103 is located between two adjacent second-conductivity-type body regions 230, and is spaced apart from the second-conductivity-type body regions 230 and not connected to the second-conductivity-type body regions 230. Specifically, when the recess 103 is etched, a spacing exists between the boundary of the etching region and any second-conductivity-type body region 230, so that the semiconductor substrate 100 (specifically, the epitaxial layer 120) is at least partially located between the recess 103 and any second-conductivity-type body region 230. In this way, the channel of the transistor is avoided from being affected.

[0076] As a specific embodiment, the line width of the recess 103 is greater than or equal to 1 / 3 of the spacing between two adjacent second-conductivity-type body regions 230, and less than or equal to 1 / 2 of the spacing between two adjacent second-conductivity-type body regions 230. Research shows that when the line width of the recess 103 is less than 1 / 3 of the spacing between two adjacent second-conductivity-type body regions 230, the effect on the gate oxide capacitance is limited, so that the Cgd reduction at low voltage cannot be well achieved. When the line width of the recess 103 is greater than 1 / 2 of the spacing between two adjacent second-conductivity-type body regions 230, other static parameters of the device can be affected. For example, the line width of the recess 103 is 1 μm.

[0077] The gate dielectric layer 310 can have a substantially flat upper surface, so as to ensure that the thickness at the position of the recess 103 is greater than the thickness at the position of the portion of the gate dielectric layer 310 covering the second-conductivity-type body region 230. In addition, the gate 320 formed on the gate dielectric layer 310 can also have a substantially flat lower surface.

[0078] As a specific embodiment, the depth of the recess 103 is greater than or equal to 1 / 3 of the spacing between two adjacent second-conductivity-type body regions 230, and less than or equal to 1 / 2 of the spacing between two adjacent second-conductivity-type body regions 230. Research shows that, similar to the line width of the recess 103, when the depth of the recess 103 is less than 1 / 3 of the spacing between two adjacent second-conductivity-type body regions 230, the increase of tox is limited, so that the effect on the gate oxide capacitance is limited, and the Cgd reduction at low voltage cannot be well achieved. When the depth of the recess 103 is greater than 1 / 2 of the spacing between two adjacent second-conductivity-type body regions 230, the on-resistance Rdson can be affected. For example, the depth of the recess 103 is 0.5 μm to 2 μm.

[0079] It should be noted that the embodiment of the present application does not require the depth of the recess 103 to be equal to the line width of the recess 103.

[0080] In an optional specific example, the material of the portion 311 of the gate dielectric layer 310 located in the recess 103 is different from the material of the portion 312 of the gate dielectric layer 310 located on the second-conductivity-type body region 230 (for example, refer to Figure 6 and Figure 7 ).

[0081] To increase the gate oxide capacitance, the material of the portion 311 of the gate dielectric layer 310 located within the recess 103 can include a high-K dielectric material.

[0082] The material of the portion of the gate dielectric layer 310 located directly above the recess 103 (the portion above the first surface 101) can be the same as the material of the portion 311 located within the recess 103, or can be the same as the material of the portion 312 located on the second conductivity type body region 230.

[0083] As a specific embodiment, the vertical transistor further comprises: a plurality of second conductivity type pillars 220 spaced apart within the semiconductor substrate 100 to space apart the first conductivity type pillars 121 between two adjacent second conductivity type pillars 220; the second conductivity type pillars 220 and the first conductivity type pillars 121 are alternately arranged to form a super junction structure; and a plurality of second conductivity type body regions 230 are respectively located above the plurality of second conductivity type pillars 220. It can be understood that in this embodiment, the vertical transistor is specifically a super junction VDMOS.

[0084] The super junction VDMOS device is an important power device that has appeared in recent years, and its basic principle is the charge balance principle. By introducing a super junction structure of P pillars and N pillars spaced apart in the drift region of a common power MOSFET, the trade-off relationship between the on-resistance and the breakdown voltage of the common MOSFET is greatly improved.

[0085] It should be understood that although each structural diagram of the present application is exemplified by a super junction VDMOS transistor, the vertical transistor and the preparation method thereof provided by the embodiments of the present application are obviously also applicable to a common vertical MOSFET.

[0086] Please continue to refer to Figure 2 , the second conductivity type pillars 220 and the first conductivity type pillars 121 are both located within the epitaxial layer 120.

[0087] As an optional embodiment, the second conductivity type pillars 220 can be formed by: first providing a semiconductor substrate 100 including a relatively thin epitaxial layer, then epitaxially growing multiple times and simultaneously implanting second conductivity type impurities in selected regions and annealing, thereby forming second conductivity type pillars 220 with a designed depth. As another optional embodiment, the second conductivity type pillars 220 are formed by: first providing a semiconductor substrate 100 including an epitaxial layer with a designed thickness, then forming a plurality of spaced-apart trenches 210 from the epitaxial layer, and epitaxially growing second conductivity type pillars 220 within the plurality of trenches 210. Both of these two methods are conventional processes in the art, and will not be described in detail here.

[0088] Next, please refer to Figure 10 andFigure 11 . Figure 10 This is a schematic diagram of a simulation structure of a vertical transistor provided in an embodiment of this application; the simulation area in the figure is a half-pitch structure of a single cell. The cell pitch is 12 μm; the linewidth of the groove 103 is 1 μm, and its depth is 0.5 μm. Figure 11 This is a schematic diagram of a simulated structure of a pair of vertical transistors in a scaled configuration. The scaled configuration is similar to... Figure 10 The embodiments shown have the same structural dimensions and manufacturing process; the only difference is that the comparative example does not have the groove 103 (please refer to...). Figure 10 and Figure 11 (Middle elliptical dashed box).

[0089] Next, please refer to Figure 12 and Figure 13 In the graph, the horizontal axis X represents Vds, and the vertical axis Y represents Cgd; the dashed line indicates... Figure 11 The grid-drain capacitance curves shown are for comparison (represented by Cgd_BL in the figure); the solid line represents... Figure 10 The gate-drain capacitance curve of the illustrated embodiment is shown (represented by Cgd_new in the figure). Simulation results verify that under low voltage conditions (i.e., when the Vds value is small), the following can be referenced: Figure 13 The solid line has a lower initial capacitance, and its capacitance is lower than that of the dashed line within 10V; however, under high voltage, the difference in capacitance between the two is negligible.

[0090] Next, please refer to Figure 14 In the figure, the horizontal axis X represents Qg, and the vertical axis Y represents the gate voltage; the dashed line indicates... Figure 11 The curves showing the gate charge in the comparative example are denoted by Qg_BL in the figure; the solid line represents... Figure 10 The curves for the gate charge of the illustrated embodiment (represented by Qg_new in the figure) are shown. Simulation results verify that the first rising curves of both embodiments are basically the same, at which point Cgd is relatively small, and Qg is mainly influenced by Qgs. As the Gate Voltage reaches the plateau voltage, Vds begins to decrease. When Vds drops below 20V, the gate-drain junction capacitance becomes sufficiently large, and the smaller gate oxide capacitance begins to take effect, causing the Cgd of the embodiment to decrease compared to the comparative embodiment, thus reducing Qgd. As shown in the figure, the Qgd of the embodiment decreases by about 15% compared to the comparative embodiment. After the plateau voltage, the Gate Voltage continues to increase. At this point, Qg is mainly determined by Cgs and Cgd at low Vds. Because the Cgd of the embodiment is smaller at low Vds, the rising rate of Qgd in the second rising curve of the figure is smaller than that of the comparative embodiment. The curves show that at a fixed gate drive voltage (20V), the total Qg of the embodiment structure decreases by about 10% compared to the comparative structure.

[0091] On this basis, the application further provides a preparation method of the vertical transistor. Please refer to Figure 3 The method comprises the following steps:

[0092] Step S01, providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the semiconductor substrate having a first conductive type;

[0093] Step S02, forming a plurality of second conductive type body regions extending from the first surface to the interior of the semiconductor substrate; wherein the second conductive type is different from the first conductive type;

[0094] Step S03, forming a groove extending from the first surface to the interior of the semiconductor substrate, the groove being located between two adjacent second conductive type body regions;

[0095] Step S04, forming a gate dielectric layer extending from the groove to above the first surface, the gate dielectric layer covering part of the second conductive type body region;

[0096] Step S05, forming a gate on the gate dielectric layer;

[0097] Step S06, forming a source region in the second conductive type body region;

[0098] Step S07, forming a drain on the second surface.

[0099] It should be understood that, although Figure 3 each step is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow; moreover, these steps are not necessarily executed in sequence, and the application does not exclude the case that at least two steps are executed at the same time or are alternately executed. The execution timing between the steps should be determined according to the specific logical relationship.

[0100] Next, the vertical transistor and the preparation method thereof provided by the application will be further described in detail in combination with Figures 4 to 9 .

[0101] First, please refer to Figure 4 . Step S01 is executed to provide a semiconductor substrate 100, the semiconductor substrate 100 comprising a first surface 101 and a second surface 102 opposite to each other, the semiconductor substrate 100 having a first conductive type.

[0102] As a specific implementation, before step S02, the method further comprises: forming a plurality of second-conductivity-type pillars 220, which are arranged in the semiconductor substrate 100 at intervals to form first-conductivity-type pillars 121 between two adjacent second-conductivity-type pillars 220; and the second-conductivity-type pillars 220 and the first-conductivity-type pillars 121 are arranged alternately to form a super-junction structure.

[0103] As an optional implementation, step 101 specifically comprises: first providing a semiconductor substrate 100 including a relatively thin epitaxial layer (i.e., including a semiconductor base 110 and a part of an epitaxial layer 120), then performing epitaxial growth multiple times while injecting second-conductivity-type impurities into selected regions (which can refer to 210 in the figure) and annealing, so as to form second-conductivity-type pillars 220 with a designed depth. At this time, the semiconductor substrate 100 includes the semiconductor base 110 and the epitaxial layer 120 epitaxially grown on the semiconductor base 110; wherein the first surface 101 is specifically the upper surface of the epitaxial layer 120, and the second surface 102 is specifically the lower surface of the semiconductor base 110.

[0104] As another optional implementation, step 101 specifically comprises: first providing a semiconductor substrate 100 including an epitaxial layer 120 with a designed thickness, and the first surface 101 is specifically the upper surface of the epitaxial layer 120, then forming a plurality of spaced-apart trenches 210 extending into the epitaxial layer 120 on the first surface 101, and epitaxially growing second-conductivity-type pillars 220 in the plurality of trenches 210.

[0105] Next, please refer to Figure 5 Step S02 is performed to form a plurality of second-conductivity-type body regions 230 extending from the first surface 101 to the interior of the semiconductor substrate 100; wherein the second conductivity type is different from the first conductivity type.

[0106] In the above specific implementation with the super-junction structure, forming the plurality of second-conductivity-type body regions 230 comprises: forming the plurality of second-conductivity-type body regions 230 respectively above the plurality of second-conductivity-type pillars 220. The forming method of the second-conductivity-type body regions 230 can refer to the above embodiments, which will not be described here.

[0107] Next, please continue to refer to Figure 5 Step S03 is performed to form a recess 103 extending from the first surface 101 to the interior of the semiconductor substrate 100, and the recess 103 is located between two adjacent second-conductivity-type body regions 230.

[0108] Exemplarily, a patterned mask layer can be first formed on the first surface 101 by a photolithography process, and then the epitaxial layer 120 is etched by means of the mask layer to form the recess 103.

[0109] As a specific embodiment, the line width of the recess 103 is in the range of greater than or equal to 1 / 3 of the interval between two adjacent second-conductivity-type body regions 230 and less than or equal to 1 / 2 of the interval between two adjacent second-conductivity-type body regions 230. Research shows that when the line width of the recess 103 is less than 1 / 3 of the interval between two adjacent second-conductivity-type body regions 230, the effect on the gate oxide capacitance is limited, thus failing to achieve a good reduction of Cgd at low voltage. When the line width of the recess 103 is greater than 1 / 2 of the interval between two adjacent second-conductivity-type body regions 230, it may affect other static parameters of the device. Exemplarily, the line width of the recess 103 is 1 μm.

[0110] As a specific embodiment, the depth of the recess 103 is in the range of greater than or equal to 1 / 3 of the interval between two adjacent second-conductivity-type body regions 230 and less than or equal to 1 / 2 of the interval between two adjacent second-conductivity-type body regions 230. Research shows that similar to the line width of the recess 103, when the depth of the recess 103 is less than 1 / 3 of the interval between two adjacent second-conductivity-type body regions 230, the increase of tox is limited, thus the effect on the gate oxide capacitance is limited, failing to achieve a good reduction of Cgd at low voltage. When the depth of the recess 103 is greater than 1 / 2 of the interval between two adjacent second-conductivity-type body regions 230, it may affect other static parameters of the device. Exemplarily, the depth of the recess 103 is 0.5 μm to 2 μm.

[0111] It should be noted that the embodiment of the present application does not require the depth of the recess 103 to be equal to the line width of the recess 103.

[0112] Next, please continue to refer to Figure 6 and Figure 7 Step S04 is performed to form a gate dielectric layer 310 extending from the recess 103 to above the first surface 101, the gate dielectric layer 310 covering part of the second-conductivity-type body region 230.

[0113] Optionally, first refer to Figure 6 to form a part 311 filled in the recess 103; and then refer to Figure 7 to grow a layer of gate dielectric material covering the first surface 101 (at this time, a part 312 located on the second-conductivity-type body region 230 is formed).

[0114] Optionally, the gate dielectric layer 310 can have a substantially flat upper surface. For example, this can be achieved by performing a planarization process after forming the part 311; or for example, this can be achieved by performing a planarization process after forming the part 312. The present application does not make a specific limitation in this regard.

[0115] In an alternative embodiment, the gate dielectric layer 310 is formed by: depositing a first dielectric material in the recess 103 by a first deposition process; and depositing a second dielectric material on the first surface 101 by a second deposition process, the second dielectric material covering at least a portion of the second conductivity type body region 230; wherein the first dielectric material is different from the second dielectric material.

[0116] To increase the gate oxide capacitance, the first dielectric material can comprise a high-K dielectric material. The second dielectric material can be an oxide, such as silicon oxide.

[0117] Please refer to Figure 15 , considering the structural features of the recess 103 and its aspect ratio, in a specific example, the gate dielectric layer 310 is formed by: depositing a gate dielectric material in the recess 103; removing part of the gate dielectric material deposited at the upper opening of the recess 103; again depositing a gate dielectric material in the recess 103; the gate dielectric material not removed forms a part of the gate dielectric layer 310. The solid line in the figure represents the position of the upper surface of the gate dielectric material in the corresponding step; the dashed line in the figure represents the position of the upper surface of the gate dielectric material in the previous step, thereby showing the specific operation of the current step by comparing the solid line and the dashed line.

[0118] It should be understood that the steps of depositing the gate dielectric material and removing part of the gate dielectric material deposited at the upper opening of the recess 103 are performed alternately. The number of times the two steps are performed depends on the actual process conditions, although Figure 15 three deposition steps and two removal steps are shown in , which is only illustrative and does not limit the present application.

[0119] Figure 8 Next, please refer to . Step S05 is performed to form the gate 320 on the gate dielectric layer 310.

[0120] The material of the gate 320 is, for example, polysilicon.

[0121] After the gate dielectric material and the gate material are sequentially deposited on the first surface 101, the gate dielectric layer 310 and the gate 320 can be defined by an etching process; wherein the adjacent two gates 320 have an opening exposing the semiconductor substrate 100, and the position of the opening corresponds to the position of the second conductivity type pillar 220 one by one. The gate dielectric layer 310 is located between the gate 320 and the semiconductor substrate 100.

[0122] In addition, please continue to refer to Figure 8 , in order to protect the gate 320, an insulating side wall can also be formed on the sidewall of the gate 320, and a protective layer 330 can also be formed on the upper surface of the gate 320. In this way, the gate structure 300 is formed.

[0123] Next, refer to Figure 9 Step S06 is performed to form the source region 240 in the second-conductivity-type body region 230.

[0124] Specifically, the source region 240 can be formed by an ion implantation process. In actual production, a window for ion implantation can be defined by a photolithography process.

[0125] Further, a source ohmic contact region (not shown in the figure) of the transistor can also be formed.

[0126] Next, step S07 is performed to form the drain 500 on the second surface 102 (refer to Figure 2 ).

[0127] Before forming the drain 500, a step of forming the source 400 on the first surface 101 can also be included. Exemplarily, the source 400 can be formed by depositing a metal material layer and patterning by a photolithography process. The source 400 forms ohmic contact with the source ohmic contact region, thereby forming conductive connection with the source region 240.

[0128] In the present embodiment, only the etching step of the recess 103 and the deposition step of the partial 311 of the gate dielectric layer 310 are added, and compared with the conventional process flow, there is no great change as a whole, which can reduce a series of potential risks caused by changes in process conditions.

[0129] It should be noted that the preparation method of the vertical transistor provided in the embodiments of the present application and the vertical transistor provided in the embodiments of the present application belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be combined arbitrarily without conflict. However, it should be further noted that the combination of each technical feature of the vertical transistor provided in the embodiments of the present application can already solve the technical problems to be solved by the present application; thus, the vertical transistor provided in the embodiments of the present application can not be limited by the preparation method of the vertical transistor provided in the embodiments of the present application, and any vertical transistor prepared by a preparation method that can form the structure of the vertical transistor provided in the embodiments of the present application is within the scope of protection of the present application.

[0130] It should be understood that the above embodiments are exemplary and are not intended to include all possible embodiments included in the claims. Various modifications and changes can also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, each technical feature of the above embodiments can also be combined arbitrarily to form another embodiment of the present application which can not be explicitly described. Therefore, the above embodiments only express several implementation manners of the present application, and do not limit the protection scope of the patent of the present application.

Claims

1. A vertical transistor, characterized by comprising: Comprising: a semiconductor substrate including a first surface and a second surface opposite to each other, the semiconductor substrate having a first conductivity type; a plurality of second conductivity type body regions extending from the first surface to an interior of the semiconductor substrate; wherein the second conductivity type is different from the first conductivity type; a source region within the second conductivity type body region, a drain on the second surface; a recess between two adjacent second conductivity type body regions, extending from the first surface to the interior of the semiconductor substrate; the recess has a depth in a range from greater than or equal to 1 / 3 of a pitch between the two adjacent second conductivity type body regions and less than or equal to 1 / 2 of the pitch between the two adjacent second conductivity type body regions; a gate dielectric layer extending from within the recess to above the first surface and covering a partial area of the second conductivity type body region; a material of a portion of the gate dielectric layer within the recess includes a high-K dielectric material; a gate on the gate dielectric layer.

2. The vertical transistor according to claim 1, wherein Further comprising: a plurality of second conductivity type pillars spaced within the semiconductor substrate to space a first conductivity type pillar between two adjacent second conductivity type pillars; the second conductivity type pillars and the first conductivity type pillar are alternately arranged to form a super junction structure; a plurality of the second conductivity type body regions are respectively above a plurality of the second conductivity type pillars.

3. The vertical transistor according to claim 1 or 2, characterized by The recess has a line width in a range from greater than or equal to 1 / 3 of a pitch between the two adjacent second conductivity type body regions and less than or equal to 1 / 2 of the pitch between the two adjacent second conductivity type body regions.

4. The vertical transistor according to claim 1 or 2, wherein The material of the portion of the gate dielectric layer within the recess is different from a material of a portion of the gate dielectric layer on the second conductivity type body region.

5. A method for manufacturing a vertical transistor, characterized by, The method comprising: providing a semiconductor substrate including a first surface and a second surface opposite to each other, the semiconductor substrate having a first conductivity type; forming a plurality of second conductivity type body regions extending from the first surface to an interior of the semiconductor substrate; wherein the second conductivity type is different from the first conductivity type; forming a recess between two adjacent second conductivity type body regions, the recess extending from the first surface to the interior of the semiconductor substrate; the recess has a depth in a range from greater than or equal to 1 / 3 of a pitch between the two adjacent second conductivity type body regions and less than or equal to 1 / 2 of the pitch between the two adjacent second conductivity type body regions; forming a gate dielectric layer extending from within the recess to above the first surface, the gate dielectric layer covering a partial area of the second conductivity type body region; a material of a portion of the gate dielectric layer within the recess includes a high-K dielectric material; forming a gate on the gate dielectric layer; forming a source region within the second conductivity type body region; forming a drain on the second surface.

6. The method of claim 5, wherein Before forming the plurality of the second-conductivity-type body regions, the method further comprises: forming a plurality of second-conductivity-type pillars, the plurality of the second-conductivity-type pillars are spaced apart in the semiconductor substrate to leave a first-conductivity-type pillar between two adjacent second-conductivity-type pillars; the second-conductivity-type pillars and the first-conductivity-type pillars are arranged alternately to form a super-junction structure; forming the plurality of the second-conductivity-type body regions comprises: forming the plurality of the second-conductivity-type body regions respectively above the plurality of the second-conductivity-type pillars.

7. The method for manufacturing a vertical transistor according to claim 5 or 6, wherein The line width of the recess is in a range of: greater than or equal to 1 / 3 of the interval between two adjacent second-conductivity-type body regions, and less than or equal to 1 / 2 of the interval between two adjacent second-conductivity-type body regions.

8. The method for manufacturing a vertical transistor according to claim 5 or 6, wherein forming the gate dielectric layer comprises: depositing a first dielectric material in the recess by a first deposition process; depositing a second dielectric material on the first surface by a second deposition process, the second dielectric material covers at least a part of the second-conductivity-type body region; wherein the first dielectric material is different from the second dielectric material.

9. The method for manufacturing a vertical transistor according to claim 5 or 6, wherein forming the gate dielectric layer comprises: depositing a gate dielectric material in the recess; removing part of the gate dielectric material deposited at the upper opening of the recess; depositing the gate dielectric material in the recess again; the gate dielectric material not removed forms a part of the gate dielectric layer.

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