Switched capacitor converter, corresponding method, power supply system and electronic device

Abstract

The present disclosure relates to switched capacitor converters, corresponding methods, power supply systems and electronic devices. A first circuit branch and a second circuit branch are coupled between an input node and ground. Each circuit branch comprises a first transistor to a fourth transistor coupled in series with an output node. A first capacitor is coupled between a first capacitor node intermediate the first transistor and the second transistor and a second capacitor node. A second capacitor is coupled between a third capacitor node intermediate the first transistor and the second transistor and a fourth capacitor node. An inter-branch circuit block between the first branch and the second branch comprises a first inter-branch transistor coupled between the first capacitor node in the first circuit branch and the fourth capacitor node in the second circuit branch and a second inter-branch transistor coupled between the third capacitor node in the second circuit branch and the second capacitor node in the first circuit branch.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Italian Patent Application No. 102021000020597, filed on July 30, 2021, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This specification relates to electronic conversion circuits and methods, such as switched capacitor converter (SCC) topologies.

[0004] For example, one or more embodiments can be used in a switching DC-DC voltage converter to provide regulated DC power. Background Technology

[0005] DC-DC voltage converters employing the switched capacitor converter (SCC) type differ from other topologies that use capacitors as energy storage devices, such as known buck or boost converters. Optionally, a resonant inductor with a reduced size compared to the inductor used in buck or boost converter topologies can be introduced to reduce capacitor charging / discharging losses (currently referred to as inherent power losses). This is achieved while maintaining high power density, thanks to the reduced size of the resonant inductor configured to resonate with the capacitor at the switching frequency of the SCC.

[0006] In a conventional SCC circuit, the output voltage corresponds to the input voltage, which is scaled (amplified or reduced) at a fixed conversion ratio based on a specific circuit topology (such as series-parallel, Dickson, cascade multiplier, and ladder topology).

[0007] Introducing a resonant inductor also provides the possibility of continuously adjusting the output voltage of the SCC.

[0008] Numerous publications have focused on SCC circuit topologies, as demonstrated by, for example, the following references (each cited in this paper):

[0009] [1] S. Jiang et al.'s "Switched Tank Converters" (IEEE Transactions on Power Electronics, vol.34, no.6, pp.5048-5062, June 2019, doi:10.1109 / TPEL.2018.2868447) proposes a novel switched slot converter (STC) that uses an LC resonant tank to partially replace the flying capacitor for energy transfer; multiple STCs can share parallel operation with the inherent droop current to provide scalability and control simplicity;

[0010] [2] C. Schaef et al., “A 3-Phase Resonant Switched Capacitor Converter Delivering 7.7W at 85% Efficiency Using 1.1nH PCB Trace Inductors” (IEEE Journal of Solid-State Circuits, vol.50, no.12, pp.2861-2869, Dec.2015, doi:10.1109 / JSSC.2015.2462351), discusses switched capacitor (SC) converters, particularly resonant switched capacitor (ReSC) topologies with a small amount of inductance introduced in series with flying capacitors to eliminate charge-sharing losses, thereby achieving efficient operation in low-cost process options. The three-phase interleaved topology can provide up to 7.7W of power (power density of 0.91W / mm2 or 6.4kW / in3) with 85% efficiency using bootstrap n-channel power systems and single-digit nH inductors embedded in flip-chip components.

[0011] [3] MDSeeman et al., “Analysis and Optimization of Switched-Capacitor DC–DC Converters” (IEEE Transactions on Power Electronics, vol. 23, no. 2, pp. 841-851, March 2008, doi: 10.1109 / TPEL.2007.915182), discuss an analytical method for fully determining the steady-state performance of switched-capacitor (SC) DC-DC converters by evaluating their output impedance. The developed simple formula allows for optimization of capacitor size to meet constraints such as total capacitance or total energy storage limits, and also allows for optimization of switch size, constrained by the total switching conductance or the product of total switching volt-amperes (VA). For medium to high conversion ratios, the performance of the ladder-type converter (based on conduction losses) is superior to that of conventional magnetically based converters; and

[0012] [4] Y.Li et al.'s “Resonant switched capacitor stacked topology enabling high DC-DC voltage conversion ratios and efficient wide range regulation” (2016 IEEE Energy Conversion Congress and Exposition (ECCE), 2016, pp. 1-7, doi: 10.1109 / ECCE.2016.7855401) proposed a stacked topology resonant switched capacitor DC-DC converter to achieve high voltage conversion ratios, wherein the topology can be extended to any N-to-1 DC-DC conversion application with only a single inductor.

[0013] Existing solutions may suffer from one or more of the following drawbacks: In ladder-topology-based SCC circuits, the number of capacitors increases twice as fast as in other topologies with a conversion ratio of 1 / N less than 1 / 2; area footprint can also be an issue in ladder-topology-based SCC circuits.

[0014] Dickson and multiplier topologies involve capacitors and transistors with relatively high ratings, i.e., the maximum voltage applied to the device during steady-state operation. Low voltage ratings improve the device's performance, while using components (capacitors and transistors) with higher voltage ratings leads to a degraded converter performance.

[0015] There is a need in this field to overcome the above-mentioned shortcomings. Summary of the Invention

[0016] One or more embodiments may relate to a circuit.

[0017] An example of this type of electronic converter is a switched capacitor circuit (SCC).

[0018] One or more embodiments may relate to a corresponding method.

[0019] One or more embodiments may relate to a corresponding power system (e.g., equipped on a mobile electronic device).

[0020] Due to the higher energy density of capacitors compared to inductors, one or more embodiments facilitate the achievement of high power density in discrete and integrated solutions.

[0021] One or more embodiments facilitate the provision of a ladder SCC circuit that can perform the conversion using a reduced number of components that have a relatively low rated voltage for any conversion ratio 1 / N for integer N≥3.

[0022] In particular, the embodiment reduces the total area footprint compared to conventional ladder converters with similar efficiency or output resistance.

[0023] Due to the lower rated voltage of the components, one or more embodiments show performance improvements relative to other converter circuit topologies such as Dickson and multipliers.

[0024] One or more embodiments utilize phase interleaving to provide a DC current path from input to output.

[0025] One or more embodiments involve reducing the number of transistors per interleaved branch relative to a conventional topology.

[0026] One or more embodiments utilize ladder topology to improve the use of passive and active components, thereby producing superior quality factors, such as efficiency and / or device cost.

[0027] One or more embodiments are further characterized by a smaller number of capacitors, particularly for high conversion ratios.

[0028] One or more embodiments facilitate the provision of a bus DC-DC converter with a high and fixed buck conversion ratio and high efficiency. Attached Figure Description

[0029] One or more embodiments will now be described by reference only to the accompanying drawings, in which:

[0030] Figure 1 This is an example diagram of a power supply system based on this disclosure;

[0031] Figure 2 This is an example diagram of the ladder topology of the SCC circuit;

[0032] Figure 2A and Figure 2B It is an operation Figure 2 Example diagram of the circuit method shown;

[0033] Figure 3 This is an example diagram of the interleaved topology of a converter circuit;

[0034] Figure 4 This is an example diagram of the topology of the SCC circuit according to this disclosure;

[0035] Figure 5 This is an example diagram of an alternative topology for the SCC circuit according to this disclosure;

[0036] Figure 5A and Figure 5B It is an operation Figure 5 Example diagram of the circuit method shown;

[0037] Figure 6 These are example diagrams of alternative topologies for converter circuits according to this disclosure; and

[0038] Figure 7 yes Figure 6 An example diagram of a portion of the circuit shown. Detailed Implementation

[0039] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or by other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described in order to avoid obscuring certain aspects of the embodiments.

[0040] References to “embodiment” or “one embodiment” within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in connection with that embodiment is included in at least one embodiment. Therefore, phrases such as “in an embodiment” or “in one embodiment” that may appear in one or more places throughout this specification do not necessarily refer to one and the same embodiment.

[0041] Furthermore, specific constructions, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0042] The accompanying diagram is a simplified version and is not drawn to scale.

[0043] In all the accompanying figures, the same parts or elements are indicated by the same reference numerals / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0044] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0045] For simplicity, the same reference symbols may be used in the following detailed description to denote nodes / lines in a circuit and signals that may appear at those nodes or lines.

[0046] like Figure 1 As shown, electronic device 10 is equipped with a power management circuit. Electronic device 10 includes: a power management circuit configured to store the supply voltage level V. IN The energy source 12 (e.g., a battery); coupled to the energy source 12 and configured to receive a supply voltage level V from the energy source 12 at a power node or line. IN The bus converter 14 (e.g., an SCC circuit), wherein the bus converter 14 is further configured to provide an regulated voltage level V based on the received supply voltage level. OUTFor example, approximately 48V; a group of DC-DC converters 16 including DC-DC converter circuitry (e.g., having the same or different topologies), the group of DC-DC converters 16 being coupled to a bus converter 14 and configured to receive an regulated voltage level V from the bus converter 14. OUT The group of DC-DC converters 16 is also coupled to a group of loads 18, wherein the DC-DC converters in the group of DC-DC converters 16 are coupled to the corresponding loads in the group of loads 18 and are configured to provide regulated voltage levels thereto (e.g., three voltage regulators coupled to three loads), and are configured to provide regulated voltage levels based on supply voltage levels received from the bus converter (e.g., approximately 3.3V, 5V, and 12V respectively); and a processing circuit system (PC) 20, which is coupled to the bus converter 14 and / or the group of DC-DC converters 16 and is configured to control their operation, for example by providing them with control signals φ1, φ2, as described below.

[0047] In particular, the electronic device 10 is a portable device (such as a mobile phone or laptop computer) that is (e.g., battery-powered), making the efficiency of the DC-DC converter circuits 14, 16 and the battery power management relevant to the performance of the device 10.

[0048] A power supply system as illustrated herein may include: a DC voltage source (e.g., 12) configured to provide a first DC voltage level referenced to ground (e.g., GND); a set of converter circuits (e.g., 14, 16) including at least one circuit according to the present disclosure; and a control circuit (e.g., 20) coupled to the set of converter circuits to provide control signals (e.g., φ1, φ2) thereto; wherein the set of converter circuits is configured to be coupled to a set of corresponding loads (e.g., Z). L , 18) to provide it with at least one second DC voltage level (e.g., V OUT ).

[0049] Electronic devices (e.g., 10) illustrated herein may be equipped with a power system according to this disclosure.

[0050] Due to its high efficiency and relatively high and fixed buck conversion ratio, the switched capacitor converter (SCC) is suitable for device 10.

[0051] like Figure 2 As shown, the SCC circuit 200, particularly the SCC circuit 200 having a ladder topology with a conversion ratio of 3:1, includes: a voltage level V referenced to ground GND. IN (For example, from energy source 10) input node V IN Configured to couple to load impedance Z L(For example, the group of DC converters 30) to provide it with a regulated output voltage V OUT Output node V OUT ; and a set of (e.g., MOS) transistors M1, M2, M3, M4, M5, M6, each transistor having a corresponding control node and a corresponding current path passing between a first (e.g., drain) node and a second (e.g., source) node, the set of transistors M1, M2, M3, M4, M5, M6 being arranged to have current paths along the input node V IN The corresponding current path connected in series with the current line between the ground (GND).

[0052] like Figure 2 As shown, the group of transistors M1, M2, M3, M4, M5, and M6 includes: a first transistor M1, a third transistor M3, and a fifth transistor M5 configured to receive a first control signal φ1 (e.g., from control circuit 20) at a respective control node. The first transistor M1, the third transistor M3, and the fifth transistor M5 are configured to turn on the respective current paths passing through them based on the first control signal φ1 having a first value (e.g., "high" or "1") and not turn on based on the first control signal φ1 having a second value (e.g., "low" or "0"). The group of transistors M1, M2, M3, M4, M5, and M6 further includes a second transistor M2, a fourth transistor M4, and a sixth transistor M6 configured to receive a second control signal φ2 (e.g., from control circuit 20) at a respective control node. The second transistor M2, the fourth transistor M4, and the sixth transistor M6 are configured to turn on their respective current paths based on a first value (e.g., "1") of the second control signal φ2 and not turn on based on a second value (e.g., "0") of the second control signal φ2.

[0053] In one or more embodiments, the control circuit 20 is configured to generate a second control signal φ2 as an inverted version of the first control signal φ1, that is, with a phase difference of π or 180° relative to the first control signal φ1.

[0054] like Figure 2 As shown, the SCC circuit 200 further includes a first capacitor C1 coupled to the group of transistors M1, M2, M3, M4, M5, and M6, the first capacitor C1 having a first capacitor terminal N coupled (e.g., directly) between the first transistor M1 and the second transistor M2. 12 And the second capacitor terminal N coupled (e.g., directly) between the third transistor M3 and the fourth transistor M4 34 A second capacitor C2 is coupled to the group of transistors M1, M2, M3, M4, M5, and M6. The second capacitor C2 has a first capacitor terminal N coupled (e.g., directly) between the second transistor M2 and the third transistor M3.23 And the output node V coupled (e.g., directly) between the fourth transistor M4 and the fifth transistor M5 OUT The second capacitor terminal N at the location 45 A third capacitor C3 is coupled to the group of transistors M1, M2, M3, M4, M5, and M6. The third capacitor C3 has a first capacitor terminal N coupled (e.g., directly) between the third transistor M3 and the fourth transistor M4. 34 And the second capacitor terminal N coupled (e.g., directly) between the fifth transistor M5 and the sixth transistor M6 56 ; and having coupling (e.g., directly) to the output node V OUT The first capacitor terminal N 45 And a filter capacitor C0 coupled (e.g., directly) to the second capacitor terminal of ground GND.

[0055] For example, the first capacitor C1, the second capacitor C2, and the third capacitor C3 have the same capacitance, such as C1 = C2 = C3 = C.

[0056] For example, operation Figure 2 The SCC circuit 200 shown includes two operating phases, wherein the behavior of the circuit 200 varies based on which of the switching transistors M1, M2, M3, M4, M5, and M6 is switched to the on / off state.

[0057] like Figure 2A As shown, in the first operation stage, when the first control signal φ1 has a first value and the second control signal φ2 has a second value, the first capacitor C1 becomes connected in series with the third capacitor C3, the third capacitor C3 becomes connected in parallel with the second capacitor C2, and the second capacitor C2 then becomes connected in series with the output capacitor C0 at the input node V. IN With output node V OUT Between, so that current flows from input node V IN It is drawn to charge the first capacitor C1 and flows to the load Z. L .

[0058] like Figure 2B As shown, in the second operation stage, when the second control signal φ2 has a first value and the first control signal φ1 has a second value, the first capacitor C1 becomes connected in series with the third capacitor C3 and in parallel with the second capacitor C2. The second capacitor C2 then becomes connected in series with the output capacitor C0 at the output node V. OUT Between GND and ground, the charge previously stored on the capacitor flows via current toward the output node V. OUT Load Z at the location L Transfer.

[0059] like Figure 2A and Figure 2B As shown, in each of these two operational phases, the charge flow relative to the total output charge q is indicated by arrows, for example, pointing to the "top" of the page to indicate the charging of the capacitor and pointing to the "bottom" of the page to indicate the discharging of the capacitor.

[0060] For example, in order to maintain the charge balance in each capacitor C1, C2, C3, C0 of circuit 200, from input node V IN The total charge q injected into the circuit is equal to a portion of the total output charge, for example, 1 / 3. As a result, considering the ideal case where there are no dissipative components in circuit 200, the output power equals the input power, leading to an output voltage V... OUT It is a part of the input voltage, for example, V OUT =V IN / 3.

[0061] For simplicity, the following discussion focuses on the basic principles of one or more embodiments of an SCC converter circuit with a 3:1 ladder topology. However, it should be understood that this topology is purely exemplary and is by no means a limitation.

[0062] For example, any N-to-1 converter circuit (integer N greater than or equal to 2) with a conventional ladder topology can be assembled to provide twice the number of N transistors (M1, M2, M3, M4, M5, M6) and N (e.g., equal capacitance) capacitors (C1, C2, C3) to couple the first end of the i-th capacitor Ci between the i-th transistor and the (i+1)-th transistor, and the second end of the i-th capacitor Ci between the (i+2)-th transistor and the (i+3)-th transistor.

[0063] As is known to those skilled in the art, any SCC topology having any N to m voltage converter ratio (including...) Figure 2 SCC circuits with a 3:1 converter ratio can all be like the input node V IN With output node V OUT An ideal DC-DC transformer (with a series resistor R on the secondary side of the ideal transformer) OUT The model is the same, where the resistor R OUT This indicates the voltage relative to the nominal output voltage V. OUT The output voltage drop and losses due to the conduction and charging / discharging of converter 200.

[0064] like Figure 3As shown, the SCC circuit can exhibit an interlaced ladder topology obtained using an interlacing method, which includes the following steps: providing a first SCC circuit branch 200A, for example, a ladder topology having a 3:1 conversion ratio; generating at least one mirror-symmetric copy 200B of the SCC circuit 200A, for example... Figure 3 The second circuit branch 200B shown; will copy the input node V of the second circuit branch 200B of the first circuit branch 200A. IN and output node V OUT Coupled to the same node as the provided first circuit branch 200A; and using the same mirror-symmetric transistor M used to drive the "original" circuit branch 200A. 1A M 2A M 3A M 4A M 5A M 6A The control signal is the opposite of the control signal used to drive the transistor M in the second circuit branch 200B. 1B M 2B M 3B M 4B M 5B M 6B The control node.

[0065] For example, interleaving promotes the reduction of output voltage ripple by utilizing K parallel copies of branch 200A, including a corresponding set of switching transistors M1, M2, M3, M4, M5, M6, each branch being operated by control signals φ1, φ2 with relative phase shifts between them, for example, approximately 360° / K or 2π / K, where K is the number of circuit branches 200A, 200B in the converter circuit, which can conceptually be equal to any positive integer value.

[0066] It is important to note that while interleaving increases the number of electronic components in the converter circuitry, it does not automatically lead to an increase in area footprint because the size of the components in each branch can be reduced compared to a "single-branch" implementation of the converter. This is because the transistors and capacitors of the two "branches" of an interleaved converter are designed to manage half the total output power compared to a "single-branch" implementation (see, for example, [link to relevant documentation]). Figure 2 ).

[0067] like Figure 3 As shown, the second capacitor C2 is shared between the first circuit section 200A and the second circuit section 200B.

[0068] As mentioned earlier, the ladder N-to-1 circuit topology includes multiple transistors or switches and multiple capacitors, which increase with the transition order N, for example, according to Table I below:

[0069] N Number of switches Number of capacitors 2 4 1 3 6 3 4 8 5 5 10 7

[0070] The inventor has observed that, in cases such as Figure 3 In the circuit shown, the net charge from the first circuit section 200A is equal to the net charge entering the replica circuit section 200B, therefore zero net charge enters C2. Simultaneously, the second capacitor C2 functions as an indispensable bypass capacitor. For example, although the function of the second capacitor C2 is limited, its size may be suitable for manufacturing... Figure 3 The circuit shown is dominant.

[0071] like Figure 4 As shown, the alternative 3:1 SCC converter circuit topology 400 includes: configured to receive voltage level V IN (For example, from the input node V of energy source 12) IN Configured to couple to load impedance Z L (For example, the group of DC converters 16) to provide it with a regulated output voltage V OUT Output node V OUT ; and a set of reduced transistors M 1A M 2A M 3A M 4A Each transistor has a corresponding control node and a corresponding current path passing between the drain node and the source node, and this group of reduced transistors M 1A M 2A M 3A M 4A Arranged to have along the input node V IN The corresponding current path connected in series with the current line between the ground (GND).

[0072] This group of reduced transistors M 1A M 2A M 3A M 4A Includes: a first transistor M configured to receive a first control signal φ1 (e.g., from control circuit 20) at a corresponding control node. 1A and the third transistor M 3A The first transistor M 1A and the third transistor M 3A A second transistor M is configured to conduct when the corresponding current path passing through it has a first value (e.g., "high" or "1") based on the first control signal φ1 and not conduct when it has a second value (e.g., "low" or "0"); and a second transistor M is configured to receive a second control signal φ2 (e.g., from control circuit 20) at the corresponding control node. 2A and the fourth transistor M 4AThe second transistor M2 and the fourth transistor M4 are configured to turn on the corresponding current paths passing through them based on a first value (e.g., "high" or "1") of the second control signal φ2 (which is the opposite of the first signal φ1) and not turn on based on a second value (e.g., "low" or "0") of the second control signal φ2.

[0073] like Figure 4 As shown, circuit 400 further includes: coupled to the group of transistors M 1A M 2A M 3A M 4A The first capacitor C1 has a first capacitor terminal N coupled (e.g., directly) to the drain of the second transistor M2. 12 and coupled (e.g., directly) to the second capacitor terminal N between the third transistor M3 and the fourth transistor M4 34 Coupled to the group of reduced transistors M 1A M 2A M 3A M 4A The second capacitor C 2A The second capacitor C 2A It has coupling (e.g., directly) to the first transistor M 1A The first capacitor terminal S1 of the source (or drain) node and the second capacitor terminal N coupled (e.g., directly) to the drain (or source) of the second transistor M2. 12 ; and having coupling (e.g., directly) to the output node V OUT The first capacitor terminal N 23 And a filter capacitor C0 coupled to the second capacitor terminal of ground GND (e.g., directly).

[0074] For example, the first capacitor C 1A Second capacitor C 2A The filter capacitor C0 has the same capacitance, for example, C 1A =C 2A =C0=C.

[0075] like Figure 4 As shown, in the first stage, for example, when the first signal φ1 is at a first value (e.g., φ1 = "1"), both the first capacitor C1 and the output capacitor C0 are charged, causing the output voltage V to... OUT It is the input voltage V IN A portion (one-third) (e.g., V) OUT =V IN / 3). Meanwhile, due to the insertion of the first transistor M... 1A Second transistor M 2A The second capacitor C 2AIt cannot be charged, so no charge can be drawn from the input node V of circuit 400. IN Transfer to output node V OUT .

[0076] like Figure 5 As shown, applicable to Figure 1 The alternative interleaved 3:1 SCC converter of device 10 can facilitate the provision of input node V IN To output node V OUT Charge transfer.

[0077] like Figure 5 As shown, the interleaved 3:1 SCC converter circuit includes: substantially equal to Figure 4 The circuit 400 shown has a first “left” circuit branch 400A; and a second “right” circuit branch 400B, which includes a mirror-symmetric copy of the circuit arrangement in the “left” branch 400A, wherein transistor M 1B M 2B M 3B M 4B Compared to the "dual" transistor M 1A M 2A M 3A M 4A Controlled.

[0078] Specifically, in the example under consideration, transistor M in the second circuit branch 400B 1B M 2B M 3B M 4B The control node is configured to be a mirror-symmetric transistor M that drives the "original" first circuit branch 400A. 1A M 2A M 3A M 4A The control signal is the opposite of the control signal used to drive it.

[0079] like Figure 5 As shown, the first branch 400A and the second branch 400B are located in the corresponding second transistor M. 2A M 2B With the third transistor M 3A M 3B The intermediate node is coupled between them, and this node is further coupled to the output capacitor C0, which is configured to operate at a load Z coupled to it. L The output voltage Vout is provided at the point; and via the first interbranch transistor M with the control node. 5A and the current path passing between the drain node and the source node, wherein the first coupled transistor M 5A The first (e.g., source) node S 1AThe second capacitor C is coupled in the first circuit branch 400A 2A The first end S 1A In the middle, the first interbranch transistor M 5A The second (e.g., drain) node N 12B The second capacitor C is coupled in the second circuit branch 400B. 2B The first end N 12B In the middle, the first branch inter-transistor M 5A The current path is configured based on the first transistor M in the first circuit branch 400A. 1A The control signal φ1 at the control node is opposite to the control signal φ2, which is selectively turned on and off; and via the second inter-branch transistor M with the control node 5B And the current path passing between the corresponding drain node and source node, wherein the second interbranch transistor M 5B The first (e.g., drain) node S 1B The second capacitor C is coupled in the second circuit branch 400B. 2B The first end S 1B In the middle, the second coupled transistor M 5B The second (e.g., source) node N 12A The second capacitor C is coupled in the first circuit branch 400A 2A The first end N 12A In the middle, the transistor M between the second branch 5B The current path is configured based on the first transistor M in the second circuit branch 400B. 1B The control signal φ2 at the control node is opposite to the control signal φ1, which is selectively turned on and off.

[0080] like Figure 5A As shown, when the first control signal φ1 has a first value (e.g., φ1 = "1") and the second control signal φ2 has a second value (e.g., φ2 = "0"), the first capacitor C in the first branch 400A... 1A It becomes the second capacitor C in the first branch 400A. 2A and with output node V out The output capacitor C0 is connected in series with ground GND, while the first capacitor C in the second branch 400B is connected in series with ground GND. 1B It becomes the second capacitor C in the second branch 400B. 2B The second capacitor C in the second branch 400B is connected in series. 2B This then transforms into the first capacitor C in the first branch 400A. 1A Parallel connection allows current to flow from the input node V. IN It is drawn in and flows to load Z L.

[0081] like Figure 5B As shown, when the second control signal φ2 has a first value (e.g., φ2 = "1") and the first control signal φ1 has a second value (e.g., φ1 = "0"), the first capacitor C in the second branch 400B... 1B It becomes the second capacitor C in the second branch 400B. 2B and with at input node V IN With output node V OUT The output capacitor C0 is connected in series between the two capacitors, while the first capacitor C in the first branch 400A is connected in series. 1A It becomes the second capacitor C in the first branch 400A. 2A The second capacitor C in the first branch 400A is connected in series. 2A This then becomes the first capacitor C in the second branch 400B. 1B Parallel connection allows current to flow from the input node V. IN It is drawn in and flows to load Z L .

[0082] Compared to Figure 3 The arrangement shown, Figure 5 The circuit arrangement shown cancels out the bypass capacitor (e.g., Figure 3 The use of C2) in the [branch name] is reduced, and the number of transistors per branch is decreased. Specifically, Figure 5 The circuit shown facilitates a voltage conversion factor of 3:1, with each circuit branch 400A, 400B having only one pair of capacitors C. 1A C 2A Furthermore, each branch 400A and 400B has four transistors M. 1A M 2A M 3A M 4A (plus interbranch transistor M) 5A ).

[0083] For example, the first capacitor C 1A C 1B Second capacitor C 2A C 2B The filter capacitor C0 has the same capacitance, for example, C 1A =C 2A =C 1B =C 2B =C0=C.

[0084] Note that the preceding discussion of alternative SCC circuits with a 3:1 conversion ratio can be extended to any SCC circuit that actually has any integer N:1 conversion ratio, where N>=3.

[0085] The circuit illustrated herein may include: a first DC voltage level (e.g., V) configured to be coupled to a DC voltage source to receive a reference ground. IN The input node of ) (e.g., V) IN ); and a first circuit branch (e.g., 400A) and a second circuit branch (e.g., 400B) between the input node and ground. Each of the first and second circuit branches includes: a first transistor (e.g., M 1A M 1B ), second transistor (e.g., M) 2A M 2B ), third transistor (e.g., M) 3A M 3B ) and the fourth transistor (e.g., M) 4A M 4B The transistors are arranged such that the current flow paths through the first, second, third, and fourth transistors are cascaded between the input node and ground, and the output node (e.g., V) is connected in a manner that allows current to flow through them to be cascaded between the input node and ground. OUT ) is configured as a load coupled between the second and third transistors (e.g., Z) L This circuit also includes a capacitor (e.g., C) arranged in parallel with the second and third transistors to provide a second DC voltage level. 1A C 1B ).

[0086] For example: in the first circuit branch, the first transistor (e.g., M) 1A ) and the third transistor (e.g., M) 3A The control node is configured to receive a first control signal (e.g., φ1) and is configured to turn on and off based on a first value or a second value of the first control signal, and a second transistor (e.g., M) is provided. 2A ) and the fourth transistor (e.g., M) 4A The control node is configured to receive a second control signal (e.g., φ2) that is inverse of the first control signal and is configured to turn on and off based on the second control signal having a first value or a second value. Furthermore, in the second circuit branch (e.g., 400B), the first transistor (e.g., M...) 1B ) and the third transistor (e.g., M) 3B The control node is configured to receive a second control signal and is configured to turn on and off based on the second control signal having either the first or the second value described above, and the second transistor (e.g., M) has a control node ... 2B ) and the fourth transistor (e.g., M) 4BIt has a control node configured to receive a first control signal and configured to be turned on or off based on the first control signal having the first value or the second value of the first control signal.

[0087] The circuit also includes at least one inter-branch circuit block (e.g., 70; 70A, 70B), wherein the at least one inter-branch circuit block includes: a first capacitor node (e.g., S) coupled between a first transistor and a second transistor located in the first circuit branch. 1A ) and the second capacitor node (e.g., N) 12A The first capacitor between (e.g., C) 2A ); the third capacitor node (e.g., S) coupled between the first and second transistors in the second circuit branch. 1B ) and the fourth capacitor node (e.g., N) 12B The second capacitor between (e.g., C) 2B ); First interbranch transistor (e.g., M) 5A The first branch transistor has a control node configured to receive a second control signal and a current path passing between a first capacitor node in a first circuit branch and a fourth capacitor node in a second circuit branch; and a second inter-branch transistor has a control node configured to receive a first control signal and a current path passing between a third capacitor node in a second circuit branch and a second capacitor node in a first circuit branch.

[0088] like Figure 6 As shown, the core of the converter circuit includes transistors in two branches, 400A and 400B, and a "bypass" transistor M. 2A M 3A The first capacitor C 1A C 1B The circuit branches 400A and 400B are coupled to the first transistor M. 1A M 1B The first node or the second node S 1A S 1B The first capacitor C in the corresponding circuit branches 400A and 400B 1A C 1B The first end N 12A N 12B The section between them includes a stack of cascaded circuit blocks 70A and 70B, wherein the number of stacked circuit blocks determines a conversion ratio of m to 1.

[0089] like Figure 7 As shown, it is suitable for cascading to Figure 6 Circuit block 70 in the exemplary circuit includes the pair of capacitors C. 2A C 2Band a pair of interbranch transistors M 5A M 5B (See previous section on...) Figure 5 (Discussion).

[0090] For example, coupling a single circuit block 70 to Figure 6 The core circuit shown provides, for example Figure 5 The SCC circuit shown has a first conversion ratio (e.g., m = 3). Furthermore, the cascaded coupling of two circuit blocks 70A and 70B is... Figure 6 The core circuit shown provides an SCC circuit with a second conversion ratio (e.g., m = 4). Furthermore, the triplet of circuit block 70 is coupled to... Figure 6 The core circuit shown provides an SCC circuit with a third conversion ratio (e.g., m = 5). The foregoing can be repeated to couple the j+1 circuit blocks 70 with j>=0 to... Figure 6 The core circuit shown provides an SCC circuit with a conversion ratio of m = 3 + j.

[0091] For conventional solutions, such as Figure 6 The arrangement shown (in which any number of circuit blocks 70 can be cascaded in theory) can use a (maximum) voltage rating equal to the V of the branch element. OUT The sum equals 2V of the inter-branch element. out The (capacitor and switch) components provide SCC circuits with virtually any conversion ratio N:1.

[0092] The circuit illustrated herein may include a plurality of inter-branch circuit blocks (e.g., 70A, 70B) arranged in a cascaded manner between a first transistor and a second transistor in a first circuit branch and a second circuit branch. Each of the plurality of such inter-branch circuit blocks (e.g., 70 blocks) includes: a first capacitor node (e.g., S) coupled between the first transistor and the second transistor in the first circuit branch. 1A ) and the second capacitor node (e.g., N) 12A The first capacitor between (e.g., C) 2A ); the third capacitor node (e.g., S) coupled between the first and second transistors in the second circuit branch. 1B ) and the fourth capacitor node (e.g., N) 12B The second capacitor between (e.g., C) 2B ); having a control node configured to receive a second control signal and a first inter-branch transistor (e.g., M) through which a current path passes between a first capacitor node in a first circuit branch and a fourth capacitor node in a second circuit branch. 5A); and a second inter-branch transistor (e.g., M) having a control node configured to receive a first control signal and a current path passing between a third capacitor node in the second circuit branch and a second capacitor node in the first circuit branch. 5B ).

[0093] A method of operating a circuit according to the present disclosure may include: providing a first control signal (e.g., φ1) to a control node of a first transistor and a third transistor in a first branch, a corresponding first transistor and a third transistor in a second branch, and a second transistor in each inter-branch circuit block; and providing a second control signal (e.g., φ2) as an inverted version of the first signal to a control node of a second transistor and a fourth transistor in the first branch, a corresponding second transistor and a fourth transistor in the second branch, and a first inter-branch transistor in each inter-branch circuit block.

[0094] The circuit illustrated herein may include j+1 of the aforementioned inter-branch circuit blocks, where j>=0, and the second DC voltage level is an integer fraction 1 / N of the first DC voltage level, where N=3+j.

[0095] In the circuit illustrated herein, the capacitors in each of the first and second circuit branches have the same capacitance.

[0096] In the circuit illustrated herein, the first and second capacitors in at least one interbranch circuit block have the same capacitance.

[0097] Note that fair comparisons can be performed between topologies that provide the same conversion ratio.

[0098] As mentioned earlier, any SCC circuit can be modeled as an equivalent transformer circuit, which is configured to receive the input voltage on the primary side and have an output resistance R on the secondary side. OUT (f).

[0099] Based on this model, a pair of quality factors can be defined for SCC circuits, such as: Slow Switch Limit (SSL) configured to describe the characteristics of the circuit at low frequencies (mainly charge / discharge losses); and Fast Switch Limit (FSL) configured to describe the characteristics of the circuit at high frequencies (mainly conduction losses).

[0100] An equivalent resistance can be defined for each of these two parameters in a manner known to those skilled in the art, and this equivalent resistance can be expressed as:

[0101]

[0102]

[0103] Where: C i R is the capacitance value of the i-th capacitor. i It is the on-resistance of the i-th transistor, a c,i It is the vector of charge flow in the composite capacitor, a r,i It is the vector of charge flow in the synthesized transistor.

[0104] For alternative locations, the same quantity can be expressed as:

[0105]

[0106]

[0107] Where: C TOT It is the global converter capacitor C TOT G TOT It is the global converter conductance G TOT And C TOT and G TOT All are proportional to the area occupied by the SCC circuit.

[0108] Therefore, the SSL and FSI coefficients can be expressed as:

[0109]

[0110]

[0111] For example, the lower the SSL or FSL (which varies depending on the chosen circuit topology), the more R it provides. OUT The value of C TOT or G TOT The smaller.

[0112] In one or more embodiments, regardless of the technology of the electronic components (e.g., discrete or integrated), area benefits can be maximized by using the minimum absolute number of transistors and capacitors, thereby facilitating the achievement of the minimum FSL coefficient.

[0113] Table II below summarizes the performance comparison of 3 to 1 converter circuits and 4 to 1 converter circuits in various topologies (including those according to this disclosure), showing the performance improvements discussed above.

[0114] Topology SSL FSL Number of switches Number of capacitors staircase 1 7.11 12 4 (+1 BP) Figure 3 1 5.44 10 4 staircase 2.25 6.25 16 6 (+2 BP) Stacked staircases 0.56 9 16 6 (+2 BP) Dickson's cross 0.56 6.25 16 6 Figure 6 2.25 6.25 12 6

[0115] It should also be understood that the various individual implementation options illustrated in the accompanying drawings are not necessarily intended to be employed in the same combinations illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the drawings.

[0116] The claims are an integral part of the technical teachings provided herein with reference to the embodiments.

[0117] Details and embodiments may vary, even significantly, relative to what has been described by way of example only, without departing from the scope of protection. The scope of protection is defined by the appended claims.

Claims

1. A circuit comprising: A first circuit branch, coupled between the DC input node and the reference node, wherein the first circuit branch includes: The first transistor is coupled between the DC input node and the first capacitor node; A first capacitor, connected in series with the first transistor and coupled between the first capacitor node and the second capacitor node; and The second transistor is connected in series with the first capacitor and coupled between the second capacitor node and the output node; The first transistor and the second transistor are respectively gate-controlled by a first signal and a second signal that are 180° out of phase with each other; The second circuit branch is coupled between the DC input node and the reference node; The third transistor is coupled between the DC input node and the third capacitor node; A second capacitor is connected in series with the third transistor and coupled between the third capacitor node and the fourth capacitor node; and The fourth transistor is connected in series with the second capacitor and coupled between the fourth capacitor node and the output node; The third transistor and the fourth transistor are respectively gate-controlled by the second signal and the first signal; The fifth transistor, gate-controlled by the second signal and coupled between the first capacitor node and the fourth capacitor node; and The sixth transistor is gate-controlled by the first signal and coupled between the second capacitor node and the third capacitor node.

2. The circuit according to claim 1: The first circuit branch further includes: The seventh transistor is gate-controlled by the first signal and is coupled in series with the second transistor between the output node and the fifth capacitor node; as well as A third capacitor is coupled between the second capacitor node and the fifth capacitor node; as well as The second circuit branch further includes: The eighth transistor is gate-controlled by the second signal and is coupled in series with the fourth transistor between the output node and the sixth capacitor node; as well as A fourth capacitor is coupled between the fourth capacitor node and the sixth capacitor node.

3. The circuit according to claim 2: The first circuit branch further includes a ninth transistor, which is gate-controlled by the second signal and is coupled in series with the seventh transistor between the fifth capacitor node and the reference node; and The second circuit branch further includes a tenth transistor, which is gate-controlled by the first signal and is coupled in series with the eighth transistor between the sixth capacitor node and the reference node.

4. A power supply system, comprising: DC voltage supply, coupled to DC input node and reference node; A converter circuit, formed by at least one circuit according to claim 1; A control circuit, coupled to a set of converter circuits, to provide the first signal and the second signal; The output node is configured to be coupled to a corresponding load to provide a DC voltage level to the load.

5. An electronic device equipped with the power supply system according to claim 4.

6. The electronic device of claim 5, wherein the DC voltage supply is a battery, and the electronic device is a portable electronic device.

7. A circuit comprising: An input node is configured to be coupled to a DC voltage source to receive a first DC voltage level referenced to ground from the DC voltage source; A first circuit branch and a second circuit branch are located between the input node and ground, wherein each of the first circuit branch and the second circuit branch comprises: A first transistor, a second transistor, a third transistor, and a fourth transistor are arranged such that current flow paths through the first transistor, the second transistor, the third transistor, and the fourth transistor are cascaded between the input node and ground, wherein an output node between the second transistor and the third transistor is configured to couple to a load to provide a second DC voltage level to the load; and A capacitor is arranged in parallel with the second transistor and the third transistor; In the first circuit branch, the first transistor and the third transistor have control nodes configured to receive a first control signal and are configured to be turned on and off based on the first control signal having a first value or a second value of the first control signal; and the second transistor and the fourth transistor have control nodes configured to receive a second control signal that is inverse of the first control signal and are configured to be turned on and off based on the second control signal having a first value or a second value of the second control signal. In the second circuit branch, the first transistor and the third transistor have control nodes configured to receive the second control signal and are configured to be turned on and off based on the second control signal having the first value or the second value of the second control signal; and the second transistor and the fourth transistor have control nodes configured to receive the first control signal and are configured to be turned on and off based on the first control signal having the first value or the second value of the first control signal. At least one inter-branch circuit block, including: A first capacitor is coupled between a first capacitor node and a second capacitor node located between the first transistor and the second transistor in the first circuit branch. The second capacitor is coupled between the third capacitor node and the fourth capacitor node, which are located between the first transistor and the second transistor in the second circuit branch. A first inter-branch transistor has a control node configured to receive the second control signal, and a current path passing through the first inter-branch transistor between the first capacitor node in the first circuit branch and the fourth capacitor node in the second circuit branch; and The second interbranch transistor has a control node configured to receive the first control signal, and a current path passing through the second interbranch transistor between the third capacitor node in the second circuit branch and the second capacitor node in the first circuit branch.

8. The circuit of claim 7, comprising a plurality of said inter-branch circuit blocks, the plurality of said inter-branch circuit blocks being arranged in a cascaded manner between the first transistor and the second transistor in the first circuit branch and the second circuit branch.

9. The circuit of claim 7, wherein the circuit comprises a number j+1 inter-branch circuit blocks, wherein j>=0, and wherein the second DC voltage level is an integer fraction 1 / N of the first DC voltage level, wherein N=3+j.

10. The circuit of claim 7, wherein the capacitors in each of the first circuit branch and the second circuit branch have the same capacitance.

11. The circuit of claim 7, wherein the first capacitor and the second capacitor in the at least one inter-branch circuit block have the same capacitance.

12. The circuit according to claim 7, further comprising: A first control signal is provided to the control node of the first transistor and the third transistor in the first branch, the control node of the corresponding first transistor and the third transistor in the second branch, and the second transistor in each inter-branch circuit block; as well as A second control signal, as an inverted version of the first control signal, is provided to the control nodes of the second and fourth transistors in the first branch, the corresponding control nodes of the second and fourth transistors in the second branch, and the control node of the first inter-branch transistor in each inter-branch circuit block.

13. A power supply system, comprising: A DC voltage source is configured to provide a first DC voltage level referenced to ground; A set of converter circuits, including at least one circuit according to claim 7; A control circuit, coupled to the set of converter circuits, to provide control signals to the set of converter circuits; The set of converter circuits is configured to be coupled to a set of corresponding loads to provide at least one second DC voltage level to the set of corresponding loads.

14. An electronic device equipped with a power supply system according to claim 13.

15. The electronic device of claim 14, wherein the DC voltage source is a battery and the electronic device is a portable electronic device.

Images