Fractional order capacitor circuit with dc voltage bias and control method thereof

Abstract

This invention discloses a fractional-order capacitor circuit with DC voltage bias and its control method. The fractional-order capacitor circuit with DC voltage bias consists of an input capacitor C and a potential balancing inductor L. s LC low-pass filter, DC-AC converter and energy storage capacitor C d Composition. Through the energy storage capacitor C d Energy exchange between the input capacitor C and the energy storage capacitor C can maintain the energy storage capacitor C. d Under stable voltage conditions, the input port voltage and input current of the fractional-order capacitor circuit with DC voltage bias exhibit fractional-order impedance voltage-current characteristics. The fractional-order capacitor with DC voltage bias proposed in this invention has an order between 0 and 2. Without an external power supply, it can realize positive and negative resistive fractional-order capacitors with adjustable order, suitable for applications requiring flexible adjustment of the capacitor order.

Description

Technical Field

[0001] This invention relates to the field of fractional-order device technology, specifically to a fractional-order capacitor circuit with DC voltage bias and its control method. Background Technology

[0002] Capacitors are among the most commonly used energy storage devices in power electronics. In most studies, capacitors are analyzed as ideal devices, i.e., pure capacitors, also known as integer-order capacitors. However, pure capacitors do not exist in reality; they have parasitic resistance. A common equivalent model is a pure capacitor connected in series with a resistor. Therefore, fractional-order theory is used to describe the impedance characteristics of capacitors to more accurately establish their models. In practical applications, both the capacitance and resistance values ​​change with increasing temperature and over time. Misalignment of capacitor parameters can adversely affect the performance of power electronic converters. For example, in dual-capacitor active power decoupling, it can reduce the maximum power decoupling capability and introduce harmonics into the system (Z. Lin, L. He, H. Zhou, “A Second Harmonic Current Suppressing Method Based on Negative-Order Capacitor”, IEEE Transactions on Power Electronics, 37(7):8465-8475, 2022.). In midpoint clamp (NPC) or modular multilevel inverters (MMC), split capacitors are often used for voltage division to reduce DC bus voltage fluctuations in submodules (Y. Tang, F. Blaabjerg, P. Loh, C. Jin and P. Wang, “Decoupling of Fluctuating Power in Single-Phase Systems Through a Symmetrical Half-Bridge Circuit”, in IEEE Transactions on Power Electronics, vol. 30, no.4, pp.1855-1865, April). (2015, doi:10.1109 / TPEL.2014.2327134.) Capacitor parameter deviation can cause uneven voltage distribution and potentially damage devices. Replacing ordinary capacitors with adjustable fractional-order capacitors can effectively solve the problem of capacitor parameter deviation.

[0003] Currently, the methods for constructing fractional capacitors can be broadly classified into two categories: passive fractional capacitor construction methods and active fractional capacitor construction methods.

[0004] The first type of passive fractional capacitor construction method is based on the approximation theory of fractional differential operators. It decomposes the fractional capacitor with a certain order into a combination of passive components and obtains the precise values ​​of capacitor, inductor and resistor to construct the fractional capacitor. The disadvantages are that the calculation process is cumbersome, a large number of passive components are required, the accuracy of the component values ​​is required, the order can only vary between 0 and 1, and the order is not adjustable. Once the order is changed, the original circuit structure will no longer be applicable.

[0005] The second type of active fractional-order capacitor construction method utilizes a power electronic converter and ordinary capacitors to form a two-port network. By controlling the converter's output, the voltage and current characteristics of the ports are altered, thereby achieving the impedance characteristics of a fractional-order capacitor. The fractional-order capacitors constructed using this method are typically between 0 and 2 orders, and the order is adjustable. However, to achieve negative resistance characteristics, an additional DC source is usually required on the converter's input side to provide energy, reducing its practical value. If the DC bus is used directly as the energy source, the pulsating power at the fractional-order capacitor ports will be fed back to the DC side, causing harmonic pollution. Furthermore, some structures use resistors for potential balancing, adding additional losses and significantly reducing system efficiency.

[0006] In the above scenario, the capacitor voltages are all DC biased. Using this DC bias as the energy source for the fractional capacitors not only simplifies the circuit and improves practicality while achieving the impedance characteristics of the fractional capacitors, but also avoids harmonic effects on the DC bus. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a fractional capacitor circuit with DC voltage bias and its control method. The order of the unpowered fractional capacitor is between 0 and 2, and the order is flexibly adjustable. By controlling the output of the converter, positive resistive fractional capacitors and negative resistive fractional capacitors can be realized. Energy balance between the input and output sides of the converter can be achieved without adding an additional DC source, and no additional losses are introduced.

[0008] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0009] A fractional-order capacitor circuit with DC voltage bias includes: an input capacitor C and a potential balancing inductor L. s LC low-pass filter, DC-AC converter and energy storage capacitor C d The positive plate of the input capacitor C is connected to the potential balancing inductor L. s One end is connected, the negative plate is connected to the negative output terminal of the LC low-pass filter, and the potential balancing inductor L... sThe other end is connected to the positive output of the LC low-pass filter. The input port of the LC low-pass filter is connected to the output port of the DC-AC converter. The input port of the DC-AC converter is connected to the energy storage capacitor C. d The input capacitor C has a sinusoidal voltage with DC bias across its terminals, and this DC bias is achieved through a DC-AC converter for the energy storage capacitor C. d The charging process involves using a DC-biased sinusoidal voltage at the positive and negative outputs of the LC low-pass filter. The sinusoidal component of this voltage is used to control the order of the power-free fractional capacitor via a DC-AC converter. During operation, the power-free fractional capacitor circuit simultaneously stores energy in the capacitor C. d The voltage is stabilized and the sinusoidal voltage is output at the positive and negative output terminals of the LC low-pass filter, and the voltage and current at the input capacitor C port achieve the impedance characteristics of a fractional capacitor.

[0010] In a preferred embodiment: the frequency domain expression of the equivalent fractional-order capacitance impedance of the input capacitor C port is:

[0011]

[0012] In the formula, U foc (jω) and I foc (jω) are the voltage and current phasors at the input capacitor C port, respectively; ω is the operating angular frequency; C α α is the capacitance value of the fractional capacitor; α is the order and 0≤α≤2;

[0013] When α = 0, the fractional impedance is equivalent to a positive resistor; when 0 < α < 1, the fractional impedance is equivalent to a positive resistive fractional capacitor; when α = 1, the fractional impedance is equivalent to a pure capacitor; when 1 < α < 2, the fractional impedance is equivalent to a negative resistive fractional capacitor; when α = 2, the fractional impedance is equivalent to a negative resistor.

[0014] The present invention also provides a control method for the above-mentioned fractional capacitor circuit with DC voltage bias, characterized in that: the DC-AC converter adopts a dual PI hybrid control strategy;

[0015] The dual PI hybrid control strategy is described as follows: based on the desired fractional-order capacitor impedance characteristics, the reference value u of the LC low-pass filter output voltage can be calculated. f-ref By adjusting the output voltage u of the LC low-pass filter f Sampling is performed, compared with the reference voltage u f-ref The difference is input to the PI controller to obtain the modulation signal v1; according to the input and output voltage constraints of the PWM type DC-AC converter, the energy storage capacitor C can be obtained. d Voltage reference value U Cd-ref The range of values ​​for C is determined by the energy storage capacitor C.d Voltage U Cd Sampling is performed, and the reference voltage U is compared with the reference voltage. Cd-ref The difference is input to the PI controller to obtain the modulation signal v2; then, the modulation signals v1 and v2 are superimposed by an adder to obtain the modulation signal m. The modulation signal m is compared with the carrier wave to generate the corresponding PWM control for the two sets of switching transistors S of the DC-AC converter. f1 S f4 and S f2 S f3 The switching on and off of the circuit simultaneously controls the input voltage u of the LC low-pass filter. f and energy storage capacitor C d Voltage U Cd Regulation; among them, the DC-AC converter has two sets of switching transistors S during operation. f1 S f4 and S f2 S f3 Complementary conduction.

[0016] In a preferred embodiment: the LC low-pass filter output voltage reference value u f-ref The calculation formula is:

[0017]

[0018] Where L s It is the inductance value of the potential-balanced inductor, α and C α These are the order and capacitance value of the constructed fractional capacitor, respectively. C is the capacitance value of the input capacitor, and U... Cfoc and These are the amplitude and phase of the voltage across the input capacitor C, respectively.

[0019] The energy storage capacitor C d Voltage reference value U Cd-ref The formula for calculating the range of values ​​is:

[0020] U Cd-min ≥(u Ls +u Cfoc ) max

[0021] Where u Ls and u Cfoc These are the potential balance inductors L s And the voltage across the input capacitor C.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] 1) A method for constructing and controlling a fractional capacitor with DC voltage bias is proposed. The structure is simple, easy to implement, does not introduce additional losses, does not require an external power supply, and is highly practical.

[0024] 2) Without changing the circuit connection method, it is possible to realize positive resistive fractional capacitors and negative resistive fractional capacitors with orders between 0 and 2.

[0025] 3) The required components are low-cost (2 inductors, 3 capacitors, 4 switching transistors, 3 sensors) and the control is simple.

[0026] 4) The impedance characteristics of a fractional capacitor with DC voltage bias can be adjusted over a wide range within the phase plane. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a fractional capacitor circuit with DC voltage bias.

[0028] Figure 2 It is a fractional-order capacitive impedance phase plane with an order between 0 and 2;

[0029] Figure 3 It is an AC phasor relationship diagram of a fractional-order capacitor circuit with DC voltage bias;

[0030] Figure 4 This is a block diagram of a closed-loop control system for a fractional-order capacitor circuit with DC voltage bias.

[0031] Figure 5 This is a simulation result of the input voltage and input current of a fractional-order capacitor circuit with DC voltage bias in steady state.

[0032] Where C is the input capacitor C, L s - Potential balance inductor C, L f The filter inductor in an -LC low-pass filter, C f The filter capacitor in an -LC low-pass filter, S f1 -The first constituent switch of the first bridge arm of the DC-AC converter, S f2 -The second constituent switch of the first bridge arm of the DC-AC converter, S f3 -The first constituent switch of the second bridge arm of the DC-AC converter, S f4 -The second constituent switch of the second bridge arm of the DC-AC converter, C d -DC-AC converter DC-side energy storage capacitor C d ,u Cfoc -Input voltage, i Cfoc -Input current, u f - Output voltage of the low-pass filter, U cd -DC-AC converter DC-side energy storage capacitor voltage. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading this invention, any modifications of the invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.

[0034] Reference Figure 1 The positive plate of the input capacitor C is connected to the potential balancing inductor L. s One end is connected, the negative plate is connected to the negative output terminal of the LC low-pass filter, and the potential balancing inductor L... s The other end is connected to the positive output of the LC low-pass filter. The input port of the LC low-pass filter is connected to the output port of the DC-AC converter. The input port of the DC-AC converter is connected to the energy storage capacitor C. d The input capacitor C has a sinusoidal voltage with DC bias across its terminals. This DC bias can be applied to the energy storage capacitor C using a DC-AC converter. d The charging process involves using a DC-biased sinusoidal voltage at the positive and negative outputs of an LC low-pass filter. The sinusoidal component of this voltage can be used to control the order of the fractional capacitor without an external power supply via a DC-AC converter. This fractional capacitor circuit without an external power supply can simultaneously store energy in the capacitor C during operation. d The voltage is stabilized and the sinusoidal voltage is output at the positive and negative output terminals of the LC low-pass filter, and the voltage and current at the input capacitor C port achieve the impedance characteristics of a fractional capacitor.

[0035] The frequency domain expression for the equivalent fractional capacitor impedance at the input capacitor C port of the aforementioned control method for a fractional capacitor circuit with DC voltage bias is as follows:

[0036]

[0037] In the formula, U foc (jω) and I foc (jω) are the voltage and current phasors at the input capacitor C port, respectively; ω is the operating angular frequency; C α α is the capacitance value of the fractional capacitor; α is the order and 0≤α≤2;

[0038] When α = 0, the fractional-order impedance is equivalent to a positive resistor; when 0 < α < 1, the fractional-order impedance is equivalent to a positive resistive fractional-order capacitor; when α = 1, the fractional-order impedance is equivalent to a pure capacitor; when 1 < α < 2, the fractional-order impedance is equivalent to a negative resistive fractional-order capacitor; when α = 2, the fractional-order impedance is equivalent to a negative resistor. Plotting the real part of the fractional-order capacitor impedance as the abscissa and the imaginary part as the ordinate, the positions of fractional-order capacitor impedances of different orders in the phase plane can be shown, such as... Figure 2 As shown.

[0039] When the input voltage u Cfoc Input current i Cfoc When all signals are sinusoidal signals of the same frequency, the input voltage u should be... Cfoc and input current i Cfoc The impedance characteristics of a fractional capacitor result in the low-pass filter output voltage u. f It should also be a sinusoidal signal of the same frequency, and the potential-balanced inductor L s voltage u Ls For u f with u Cfoc The difference is therefore also a sinusoidal signal of the same frequency. Let u... Cfoc i Cfoc i C u f and u Ls Using phasors respectively as well as Indicate, and with The direction is the real axis direction. If the direction is the imaginary axis and a complex plane is constructed, then the phasor relationship of the above five quantities can be expressed as:

[0040]

[0041]

[0042]

[0043]

[0044]

[0045] Where, φ i φ f and φ Ls They are and Lag Angle, U Cfoc I Cfoc I C U f and U Ls They are phasors and The amplitude, jωL s It is a potential-balanced inductor L s The impedance value is the angular frequency of the sinusoidal signal mentioned above. The specific relationship on the phase plane is as follows: Figure 3 As shown.

[0046] The present invention employs the following control method:

[0047] like Figure 4The diagram shows a control block diagram for a fractional-order capacitor circuit with DC voltage bias, where the order is between 0 and 2. Based on the desired fractional-order capacitor impedance characteristics, the reference value u for the output voltage of the LC low-pass filter can be calculated. f-ref By adjusting the output voltage u of the LC low-pass filter f Sampling is performed, compared with the reference voltage u f-ref The difference is input to the PI controller to obtain the modulation signal v1; according to the input and output voltage constraints of the PWM type DC-AC converter, the energy storage capacitor C can be obtained. d Voltage reference value U Cd-ref The range of values ​​for C is determined by the energy storage capacitor C. d Voltage U Cd Sampling is performed, and the reference voltage U is compared with the reference voltage. Cd-ref The difference is input to the PI controller to obtain the modulation signal v2; then, the modulation signals v1 and v2 are superimposed by an adder to obtain the modulation signal m. The modulation signal m is compared with the carrier wave to generate the corresponding PWM control for the two sets of switching transistors S of the DC-AC converter. f1 S f4 and S f2 S f3 The switching on and off of the circuit simultaneously controls the input voltage u of the LC low-pass filter. f and energy storage capacitor C d Voltage U Cd The regulation; in which, during the operation of the DC-AC converter, the two switches of the same bridge arm conduct complementaryly.

[0048] The LC low-pass filter output voltage reference value u f-ref The calculation formula is

[0049]

[0050] Where L s It is the inductance value of the potential-balanced inductor, α and C α These are the order and capacitance value of the constructed fractional capacitor, respectively. C is the capacitance value of the input capacitor, and U... Cfoc and These are the amplitude and phase of the voltage across the input capacitor C, respectively.

[0051] The energy storage capacitor C d Voltage reference value U Cd-ref The formula for calculating the range of values ​​is:

[0052] U Cd-min ≥(u Ls +u Cfoc ) max (8)

[0053] Simulations were conducted based on the parameter selection method described above. Considering system efficiency, the design parameters of a fractional-order capacitor circuit with DC voltage bias are shown in the table below. The input voltage u... Cfoc The energy storage capacitor C is composed of a 60V / 50Hz sinusoidal voltage and a 60V DC voltage superimposed. d The voltage control is 60V, the input capacitor C is 60μF, and the inductor L in the low-pass filter is... f The capacitance is 2.5mH, and the capacitance C is... f The potential balance inductance is 4.7μF. s 1mH, switching frequency f s It is 10kHz.

[0054]

[0055]

[0056] Figure 5 (a) represents the input voltage, input current, and energy storage capacitance C when the fractional capacitor impedance is 10 ohms and the order is 0 (i.e., positive resistance). d Simulated voltage waveform. In steady state, the input current phase lags the input voltage phase by φ. i =0°, consistent with the definition of the 0th order fractional impedance.

[0057] Figure 5 (b) represents the input voltage, input current, and energy storage capacitance C when the fractional-order capacitor has an impedance of 10 ohms and an order of 0.5, i.e., a positive resistive fractional-order capacitor. d Simulated voltage waveform. In steady state, the input current phase lags the input voltage phase by φ. i = -45°, consistent with the definition of the impedance of a 0.5th order fractional capacitor.

[0058] Figure 5 (c) represents the input voltage, input current, and energy storage capacitance C when the fractional capacitor impedance is 10 ohms and the order is 1, i.e., a pure capacitor. d Simulated voltage waveform. In steady state, the input current phase lags the input voltage phase by φ. i =-90°, consistent with the definition of first-order fractional capacitor impedance.

[0059] Figure 5 (d) represents the input voltage, input current, and energy storage capacitance C when the fractional-order capacitor has an impedance of 10 ohms and an order of 1.5, i.e., a negative resistive fractional-order capacitor. d Simulated voltage waveform. In steady state, the input current phase lags the input voltage phase by φ. i = -135°, consistent with the definition of the impedance of a 1.5th order fractional capacitor.

[0060] Figure 5(e) represents the input voltage, input current, and energy storage capacitance C when the fractional capacitor impedance is 10 ohms and the order is 2, i.e., a negative resistance. d Simulated voltage waveform. In steady state, the input current phase lags the input voltage phase by φ. i =180°, consistent with the definition of the impedance of a second-order fractional capacitor.

[0061] The above is only one specific embodiment of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept shall be considered as infringing the protection scope of the present invention.

Claims

1. A fractional-order capacitor circuit with DC voltage bias, characterized in that... include: Input capacitor C, potential balancing inductor L s LC low-pass filter, DC-AC converter and energy storage capacitor C d The positive plate of the input capacitor C is connected to the potential balancing inductor L. s One end is connected, the negative plate is connected to the negative output terminal of the LC low-pass filter, and the potential balancing inductor L... s The other end is connected to the positive output of the LC low-pass filter. The input port of the LC low-pass filter is connected to the output port of the DC-AC converter. The input port of the DC-AC converter is connected to the energy storage capacitor C. d The input capacitor C has a sinusoidal voltage with DC bias across its terminals, and this DC bias is achieved through a DC-AC converter for the energy storage capacitor C. d The charging process involves using a DC-biased sinusoidal voltage at the positive and negative outputs of the LC low-pass filter. The sinusoidal component of this voltage is used to control the order of the power-free fractional capacitor via a DC-AC converter. During operation, the power-free fractional capacitor circuit simultaneously stores energy in the capacitor C. d The voltage is stabilized, and the sinusoidal voltages at the positive and negative output terminals of the LC low-pass filter are output, enabling the voltage and current at the input capacitor C port to achieve the impedance characteristics of a fractional capacitor. The frequency domain expression of the equivalent fractional capacitor impedance at the input capacitor C port is: In the formula, U foc (jω) and I foc (jω) are the voltage and current phasors at the input capacitor C port, respectively; ω is the operating angular frequency; C α It is the capacitance value of a fractional capacitor; α is the order and 0 ≤ α ≤ 2; When α = 0, the fractional impedance is equivalent to a positive resistor; when 0 < α < 1, the fractional impedance is equivalent to a positive resistive fractional capacitor; when α = 1, the fractional impedance is equivalent to a pure capacitor; when 1 < α < 2, the fractional impedance is equivalent to a negative resistive fractional capacitor; when α = 2, the fractional impedance is equivalent to a negative resistor. The control method for the fractional capacitor circuit with DC voltage bias described above: The DC-AC converter adopts a dual PI hybrid control strategy; The dual PI hybrid control strategy is described as follows: based on the desired fractional-order capacitor impedance characteristics, the reference value u of the LC low-pass filter output voltage can be calculated. f-ref By adjusting the output voltage u of the LC low-pass filter f Sampling is performed, compared with the reference voltage u f-ref The difference is input to the PI controller to obtain the modulation signal v1; according to the input and output voltage constraints of the PWM type DC-AC converter, the energy storage capacitor C can be obtained. d Voltage reference value U Cd-ref The range of values ​​for C is determined by the energy storage capacitor C. d Voltage U Cd Sampling is performed, and the reference voltage U is compared with the reference voltage. Cd-ref The difference is input to the PI controller to obtain the modulation signal v2; then, the modulation signals v1 and v2 are superimposed by an adder to obtain the modulation signal m. The modulation signal m is compared with the carrier wave to generate the corresponding PWM control for the two sets of switching transistors S of the DC-AC converter. f1 S f4 and S f2 S f3 The switching on and off of the circuit simultaneously controls the input voltage u of the LC low-pass filter. f and energy storage capacitor C d Voltage U Cd Regulation; among them, the DC-AC converter has two sets of switching transistors S during operation. f1 S f4 and S f2 S f3 Complementary conduction.

2. The fractional-order capacitor circuit with DC voltage bias according to claim 1, characterized in that: The LC low-pass filter output voltage reference value u f-ref The calculation formula is: Where L s It is the inductance value of the potential-balanced inductor, α and C α These are the order and capacitance value of the constructed fractional capacitor, respectively. C is the capacitance value of the input capacitor, and U... Cfoc and These are the amplitude and phase of the voltage across the input capacitor C, respectively. The energy storage capacitor C d Voltage reference value U Cd-ref The formula for calculating the range of values ​​is: IN Cd-min ≥(in Ls +U Cfoc ) max Where u Ls and U Cfoc These are the potential balance inductors L s And the voltage across the input capacitor C.

Images