Low power finite impulse response filter

Abstract

Embodiments of the present disclosure relate to low power finite impulse response filters. A finite impulse response (FIR) filter includes a plurality of registers. A data input terminal of each register is directly coupled to an input of the FIR filter. On each clock cycle of a filter clock signal, a new data value is transferred to each register. On each clock cycle, only one register processes the data value. A ring counter is coupled to the registers and determines which register processes the data value on each clock cycle.

Description

Technical Field

[0001] This disclosure generally relates to digital filters. More specifically, this disclosure relates to finite impulse response filters. Background Technology

[0002] Many integrated circuits include signal processing circuitry. Signal processing circuitry can include various processing blocks for processing analog and digital signals. Various filter blocks can be used to filter analog and digital signals.

[0003] There are many types of digital filters that can be used as part of a digital signal processor to filter digital signals. One example of a digital filter is the Finite Impulse Response (FIR) filter. Full-throughput FIR filters are often a major component of the signal processing chain. FIR filters can consume a significant amount of power. In some cases, FIR filters can account for more than 50% of the total power consumption of a digital signal processing filter chain. This is partly due to the fact that many FIR filters use power-intensive convolution operations.

[0004] While reducing the power consumption of FIR filters may be desirable, such reductions typically come at the cost of performance. It has proven difficult to achieve low-power FIR filters with high performance. Summary of the Invention

[0005] Embodiments of this disclosure provide an FIR filter that consumes very little power while providing very high performance. The FIR filter receives a new data value in each cycle of the filter clock. Each of the multiple input registers receives each data value simultaneously. However, only one input register processes the data value per clock cycle. This arrangement, coupled with a compatible arrangement with downstream circuitry, provides a very high-performance and low-power FIR filter.

[0006] The FIR filter may include a ring counter with multiple flip-flops coupled in a ring configuration. The output of each flip-flop is provided to the data input of the next flip-flop and the clock input terminal of the corresponding input register. A single pulse passes through the ring counter such that, in each clock cycle, only one flip-flop has its output high. The input register coupled to the flip-flop with the high output processes the data value in any given clock cycle. This not only provides the aforementioned benefit of ensuring that only one input register processes the data value in each clock cycle, but also significantly simplifies and reduces the power consumption associated with distributing the clock signal to the input registers.

[0007] An FIR filter may include multiple convolution operators, each coupled to a corresponding input register. The FIR filter may also include multiple multiplexers coupled to the convolution operators. Each multiplexer provides a different convolution constant to its corresponding convolution operator in each clock cycle. The FIR filter includes an adder that sums the outputs of all the convolution operators.

[0008] As will be explained in more detail below, various configurations of FIR filters can be implemented based on the principles of this disclosure. Attached Figure Description

[0009] Figure 1 This is a block diagram of an FIR filter according to some embodiments.

[0010] Figure 2 This is a schematic diagram of an FIR filter according to some embodiments.

[0011] Figure 3 These are signals associated with an FIR filter according to some embodiments.

[0012] Figure 4 This is a schematic diagram of a convolution operator for an FIR filter according to some embodiments.

[0013] Figure 5 This is a flowchart of a method for operating an FIR filter according to some embodiments. Detailed Implementation

[0014] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that embodiments can be practiced without one or more of these specific details or by utilizing other methods, components, materials, etc. In other instances, known structures, circuits, and processes associated with finite impulse response filters have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0015] Unless the context otherwise requires, throughout the specification and appended claims, the word “comprising” and its variations, such as “including” and “containing”, shall be interpreted as having an open, inclusive meaning, i.e., “including but not limited to”. Furthermore, the terms “first,” “second,” and similar sequence indicators shall be interpreted as interchangeable unless the context clearly specifies otherwise.

[0016] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0017] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural references unless otherwise clearly indicated. It should also be noted that the term “or” is generally used in its broadest sense, meaning “and / or,” unless otherwise clearly indicated.

[0018] Figure 1 This is a block diagram of an FIR filter 100 according to some embodiments. As will be described in more detail below, the FIR filter 100 utilizes a parallel input data distribution and a single-pulse clock distribution to consume relatively little power while providing very high performance. Various arrangements of the circuit components can be utilized based on the principles of this disclosure without departing from the scope of this disclosure.

[0019] FIR filter 100 includes filter input 102. Filter input 102 receives a series of data values. FIR filter 100 is managed by a filter clock signal. Filter input 102 receives a new data value in each cycle of the clock signal. The data values ​​can be multi-bit data values. For example, each data value can be an eight-bit data value, a 12-bit data value, a 16-bit data value, etc.

[0020] The FIR filter 100 includes multiple registers 104. Each register 104 has a data input, a data output, and a clock input. Each register 104 acts as a temporary memory for storing data values ​​received from the filter input 102. Each register is configured to receive a data value at its data input terminal and output the data value at its data output terminal.

[0021] The data input terminals of each register 104 are coupled to the filter input 102. The data input terminals of registers 104 are connected in parallel with each other. Data values ​​from the filter input 102 are provided to the data input terminals of each register 104 substantially simultaneously. The benefits of this configuration will become more apparent below.

[0022] Each register 104 may include multiple flip-flops. If the data value is a 16-bit data value, then each register may include 16 flip-flops. Each flip-flop receives a specific bit of the data value and outputs that bit at its data output terminal. The data output terminals of the registers include multiple individual bit outputs, which together constitute the data output terminals. Therefore, the data output terminals of register 104 include the data output terminals of the multiple flip-flops that constitute register 104.

[0023] Traditional FIR filter designs include multiple registers coupled together in a shift register configuration. In this shift register configuration, the data input terminal of the first register receives the input data value directly from the filter input. Following the first register, the data input terminals of each register in the register chain are directly coupled to the data output terminals of the register immediately preceding it in the chain. On the first clock cycle, the first register receives the first data value. On the second clock cycle, the first register first receives the second data value and the value passed from the first register to the second register. On the third clock cycle, the first register receives the third data value, the second data value is passed to the second register, and the first data value is passed to the third register. Thus, each register processes a data value on each clock cycle. In an example where each register includes 16 flip-flops, all 16 flip-flops of all registers process the data value on each clock cycle. This results in significant power consumption.

[0024] Furthermore, in the traditional design of FIR filters, in order to ensure that the clock terminals of all flip-flops in all registers meet their timing windows, a complex clock tree is designed to ensure that the rising edges of the clock signal arrive at each clock terminal of each flip-flop in each register essentially simultaneously. This consumes a large amount of circuit area and a significant amount of power.

[0025] Back Figure 1 The FIR filter 100 includes a ring counter 112. The ring counter 112 acts as a clock signal for the register 104. The ring counter 112 includes multiple outputs. Each output of the ring counter 112 is coupled to a clock input terminal of the corresponding register 104. The ring counter 112 receives the filter clock signal but does not supply the filter clock signal to the register 104. Instead, on each cycle of the filter clock signal, only one output of the ring counter is high. The ring counter 112 operates as if a single pulse were traveling around the ring. On the first cycle of the filter clock, the pulse is at the first output of the ring counter 112, while all other outputs of the ring counter 112 are low. On the second cycle of the filter clock, the pulse is at the second output of the ring counter 112, while all other outputs of the ring counter 112 are low, and so on, as the pulse travels through all the outputs of the ring counter 112.

[0026] If there are n registers 104 and n outputs of the ring counter 112, each output of the ring counter 112 goes high once every n cycles of the filter clock. On the first cycle of the filter clock, a first data value is received at each of the data input terminals of register 104. The pulse is at the first output of the ring counter 112, while all other outputs of the ring counter 112 are low. This means that only the clock input terminal of the first register 104 goes high. Therefore, only the first register 104 passes the first data value to its data output terminal. On the second cycle of the filter clock, a second data value is received at each of the data input terminals of register 104. The pulse is now at the second output of the ring counter 112, while all other outputs of the ring counter 112 are low. This means that only the clock input terminal of the second register 104 goes high. Therefore, only the second register 104 passes the second data value to its data output terminal. This continues, and eventually all n registers 104 hold their respective data values. The pulse eventually returns to the first output of the ring counter 112, and receives the (n+1)th data value, passing it to the data output terminal of the first register, thereby replacing the first data value. In this way, each register 104 processes a data value once every n clock cycles. Each data value is processed by only one register 104.

[0027] In some embodiments, the ring counter 112 includes a plurality of flip-flops linked in a circular chain. The data input terminal of each flip-flop is coupled to the data output terminal of the next flip-flop in the chain. The data input terminal of the first flip-flop is coupled to the data output terminal of the last flip-flop. The data output terminal of each flip-flop corresponds to a corresponding output of the ring counter 112. Therefore, the data output terminal of each flip-flop is coupled to a corresponding register 104. The clock terminal of each flip-flop receives a filtered clock signal. The first flip-flop in the chain has a reset condition that causes its output to go high upon reset. This is a reset start pulse. None of the other flip-flops in the chain of flip-flops in the ring counter 112 has this reset condition.

[0028] When the first flip-flop receives a reset signal, its data output goes high. This corresponds to the first output of the ring counter 112 going high. The clock input terminal of the first register 104 also goes high, and the first register 104 processes the data value as previously described. Because the output of the first flip-flop goes high during the first clock cycle, the input of the second flip-flop is high during the first clock cycle. At the rising edge of the second clock cycle, the high value is passed from the input of the second flip-flop to its output. At the rising edge of the third clock cycle, the high value is passed from the input of the third flip-flop to its output. This continues indefinitely around the ring of flip-flops. The output of each flip-flop goes high once every n clock cycles. Other configurations of the ring counter 112 may be used without departing from the scope of this disclosure. Furthermore, other circuitry may be used to make the clock input terminal of only one register in register 104 go high in each clock cycle without departing from the scope of this disclosure.

[0029] The FIR filter 100 includes a convolution operator 106. A corresponding convolution operator 106 exists for each register 104. Each convolution operator 106 includes a data input terminal, a data output terminal, and one or more convolution coefficient input terminals. The data input terminal of each convolution operator 106 is coupled to the data output terminal of the corresponding register 104.

[0030] When the first convolution unit receives a first data value from the first register 104, the first convolution unit 106 performs a convolution operation on the first data value. The first convolution unit 106 performs the convolution operation on the first data value by convolving it with one or more convolution coefficients. The first convolution unit 106 outputs the convolution data value at its data output terminal. Each convolution unit in the convolution unit 106 performs a convolution operation on the data value at the data output terminal of the corresponding register 104.

[0031] A convolution operation may include adding an addition parameter to a data value. A convolution operation may then include multiplying the sum by the convolution or multiplication parameter.

[0032] In a traditional FIR filter, each convolution operator has one or more fixed convolution coefficients. Because each data value passes through each register of a traditional FIR filter, each data value ultimately passes through each convolution operator and is convolved with the individual convolution coefficients of each convolution operator.

[0033] However, in the FIR filter 100, each data value passes through only one register in register 104 and therefore only one convolution operator in convolution operator 106. To ensure that each data value is convolved using each of the multiple convolution operators, the convolution operator 106 of the FIR filter 100 does not receive static convolution coefficients. Instead, the convolution coefficients of each convolution operator 106 change every clock cycle. In the example with n registers 104 and n convolution operators 106, there can also be n different convolution coefficient values. Because the first data value is held at the output of the first register 104 for n clock cycles, if the first convolution operator 106 receives different convolution coefficients every clock cycle, then the first convolution operator 106 convolves the first data value with each of the n convolution coefficients.

[0034] The FIR filter 100 includes multiple multiplexers 114 to ensure that each data value is convolved with each convolution coefficient. Each multiplexer 114 has n inputs, one output, and a control terminal. Each multiplexer 114 receives different convolution coefficients at its inputs. The output of each multiplexer 114 is coupled to the convolution coefficient input terminal of a corresponding convolution operator 106. The control terminal of each multiplexer 114 receives a signal that causes the output of the multiplexer 114 to switch to the next input each clock cycle, such that each input is passed to the output once every n clock cycles. In this way, each convolution operator 106 receives each convolution coefficient every n clock cycles. In some cases, there may be fewer than n convolution coefficients, such as n / 2 convolution coefficients. The multiplexers 114 can be operated appropriately to ensure that each convolution coefficient is passed to each convolution operator at least once every n clock cycles. Other configurations of the convolution operators 106a and multiplexers 114 can be utilized without departing from the scope of this disclosure.

[0035] The FIR filter 100 includes an adder 108. The adder 108 includes n input terminals and one output terminal. Each input terminal is coupled to the data output terminal of a corresponding convolution operator 106. Therefore, the adder 108 receives all convolutional data values ​​from the convolution operator 106. The adder 108 adds the convolutional data values ​​together and provides a sum data value 108 at its data output terminal. Although in Figure 1 The diagram shows a single adder 108, but in reality, there can be multiple adders 108 that operate together to sum the outputs of all convolution operators 106.

[0036] FIR filter 100 includes filter output 110. Filter output 110 receives the sum data value from adder 108 and outputs the sum data value as the final output of FIR filter 100.

[0037] Figure 2 This is a schematic diagram of an FIR filter 100 according to some embodiments. The FIR filter 100 includes a data input terminal IN. The data input terminal IN receives a series of data values. A new data value is received at each cycle of the filter clock received by the FIR filter 100.

[0038] The filter clock can be a high-frequency filter clock. The frequency of the filter clock can be between 1 GHz and 5 GHz. Therefore, the FIR filter 100 can operate at high frequencies while maintaining relatively low power consumption. The filter clock can have other frequency ranges without departing from the scope of this disclosure.

[0039] The FIR filter 100 includes six registers 104a-f. Although Figure 2 An example is shown where there are six registers 104a-f, but Figure 2 The circuit can be generalized to n registers. Therefore, in Figure 2 In the example, n = 6, but other values ​​of n may be used without departing from the scope of this disclosure.

[0040] The data input terminals of each register 104a-f are coupled to the filter input IN. Therefore, each register 104a-f receives each data value substantially simultaneously at its data input terminals.

[0041] The FIR filter 100 includes a ring counter 112. The ring counter 112 includes six flip-flops 116a-f. Each flip-flop 116a-f includes a data input terminal, a data output terminal, and a clock input terminal. The flip-flops 116a-f are coupled in a ring configuration. The data output terminal of flip-flop 116a is coupled to the data input terminal of flip-flop 116b. The data output terminal of flip-flop 116b is coupled to the data input terminal of flip-flop 116c. The data output terminal of flip-flop 116c is coupled to the data input terminal of flip-flop 116d. The data output terminal of flip-flop 116d is coupled to the data input terminal of flip-flop 116e. The data output terminal of flip-flop 116e is coupled to the data input terminal of flip-flop 116f. The data output terminal of flip-flop 116f is coupled to the data input terminal of flip-flop 116a.

[0042] In one example, flip-flop 116a has a different set / reset condition than the other flip-flops 116b-f. Once a reset signal is received at the set / reset terminal (not shown), the output of flip-flop 116a goes high on the rising edge of the first clock cycle, even if the data input terminal is initially low. This corresponds to the start of a pulse that forms a complete circuit around the ring oscillator 112 every six clock cycles. The set / reset terminals of flip-flops 116a-f are located at... Figure 2Not shown in the image. Although Figure 2 Although not shown in the diagram, the clock input terminals of flip-flops 116a-f all receive the filter clock signal.

[0043] At the rising edge of the second clock cycle, the data output terminal of flip-flop 116b goes high because the data input terminal of flip-flop 116a is high at the rising edge of the second clock cycle. The data output terminal of flip-flop 116a goes low at the rising edge of the second clock cycle. The data output terminals of all other flip-flops are low. At the rising edge of the third clock cycle, the data output terminal of flip-flop 116c goes high. At the rising edge of the fourth clock cycle, the data output terminal of flip-flop 116d goes high. At the rising edge of the fifth clock cycle, the data output terminal of flip-flop 116e goes high. At the rising edge of the sixth clock cycle, the data output terminal of flip-flop 116f goes high. At the rising edge of the seventh clock cycle, the data output terminal of flip-flop 116a goes high again, and this cycle repeats indefinitely as the pulse travels around the ring counter 112.

[0044] The data output terminal of flip-flop 116a is coupled to the clock input terminal of register 104a. The data output terminal of flip-flop 116b is coupled to the clock input terminal of register 104b. The data output terminal of flip-flop 116c is coupled to the clock input terminal of register 104c. The data output terminal of flip-flop 116d is coupled to the clock input terminal of register 104d. The data output terminal of flip-flop 116e is coupled to the clock input terminal of register 104e. The data output terminal of flip-flop 116f is coupled to the clock input terminal of register 104f.

[0045] In the first clock cycle, a first data value is received at IN. In the first clock cycle, the clock input terminal of register 104a goes high. The first data value is transferred from the data input terminal of register 104a to the data output terminal of register 104a. In the second clock cycle, the clock input terminal of register 104b goes high and IN receives a second data value. The second data value is transferred from the filter input IN to the data output terminal of the second register 104b. In the third clock cycle, the clock input terminal of register 104c goes high and IN receives a third data value. The third data value is transferred from the filter input IN to the data output terminal of the third register 104c. In the fourth clock cycle, the clock input terminal of register 104d goes high and IN receives a fourth data value. The fourth data value is transferred from the filter input IN to the data output terminal of register 104d. In the fifth clock cycle, the clock input terminal of register 104e goes high and IN receives a fifth data value. The fifth data value is transferred from the filter input IN to the data output terminal of register 104d. In the sixth clock cycle, the clock input terminal of register 104f goes high and IN receives the sixth data value. The sixth data value is passed from the filter input IN to the data output terminal of register 104f. In the seventh clock cycle, the clock input terminal of register 104a goes high and IN receives the seventh data value. The seventh data value is passed to the data output terminal of register 104a. This continues within one cycle because each register 104a-f processes the data value once every six clock cycles. The data output terminal of each register 104a-f holds the data value for six clock cycles.

[0046] The FIR filter 100 includes six convolution operators 106a-f. Each convolution operator 106a-f includes a data input terminal, a data output terminal, and a convolution coefficient input terminal. The data input terminal of convolution operator 106a is coupled to the data output terminal of register 104a. The data input terminal of convolution operator 106b is coupled to the data output terminal of register 104b. The data input terminal of convolution operator 106c is coupled to the data output terminal of register 104c. The data input terminal of convolution operator 106d is coupled to the data output terminal of register 104d. The data input terminal of convolution operator 106e is coupled to the data output terminal of register 104e. The data input terminal of convolution operator 106f is coupled to the data output terminal of register 104f.

[0047] FIR filter 100 includes six multiplexers 114a-f. Each multiplexer 114a-f includes six input terminals and one output terminal. Each of the six input terminals of each multiplexer 114a-f receives one of the six convolution coefficients C1-C6. Each multiplexer 114a-f receives the six convolution coefficients C1-C6 in a different order. The output of multiplexer 114a is coupled to the convolution coefficient input terminal of convolution operator 106a. The output of multiplexer 114b is coupled to the convolution coefficient input terminal of convolution operator 106b. The output of multiplexer 114c is coupled to the convolution coefficient input terminal of convolution operator 106c. The output of multiplexer 114d is coupled to the convolution coefficient input terminal of convolution operator 106d. The output of multiplexer 114e is coupled to the convolution coefficient input terminal of convolution operator 106e. The output of multiplexer 114f is coupled to the convolution coefficient input terminal of convolution operator 106f.

[0048] In each clock cycle, multiplexers 114a-f couple different inputs to their outputs, such that every six clock cycles, each convolution coefficient C1-C6 is provided to each convolution operator 106a-f, albeit in a different order. For example, in the first clock cycle, multiplexer 114a outputs convolution coefficient C1, while multiplexer 114b outputs convolution coefficient C2. In the second clock cycle, multiplexer 114a outputs convolution coefficient C2. In the third clock cycle, multiplexer 114a outputs the third convolution coefficient C3. In the fourth clock cycle, multiplexer 114a outputs the fourth convolution coefficient C4. In the fifth clock cycle, multiplexer 114a outputs the fifth convolution coefficient C5. In the sixth clock cycle, multiplexer 114a outputs the sixth convolution coefficient C6. Convolution coefficients C1-C6 can correspond to various scalar values ​​used for convolution operations.

[0049] The convolution unit 106a-f outputs a convolutional data value that corresponds to the data value output from register 104a-f, but is convolved with convolution coefficients C1-C6. The convolutional data value changes each clock cycle as the output of multiplexer 114a-f changes.

[0050] The FIR filter 100 includes an adder 108. The adder 108 sums the convolutional data values ​​in each clock cycle. The output of the adder 108 is the output of the FIR filter 100.

[0051] Figure 3 This illustrates the relationship according to some embodiments. Figure 2Multiple graphs of the signal associated with the FIR filter 100 are shown. Graph 300 corresponds to the filter clock signal. Graph 302 corresponds to the data output terminal of flip-flop 116a. Graph 304 corresponds to the data output terminal of flip-flop 116b. Graph 306 corresponds to the data output terminal of flip-flop 116c. Graph 308 corresponds to the data output terminal of flip-flop 116d. Graph 310 corresponds to the data output terminal of flip-flop 116e. Graph 312 corresponds to the data output terminal of flip-flop 116f. Graphs 302 to 312 similarly correspond to the clock input terminals of registers 104a-f.

[0052] At time t1, a ring counter pulse is initiated at the rising edge of the first clock cycle. This corresponds to the data output terminal of flip-flop 116a going high. At time t2, at the rising edge of the second clock signal, the data output terminal of flip-flop 116a goes low and the data output terminal of flip-flop 116b goes high. At time t3, at the rising edge of the third clock cycle, the data output terminal of flip-flop 116b goes low and the data output terminal of flip-flop 116c goes high. At time t4, at the rising edge of the fourth clock cycle, the data output terminal of flip-flop 116c goes low and the data output terminal of flip-flop 116d goes high. At time t5, at the rising edge of the fifth clock cycle, the data output terminal of flip-flop 116d goes low and the data output terminal of flip-flop 116e goes high. At time t6, at the rising edge of the sixth clock cycle, the data output terminal of flip-flop 116e goes low and the data output terminal of flip-flop 116f goes high. At the rising edge of the seventh clock cycle, the data output terminal of flip-flop 116f goes low and the data output terminal of flip-flop 116a goes high.

[0053] The output signal of each flip-flop of the ring counter 112 can be considered as the corresponding register clock signal. The corresponding register clock signal has a period of n*fc, where fc is the frequency of the filter clock. The corresponding register clock signals differ from conventional clock signals in that each is high only for 1 / n of each register clock cycle, instead of being high for half of each register clock cycle. Signals 302 and 312 correspond to the register clock signals.

[0054] Figure 4This is a schematic diagram of a convolution operator 106a according to some embodiments. The convolution operator 106a includes an adder 120 and a multiplier 122. The adder 120 receives data values ​​from the data output terminal of register 104a. The adder 120 also receives the output of multiplexer 124. Multiplexer 124 receives data values ​​from the data output terminals of other registers 104 and outputs these data values ​​to adder 120, changing the selected input in each clock cycle. Adder 120 adds the data values ​​from register 104a to the data values ​​from multiplexer 124 and passes the sum to multiplier 122. Multiplier 122 multiplies the sum from adder 120 by convolution coefficients C1-C6 provided by multiplexer 114a. The output of multiplier 122 corresponds to the output of convolution operator 106a. Each convolution operator in convolution operators 106a-f can be configured to... Figure 4 The convolutional operator 106a is similar. There are corresponding multiplexers 124 coupled to each convolutional operator 106a-f.

[0055] Figure 5 This is a flowchart of a method 500 for operating an FIR filter according to some embodiments. Method 500 can utilize information regarding... Figure 1-4 The circuitry, system, components, and processes are described. At 502, method 500 includes providing data values ​​from the filter input of a finite impulse response filter to a data input terminal of each of a plurality of registers. At 504, method 500 includes allowing pulses to pass through a ring counter that includes a plurality of flip-flops coupled to the registers in a ring configuration. At 506, method 500 includes using the ring counter to control the registers based on pulses.

[0056] In some embodiments, the FIR filter includes a filter input and multiple registers, each register having a data input, a data output, and a clock input terminal coupled to the filter input. The FIR filter includes a ring counter coupled to the clock input terminal of the register.

[0057] In some embodiments, the FIR filter includes n registers, each register including an input, an output, and a clock input. The FIR filter includes a ring counter comprising n flip-flops coupled in a ring configuration, each flip-flop coupled to the clock input of a corresponding register.

[0058] In some embodiments, a method includes passing data values ​​from the filter input of a finite impulse response filter to the data input terminal of each of a plurality of registers. The method includes passing a pulse through a ring counter coupled to the register and including a plurality of flip-flops coupled in a ring configuration, and using the ring counter to control the clock input terminal of the register based on the pulse.

[0059] The various embodiments described above can be combined to provide further embodiments. Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents granted by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A finite impulse response (FIR) filter, comprising: Filter input; Multiple registers, each register having: Data input terminals; Data output terminals; as well as Clock input terminal; as well as A ring counter, coupled to the clock input terminal of the register. Each register simultaneously receives the corresponding data value from the filter input, but only one register processes its received data value and passes it to the corresponding data output terminal in each clock cycle.

2. The FIR filter according to claim 1 further includes a plurality of convolution operators, each convolution operator being coupled to the data output terminal of a corresponding register.

3. The FIR filter according to claim 2 further includes a plurality of first multiplexers, each first multiplexer being coupled to a corresponding convolution operator.

4. The FIR filter according to claim 3, wherein, Each first multiplexer receives multiple convolution coefficients and outputs one of the convolution coefficients to the corresponding convolution operator.

5. The FIR filter according to claim 2 further includes a plurality of second multiplexers, each second multiplexer being coupled to a corresponding convolution operator.

6. The FIR filter according to claim 5, wherein, Each second multiplexer receives output signals from a plurality of the registers and outputs one of the output signals to the convolution operator.

7. The FIR filter according to claim 2 further includes an adder coupled to the convolution operator.

8. The FIR filter according to claim 7, wherein, The adder is configured to sum the output signal of the convolution operator.

9. The FIR filter according to claim 1, wherein, The ring counter includes multiple flip-flops coupled in a ring configuration, each flip-flop having an output coupled to a clock input terminal of a corresponding register and the input of the next flip-flop in the ring configuration.

10. A finite impulse response (FIR) filter, comprising: There are n registers, each register including: Data input terminals; Data output terminals; and Clock input terminal; and A ring counter comprising n flip-flops coupled in a ring configuration, each flip-flop being coupled to the clock input of a corresponding register. Each register simultaneously receives the corresponding data value, but only one register processes the received data value and transmits it to the corresponding data output terminal in each clock cycle.

11. The FIR filter of claim 10, further comprising a filter input coupled to the data input terminal of each register.

12. The FIR filter according to claim 11, wherein, The filter input is configured to pass input data values ​​to the data input terminal of each register according to a filter clock signal having a first frequency.

13. The FIR filter according to claim 12, wherein, Each flip-flop outputs a corresponding register clock signal with a second frequency to the clock input terminal of the corresponding register.

14. The FIR filter according to claim 13, wherein, The second frequency is approximately equal to the first frequency divided by n.

15. The FIR filter according to claim 14, wherein, Each register clock signal in the register clock signals is out of phase with each other.

16. The FIR filter according to claim 14, wherein, In each cycle of the filter clock, only one register clock signal is high.

17. A method for operating a finite impulse response (FIR) filter, comprising: The data values ​​from the filter input of the FIR filter are simultaneously passed to the data input terminals of each of the multiple registers; The pulse is passed through a ring counter, which is coupled to the register and includes multiple flip-flops coupled in a ring configuration; Based on the pulse, the clock input terminal of the register is controlled using the ring counter; as well as Only one register processes the received data value in each clock cycle and passes it to the corresponding data output terminal.

18. The method of claim 17, further comprising providing a corresponding data value from the filter input at each clock cycle of the filter clock signal.

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