1.5 frequency divider based on phase interpolator

Abstract

This application relates to the field of integrated circuit technology and discloses a 1.5 divider based on a phase interpolator with an output duty cycle of 50%, comprising: a 1.5 divider, a phase interpolator, and a duty cycle adjustment module connected in sequence. The 1.5 divider outputs a pair of divided signals with duty cycles of 1 / 3 and 2 / 3 respectively, and a division ratio of 1.5, based on a pair of positive and negative clock signals. The average duty cycle of the pair of divided signals is 1 / 2. The phase interpolator slows down the signal edges of the pair of divided signals and outputs an interpolated signal to the duty cycle adjustment module. The phase of the interpolated signal is the average phase of the pair of divided signals. The duty cycle adjustment module finely adjusts the duty cycle of the interpolated signal to 1 / 2.

Description

Technical Field

[0001] This invention generally relates to the field of integrated circuit technology, and particularly to a 1.5 frequency divider based on a phase interpolator with an output duty cycle of 50%. Background Technology

[0002] Assuming the frequency synthesizer needs to generate a signal with twice the frequency range, a voltage-controlled oscillator (VCO) with twice the tuning frequency range is required. However, achieving a VCO with twice the tuning frequency range is generally difficult because there is often a trade-off between the tuning range and the noise of the VCO. In practical design, two VCOs are usually needed to achieve twice the tuning frequency coverage, but this significantly increases the circuit design cycle and the area occupied by the circuit. If a divider with a 50% output duty cycle (1 / 2) were available, the tuning range of the VCO could be reduced by one-third, allowing the design goal to be met with a single resonant cavity. Currently, there are several methods to implement a divider with a 50% (1 / 2) output duty cycle:

[0003] 1. The signal is divided into three parts by logic circuitry, and then doubled using a phase-locked loop (PLL) structure based on a ring oscillator, ultimately achieving a 1.5 frequency division. However, ring oscillators have poor noise performance and are unsuitable for high-speed, high-precision applications. Furthermore, the PLL-based approach significantly increases system design complexity by considering the ring oscillator's tuning range and the PLL's stability.

[0004] 2. By dividing the signal into three parts using logic circuits and then using subharmonic injection locking to achieve a 2-fold division, a 1.5-fold division can also be achieved. However, this approach requires an additional resonant cavity, significantly increasing the loop area. Furthermore, the injection locking technique introduces a large spur, which greatly worsens the fixed jitter of the output signal. Additionally, it is difficult to achieve a 50% duty cycle output signal.

[0005] 3. By mixing the input clock signal with a signal at one-third of the input clock frequency, and then low-pass filtering the mixed signal, a signal at two-thirds of the input clock frequency can be obtained. However, the 1.5 divider based on the mixer structure will have redundant spurious noise that is difficult to filter out, which greatly worsens the fixed jitter of the output signal. At the same time, it is difficult to achieve a 50% duty cycle output signal. These disadvantages limit the widespread application of the solution. Summary of the Invention

[0006] The purpose of this invention is to provide a 1.5 frequency divider based on a phase interpolator to reduce the tuning range of a voltage-controlled oscillator.

[0007] This application discloses a 1.5 divider based on a phase interpolator with an output duty cycle of 50%, comprising: a 1.5 divider and a phase interpolator connected in sequence; wherein,

[0008] The 1.5 divider outputs a pair of frequency divider signals with duty cycles of 1 / 3 and 2 / 3 respectively and a division ratio of 1.5 based on a pair of positive and negative clock signals, and the average duty cycle of the pair of frequency divider signals is 1 / 2;

[0009] The phase interpolator slows down the signal edges of the pair of frequency-divided signals and outputs an interpolated signal, the phase of which is the average of the phases of the pair of frequency-divided signals.

[0010] In a preferred embodiment, the divider-by-1.5 includes:

[0011] The divide-by-3 frequency divider includes a first flip-flop, a second flip-flop, and a first NAND logic. The pair of positive and negative clock signals are coupled to the first flip-flop and the second flip-flop. The output of the first flip-flop outputs a first divided frequency signal and is connected to the first input of the first NAND logic. The output of the first NAND logic outputs a second divided frequency signal and is connected to the input of the second flip-flop. The output of the second flip-flop outputs a third divided frequency signal and is connected to the second input of the first NAND logic and the input of the first flip-flop.

[0012] The first frequency multiplier acquires the second and third frequency division signals and outputs a positive-phase frequency division signal with a duty cycle of 2 / 3 and a division ratio of 1.5.

[0013] The second frequency multiplier acquires the first frequency division signal and the second frequency division signal and outputs a frequency division signal with a duty cycle of 2 / 3 and a division ratio of 1.5 that is 1 / 3 period out of phase with the positive frequency division signal to the first inverter. The first inverter outputs a frequency division signal with a duty cycle of 1 / 3 and a division ratio of 1.5.

[0014] In a preferred embodiment, the first frequency multiplier includes a third flip-flop, a first latch, a first NOR logic, a second NOR logic, and a third NOR logic. The pair of positive and negative clock signals are coupled to the third flip-flop and the first latch. The input of the first latch is coupled to the second frequency divider signal. The output of the first latch and the positive clock signal are coupled to the two inputs of the second NOR logic. The input of the third flip-flop is coupled to the third frequency divider signal. The output of the third flip-flop and the negative clock signal are coupled to the two inputs of the first NOR logic. The outputs of the first NOR logic and the second NOR logic are coupled to the two inputs of the third NOR logic. The third NOR logic outputs a frequency divider signal with a duty cycle of 2 / 3 and a division ratio of 1.5 for the positive phase.

[0015] In a preferred embodiment, the first flip-flop, the second flip-flop, and the third flip-flop are D flip-flops.

[0016] In a preferred embodiment, the second frequency multiplier includes a fourth flip-flop, a second latch, a fourth NOR logic, a fifth NOR logic, and a sixth NOR logic. The pair of positive and negative clock signals are both coupled to the fourth flip-flop and the second latch. The input of the second latch is coupled to the second frequency divider signal. The output of the second latch and the positive clock signal are coupled to the two inputs of the fifth NOR logic. The input of the fourth flip-flop is coupled to the first frequency divider signal. The output of the fourth flip-flop and the negative clock signal are coupled to the two inputs of the fourth NOR logic. The outputs of the fourth NOR logic and the fifth NOR logic are coupled to the two inputs of the sixth NOR logic. The sixth NOR logic output is a frequency divider signal with a duty cycle of 2 / 3 and a division ratio of 1.5, which is 1 / 3 of a cycle out of phase with the positive frequency divider signal.

[0017] In a preferred embodiment, the first flip-flop, the second flip-flop, and the fourth flip-flop are D flip-flops.

[0018] In a preferred embodiment, the phase interpolator includes: a second inverter, a third inverter, a first resistor, a second resistor, a first adjustable resistor, and a second adjustable resistor. The input of the second inverter is coupled to the positive-phase frequency division signal, and the output of the second inverter is connected to one end of the first resistor and one end of the first adjustable resistor, with the other end of the first adjustable resistor grounded. The input of the third inverter is coupled to the inverted frequency division signal, and the output of the third inverter is connected to one end of the second resistor and one end of the second adjustable resistor, with the other end of the second adjustable resistor grounded. The other ends of the first resistor and the second resistor are connected together and output the interpolated signal.

[0019] In a preferred embodiment, the system further includes a duty cycle adjustment module, which receives the interpolation signal and adjusts the duty cycle of the interpolation signal to 1 / 2. The duty cycle adjustment module includes a first capacitor, a second capacitor, a first adjustable inverter, a second adjustable inverter, a third resistor, and a fourth resistor. One end of the first capacitor is connected to the interpolation signal, and the other end is connected to the input terminal of the first adjustable inverter. The output terminal of the first adjustable inverter is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the input terminal of the second adjustable inverter. The third resistor is connected between the input terminal and the output terminal of the first adjustable inverter, and the fourth resistor is connected between the input terminal and the output terminal of the second adjustable inverter.

[0020] In a preferred embodiment, the ratio of the transistors in the first adjustable inverter and / or the second adjustable inverter is adjusted to adjust the threshold voltage of the first adjustable inverter and / or the second adjustable inverter.

[0021] In a preferred embodiment, the threshold voltages of the first adjustable inverter and the second adjustable inverter are adjusted in opposite directions.

[0022] Compared to existing technologies, the 1.5 frequency divider based on a phase interpolator of the present invention has the following advantages:

[0023] 1. The 1.5 divider scheme based on phase interpolation can be used in high-speed and high-precision applications because the speed of phase interpolation is basically close to that of inverter. Therefore, the 1.5 divider of phase interpolation can achieve a very high operating frequency and very low power consumption.

[0024] 2. An output signal with a duty cycle of 50% can be accurately achieved through a phase interpolator and a duty cycle adjustment circuit.

[0025] 3. Since the output signal is obtained by phase interpolation, and in high-speed applications, phase interpolation only requires adjustment of a very small equivalent delay, the output jitter can be relatively small.

[0026] 4. This circuit can be implemented using a very simple analog circuit structure, without even an operational amplifier, and without the need for large areas of passive capacitors and passive inductors. Therefore, the circuit area is greatly reduced, saving costs, and the circuit can be easily migrated to process nodes.

[0027] 5. Since the phase interpolator is an open-loop structure, it does not need to consider loop stability issues as in phase-locked loop structures. Furthermore, the implementation of the phase interpolator in this scheme is relatively simple, which can greatly reduce the complexity of circuit design.

[0028] 6. Since this scheme is based on the structure of a phase interpolator, phase interpolation has good robustness compared to other open-loop calibration methods, which can ensure good consistency of the scheme under different process angles, power supply voltages and temperatures.

[0029] 7. It can use differential signals as input signals without requiring multi-phase clocks as input signals, thus greatly reducing the requirements for input clock circuits.

[0030] 8. This circuit can usually be used to reduce the tuning range of a voltage-controlled oscillator (VCO). This reduces the difficulty of compromising various parameters in the VCO circuit and also reduces the area occupied by the VCO.

[0031] This specification contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0032] Figure 1A schematic diagram of a 1.5 frequency divider based on a phase interpolator is shown in one embodiment of the present invention.

[0033] Figure 2 A schematic diagram of a frequency divider excluding 1.5 is shown in one embodiment of the present invention.

[0034] Figure 3 A schematic diagram of a frequency divider (excluding 3) is shown in one embodiment of the present invention.

[0035] Figure 4 A schematic diagram of a first frequency multiplier is shown in one embodiment of the present invention.

[0036] Figure 5 The diagram shows a waveform of the positive phase frequency division signal generated by the 1.5 frequency divider in one embodiment of the present invention.

[0037] Figure 6 A schematic diagram of a phase interpolator according to an embodiment of the present invention is shown.

[0038] Figure 7 A waveform diagram of a phase interpolator according to an embodiment of the present invention is shown.

[0039] Figure 8 A schematic diagram of a duty cycle adjustment module in one embodiment of the present invention is shown. Detailed Implementation

[0040] Various aspects and examples of this application will now be described. The following description provides specific details for a thorough understanding and implementation of these examples. However, those skilled in the art will understand that this application can be practiced without many of these details.

[0041] Additionally, some well-known structures or functions may not be shown or described in detail in order to be concise and avoid unnecessarily obscuring the relevant descriptions.

[0042] The terminology used in the description given below is intended to be interpreted in its broadest and most reasonable manner, even when used in conjunction with the detailed description of certain specific examples of this application. Some terms may even be emphasized below; however, any term intended to be interpreted in any restrictive manner will be explicitly and specifically defined in this detailed description section.

[0043] One embodiment of this application provides a 1.5 frequency divider based on a phase interpolator. Figure 1 A block diagram of a 1.5 divider 100 based on a phase interpolator is shown. The 1.5 divider 100 includes: a 1.5 divider 110, a phase interpolator 120, and a duty cycle adjustment module 130.

[0044] The 1.5 divider 110 outputs a pair of frequency divider signals 1p5out1 and 1p5out2 with duty cycles of 1 / 3 and 2 / 3 and a division ratio of 1.5, based on a pair of positive and negative clock signals clk and clkb.

[0045] The phase interpolator 120 slows down the edges of the pair of frequency-divided signals 1p5out1 and 1p5out2 and outputs an interpolated signal pi_out to the duty cycle adjustment module 130. The phase of the interpolated signal pi_out is the average of the phases of the pair of frequency-divided signals 1p5out1 and 1p5out2. The duty cycle adjustment module 130 adjusts the duty cycle of the interpolated signal pi_out to 1 / 2.

[0046] In a preferred embodiment, Figure 2 A block diagram of a divider-by-1.5 frequency divider 110 is shown. The divider-by-1.5 frequency divider includes a divider-by-3 frequency divider 111, a first frequency multiplier 112, a second frequency multiplier 113, and a first inverter 114. The divider-by-3 frequency divider 111 couples a pair of inverted and outverted clock signals clk and clkb to generate three divided signals D1, D2, and D3. Two of these, D2 and D3, are coupled to the first frequency multiplier 112. The pair of inverted and outverted clock signals clk and clkb in the first frequency multiplier 112 performs logical operations on the two divided signals D2 and D3 to form a positive-phase divided signal 1p5out1 with a duty cycle of 2 / 3 and a division ratio of 1.5. Two of the frequency multipliers, D1 and D2, are coupled to the second frequency multiplier 113. In the second frequency multiplier 113, a pair of positive and negative clock signals, clk and clkb, perform logical operations on the two frequency division signals D1 and D2 to form a frequency division signal with a duty cycle of 2 / 3 and a division ratio of 1.5. After being inverted by the first inverter 114, it forms a frequency division signal 1p5out2 with a duty cycle of 1 / 3 and a division ratio of 1.5.

[0047] In one embodiment, Figure 3 A schematic diagram of a divide-by-3 frequency divider 111 is shown. The divide-by-3 frequency divider includes a first flip-flop 1111, a second flip-flop 1112, and a first NAND logic 1113. The pair of positive and negative clock signals clk and clkb are both coupled to the first flip-flop 1111 and the second flip-flop 1112. The output of the first flip-flop 1111 outputs a first divided signal D1, which is connected to the first input of the first NAND logic 1113. The output of the first NAND logic 1113 outputs a second divided signal D2, which is connected to the input of the second flip-flop 1112. The output of the second flip-flop 1113 outputs a third divided signal D3, which is connected to the second input of the first NAND logic 1113 and the input of the first flip-flop 1111.

[0048] The first frequency multiplier acquires the second and third divided frequency signals and outputs a positive-phase divided frequency signal with a duty cycle of 2 / 3 and a division ratio of 1.5. In one embodiment, Figure 4 A schematic diagram of the first frequency multiplier 112 is shown. The first frequency multiplier 112 includes a third flip-flop 1121, a first latch 1122, a first NOR logic 1123, a second NOR logic 1124, and a third NOR logic 1125. The pair of positive and negative clock signals clk and clkb are both coupled to the third flip-flop 1121 and the first latch 1122. The input of the first latch 1122 is coupled to the second frequency divider signal D2, and the output of the first latch 1122 and the positive clock signal clk are coupled to the second NOR logic 1124. The third flip-flop 1121 has two input terminals. The input terminal of the third flip-flop 1121 is coupled to the third frequency divider signal D3. The output terminal of the third flip-flop 1121 and the inverted clock signal clkb are coupled to the two input terminals of the first NOR logic 1123. The output terminals of the first NOR logic 1123 and the second NOR logic 1124 are coupled to the two input terminals of the third NOR logic 1125. The third NOR logic 1125 outputs the positive-phase frequency divider signal 1p5out1 with a duty cycle of 2 / 3 and a frequency division ratio of 1.5.

[0049] The second frequency multiplier acquires the first frequency division signal and the second frequency division signal and outputs a frequency division signal with a duty cycle of 2 / 3 and a frequency division ratio of 1.5 that is 1 / 3 period out of phase with the positive frequency division signal to the first inverter. The first inverter outputs a frequency division signal with a duty cycle of 1 / 3 and a frequency division ratio of 1.5. In one embodiment, the second frequency multiplier includes a fourth flip-flop, a second latch, a fourth NOR logic, a fifth NOR logic, and a sixth NOR logic. The pair of positive and negative clock signals are coupled to the fourth flip-flop and the second latch. The input of the second latch is coupled to the second frequency divider signal. The output of the second latch and the positive clock signal are coupled to the two inputs of the fifth NOR logic. The input of the fourth flip-flop is coupled to the first frequency divider signal. The output of the fourth flip-flop and the negative clock signal are coupled to the two inputs of the fourth NOR logic. The outputs of the fourth NOR logic and the fifth NOR logic are coupled to the two inputs of the sixth NOR logic. The sixth NOR logic output is a frequency divider signal with a duty cycle of 2 / 3 and a division ratio of 1.5, which is 1 / 3 period out of phase with the positive frequency divider signal. This frequency divider signal is then processed by a first inverter 114 to form a frequency divider signal 1p5out2 with a duty cycle of 1 / 3 and a division ratio of 1.5.

[0050] In one embodiment, the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are D flip-flops.

[0051] In one embodiment, Figure 6 A schematic diagram of a phase interpolator 120 is shown. The phase interpolator 120 includes: a second inverter 121, a third inverter 122, a first resistor R1, a second resistor R2, a first adjustable resistor RX1, and a second adjustable resistor RX2. The input of the second inverter 121 is coupled to the positive-phase frequency divider signal 1p5out1. The output of the second inverter 121 is connected to one end of the first resistor R1 and one end of the first adjustable resistor RX1. The other end of the first adjustable resistor RX2 is grounded. The input of the third inverter 122 is coupled to the inverted frequency divider signal 1p5out2. The output of the third inverter 122 is connected to one end of the second resistor R2 and one end of the second adjustable resistor RX2. The other end of the second adjustable resistor RX2 is grounded. The other ends of the first resistor R1 and the second resistor R2 are connected and output the interpolation signal pi_out. Figure 7 A waveform diagram of the phase interpolator 120 is shown.

[0052] In one embodiment, Figure 8 A schematic diagram of the duty cycle adjustment module 130 is shown. The duty cycle adjustment module 130 includes: a first capacitor C1, a second capacitor C2, a first adjustable inverter 131, a second adjustable inverter 132, a third resistor R3, and a fourth resistor R4. One end of the first capacitor C1 is connected to the interpolation signal pi_out, and the other end is connected to the input terminal of the first adjustable inverter 131. The output terminal of the first adjustable inverter 131 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the input terminal of the second adjustable inverter 132. The third resistor R3 is connected between the input and output terminals of the first adjustable inverter 131, and the fourth resistor R4 is connected between the input and output terminals of the second adjustable inverter 132.

[0053] In one embodiment, the ratio of the transistors in the first adjustable inverter 131 and / or the second adjustable inverter 132 is adjusted to adjust the threshold voltage of the first adjustable inverter 131 and / or the second adjustable inverter 132. In another embodiment, the threshold voltages of the first adjustable inverter 131 and the second adjustable inverter 132 are adjusted in opposite directions.

[0054] The working process of the 1.5 frequency divider based on the phase interpolator in this application is described below.

[0055] like Figure 1As shown, the 1.5 divider based on the phase interpolator includes a divider 110 with a division ratio of 1.5, a phase interpolator 120, and a duty cycle adjustment module 130.

[0056] A frequency divider with an output duty cycle of 1 / 3 and a division ratio of 1.5, such as... Figure 2 As shown in the diagram, this module consists of two parts: a divider-by-3 and two frequency multipliers. Figure 3 For the specific implementation of the divider-by-3, Figure 4 This describes the specific implementation of the frequency multiplier. First, a 3-divided signal is generated using a divide-by-3 frequency divider. Then, two re-timed 3-divided signals are selected using in-phase and out-of-phase clocks respectively. The two clocked signals are then passed through a OR gate to form a 1.5-divided output signal with a 2 / 3 duty cycle, effectively multiplying the 3-divided signal. The specific signal waveforms for each node are shown in Figure 5, where T2, T4, T3, and T5 are the node signals in the frequency multiplier with the output signal 1p5_out1. It should be noted that the two frequency multipliers have the same structure, which will not be elaborated upon here. Due to the selection of different 3-divided signals, the output signals of the two frequency multipliers differ in phase by 1 / 3 of a period.

[0057] This invention provides only one implementation example of a 1.5 frequency divider. Of course, it is also feasible to implement the 1.5 frequency divider function through other logic circuits.

[0058] The specific implementation of the phase interpolator module is as follows: Figure 6 As shown in the figure. The basic principle of this phase interpolator is to first slow down the signal edges of the input 1p5_out1 and 1p5_out2 signals. This improves the linearity of the phase interpolation, making the phase of the output signal pi_out close to the ideal phase interpolation result, and ensuring that the duty cycle of the output signal pi_out is approximately 50%. The phase interpolation circuit is implemented using two inverters coupled by external resistors. The size of the two inverters and the resistance value of the external resistors are the same, ensuring that the phase of the phase interpolator output is the average of the phases of the 1p5_out1 and 1p5_out2 signals, thereby calibrating the duty cycle of the output signal to 50%. The specific signal waveform of this module is shown in the figure. Figure 7 As shown.

[0059] It should be understood that a 1.5 divider can also be implemented using other phase interpolator structures. For example, a current-steering phase interpolator could be used instead of... Figure 6 The same effect can be achieved through the same implementation method.

[0060] The circuit of the duty cycle adjustment module is as follows: Figure 8As shown, the duty cycle adjustment module is based on a DC-blocking inverter with an adjustable threshold voltage. The signal duty cycle is adjusted by combining DC blocking and threshold voltage adjustment. The threshold voltages of the two cascaded DC-blocking inverters need to be adjusted in opposite directions. This adjustment also helps to compensate for circuit mismatches by utilizing the circuit's symmetry. The threshold voltage adjustment is achieved by adjusting the ratio of PMOS and NMOS transistors in the inverter. The duty cycle adjustment module is not essential in some applications.

[0061] In other embodiments of this application, the duty cycle adjustment module may use a feedback loop pair to ensure an accurate 50% duty cycle output. It should be understood that if the actual circuit implementation of the phase interpolator performs well, the duty cycle adjustment module may not even be necessary in other embodiments of this application.

[0062] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0063] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.

[0064] This specification includes combinations of various embodiments described herein. Individual references to embodiments (e.g., “one embodiment”, “some embodiments”, or “preferred embodiments”) do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word “or” is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.

[0065] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A 1.5 frequency divider based on a phase interpolator with an output duty cycle of 50%, characterized in that, include: The frequency divider and phase interpolator are connected in sequence; among them, The 1.5 divider outputs a pair of frequency divider signals with duty cycles of 1 / 3 and 2 / 3 respectively and a division ratio of 1.5 based on a pair of positive and negative clock signals, and the average duty cycle of the pair of frequency divider signals is 1 / 2; The phase interpolator slows down the signal edges of the pair of frequency-divided signals and outputs an interpolated signal. The phase of the interpolated signal is the average of the phases of the pair of frequency-divided signals, and the output duty cycle of the phase interpolator is 50%.

2. The 1.5 frequency divider based on a phase interpolator according to claim 1, characterized in that, The divider-by-1.5 includes: The divide-by-3 frequency divider includes a first flip-flop, a second flip-flop, and a first NAND logic. The pair of positive and negative clock signals are coupled to the first flip-flop and the second flip-flop. The output of the first flip-flop outputs a first divided frequency signal and is connected to the first input of the first NAND logic. The output of the first NAND logic outputs a second divided frequency signal and is connected to the input of the second flip-flop. The output of the second flip-flop outputs a third divided frequency signal and is connected to the second input of the first NAND logic and the input of the first flip-flop. The first frequency multiplier acquires the second and third frequency division signals and outputs a positive-phase frequency division signal with a duty cycle of 2 / 3 and a division ratio of 1.

5. The second frequency multiplier acquires the first frequency division signal and the second frequency division signal and outputs a frequency division signal with a duty cycle of 2 / 3 and a division ratio of 1.5 that is 1 / 3 period out of phase with the positive frequency division signal to the first inverter. The first inverter outputs a frequency division signal with a duty cycle of 1 / 3 and a division ratio of 1.

5.

3. The 1.5 frequency divider based on a phase interpolator according to claim 2, characterized in that, The first frequency multiplier includes a third flip-flop, a first latch, a first NOR logic, a second NOR logic, and a third NOR logic. The pair of positive and negative clock signals are coupled to the third flip-flop and the first latch. The input of the first latch is coupled to the second frequency divider signal. The output of the first latch and the positive clock signal are coupled to the two inputs of the second NOR logic. The input of the third flip-flop is coupled to the third frequency divider signal. The output of the third flip-flop and the negative clock signal are coupled to the two inputs of the first NOR logic. The outputs of the first NOR logic and the second NOR logic are coupled to the two inputs of the third NOR logic. The third NOR logic outputs a frequency divider signal with a duty cycle of 2 / 3 and a division ratio of 1.5 for the positive phase.

4. The 1.5 frequency divider based on a phase interpolator according to claim 3, characterized in that, The first flip-flop, the second flip-flop, and the third flip-flop are D flip-flops.

5. The 1.5 frequency divider based on a phase interpolator according to claim 2, characterized in that, The second frequency multiplier includes a fourth flip-flop, a second latch, a fourth NOR logic, a fifth NOR logic, and a sixth NOR logic. The pair of positive and negative clock signals are coupled to the fourth flip-flop and the second latch. The input of the second latch is coupled to the second frequency divider signal. The output of the second latch and the positive clock signal are coupled to the two inputs of the fifth NOR logic. The input of the fourth flip-flop is coupled to the first frequency divider signal. The output of the fourth flip-flop and the negative clock signal are coupled to the two inputs of the fourth NOR logic. The outputs of the fourth NOR logic and the fifth NOR logic are coupled to the two inputs of the sixth NOR logic. The sixth NOR logic output is a frequency divider signal with a duty cycle of 2 / 3 and a division ratio of 1.5, which is 1 / 3 of a cycle out of phase with the positive frequency divider signal.

6. The 1.5 frequency divider based on a phase interpolator according to claim 5, characterized in that, The first flip-flop, the second flip-flop, and the fourth flip-flop are D flip-flops.

7. The 1.5 frequency divider based on a phase interpolator according to claim 1, characterized in that, The phase interpolator includes: a second inverter, a third inverter, a first resistor, a second resistor, a first adjustable resistor, and a second adjustable resistor. The input of the second inverter is coupled to the positive-phase frequency division signal. The output of the second inverter is connected to one end of the first resistor and one end of the first adjustable resistor, with the other end of the first adjustable resistor grounded. The input of the third inverter is coupled to the negative-phase frequency division signal. The output of the third inverter is connected to one end of the second resistor and one end of the second adjustable resistor, with the other end of the second adjustable resistor grounded. The other ends of the first resistor and the second resistor are connected and output the interpolated signal.

8. The 1.5 frequency divider based on a phase interpolator according to claim 1, characterized in that, Also includes: A duty cycle adjustment module receives the interpolation signal and adjusts the duty cycle of the interpolation signal to 1 / 2. The duty cycle adjustment module includes: a first capacitor, a second capacitor, a first adjustable inverter, a second adjustable inverter, a third resistor, and a fourth resistor. One end of the first capacitor is connected to the interpolation signal, and the other end is connected to the input terminal of the first adjustable inverter. The output terminal of the first adjustable inverter is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the input terminal of the second adjustable inverter. The third resistor is connected between the input terminal and the output terminal of the first adjustable inverter, and the fourth resistor is connected between the input terminal and the output terminal of the second adjustable inverter.

9. The 1.5 frequency divider based on a phase interpolator according to claim 8, characterized in that, Adjust the ratio of the transistors in the first adjustable inverter and / or the second adjustable inverter to adjust the threshold voltage of the first adjustable inverter and / or the second adjustable inverter.

10. The 1.5 frequency divider based on a phase interpolator according to claim 9, characterized in that, The threshold voltages of the first adjustable inverter and the second adjustable inverter are adjusted in opposite directions.

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