Image sensor and camera

Abstract

The utility model discloses an image sensor comprising an image reading unit, the image reading unit comprises s image reading sub-modules, and s is an integer greater than 1; each image reading sub-module comprises n pixel quantization units, and n is an integer greater than 1; and each pixel quantization unit comprises k + 1 clocks and image field intensity signal counters which are arranged in series. A camera including the image sensor is also disclosed. The image sensor provided by the utility model greatly improves the overall working frequency of the circuit, and also shortens a large amount of counter clock tree analysis time. The method has better flexibility, greatly shortens the analysis time of a back-end tool, and supports higher counting frequency.

Description

Technical Field

[0001] This utility model relates to an image sensor and belongs to the field of image sensor technology. Background Technology

[0002] With the increasing number of pixels in image sensors, traditional solutions for quantizing each pixel primarily use synchronous counters. However, as frame rate demands increase, requiring higher quantization clock frequencies, synchronous counters struggle to meet these timing requirements. Asynchronous counters can effectively address this issue, but quantizing a large number of pixels individually using asynchronous counters necessitates the use of numerous asynchronous counters. This results in a large number of clocks requiring analysis by digital circuit backend tools, making it difficult or impossible to complete the analysis of all clocks in a short time.

[0003] Therefore, a new image sensor is needed to solve the above problems. Summary of the Invention

[0004] Purpose of the invention: To address the technical problems existing in the prior art, this utility model provides an image sensor.

[0005] Technical solution: To achieve the above objectives, this utility model provides an image sensor, including an image reading unit.

[0006] 1) The image reading unit comprises s image reading sub-modules, where s is an integer greater than 1; and

[0007] 2) Each of the image reading submodules includes n pixel quantization units, where n is an integer greater than 1; and

[0008] 3) Each pixel quantization unit includes k+1 serially arranged clock and image field strength signal counters, and each clock and image field strength signal counter includes a divider, which is connected to the next clock and image field strength signal counter. The divider is configured such that the signal to be processed includes two parts: a clock signal and a field strength signal. After passing through the divider, the signal to be processed is input to the next clock and image field strength signal counter, and the frequency of the next clock and image field strength signal counter is half the clock frequency of the previous clock and image field strength signal counter. The output of the k+1 serially arranged clock and image field strength signal counters included in the pixel quantization unit is the quantization result of the pixel quantization unit in this operation.

[0009] Beneficial effects: The image sensor of this invention significantly improves the overall operating frequency of the circuit and reduces the analysis time of a large number of counter clock trees. It offers greater flexibility, greatly shortens the analysis time of back-end tools, and supports higher counting frequencies.

[0010] The present invention also discloses a camera, including the image sensor described above.

[0011] Beneficial effects: The camera of this invention significantly improves the overall operating frequency of the circuit and greatly reduces the time required for counter clock tree analysis. It offers greater flexibility, significantly shortens the analysis time of back-end tools, and supports higher counting frequencies. Attached Figure Description

[0012] Figure 1 A schematic diagram illustrating pixel quantization using a single asynchronous counter;

[0013] Figure 2 A schematic diagram illustrating the quantization of m pixels using m asynchronous counters;

[0014] Figure 3 This is a schematic diagram showing n asynchronous counters as sub-modules;

[0015] Figure 4 This is a diagram illustrating how submodules can be reused. Detailed Implementation

[0016] The preferred embodiments of the present invention will now be described in conjunction with the accompanying drawings, which will more clearly and completely illustrate the technical solution of the present invention.

[0017] Please see Figures 1-4 As shown, this utility model discloses an image sensor, including an image reading unit. The image reading unit includes s image reading sub-modules, where s is an integer greater than 1. Each image reading sub-module includes n pixel quantization units, where n is an integer greater than 1. Each pixel quantization unit includes k+1 serially arranged clock and image field strength signal counters.

[0018] Preferably, a frequency divider is also included, with a frequency divider provided between adjacent clock and image field strength signal counters. The clock signal of each clock and image field strength signal counter is divided by two by the frequency divider and then input to the next clock and image field strength signal counter, serving as the clock frequency of that clock and image field strength signal counter. When the image field strength signal of each clock and image field strength signal counter is transmitted to the next stage clock and image field strength signal counter, it is divided by two along with the clock signal, and the image field strength signal is output in the form of Q0 to Qk respectively. Q0 to Qk are combined as the image field strength signal of the image sensor.

[0019] The present invention also discloses a camera, including the image sensor described above.

[0020] Invention principle:

[0021] 1. Compared with the synchronous counter structure used in traditional image sensors, this invention can support higher clock frequencies. The counter in this invention is an asynchronous counter, and when analyzing the timing, only the timing of a single D flip-flop needs to be analyzed. However, when using a traditional synchronous counter, the timing of all D flip-flops in the counter needs to be analyzed.

[0022] 2. This utility model divides the huge counter circuit into s sub-modules on an average basis. Only the clock tree analysis of the s sub-modules needs to be completed, which greatly shortens the analysis time of the back-end tools.

[0023] 3. The number of sub-modules that can be flexibly divided into on average can be adjusted according to the number of counter circuits, providing excellent flexibility.

[0024] This invention's image sensor significantly improves the overall operating frequency of the circuit and reduces the time required for counter clock tree analysis. It offers greater flexibility, greatly shortens the analysis time for backend tools, and supports higher counting frequencies. Example

[0025] This invention provides a back-end tool analysis method for clock trees of a large number of asynchronous counters. It mainly involves dividing multiple asynchronous counters into multiple sub-modules, each containing n asynchronous counters. First, the clock tree of each sub-module is analyzed. After the analysis is complete, the sub-module is reused multiple times. This avoids the need for the tool to analyze a large number of clocks at once, thus improving the overall operating frequency of the circuit and shortening the time required for analyzing the clock trees of a large number of asynchronous counters.

[0026] It includes the following steps:

[0027] Step 1: For each pixel, quantize it using a k+1 bit asynchronous counter. The pixel circuit input signal is EN, and the width of its high level represents its charge. When EN is high, the asynchronous counter starts working. The falling edge of the Q output of the low-order flip-flop serves as the clock for the adjacent high-order bit. The counter internally generates k derived clocks. When the EN signal is low, counting stops, and the counter result (Qk-Q0) output by the flip-flop is read, which gives the quantized result of the pixel charge. (See diagram below.) Figure 1 As shown;

[0028] Step 2: Assume the image sensor needs to quantize m pixels each time, and each pixel outputs an EN signal (EN0-ENm). This requires m asynchronous counters for quantization, as illustrated in the diagram below. Figure 2 As shown;

[0029] Step 3: Divide the m asynchronous counters into s sub-modules, each sub-module containing n asynchronous counters. Use backend tools to analyze the n image sensors, as shown in the diagram. Figure 3 As shown;

[0030] Step 4: After completing the submodule clock tree analysis in Step 3, reuse the submodules to obtain a module with m asynchronous counters. This completes the clock tree analysis of the m asynchronous counter module. (See diagram below.) Figure 4 As shown.

[0031] Based on the steps above, the problem that backend tools cannot perform clock tree analysis on a large number of asynchronous counters can be solved by dividing multiple asynchronous counters into multiple sub-modules, performing clock tree analysis on the sub-modules, and then reusing them.

[0032] The above-described specific embodiments are merely preferred embodiments of the present utility model and are not intended to limit the scope of protection of the present utility model. Any modifications, substitutions, and improvements made by those skilled in the art to the technical solutions of the present utility model based on the provided text description and drawings, without departing from the design concept and spirit of the present utility model, should fall within the scope of protection of the present utility model.

Claims

1. An image sensor, comprising an image reading unit, characterized in that, 1) The image reading unit comprises s image reading sub-modules, where s is an integer greater than 1; and 2) Each of the image reading submodules includes n pixel quantization units, where n is an integer greater than 1; and 3) Each pixel quantization unit includes k+1 serially arranged clock and image field strength signal counters, and each clock and image field strength signal counter includes a divider, which is connected to the next clock and image field strength signal counter. The divider is configured such that the signal to be processed includes two parts: a clock signal and a field strength signal. After passing through the divider, the signal to be processed is input to the next clock and image field strength signal counter, and the frequency of the next clock and image field strength signal counter is half the clock frequency of the previous clock and image field strength signal counter. The output of the k+1 serially arranged clock and image field strength signal counters included in the pixel quantization unit is the quantization result of the pixel quantization unit in this operation.

2. A camera, characterized in that, Including the image sensor as described in claim 1.

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