A decision feedback equalizer

Abstract

The application provides a decision feedback equalizer, four possible output results are pre-calculated through a tap coefficient element, and then a final target decision result is output through a four-to-one multiplexer after processing, so that the operation frequency of the decision feedback equalizer is improved, and the power consumption is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronics, and more particularly to a decision feedback equalizer. BACKGROUND

[0002] With the serial data rate reaching 56Gbs or even 112Gbs, the traditional NRZ mode is too large due to channel loss, and the general equalization mode is more and more difficult to recover the signal. In this regard, the PAM4 mode has begun to replace the NRZ and become the mainstream coding mode. PAM4 also brings great challenges, first of all, high frequency, high speed code rate is a great challenge to the traditional analog equalization mode, so the equalization scheme of ADC+DSP has emerged as the times require. The decision feedback equalizer (Decision Feedback Equalizers, DFE) is a common equalizer used to compensate for inter-symbol interference (InterSymbol Interference, ISI) in the DSP of the SERDES receiver. The existing decision feedback equalizer needs to be improved. SUMMARY

[0003] Therefore, the present application provides a decision feedback equalizer, which effectively solves the technical problems existing in the prior art, improves the operating frequency of the decision feedback equalizer, and reduces its power consumption.

[0004] To achieve the above-mentioned purpose, the technical scheme provided by the present application is as follows:

[0005] A decision feedback equalizer, comprising: a first branch to an Nth branch, the jth branch is connected to the jth input data, N is an integer greater than or equal to 2, j is an integer greater than 0 and less than or equal to N, the jth branch comprises:

[0006] A tap coefficient element is used to retrieve a 1-tap tap coefficient, and after multiplying the tap coefficient with the first to fourth level data of the PAM4 signal, the first to fourth results are output, wherein the tap coefficient is multiplied with the ith level data to obtain the ith result, i is an integer greater than or equal to 1 and less than or equal to 4;

[0007] A summing element is used to sum the jth input data and the ith result to output the ith summing result;

[0008] A decision element is used to judge the ith summing result to output the ith decision result;

[0009] The four-to-one multiplexer of the kth branch is configured to select a target decision result from the first decision result to the fourth decision result of the kth branch according to an output of the four-to-one multiplexer of the (k+1)th branch, and the four-to-one multiplexer of the Nth branch is configured to select a target decision result from the first decision result to the fourth decision result of the Nth branch according to an output of the four-to-one multiplexer of the first branch, where k is an integer greater than or equal to 1 and less than N.

[0010] Optionally, the method further comprises: storing the tap coefficient of the 1-tap in a first register, and the tap coefficient element retrieving the tap coefficient from the first register.

[0011] Optionally, the method further comprises: storing the i-th summation result output by the summation element in a second register, and the decision element retrieving the i-th summation result from the second register.

[0012] Optionally, the method further comprises: storing the i-th decision result output by the decision element in a third register, and the four-to-one multiplexer retrieving the i-th decision result from the third register.

[0013] Optionally, the method further comprises: storing the target decision result output by the four-to-one multiplexer in a fourth register.

[0014] Optionally, N is 32.

[0015] Optionally, the decision element refers to respective average values of three eyes in at least one cycle time of an eye diagram of the PAM4 signal, and outputs the i-th decision result after the i-th summation result is decided.

[0016] Optionally, the decision element outputs the respective decision result after the respective summation result is decided according to the following formula:

[0017] The first decision result = 2*lower average value - the second decision result;

[0018] The second decision result = (lower average value + middle average value) / 2;

[0019] The third decision result = (upper average value + middle average value) / 2;

[0020] The fourth decision result = 2*upper average value - the third decision result;

[0021] Wherein, the upper mean is the average value of the upper eye in the eye diagram of the PAM4 signal, the middle mean is the average value of the middle eye in the eye diagram of the PAM4 signal, and the lower mean is the average value of the lower eye in the eye diagram of the PAM4 signal.

[0022] Optionally, the process of obtaining the intermediate mean includes: processing the j-th input data through the j-th integrator to obtain the j-th initial intermediate value; and summing and averaging the first initial intermediate value to the N-th initial intermediate value to obtain the intermediate mean.

[0023] The process of obtaining the upper mean includes: when it is determined that the j-th input data is greater than or equal to the intermediate mean, the j-th input data is processed by the j-th integrator to obtain the j-th initial upper value; the upper mean is obtained by summing and averaging all the initial upper values.

[0024] The process of obtaining the lower mean includes: when it is determined that the j-th input data is less than the intermediate mean, the j-th input data is processed by the j-th integrator to obtain the j-th initial lower value; the lower mean is obtained by summing and averaging all the initial lower values.

[0025] Optionally, the j-th integrator includes: an adder, a flip-flop, a first multiplier, and a second multiplier;

[0026] The first input terminal of the adder is connected to the j-th input data, and the second input terminal of the adder is connected to the output terminal of the second multiplier;

[0027] The first input terminal of the flip-flop is connected to the output terminal of the adder, the second input terminal of the flip-flop is connected to the output terminal of the flip-flop, and the input terminal of the second multiplier is connected to the output terminal of the flip-flop. The flip-flop is used to add the output signal of the adder and the output signal of the flip-flop and delay them by one symbol before outputting.

[0028] The input terminal of the first multiplier is connected to the output terminal of the flip-flop, and the output terminal of the first multiplier is the output terminal of the j-th integrator. The first multiplier and the second multiplier are used to adjust the bandwidth of the input signal.

[0029] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0030] This invention provides a decision feedback equalizer, comprising: a first branch to an Nth branch, wherein the jth branch is connected to the jth input data, where N is an integer greater than or equal to 2, and j is an integer greater than 0 and less than or equal to N. The jth branch includes: a tap coefficient element, wherein the tap coefficient element is used to retrieve the tap coefficient of a 1-tap, and multiplies the tap coefficient by the first level data to the fourth level data of the PAM4 signal respectively, and outputs the first result to the fourth result, wherein the tap coefficient is multiplied by the i-th level data to obtain the i-th result, where i is an integer greater than or equal to 1 and less than or equal to 4. A summing element is used to sum the j-th input data with the ith result and output the ith summing result; a decision element is used to make a decision on the ith summing result and output the ith decision result; a 4-to-1 multiplexer is used to select a target decision result from the first decision result to the fourth decision result of the k-th branch based on the output of the (k+1)-th branch 4-to-1 multiplexer, wherein the 4-to-1 multiplexer of the N-th branch is used to select a target decision result from the first decision result to the fourth decision result of the N-th branch based on the output of the 4-to-1 multiplexer of the first branch, and k is an integer greater than or equal to 1 and less than N.

[0031] As can be seen from the above, the technical solution provided by the present invention pre-calculates four possible output results through tap coefficient elements, and then outputs the final target decision result by a four-to-one multiplexer after processing and decision, thereby improving the operating frequency of the decision feedback equalizer and reducing its power consumption. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a decision feedback equalizer provided in an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of another decision feedback equalizer provided in an embodiment of the present invention;

[0035] Figure 3 An eye diagram of a PAM4 signal provided in an embodiment of the present invention;

[0036] Figure 4 A flowchart illustrating the process of obtaining the intermediate mean provided in an embodiment of the present invention;

[0037] Figure 5 A flowchart illustrating the process of obtaining the upper and lower means provided in an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of an integrator provided in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] As described in the background section, with serial data rates reaching 56Gbps and even 112Gbps, traditional NRZ encoding suffers from excessive channel loss, and conventional equalization methods become increasingly difficult to recover the signal. In response, PAM4 has begun to replace NRZ as the mainstream encoding method. PAM4 also presents significant challenges, primarily due to its high frequency and high bit rate, which pose a significant challenge to traditional analog equalization methods. Therefore, ADC+DSP equalization schemes have emerged. Decision Feedback Equalizers (DFEs) are common equalizers used in the DSP of SERDES receivers to compensate for inter-symbol interference (ISI). Existing decision feedback equalizers require improvement.

[0041] Based on this, the present invention provides a decision feedback equalizer, which effectively solves the technical problems existing in the prior art, improves the operating frequency of the decision feedback equalizer, and reduces its power consumption.

[0042] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 6 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0043] like Figure 1 The diagram shown is a schematic representation of a decision feedback equalizer provided in an embodiment of the present invention. The decision feedback equalizer includes: a first branch 11 to an Nth branch 1n, and a jth branch 1j connected to jth input data Dataj, where N is an integer greater than or equal to 2, and j is an integer greater than 0 and less than or equal to N. The jth branch 1j includes:

[0044] Tap coefficient element 21 is used to retrieve the tap coefficient 'a' of 1-tap, and multiply the tap coefficient 'a' by the first level data to the fourth level data of the PAM4 signal respectively, and output the first result to the fourth result, wherein the tap coefficient 'a' is multiplied by the i-th level data to obtain the i-th result, i is an integer greater than or equal to 1 and less than or equal to 4; and the first level data is -3, the second level data is -1, the third level data is 1, and the fourth level data is 3.

[0045] Summing element 22 is used to sum the j-th input data Dataj with the i-th result and output the i-th summation result.

[0046] Decision element 23 is used to make a decision on the i-th summation result and output the i-th decision result.

[0047] The 4-to-1 multiplexer 24 of the k-th branch is used to select a target decision result from the first decision result to the fourth decision result of the k-th branch based on the output of the 4-to-1 multiplexer 24 of the (k+1)-th branch. The 4-to-1 multiplexer 24 of the N-th branch 1n is used to select a target decision result from the first decision result to the fourth decision result of the N-th branch 1n based on the output of the 4-to-1 multiplexer 24 of the first branch 11. k is an integer greater than or equal to 1 and less than N.

[0048] It is understood that the first to Nth branches provided in this embodiment of the invention are parallel branches, and the j-th branch includes four parallel access ports that respectively access the j-th input data to perform summation processing with the corresponding results. In one embodiment of the invention, N is 32, that is, the decision feedback equalizer provided in this embodiment of the invention can be a parallel 32-channel decision feedback equalizer.

[0049] As can be seen from the above, the technical solution provided by the embodiments of the present invention pre-calculates four possible output results through tap coefficient elements, and then outputs the final target decision result by a four-to-one multiplexer after processing and decision, thereby improving the operating frequency of the decision feedback equalizer and reducing its power consumption.

[0050] like Figure 2 The diagram shown is a schematic diagram of another decision feedback equalizer provided in an embodiment of the present invention. The decision feedback equalizer provided by the present invention includes: a first register 31, which is used to store the tap coefficients of 1-tap, and the tap coefficient element 21 retrieves the tap coefficients from the first register 31.

[0051] And / or, such asFigure 2 As shown, the decision feedback equalizer includes: a second register 32, which is used to store the i-th summation result output by the summing element 22, and the decision element 23 obtains the i-th summation result from the second register 32.

[0052] And / or, such as Figure 2 As shown, the decision feedback equalizer includes a third register 33, which is used to store the i-th decision result output by the decision element 23, and the four-to-one multiplexer 24 obtains the i-th decision result from the third register 33.

[0053] And / or, such as Figure 2 As shown, the decision feedback equalizer includes a fourth register 34, which stores the target decision result output by the four-to-one multiplexer 24.

[0054] It is understood that the decision feedback equalizer provided in this embodiment of the invention adopts a register-based pipelined structure, which can further accelerate the operating frequency of the decision feedback equalizer and significantly improve the operating speed of the entire system. Optionally, the first register, second register, third register, and fourth register provided in this embodiment of the invention can be independent registers or they can be the same register; this invention does not impose specific limitations on this.

[0055] In one embodiment of the present invention, the decision element provided by the present invention refers to the average value of each of the three eyes within at least one period in the eye diagram of the PAM4 signal, makes a decision on the i-th summation result, and outputs the i-th decision result. Figure 3 The diagram shown is an eye diagram of a PAM4 signal provided in an embodiment of the present invention, where the horizontal axis represents time and the vertical axis represents amplitude. It can be seen that due to the four level data of the PAM4 signal, there are three eyes and four levels at each moment. The decision element makes a decision based on the average value of the middle of each eye in the eye diagram, thereby obtaining the ideal value (i.e., the decision result) corresponding to each of the four level data points.

[0056] In one embodiment of the present invention, the decision element provided by the present invention makes a decision on the corresponding summation result according to the following formula and outputs the corresponding decision result:

[0057] First judgment result = 2 * lower mean - second judgment result;

[0058] The second judgment result = (lower mean + median mean) / 2;

[0059] The third judgment result = (upper mean + middle mean) / 2;

[0060] Fourth judgment result = 2 * average value - the aforementioned third judgment result;

[0061] Wherein, the upper mean is the average value of the upper eye in the eye diagram of the PAM4 signal, the middle mean is the average value of the middle eye in the eye diagram of the PAM4 signal, and the lower mean is the average value of the lower eye in the eye diagram of the PAM4 signal.

[0062] like Figure 4 The diagram shown is a flowchart of a process for obtaining the intermediate mean provided in an embodiment of the present invention. The process of obtaining the intermediate mean mid includes: processing the j-th input data Dataj through the j-th integrator 4j to obtain the j-th initial intermediate value midj; and summing and averaging the first initial intermediate value mid1 to the N-th initial intermediate value midn to obtain the intermediate mean mid.

[0063] like Figure 5 The diagram shown is a flowchart of the process for obtaining the upper mean and lower mean according to an embodiment of the present invention. The process of obtaining the upper mean up includes: when it is determined that the j-th input data Dataj is greater than or equal to the intermediate mean mid, the j-th input data Dataj is processed by the j-th integrator 4j to obtain the j-th initial upper value upj; the upper mean up is obtained by summing and averaging all the initial upper values.

[0064] Furthermore, the process of obtaining the lower mean down includes: when it is determined that the j-th input data Dataj is less than the intermediate mean mid, the j-th input data Dataj is processed by the j-th integrator 4j to obtain the j-th initial lower value downj; and the lower mean down is obtained by summing and averaging all the initial lower values.

[0065] like Figure 6 The diagram shown is a schematic diagram of an integrator provided in an embodiment of the present invention. The integrator is a digital first-order ∑Δ integrator. The j-th integrator provided in this embodiment of the present invention includes: an adder 401, a trigger 402, a first multiplier 403, and a second multiplier 404.

[0066] The first input terminal of the adder 401 is connected to the j-th input data Dataj, and the second input terminal of the adder 401 is connected to the output terminal of the second multiplier 404.

[0067] The first input terminal of the flip-flop 402 is connected to the output terminal of the adder 401, the second input terminal of the flip-flop 402 is connected to the output terminal of the flip-flop 402, and the input terminal of the second multiplier 404 is connected to the output terminal of the flip-flop 402. The flip-flop 402 is used to add the output signal of the adder 401 and the output signal of the flip-flop 402 and delay the output by one symbol.

[0068] The input terminal of the first multiplier 403 is connected to the output terminal of the flip-flop 402, and the output terminal of the first multiplier 403 is the output terminal of the j-th integrator. The first multiplier 403 and the second multiplier 404 are used to adjust the bandwidth of the input signal, thereby changing the output curve more accurately as needed.

[0069] Understandably, the integrator design provided in this embodiment of the invention is simpler and does not require additional resources as the amount of data increases. Changing its accuracy only requires adjusting the bandwidth through the multiplier, thus eliminating the need to increase the depth of the filter.

[0070] This invention provides a decision feedback equalizer, comprising: a first branch to an Nth branch, wherein the jth branch is connected to the jth input data, where N is an integer greater than or equal to 2, and j is an integer greater than 0 and less than or equal to N. The jth branch includes: a tap coefficient element, wherein the tap coefficient element is used to retrieve the tap coefficient of a 1-tap, and multiplies the tap coefficient by the first level data to the fourth level data of the PAM4 signal respectively, and outputs the first result to the fourth result, wherein the tap coefficient is multiplied by the i-th level data to obtain the i-th result, where i is an integer greater than or equal to 1 and less than or equal to 4. A summing element is used to sum the j-th input data with the ith result and output the ith summing result; a decision element is used to make a decision on the ith summing result and output the ith decision result; a 4-to-1 multiplexer is used to select a target decision result from the first decision result to the fourth decision result of the k-th branch based on the output of the (k+1)-th branch 4-to-1 multiplexer, wherein the 4-to-1 multiplexer of the N-th branch is used to select a target decision result from the first decision result to the fourth decision result of the N-th branch based on the output of the 4-to-1 multiplexer of the first branch, and k is an integer greater than or equal to 1 and less than N.

[0071] As can be seen from the above, the technical solution provided by the embodiments of the present invention pre-calculates four possible output results through tap coefficient elements, and then outputs the final target decision result by a four-to-one multiplexer after processing and decision, thereby improving the operating frequency of the decision feedback equalizer and reducing its power consumption.

[0072] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A decision feedback equalizer, characterized in that, include: From the first branch to the Nth branch, the jth branch receives the jth input data, where N is an integer greater than or equal to 2, and j is an integer greater than 0 and less than or equal to N. The jth branch includes: A tap coefficient element is used to retrieve the tap coefficient of a 1-tap signal, and multiply the tap coefficient by the first level data to the fourth level data of the PAM4 signal respectively, and output the first result to the fourth result. The tap coefficient is multiplied by the i-th level data to obtain the i-th result, where i is an integer greater than or equal to 1 and less than or equal to 4. A summing element, which is used to sum the j-th input data with the ith result and output the ith summing result; A decision element, which is used to make a decision on the i-th summation result and output the i-th decision result; A 4-to-1 multiplexer is used to select a target decision result from the first to the fourth decision result of the k-th branch based on the output of the 4-to-1 multiplexer of the (k+1)-th branch. The 4-to-1 multiplexer of the N-th branch is used to select a target decision result from the first to the fourth decision result of the N-th branch based on the output of the 4-to-1 multiplexer of the first branch. k is an integer greater than or equal to 1 and less than N. A first register is used to store the tap coefficients of the 1-tap, and the tap coefficient element retrieves the tap coefficients from the first register. The second register is used to store the i-th summation result output by the summing element, and the decision element obtains the i-th summation result from the second register; The third register is used to store the i-th decision result output by the decision element, and the four-to-one multiplexer obtains the i-th decision result from the third register; The fourth register stores the target decision result output by the four-to-one multiplexer.

2. The decision feedback equalizer according to claim 1, characterized in that, N is 32.

3. The decision feedback equalizer according to claim 1, characterized in that, The decision element refers to the average value of each of the three eyes within at least one period in the eye diagram of the PAM4 signal, makes a decision on the i-th summation result, and outputs the i-th decision result.

4. The decision feedback equalizer according to claim 3, characterized in that, The decision element performs a decision on the corresponding summation result according to the following formula and then outputs the corresponding decision result: First judgment result = 2 * lower mean - second judgment result; The second judgment result = (lower mean + median mean) / 2; The third judgment result = (upper mean + middle mean) / 2; Fourth judgment result = 2 * average value - the aforementioned third judgment result; Wherein, the upper mean is the average value of the upper eye in the eye diagram of the PAM4 signal, the middle mean is the average value of the middle eye in the eye diagram of the PAM4 signal, and the lower mean is the average value of the lower eye in the eye diagram of the PAM4 signal.

5. The decision feedback equalizer according to claim 4, characterized in that, The process of obtaining the intermediate mean includes: processing the j-th input data through the j-th integrator to obtain the j-th initial intermediate value; and summing and averaging the first initial intermediate value to the N-th initial intermediate value to obtain the intermediate mean. The process of obtaining the upper mean includes: when it is determined that the j-th input data is greater than or equal to the intermediate mean, the j-th input data is processed by the j-th integrator to obtain the j-th initial upper value; the upper mean is obtained by summing and averaging all the initial upper values. The process of obtaining the lower mean includes: when it is determined that the j-th input data is less than the intermediate mean, the j-th input data is processed by the j-th integrator to obtain the j-th initial lower value; the lower mean is obtained by summing and averaging all the initial lower values.

6. The decision feedback equalizer according to claim 5, characterized in that, The j-th integrator includes: an adder, a flip-flop, a first multiplier, and a second multiplier; The first input terminal of the adder is connected to the j-th input data, and the second input terminal of the adder is connected to the output terminal of the second multiplier; The first input terminal of the flip-flop is connected to the output terminal of the adder, the second input terminal of the flip-flop is connected to the output terminal of the flip-flop, and the input terminal of the second multiplier is connected to the output terminal of the flip-flop. The flip-flop is used to add the output signal of the adder and the output signal of the flip-flop and delay them by one symbol before outputting. The input terminal of the first multiplier is connected to the output terminal of the flip-flop, and the output terminal of the first multiplier is the output terminal of the j-th integrator. The first multiplier and the second multiplier are used to adjust the bandwidth of the input signal.

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