Continuous time linear equalizer with multiple signal paths
By designing a CTLE that includes a broadband amplifier and a programmable resonant circuit, the problems of high power consumption and distortion of existing CTLEs are solved, achieving low power consumption and flexible frequency response, and adapting to the signal compensation effects of different communication standards.
Patent Information
- Application Number
- CN202210748921.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2022-02-18
- Filing Date
- 2022-06-28
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2042-06-28
AI Technical Summary
Existing continuous-time linear equalizers (CTLEs) suffer from high power consumption, excessive ringing that distorts the received signal and reduces the system bit error rate, and lack the flexibility to handle a wide range of data transmission rates.
The CTLE design employs a first circuit path and a second circuit path. The first circuit path is a broadband amplifier or broadband equalizer, and the second circuit path has a programmable resonant circuit. The outputs of the two are combined to compensate for signal power loss, and low power consumption and flexible frequency response are achieved through Gm units and summing circuits.
It achieves low power consumption and flexible frequency response, effectively compensating for signal power loss, reducing system bit error rate, and adapting to data transmission of different communication standards and speeds.
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Figure CN115695110B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The technology described herein relates generally to continuous time linear equalizers. BACKGROUND
[0002] When a signal propagates through a channel, signal power can be lost. A continuous time linear equalizer (CTLE) is a circuit that can compensate for the loss of signal power. SUMMARY
[0003] A continuous time linear equalizer (CTLE) can include a first circuit path having a step response that rises from a first initial value to a steady state value that is higher than the first initial value. The CTLE also includes a second circuit path in parallel with the first circuit path, the second circuit path having a step response that rises from a second initial value to a peak value and subsequently falls to a second steady state value that is approximately equal to the second initial value. The CTLE is configured to combine an output of the first circuit path and an output of the second circuit path.
[0004] The CTLE can be configured to receive a signal transmitted through a wired connection, the wired connection providing a channel for the signal.
[0005] A frequency response of the CTLE can be inversely proportional to a frequency response of the channel.
[0006] The step response of the first circuit path can have an overshoot to a first peak value before falling to the steady state value.
[0007] The first circuit path can include a Gm cell. Where Gm represents transconductance.
[0008] The Gm cell can perform a voltage to current conversion.
[0009] The Gm cell can be a first Gm cell, the first circuit path can include a first load coupled to an output of the Gm cell, and the first circuit path can include a second Gm cell that receives a signal from the first load.
[0010] The Gm cell can include a source degenerated differential pair.
[0011] The second circuit path can be programmable to change the step response of the second circuit path.
[0012] The second circuit path can include a tank circuit.
[0013] The tank circuit can include a programmable resistance.
[0014] The programmable resistance can set a height of a step response of the second circuit path.
[0015] The tank circuit can include a programmable capacitance.
[0016] The programmable capacitance can set a pulse width of a step response of the second circuit path.
[0017] The second circuit path can include a first Gm cell and a second Gm cell, wherein an output of the first Gm cell is coupled to the tank circuit and an input of the second Gm cell is connected to the tank circuit.
[0018] The CTLE can further include a summing circuit configured to combine the output of the first circuit path and the output of the second circuit path to produce a combined output.
[0019] The first Gm cell and / or the second Gm cell can include a differential pair.
[0020] The CTLE can further include a summing circuit configured to combine the output of the first circuit path and the output of the second circuit path to produce a combined output.
[0021] A continuous-time linear equalizer (CTLE) can include a first circuit path; a second circuit path in parallel with the first circuit path, the second circuit path having a step response with overshoot, wherein the CTLE is configured to combine an output of the first circuit path and an output of the second circuit path.
[0022] The first circuit path can include a wideband amplifier or a wideband equalizer.
[0023] The CTLE presented herein compensates for power loss of a signal by using the first circuit path and the second circuit path.
[0024] The foregoing overview is provided by way of explanation and is not limiting. BRIEF DESCRIPTION OF DRAWINGS
[0025] In the drawings, each identical or nearly identical component that is illustrated in various figures is represented with a like numeral. For purposes of clarity, not every component can be called out in every drawing. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the various aspects of the techniques and devices described herein.
[0026] Figure 1It is shown that the transmitter TX can transmit electrical signals over a hard wired channel.
[0027] Figure 2 It is shown that the channel has a frequency-dependent gain that decreases at higher frequencies.
[0028] Figure 3 It is shown that the CTLE can have a desired frequency-dependent gain that increases with frequency.
[0029] Figure 4 It is shown that a CTLE including a first circuit path, a second circuit path, and a summing circuit according to some embodiments.
[0030] Figure 5 It is shown that a step response of the combined output of the first circuit path, the second circuit path, and the CTLE.
[0031] Figure 6 It is shown that another example of a desired step response includes a portion of constant gain between frequencies fp1 and fz2.
[0032] Figure 7 It is shown that the first circuit path 10 can be designed to have a step response that includes overshoot.
[0033] Figure 8 It is shown that an example implementation of a CTLE according to some embodiments.
[0034] Figure 9 It is shown that an example of a summing circuit according to some embodiments.
[0035] Figure 10 It is shown that an example of a step response and a frequency response of a summing circuit according to some embodiments. Figure 9 including overshoot in the step response.
[0036] Figure 11 It is shown that another example implementation of a CTLE according to some embodiments.
[0037] Figure 12 It is shown that an example of a Gm cell according to some embodiments. DETAILED DESCRIPTION
[0038] CTLEs can be used in various applications to compensate for power loss as signals propagate through a channel. For example, as shown in FIG. 1, a transmitter TX can transmit electrical signals over a hard wired channel. Figure 1As shown, the transmitter TX can transmit electrical signals over a solid wired channel to an analog front-end (AFE), which can include a CTLE. The channel has a frequency dependent gain that decreases at higher frequencies, as shown Figure 2 As shown, the short search channel can have a relatively low insertion loss at the Nyquist frequency (e.g., -5 dB), while the long search channel can have a higher insertion loss at the Nyquist frequency (e.g., -35 dB). To compensate for the frequency dependent gain of the channel, a CTLE can be included in the receiver (RX). The CTLE can have a desired frequency dependent gain that rises with frequency, as shown Figure 3 As shown, the gain of the CTLE rises from G1 to G2 between frequencies fzand fp1. Figure 3
[0039] The inventors have recognized and appreciated that existing CTLEs can consume power, can distort received signals, and / or can produce excessive ringing that reduces system bit error rate. In addition, existing CTLEs lack flexibility to handle a wide range of data transmission rates (e.g., 10 Gbps to 112 Gbps).
[0040] In some embodiments, the CTLE 100 can include at least a first circuit path 10, a second circuit path 20, and a summing circuit 30, as shown Figure 4 The first circuit path can be a wideband amplifier or a wideband equalizer. As shown in FIG. 5, the first circuit path 10 can have a step response 10sr that rises from an initial value to a steady state value. For example, the high frequency gain G2 of the first circuit path 10 can be the same as the low frequency gain G1 of the first circuit path 10, and the step response 10sr represents the time domain response when the high frequency gain G2 is the same as the low frequency gain G1. The second circuit path 20 can have a step response 20sr that rises from an initial value, reaches a peak value, and then falls to approximately the initial value. In some embodiments, the initial value and the final value of the step response of the second circuit path can be zero or approximately zero. In this context, the term "approximately the initial value" means that the error from the initial value is within a range of 20% or less of the pulse height, e.g., the error from the initial value is 10% or 5% of the pulse height, and the term "approximately zero" means that the error from zero is within a range of 20% or less of the pulse height, e.g., the error from zero is 10% or 5% of the pulse height. The outputs of the first and second circuit paths 10, 20 are combined by the summing circuit 30. As shown in FIG. 5, the CTLE 100 can have a combined step response 100sr at the output of the CTLE 100 that can approximate the desired step response shown in FIG. 5. Figure 5 As shown in FIG. 5, the CTLE 100 can have a combined step response 100sr at the output of the CTLE 100 that can approximate the desired step response shown in FIG. 5. Figure 3 As shown in FIG. 5, the CTLE 100 can have a combined step response 100sr at the output of the CTLE 100 that can approximate the desired step response shown in FIG. 5.
[0041] Figure 6 An example of another desired CTLE step response is shown that includes a portion of constant gain between frequencies fp1 and fz2. To approximate the desired step response shown in FIG. 6, the first circuit path 10 can be designed to have a step response 10sr that includes an overshoot, as shown in FIG. 6. Figure 6 As shown in FIG. 6, the CTLE 100 can have a combined step response 100sr at the output of the CTLE 100 that can approximate the desired step response shown in FIG. 6. Figure 7 As shown in FIG. 6, the CTLE 100 can have a combined step response 100sr at the output of the CTLE 100 that can approximate the desired step response shown in FIG. 6.
[0042] Figure 8 An example implementation CTLE 100a is shown in accordance with some embodiments.
[0043] The first circuit path 10a may include a Gm unit Gm1, followed by a load Load1 and a second Gm unit Gm2. Gm1 may perform a voltage-to-current conversion (with or without gain). Load Load1 may be any suitable load, and in some examples may be, for example, a resistor, or a network comprising a combination of one or more resistors, capacitors, and / or inductors. Load1 may convert a current signal from Gm1 into a voltage signal. Gm2 may receive a voltage signal from Load1 and convert it into a current signal, which is then summed by a summing circuit 30a, in this example, which is the load Load2. In some embodiments, including Load1 and Gm2 in the first circuit path 10a may help reduce timing mismatch relative to the second circuit path 20a, which may be advantageous at high frequencies.
[0044] The second circuit path 20a may include a Gm unit Gm3, which can perform voltage-to-current conversion (with or without gain). The current signal from Gm3 is received by a resonant circuit 40, which in this example includes L1, C1, and R1 connected in parallel and grounded. However, any circuit element configuration can be used in the resonant circuit 40. The resonant circuit 40 can produce an overshoot characteristic of the step response of the second circuit path 20, such as... Figure 5 As shown. In some embodiments, the second circuit path 20a can be programmable, allowing the height and width of the step response 20sr to be varied. In the example of Figure 8, resistor R1 is programmable to change the step response. Specifically, changing resistor R1 changes the pulse height of the step response ( Figure 5 A higher R1 value produces a step response with a higher peak value, while a lower R1 value produces a step response with a lower peak value. Capacitor C1 can be programmable to change the step response, particularly the pulse width of the step response. Figure 5 A higher C1 value produces a step response with a wider pulse width, while a lower C1 value produces a step response with a smaller / narrower pulse width. The resonant circuit 40 can generate a voltage signal, which is then received by the Gm unit Gm4, which converts the voltage signal into a current signal. A summing circuit 30a sums the current signals from both the first circuit path 10a and the second circuit path 20a; in this example, the summing circuit 30a is the load Load 2. Load 2 can be a resistor, a capacitor-inductor, or any combination thereof. In some embodiments, Load 2 can be designed to produce a small overshoot in the step response. Figure 9An example of a load Load 2, according to some embodiments, is shown, e.g., one end of inductor L2 is coupled to the output of Gm2 and the output of Gm4, the other end of inductor L2 is coupled to one end of inductor L3, one end of inductor L4 is coupled to the other end of inductor L2 and the one end of inductor L3, resistor R2 is coupled between the other end of inductor L4 and ground, resistor R2 is tunable. Figure 10 An example of a step response and a frequency response of a summing circuit load 2, according to some embodiments, is shown, including overshoot in the step response.
[0045] In some embodiments, multiple second circuit paths 20 can be connected in parallel. The insertion loss of the channel can be measured, and the strength (e.g., gain) of the second circuit path can be set based on the measured insertion loss. In some embodiments, multiple second circuit paths can be connected in parallel, and one or more second circuit paths can be enabled and / or disabled based on the measured insertion loss.
[0046] Figure 11 Another example implementation CTLE 100b, according to some embodiments, is shown. In this example, circuit path 10b can include Gm1, and can be derived from Figure 8 Load1 and Gm2 can be omitted from the example ofCircuit path 20b can be the same or similar to circuit path 20a. Such embodiments can include fewer components than the example of Figure 8
[0047] According to design considerations, Figure 8 and Any Gm cell shown in 11 may have gain or no gain.
[0048] In the above embodiments, the frequency response of the CTLE can be inversely proportional to the frequency response of the channel.
[0049] Figure 12 An example of a Gm cell, according to some embodiments, is shown. Figure 8 and Any Gm cell shown in Figure 9 may be derived from Figure 12The Gm cells shown in the middle can be implemented by any of the Gm cells, or by other Gm cells. In some examples, since differential pairs have high power efficiency, the Gm cells Gm3 and / or Gm4 of the circuit path 20 can be implemented as differential pairs, the circuit path 20 can handle high frequency signals, which reduces power consumption. Among other things, high frequency signals typically have small amplitudes, so a non-linear amplifier, such as a simple differential pair, can be used to save power. Even though the input / output characteristics of this differential pair are non-linear, if the amplitude of the input signal is small, the contribution of the non-linearity to the system level performance can be negligible. The Gm cells Gm1 and / or Gm2 of the first circuit path 10 can be implemented by source-degenerated differential pairs, which have high linearity.
[0050] Additional aspects
[0051] Various aspects of the devices and techniques described herein can be used alone, in combination, or in various arrangements not specifically discussed in the embodiments described in the foregoing description, and therefore, are not limited to the details and arrangements set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment can be combined with aspects described in other embodiments in any manner.
[0052] The use of sequential terminology such as first, second, third, etc., to modify the elements of a claim, or the use of "step" followed by a numeral, does not imply that a particular order between elements or steps is required or important, unless specifically stated in the claim. The inclusion of a numerical recitation in any aspect of this specification is not intended to limit the scope of that aspect or to imply that the numerical recitation is an important or essential characteristic.
[0053] In addition, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
Claims
1. A continuous-time linear equalizer (CTLE), characterized by, comprises: a first circuit path having a step response that rises from a first initial value to a steady state value that is higher than the first initial value; and a second circuit path in parallel with the first circuit path, the second circuit path having a step response that rises from a second initial value to a peak value and subsequently falls to a second steady state value that is approximately equal to the second initial value; wherein the CTLE is configured to combine an output of the first circuit path and an output of the second circuit path. The CTLE is configured to receive a signal transmitted over a wired connection, the wired connection providing a channel for the signal.
2. The CTLE of claim 1, wherein, A frequency response of the CTLE is inversely proportional to a frequency response of the channel.
3. The CTLE of claim 2, wherein, The step response of the first circuit path has an overshoot that reaches a first peak value before falling to the steady state value.
4. The CTLE of claim 1, wherein, The first circuit path comprises a Gm cell.
5. The CTLE of claim 1, wherein, The Gm cell performs a voltage-to-current conversion. 6.The CTLE of claim 5, wherein, The Gm cell is a first Gm cell, the first circuit path includes a first load that couples an output of the Gm cell, and the first circuit path includes a second Gm cell that receives a signal from the first load. 7.The CTLE of claim 6, wherein, The Gm cell comprises a source degenerated differential pair. 8.The CTLE of claim 5, wherein, The second circuit path is programmable to change a step response of the second circuit path.
9. The CTLE of claim 1, wherein, The second circuit path comprises a resonant circuit.
10. The CTLE of claim 9, wherein, The resonant circuit comprises a programmable resistance.
11. The CTLE of claim 10, wherein, The programmable resistance sets a height of the step response of the second circuit path.
12. The CTLE of claim 11, wherein, The resonant circuit comprises a programmable capacitance.
13. The CTLE of claim 10, wherein, The programmable capacitance sets a pulse width of the step response of the second circuit path.
14. The CTLE of claim 13, wherein, The second circuit path comprises a first Gm cell and a second Gm cell, wherein an output of the first Gm cell couples the resonant circuit and an input of the second Gm cell is connected to the resonant circuit.
15. The CTLE of claim 10, wherein, The first Gm cell and / or the second Gm cell comprises a differential pair.
16. The CTLE of claim 15, wherein, Further comprising a summing circuit configured to combine an output of the first circuit path and an output of the second circuit path to produce a combined output; the second initial value of the step response of the second circuit path is approximately zero.
17. The CTLE of claim 1 or 15, wherein, The first circuit path comprises a wideband amplifier or a wideband equalizer.
18. The CTLE of claim 1, wherein,