Detection Method for Transmission Fault of 2711 Chip

Abstract

Detection method for transmission faults of 2711 chips, which relates to the technical field of chip fault detection. It solves the problems that in the application process of existing 2711 chips, the controller only connects to the sending end of the 2711 chip and does not connect to the control end, making it impossible to detect the working state of the chip and inconvenient to conduct bit error rate tests under the state of pseudo-random codes. In the present invention, first, a 2711 data transmission ground detection board is used. The sending end sends a regular self-check image, and whether the parallel data decoded by each channel is correct is detected through chipscope. Then, for the channels with abnormal reception, it is judged by detecting the ground resistance of the chip pins, the power supply voltage, the high and low levels of the control signal, and the jitter of the clock; it is also judged whether the control signal sent by the FPGA is correct by sending the synchronization word and the inverted signal of the synchronization word. In the method of the present invention, by only sending the synchronization code process, it can be judged whether it is poor transmission performance or there are errors; it can also map through the error characters at the receiving end to locate the cause of the error.

Description

Technical Field

[0001] The present invention relates to a method for detecting transmission faults of 2711 chips, and particularly to a method for detecting transmission faults of 2711 based on aerospace applications. Background Art

[0002] Usually, multiple 2711 chips are used in cameras to transmit image data. As long as there is an abnormality in the reception of one chip in the quick-look ground inspection device, the image will not be displayed, and it is difficult to specifically locate the fault at the sending end. Additionally, in applications where only output data is sent without receiving data, in order to save resources, the controller is only connected to the parallel data sending end of the 2711 chip and not to the parallel data receiving end of the 2711. Moreover, control pins such as loop-back and pre-emphasis functions are directly set to fixed levels without connecting to the controller. Therefore, the detection scheme for the chip working state through the internal loop-back function of the chip cannot be achieved, and the bit error rate test under the pseudo-random code state cannot be performed either. Summary of the Invention

[0003] In order to solve the problems that in the application process of existing 2711 chips, the controller is only connected to the sending end of the 2711 chip and not to the control end, the detection of the chip working state cannot be achieved, and it is not convenient to perform the bit error rate test under the pseudo-random code state, etc., the present invention provides a method for detecting transmission faults of 2711 chips.

[0004] A method for detecting transmission faults of 2711 chips, which is implemented through a detection system for transmission faults of 2711 chips; the fault detection system includes a sending unit and a receiving unit, and the sending unit includes a 2711 sending controller, a 2711 sending chip group, and a sending connector group;

[0005] The receiving unit includes a 2711 receiving connector group, a 2711 receiving chip group, and a 2711 parsing controller; the 2711 sending controller sends parallel image data and control signals to the 2711 sending chip group, and the 2711 sending chip group outputs high-speed serial image data, which is sent to the receiving connector group through the sending connector group and then through a connection cable group, and finally sent to the 2711 receiving chip group; under the action of the 2711 parsing controller, the 2711 receiving chip group decodes the received high-speed serial image data and sends it to the 271 decoding controller, and by monitoring the internal state of the 271 decoding controller, the faulty 2711 channel is checked and located;

[0006] The specific process of this method is as follows:

[0007] The sending unit sends the self-calibration image and uses chipscope to detect whether the parallel data decoded by each channel is correct; then for the channels with abnormal reception, it judges by detecting the ground resistance of the chip pins, the supply voltage, the high and low levels of the control signal, and the jitter of the clock; and judges whether the control signal sent by the FPGA is correct by sending the synchronization word and the inverted signal of the synchronization word.

[0008] Advantages of the present invention:

[0009] 1. In the method of the present invention, by verifying the step that all control signals of the controller have been output: namely: 1) Send the self-calibration pattern and use the chipscope function to check whether the synchronization code, frame header, frame tail and data of the transmitted data in the blanking stage are correct; use an oscilloscope to test each input pin of 2711 to see if there are waveforms with high and low level changes; 2) Only send the synchronization character, set the K-code high byte indication signal TKMSB and the K-code low byte indication signal TKLSB to 0 and 1 respectively, and use a multimeter to test the high and low levels of the 2711 input pins to judge whether they are consistent with the input control signal of the FPGA; only send the inverted signal of the synchronization character bit by bit, set TKMSB and TKLSB to 1 and 0 respectively, and use a multimeter to test the high and low levels of the 2711 input pins to judge whether they are consistent with the input control signal of the FPGA. Through the dynamic signal input and covering the two static level states, it is convenient to confirm whether the control signal of the FPGA has been sent.

[0010] 2. By only sending the synchronization code process, it can be judged whether it is poor transmission performance or there is an error; it can also map through the error characters at the receiving end to locate the cause of the error.

[0011] 3. According to the data analysis, then detect the pins by optical and X-ray, then use a multimeter to test the static characteristics, and finally use a multimeter and an oscilloscope to test the characteristics after power-on, so as to minimize the possible damage to the product during the process of troubleshooting problems. Description of the drawings

[0012] Figure 1 is the principle block diagram of the 2711 transmission fault detection system described in the present invention;

[0013] Figure 2 is the flowchart for troubleshooting abnormal problems. Specific implementation manners

[0014] Combined with Figure 1 and Figure 2 to illustrate this implementation manner, a method for detecting transmission faults of the 2711 chip, which method is as follows Figure 1Implementation of the 2711 transmission fault detection system shown. The fault detection system of the 2711 transmission fault detection system includes a sending unit and a receiving unit. The sending unit includes a 2711 sending controller, a 2711 sending chipset, and a sending connector group;

[0015] The receiving unit includes a 2711 receiving connector group, a 2711 receiving chipset, and a 2711 parsing controller; the 2711 sending controller sends parallel image data and control signals to the 2711 sending chipset. The 2711 sending chipset outputs high-speed serial image data, which is sent through the sending connector group and then through a connection cable group to the receiving connector group, and finally sent to the 2711 receiving chipset; under the action of the 2711 parsing controller, the 2711 receiving chipset decodes the received high-speed serial image data and sends it to the 2711 decoding controller. By monitoring the internal state of the 271 decoding controller, the faulty 2711 channels can be checked and located, and further positioning can be carried out.

[0016] As Figure 2 shown, the fault detection method of this embodiment is implemented by the following steps:

[0017] 1) Connect the circuit board that cannot collect images according to the Figure 1 connection method shown, send a self-calibration pattern, monitor the LSB, MSB, and parallel image data after decoding for each channel, and determine whether there are abnormalities in each received channel; confirm that the cable is normal and the receiving part is normal before connection; if normal, it means the problem lies in the fast view or the receiving part, and check the differences between the fast view and the receiving part;

[0018] 2) If the 2711 receiving chip completely decodes and supplements the control signal and parallel data, it is necessary to check whether the power supply of the 2711 chip is correct; if the 2711 receiving chip can decode the control signal and parallel data, it is necessary to check whether the power supply voltage of the 2711 chip has reached the recommended voltage value and whether the ripple is small enough;

[0019] 3) If the power supply of the 2711 chip is abnormal, handle the abnormal power supply fault of the 2711 power supply, check for connectivity faults such as poor soldering and abnormal power control signals; check the solder joints and measure the resistance to ground in real time; use a multimeter to measure the resistance to ground of the 2711 chip corresponding to the abnormal channel, and measure whether there is an abnormal resistance value. If the resistance value deviates from that of other chips by more than 50%, the resistance value to ground is abnormal, and check for poor soldering or short circuit;

[0020] 4) If the power supply voltage of the 2711 chip does not reach the recommended voltage or the ripple is too large, adjust the power supply voltage to improve the power supply voltage fluctuation;

[0021] 5) If the power supply of the 2711 chip is normal but the control signal and parallel data cannot be decoded completely, check whether the control signals (enable, loopback) of the 2711 chip are valid and whether there is a clock. If not, handle the abnormal invalid level fault of the control signal of the 2711 chip, and check the connectivity faults such as virtual soldering by checking the solder joints and measuring the resistance to ground;

[0022] 6) If the power supply of the 2711 chip is normal but the decoded control signal and parallel data are incorrect, check whether the input clock jitter of the 2711 chip is small enough. If the clock jitter is large, improve the quality of the input clock;

[0023] 7) If the power supply of the 2711 chip is normal but the control signal and parallel data cannot be decoded completely, the control signals (enable, loopback) of the 2711 chip are valid, and the clock is valid, check whether the differential output of the 2711 chip is connected to the corresponding pins of the receiving 2711 chip group. If not, handle the abnormal connectivity fault of the output differential signal of the 2711 chip, and check the connectivity faults such as virtual soldering by checking the solder joints and measuring the resistance to ground. If it is connected, return to step (1);

[0024] 8) If the power supply of the 2711 chip is normal but the decoded control signal and parallel data are incorrect and the input clock jitter is small enough, check whether the parallel data and control signal decoded in the state of only inputting the synchronization codeword by the 2711 chip are accurate. If not, check whether there is virtual soldering on the parallel data pins and the control pin TKLSB. If so, check whether the parallel data and control signal decoded in the state of adding a small amount of frame header and frame tail are accurate;

[0025] 9) If there is virtual soldering on the parallel data pins and the control pin TKLSB, handle the virtual soldering problem of the parallel data pins and the control pin TKLSB. If there is no virtual soldering, it means that the chip transmission performance is poor, and replace the chip;

[0026] 10) If the parallel data and control signal decoded in the state of adding a small amount of frame header and frame tail are correct, judge whether the parallel data and control signal decoded in the state of adding a small amount of data are correct. If it is still correct, it means that the chip transmission performance is poor, replace the chip, or modify the transmission protocol to reduce the synchronization code interval. If not, it means that the chip transmission performance is poor, and replace the chip.

[0027] 11) If the parallel data and control signal decoded in the state of adding a small amount of frame header and frame tail are incorrect, check whether there is virtual soldering on TKMSB. If there is virtual soldering, handle the virtual soldering problem of TKMSB. If there is no virtual soldering, it means that the chip transmission performance is poor, and replace the chip.

[0028] In this embodiment, the sending control program adopts a simplified program with a resource occupancy rate not exceeding 50%;

[0029] In this embodiment, the steps for verifying that all control signals of the verification controller have been output are as follows: 1) Send a self-check pattern, and check whether the synchronization code, frame header, frame tail, and data of the transmitted data are correct during the blanking stage through the chipscope function; use an oscilloscope to test each input pin of the 2711 to see if there are waveforms with high and low level changes; as shown in Table 1

[0030] Table 1 Definition of control characters for the data transmission interface

[0031]

[0032] In this embodiment, only the synchronization character is sent, TKMSB and TKLSB are respectively set to 0 and 1, and a multimeter is used to test the high and low levels of the input pins of the 2711 to determine whether they are consistent with the input control signals of the FPGA; only the inverted signal of the synchronization character bit by bit is sent, TKMSB and TKLSB are respectively set to 10, and a multimeter is used to test the high and low levels of the input pins of the 2711 to determine whether they are consistent with the input control signals of the FPGA;

[0033] In this embodiment, the specific operations for judging faults by sending synchronization characters, frame headers, and frame tail data are as follows:

[0034] 1) If only the synchronization character is sent, the decoded LSB and MSB at the receiving end are relatively random high and low levels different from those at the sending end, while the parallel data is a constant value and satisfies the mapping relationship with the synchronization code, then it is necessary that there is a dry joint in the LSB pin; if the LSB is correct and only the parallel data is wrong and cannot be synchronized, then the clock and power supply need to be checked;

[0035] 2) If sending the synchronization character is okay, then add the frame header and frame tail at equal intervals to see if there are any abnormalities;

[0036] 3) If there are no abnormalities after adding the frame header and frame tail, then gradually add image data and increase the number to see the number at which abnormalities start to occur.

[0037] In this embodiment, the 2711 transmission controller and the 2711 parsing controller use virtex 6 devices and their internal resources; the 2711 transmission chip combination and the 2711 receiving chip group use the BLK2711 chips of the 772nd Institute; the transmission connector group and the receiving connector group use the 8-core micro coaxial connectors of the 796th Factory; the connection cable group uses the 8-core micro coaxial cable of the 796th Factory.

Claims

1. Detection method for chip transmission failure, characterized in that: This method is implemented by a detection system for transmission faults of a 2711 chip; the detection system includes a sending unit and a receiving unit, and the sending unit includes a 2711 sending controller, a 2711 sending chip group and a sending connector group; The receiving unit includes a 2711 receiving connector group, a 2711 receiving chip group and a 2711 parsing controller; the 2711 sending controller sends parallel image data and control signals to the 2711 sending chip group, and the 2711 sending chip group outputs high-speed serial image data, which is sent to the receiving connector group through the sending connector group and then through the connection cable group, and finally sent to the 2711 receiving chip group; under the action of the 2711 parsing controller, the 2711 receiving chip group decodes the received high-speed serial image data and sends it to the 2711 decoding controller, and checks and locates the faulty 2711 channels by monitoring the internal state of the 271 decoding controller; The specific process of this method is as follows: The sending unit sends a self-check image to detect whether the parallel data after decoding of each channel is correct through chipscope; then for the channels with abnormal reception, it is judged by detecting the ground resistance of the chip pins, the supply voltage, the high and low levels of the control signal, and the jitter of the clock. And it is judged whether the control signal sent by the FPGA is correct by sending the synchronization word and the inverted signal of the synchronization word.

2. The detection method for the transmission failure of the 2711 chip according to claim 1, wherein: For the abnormally received channels, the specific detection process is as follows: Step 1: Use a multimeter to measure the ground resistance of the 2711 chip corresponding to the abnormal channel, and measure whether there is an abnormal resistance value. If the resistance value deviates from that of other chips by more than 50%, the ground resistance value is abnormal, and check whether there is virtual soldering or short circuit. Step 2: Use a multimeter to measure the voltage value of the power supply pin of the 2711 chip corresponding to the abnormal channel. If it exceeds the voltage range allowed by the chip manual, it is considered that the power supply is abnormal and needs to be processed; measure the voltage value of the control pin to see if it is the expected high level or low level. Step 3: Use a multimeter to measure whether the differential sending end of the 2711 chip corresponding to the abnormal channel is conducting with the corresponding connector in the sending connector group. Step 4: Use an oscilloscope to measure the power supply ripple of the 2711 chip corresponding to the abnormal channel to see if there is a problem of excessive fluctuation. Step 5: Use an oscilloscope to measure whether the clock frequency of the 2711 chip corresponding to the abnormal channel is within the nominal range and whether there is obvious jitter. Step 6: Verify that all control signals of the controller have been output. Step 7: Use a test program with low resource occupancy to judge the fault by sending synchronization characters, frame headers and frame tail data.

3. The detection method for the transmission fault of the 2711 chip according to claim 2, wherein: The specific process of Step 6 is as follows: Step 6-1: Send a self-check pattern, and check whether the synchronization character, frame header, frame tail and data of the transmitted data in the blanking stage are correct through the chipscope function; use an oscilloscope to test each input pin of the 2711 to see if there is a waveform with high and low level changes. Step 62: Only send synchronization characters. Set the K-code high byte indication signal TKMSB and the K-code low byte indication signal TKLSB to 0 and 1 respectively. Use a multimeter to measure the high and low levels of the 2711 input pin to determine whether they are consistent with the input control signal of the FPGA; only send the bitwise inverted signal of the synchronization character, set TKMSB and TKLSB to 1 and 0 respectively, and use a multimeter to measure the high and low levels of the 2711 input pin to determine whether they are consistent with the input control signal of the FPGA.

4. The detection method for the transmission failure of the 2711 chip according to claim 2, wherein: In Step 7, the specific process of judging faults by sending synchronization characters, frame headers, and frame tail data is as follows: If only synchronization characters are sent, the K-code high byte indication signal TKMSB and the K-code low byte indication signal TKLSB decoded at the receiving end are relatively chaotic high and low levels different from those at the sending end, and the parallel data is a constant value and satisfies the mapping relationship of the data code with the synchronization character, then there is a dry joint on the TKLSB pin; if there is no problem with the TKLSB pin, the clock and power supply need to be checked; If sending synchronization characters is okay, then add the frame header and frame tail at equal intervals to determine whether there is any abnormality; If there is no abnormality when adding the frame header and frame tail, then gradually add image data and increase the number to determine the number at which abnormalities start to occur.

5. The detection method for the transmission failure of the 2711 chip according to claim 2, wherein: In Step 7, the occupancy rate of the test program does not exceed 50%.

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