Semiconductor structure, forming method thereof, and three-dimensional memory

Abstract

The invention discloses a semiconductor structure, a method for forming the same, and a three-dimensional memory, the semiconductor structure comprising: a substrate having a read word line and a read bit line; a read transistor, the read transistor comprising a first channel layer and a first gate layer, the first channel layer at least partially surrounding the first gate layer from the bottom to the top of the first gate layer, the read transistor being coupled to the read word line and the read bit line respectively; a write word line and a write bit line; a write transistor, the write transistor being located on the read transistor, the write transistor comprising a second channel layer and a second gate layer, the second channel layer at least partially surrounding the second gate layer from the bottom to the top of the second gate layer, the write transistor being coupled to the write bit line, the write word line, and the first gate layer respectively. According to the semiconductor structure of the embodiment of the present invention, the control capability and integration can be improved, which is conducive to further miniaturization.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a three-dimensional memory having the same. Background Art

[0002] Unlike ordinary DRAM, which is composed of transistors and capacitors, 2T0C semiconductor memory is composed of two transistors, one of which has a gate that can form a natural capacitor and allow charge to be stored and flowed. However, the existing 2T0C semiconductor memory has relatively poor integration and poor control capabilities. Summary of the Invention

[0003] The object of the present invention is to provide a method for forming a semiconductor structure, which can increase the effective channel area of ​​the semiconductor structure, improve the control capability and integration, and also achieve further miniaturization of the semiconductor structure.

[0004] According to an embodiment of the present invention, a method for forming a semiconductor structure includes: providing a substrate having a read word line and a read bit line; forming a read transistor having a first channel layer and a first gate layer, the first channel layer at least partially surrounding the first gate layer from the bottom to the top of the first gate layer, and the read transistor being coupled to the read word line and the read bit line, respectively; forming a write word line and a write bit line on the read transistor; forming a write transistor having a second channel layer and a second gate layer, the write transistor passing through the write word line and the write bit line and being located on the read transistor and connected to the first gate layer, the second channel layer of the write word line at least partially surrounding the second channel gate layer from the bottom to the top of the second gate layer; forming a write bit line and a write word line on the write transistor, the write bit line and the write word line being connected to the second channel gate layer; wherein one end of the write transistor is connected to the gate of the read transistor.

[0005] According to some embodiments of the present invention, the base includes a substrate and the read word line and read bit line formed on the substrate, and the steps of forming the base include: providing a substrate, forming a first oxide layer on the substrate; etching the first oxide layer to form a read word line groove; filling the read word line groove to form the read word line; and forming a second oxide layer, a read bit line and a third oxide layer in sequence on the read word line and the first oxide layer.

[0006] According to some embodiments of the present invention, the step of forming a read transistor having a first channel layer and a first gate layer includes: forming a plurality of read through holes to expose the read word line; and sequentially forming a first channel layer, a first gate dielectric layer, and a first gate layer in the read through holes and on a portion of the surface of the substrate surrounding the read through holes.

[0007] According to some embodiments of the present invention, the step of forming the read transistor further includes: forming a first connection layer on the first gate layer, wherein the first connection layer, the first channel layer, the first gate dielectric layer and the first gate layer fill the read through hole.

[0008] According to some embodiments of the present invention, in the step of forming a plurality of read vias to expose the read word lines, the read vias are at least partially located within the read word lines.

[0009] According to some embodiments of the present invention, the steps of sequentially forming a first channel layer, a first gate dielectric layer, a first gate layer and a first connection layer on a portion of the surface of the substrate in and surrounding the read through hole include: forming a first initial channel layer on the surface of the substrate and the inner surface of the read through hole; sequentially forming a first initial gate dielectric layer, a first initial gate layer and a first initial connection layer on the surface of the first initial channel layer; patterning the first initial channel layer, the first initial gate dielectric layer, the first initial gate layer and the first initial connection layer, retaining a portion of the first initial channel layer, the first initial gate dielectric layer, the first initial gate layer and the first initial connection layer located in the read channel and surrounding the read through hole to form a plurality of the read transistors separated from each other.

[0010] According to some embodiments of the present invention, the step of patterning the first initial channel layer, the first initial gate dielectric layer, the first initial gate layer, and the first initial connection layer includes: etching the first initial channel layer, the first initial gate dielectric layer, the first initial gate layer, and the first initial connection layer to form first isolation trenches extending along a first direction, the first isolation trenches being located between the read vias; and filling the first isolation trenches to form a first isolation structure;

[0011] The first initial channel layer, the first initial gate dielectric layer, the first initial gate layer, the first initial connection layer and the first isolation structure are etched to form a second isolation trench extending along a second direction, wherein the second direction is perpendicular to the first direction; and the second isolation trench is filled to form a second isolation structure.

[0012] According to some embodiments of the present invention, in the step of forming the first isolation trench, the first isolation trench penetrates the read bit line and is located above the read word line.

[0013] According to some embodiments of the present invention, the step of forming a write bit line on the read transistor includes: forming a fourth oxide layer on the read transistor; etching the fourth oxide layer to form a write bit line trench; and filling the write bit line trench to form the write bit line.

[0014] According to some embodiments of the present invention, the method for forming the semiconductor structure further includes: forming a fifth oxide layer on the write bit line and the fourth oxide layer.

[0015] According to some embodiments of the present invention, the step of forming a write transistor having a second channel layer and a second gate layer includes: etching the fifth oxide layer, the write bit line and the fourth oxide layer to form a write through hole exposing the read transistor; forming a second gate dielectric layer on the inner wall surface of the side wall of the write through hole to sequentially form a second channel layer, a second gate dielectric layer and a second gate layer; forming a second channel layer on the surface of the second gate dielectric layer and the surface of the read transistor, the write word line at least partially surrounds the second channel layer to form the write transistor, the second channel layer at least partially surrounds the second gate layer, and the second gate dielectric layer is located between the second channel layer and the second gate layer.

[0016] According to some embodiments of the present invention, the step of forming a write word line on the write transistor includes:

[0017] A sixth oxide layer is formed on the surface of the write transistor and the surface of the fifth oxide layer; the sixth oxide layer is etched to form a write word line trench exposing the write transistor; and the write word line trench is filled to form the write bit line.

[0018] The present invention also provides a semiconductor structure.

[0019] According to an embodiment of the present invention, a semiconductor structure includes: a substrate having a read word line and a read bit line; a read transistor, the read transistor including a first channel layer and a first gate layer, the first channel layer at least partially surrounding the first gate layer from the bottom to the top of the first gate layer, and the read transistor is coupled to the read word line and the read bit line, respectively; a write word line and a write bit line; a write transistor, the write transistor is located on the read transistor, the write transistor including a second channel layer and a second gate layer, the write bit line at least partially surrounding the second channel layer from the bottom to the top of the second gate layer, and the write transistor is coupled to the write bit line, the write word line and the first gate layer, respectively, wherein one end of the write transistor is connected to the gate of the read transistor.

[0020] According to some embodiments of the present invention, a read through hole is defined in the substrate, passing through the read bit line and exposing the read word line. The read transistor is located in the read through hole and partially located on the substrate surface surrounding the read through hole.

[0021] According to some embodiments of the present invention, the semiconductor structure further includes a first gate dielectric layer, the first channel layer, the first gate dielectric layer and the first gate layer are stacked in sequence, and the first channel layer is located on the inner wall surface of the read through hole.

[0022] According to some embodiments of the present invention, the read transistor further includes a first connection layer, the first connection layer is located on a surface of the first gate layer, and the write transistor is located on the first connection layer.

[0023] According to some embodiments of the present invention, the semiconductor structure further includes: a first isolation structure, which extends along a first direction and is located between the read transistors, and extends downward to be located between adjacent read bit lines; and a second isolation structure, which extends along a second direction and is located on the substrate to surround the read transistor together with the first isolation structure.

[0024] According to some embodiments of the present invention, it also includes: an isolation layer, the isolation layer is formed on the substrate, the write bit line is located in the isolation layer, the isolation layer is provided with a write through hole passing through the isolation layer and the write bit line, the write through hole is located on the read transistor, and the write transistor is located in the write through hole.

[0025] According to some embodiments of the present invention, the write transistor further includes a second gate dielectric layer, and the second channel layer, the second gate dielectric layer and the second gate layer are sequentially stacked on the inner wall surface of the write through hole.

[0026] According to some embodiments of the present invention, the write word line is formed on the write transistor and connected to the second gate layer.

[0027] According to some embodiments of the present invention, the first channel layer and the second channel layer are both indium gallium zinc oxide layers. The present invention also provides a three-dimensional memory. A three-dimensional memory according to an embodiment of the present invention includes a plurality of stacked semiconductor structures described in the above embodiments.

[0028] Therefore, according to the semiconductor structure and formation method of the embodiment of the present invention, the first channel layer at least partially surrounds the first gate layer, the read transistor can form a vertical ring channel device structure, the write bit line at least partially surrounds the second channel layer, the write transistor can be formed as a ring gate transistor, the read word line and the read bit line are respectively coupled to the source and drain ends of the read transistor, and the write transistor is correspondingly formed on the read transistor, that is, the write transistor and the read transistor are stacked, the first gate layer of the read transistor is connected to the write transistor through the first connection layer, so that the source and drain ends of the write transistor are respectively coupled to the first connection layer and the write word line, and the semiconductor structure can be formed as a semiconductor 2T0C structure, the two transistors are respectively a read transistor with a vertical ring channel structure and a write transistor with a ring gate transistor structure, thereby increasing the effective channel area of ​​the two transistors, improving the channel control capability, and thereby improving the performance of the semiconductor structure, and also improving the integration of the semiconductor structure, which is conducive to further miniaturization of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0030] Figure 2-Figure 12 1 and 2 are cross-sectional views corresponding to various steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0031] Reference numerals:

[0032] 1000: Three-dimensional memory

[0033] 100: semiconductor structure;

[0034] 1: base, 11: substrate, 12: first oxide layer, 13: read word line, 14: read bit line, 15: second oxide layer, 16: read word line trench, 17: third oxide layer;

[0035] 2: read transistor, 21: first channel layer, 22: first gate dielectric layer, 23: first gate layer, 24: first connection layer;

[0036] 31: read via, 32: first initial channel layer, 33: first initial gate dielectric layer, 34: first initial gate layer, 35: first initial connection layer, 36: first isolation trench, 37: first isolation structure, 38: second isolation trench, 39: second isolation structure;

[0037] 41: fourth oxide layer, 42: fifth oxide layer, 43: sixth oxide layer;

[0038] 51: write bit line, 52: write word line, 53: write via;

[0039] 6: write transistor, 61: second channel layer, 62: second gate dielectric layer, 63: second gate layer. DETAILED DESCRIPTION

[0040] The semiconductor structure 100 and its forming method and the three-dimensional memory proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Figure 1 FIG. 1 is a flow chart of a method for forming a semiconductor structure 100 according to an embodiment of the present invention. Figure 1 As shown, a method for forming a semiconductor structure 100 according to an embodiment of the present invention may include: step S1: providing a substrate 1, wherein the substrate 1 has a read word line 13 and a read bit line 14; step S2: forming a read transistor 2 having a first channel layer 21 and a first gate layer 23, wherein the first channel layer 21 at least partially surrounds the first gate layer 23 from the bottom to the top of the first gate layer 23, and the read transistor 2 is coupled to the read word line 13 and the read bit line 14 respectively; step S3: forming a write bit line 51 on the read transistor 2; step S4: forming a write transistor 6 having a second channel layer 61 and a second gate layer, wherein the write transistor 6 passes through the write bit line 51 and is located on the read transistor 2 and is connected to the first gate layer 23, and the second channel layer 61 at least partially surrounds the second gate layer 63 from the bottom to the top of the second gate layer 63; step S5: forming a write word line 52 on the write transistor 6, wherein the write word line 52 is connected to the second gate layer 63, wherein one end of the write transistor 6 is connected to the gate of the read transistor 2.

[0042] like Figure 2-Figure 12 1 and 2 are cross-sectional views of various steps of a method for forming a semiconductor structure 100 according to an embodiment of the present invention. The method for forming the semiconductor structure 100 according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0043] like Figure 2 As shown, step S1: providing a substrate 1 , wherein the substrate 1 has a read word line 13 and a read bit line 14 .

[0044] Specifically, if Figure 1 As shown, the base 1 may include a substrate 11 and a read word line 13 and a read bit line 14 formed on the substrate 11. The substrate 11 may be, but is not limited to, a silicon substrate 11. This specific embodiment is described using a silicon substrate 11 as an example. In other embodiments, the substrate 11 may also be a semiconductor substrate 11 such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 11 is used to support the device structure thereon, and the read word line 13 and the read bit line 14 are formed on the substrate 11.

[0045] In some embodiments of the present invention, the step of forming the substrate 1 may include:

[0046] Providing a substrate 11, and forming a first oxide layer 12 on the substrate 11;

[0047] Etching the first oxide layer 12 to form a read word line trench 16;

[0048] Filling the read word line trench 16 to form the read word line 13;

[0049] A second oxide layer 15 , a read bit line 14 and a third oxide layer 17 are sequentially formed on the read word line 13 and the first oxide layer 12 .

[0050] like Figure 2 As shown, the substrate 1 may further include a first oxide layer 12, a second oxide layer 15 formed between the read word line 13 and the read bit line 14, and a third oxide layer 17 formed on the read bit line 14. Specifically, the first oxide layer 12 may be deposited on the upper surface of the substrate 11 by at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition. The first oxide layer 12 may then be etched by wet etching or dry etching to form a read word line trench 16 in the first oxide layer 12, as shown in FIG. As shown, the read word line trench 16 can extend along the second direction, and the read word line trench 16 can be formed into a long strip extending along the second direction. In this step, the read word line trench 16 can be formed in the first oxide layer 12 and does not penetrate the first oxide layer 12. A portion of the first oxide layer 12 can be retained between the read word line trench 16 and the substrate 11 to form an insulating structure; then the read word line trench 16 is filled to form a read word line 13 in the read word line trench 16, and the read word line 13 and the substrate 11 and the read word lines 13 are isolated by the first oxide layer 12.

[0051] Then, a second oxide layer 15 is deposited on the surface of the read word line 13 and the first oxide layer 12, and a read bit line 14 is deposited on the surface of the second oxide layer 15. The read bit line 14 and the read word line 13 are isolated by the second oxide layer 15. Then, a third oxide layer 17 is formed on the surface of the read bit line 14 to form the substrate 1. The third oxide layer 17 can isolate the read bit line 14 from other device structures formed on the substrate 1.

[0052] like Figure 3-Figure 8 As shown, a read transistor 2 may be formed in the substrate 1, as shown in FIG. Figure 8 As shown, the read transistor 2 is at least partially located in the substrate 1 and partially located on the surface of the substrate 1. Specifically, in step S2, the step of forming the read transistor 2 having the first channel layer 21 and the first gate layer 23 may include:

[0053] forming a plurality of read through holes 31 to expose the read word lines 13;

[0054] A first channel layer 21 , a first gate dielectric layer 22 and a first gate layer 23 are sequentially formed in the read through hole 31 and on a portion of the surface of the substrate 1 surrounding the read through hole 31 .

[0055] Specifically, if Figure 3 As shown, the substrate 1 can be etched to form a plurality of read through holes 31 in the substrate 1. The read through holes 31 penetrate the third oxide layer 17, the read bit lines 14, and the second oxide layer 15 to expose the read word lines 13. In some examples, the read through holes 31 can be etched at least to the surface of the read word lines 13 to expose the read word lines 13. Figure 3 In the example shown, the third oxide layer 17, the read bit line 14, and the second oxide layer 15 can be etched in sequence, and a portion of the read word line 13 can be etched to form a read through hole 31. The read through hole 31 can be at least partially located within the read word line 13, so that the connection between the read transistor 2 and the read word line 13 can be ensured when the read transistor 2 is subsequently formed.

[0056] like Figure 4-Figure 8 As shown, a first channel layer 21, a first gate dielectric layer 22 and a first gate layer 23 can then be formed in sequence in the read through hole 31 and on a portion of the surface of the substrate 1 surrounding the read through hole 31. The read transistor 2 can at least include a first channel layer 21, a first gate dielectric layer 22 and a first gate layer 23. The first gate dielectric layer 22 is formed between the first gate layer 23 and the first channel layer 21. The read transistor 2 can also include a first connection layer 24, i.e., a storage node (SN), to facilitate connection with the subsequently formed write transistor 6. The portion of the first channel layer 21, the first gate dielectric layer 22, the first gate layer 23 and the first connection layer 24 located in the read through hole 31 fills the read through hole 31.

[0057] Specifically, if Figure 4 As shown, a first initial channel layer 32 can be deposited inside the read through hole 31 and on the surface of the substrate 1, and the first initial channel layer 32 covers the inner wall surface of the read through hole 31 (that is, the bottom wall and side wall of the read through hole 31) and the upper surface of the substrate 1, and then a first initial gate dielectric layer 33, a first initial gate layer 34 and a first initial connection layer 35 are sequentially formed on the surface of the first initial channel layer 32, and the first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34 and the first initial connection layer 35 fill the read through hole 31, and the first initial channel layer 32 at least partially surrounds the first initial gate layer 34.

[0058] like Figure 5-Figure 7As shown, the first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34 and the first initial connection layer 35 are patterned, and portions of the first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34 and the first initial connection layer 35 located within and surrounding the read through hole 31 are retained to form a plurality of the read transistors 2 separated from each other.

[0059] Specifically, if Figure 5 As shown, the first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34 and the first initial connection layer 35 can be etched to form a plurality of first isolation trenches 36, and the plurality of first isolation trenches 36 extend along the first direction and are spaced apart along the second direction, and the first isolation trenches 36 are formed between the read through holes 31.

[0060] like Figure 6 As shown, a first isolation structure 37 may be formed in the first isolation trench 36 to fill the first isolation trench 36 . The first isolation structure 37 may be formed as an oxide layer, for example, the first isolation structure 37 may be formed as a silicon oxide layer.

[0061] like Figure 7 As shown, the remaining first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34, the first initial connection layer 35 and the first isolation structure 37 can be etched to form a plurality of second isolation trenches 38 extending along the second direction. The plurality of second isolation trenches 38 are spaced apart along the first direction and are located between the read through holes 31. Figure 7 In the example shown, the second direction is perpendicular to the first direction, and the second isolation trenches 38 and the second isolation trenches 38 are perpendicular to each other and can be formed into a grid shape, so that the first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34 and the first initial connection layer 35 can be separated to form a plurality of independent read transistors 2, thereby enabling individual control of each read transistor 2.

[0062] like Figure 8 As shown, a second isolation structure 39 can be formed in the first isolation trench 36. The second isolation structure 39 fills the second isolation trench 38. The second isolation structure 39 can be formed as an oxide layer. For example, the second isolation structure 39 can be formed as a silicon oxide layer. In this way, the first isolation structure 37 and the second isolation structure 39 can separate the multiple read through holes 31, and the multiple read transistors 2 located in the multiple read through holes 31 can be isolated. The multiple read transistors 2 are distributed in an array, and the first isolation structure 37 and the second isolation structure 39 form an isolation structure for the multiple read transistors 2.

[0063] In such Figure 8In the example shown, the first channel layer 21 is located outside the first gate layer 23, so that the first channel layer 21 of each read transistor 2 at least partially surrounds the first gate layer 23 from the bottom to the top of the first gate layer 23, thereby increasing the channel region area of ​​the read transistor 2, improving the channel control capability of the read transistor 2, and further enhancing the performance of the semiconductor structure 100, which is conducive to improving the integration density of the semiconductor structure 100.

[0064] In such Figure 8 In the example shown, the read word line 13 and the read bit line 13 are both connected to the first channel layer 21, the first channel layer 21 may include a source terminal and a drain terminal, the read word line 13 and the read bit line 14 may be connected to the source terminal and the drain terminal respectively, the first connection layer 24 is connected to the first gate layer 23, and can be connected to the first gate layer 23 through the first connection layer 24.

[0065] Optionally, combined Figure 5-Figure 8 As shown, the first isolation trench 36 and the second isolation trench 38 can both be formed into a long strip shape, and the first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34 and the first initial connection layer 35 can be divided by the first isolation trench 36 and the second isolation trench 38 to form a plurality of read transistors 2.

[0066] In some embodiments of the present invention, Figure 5 As shown, in the step of forming the first isolation trench 36, the first isolation trench 36 can be etched downward to the lower surface of the read bit line 14 and the first isolation trench 36 is located above the read word line 13. In other words, the first isolation trench 36 can be etched downward and penetrate the read bit line 36 without exposing the read word line 12. For example, the first isolation trench 36 can be etched at least to the surface of the second oxide layer 15. In some examples, the first isolation trench 36 can be etched downward to the upper surface of the second oxide layer 15 and stop. Figure 5 In the example shown, the first isolation trench 15 can be further etched down into the second oxide layer 15 to separate the read bit line 14 into multiple lines along the first direction. The first isolation trench 36 can penetrate the first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34, the first initial connection layer 35, the third oxide layer 17, the read bit line 14 and a portion of the second oxide layer 15. Figure 6 As shown, the read bit lines 14 extending along the first direction may be separated by the first isolation structure 37 , and the read bit lines 14 are connected to the first initial channel layer 32 of the read transistor 36 .

[0067] In some embodiments of the present invention, Figure 7As shown, the second isolation trench 38 can be etched down to at least the upper surface of the substrate 1, such as the upper surface of the third oxide layer 17, and stop, that is, the second isolation trench 38 at least penetrates the first initial channel layer 32, the first initial gate dielectric layer 33, the first initial gate layer 34 and the first initial connection layer 35. Further, the second isolation trench 38 can be etched down into the substrate 1, that is, the second isolation trench 38 can be etched down into the third oxide layer 17 and is located above the read bit line 14.

[0068] like Figure 9 As shown, step S3: forming a write bit line 51 on the read transistor 2.

[0069] Specifically, the step of forming the write bit line 51 may include: forming a fourth oxide layer 41 on the read transistor 2, wherein the fourth oxide layer 41 may cover the surfaces of the first connection layer 24, the first isolation structure 37, and the second isolation structure 39, and then etching the fourth oxide layer 41 to form a write bit line trench. The write bit line trench may extend along the second direction and be located correspondingly above the read transistor 2. In this step, the write bit line trench is located within the fourth oxide layer 41, and the upper surface of the write bit line trench may be flush with the upper surface of the fourth oxide layer 41. A portion of the fourth oxide layer 41 is retained between the write bit line trench and the read transistor 2 to isolate the subsequently formed write bit line 51 from the read transistor 2. Thereafter, the write bit line 51 is formed within the write bit line trench, and the write bit line 51 fills the write bit line trench. The write bit line 51 can be isolated by the fourth oxide layer 41. Then, a fifth oxide layer 42 may be formed on the surface of the write bit line 51 and the fourth oxide layer 41, and the fifth oxide layer 42 covers the upper surface of the write bit line 51 and the fourth oxide layer 41, wherein the first oxide layer 12, the second oxide layer 15, the third oxide layer 17, the fourth oxide layer 41, and the fifth oxide layer 42 may be made of the same material, for example, they may all be silicon oxide layers or they may all be a stacked structure including silicon oxide layers, and the present invention may make special limitations on this.

[0070] like Figure 10-12 As shown, step S4: forming a write transistor 6 having a second channel layer 61 and a second gate layer 63, the write transistor passes through the write bit line 51 and is located on the read transistor 2 and connected to the first gate layer 23, the second channel layer 61 at least partially surrounds the second gate layer 63.

[0071] Specifically, if Figure 10As shown, the fifth oxide layer 42, the write bit line 51 and the fourth oxide layer 41 can be etched to form a write through hole 53, and the write through hole 53 is correspondingly located above the read transistor 2 and exposes the read transistor 2. Optionally, when etching to form the write through hole 53, a mask similar to that used when etching the read through hole 31 can be used, so that the position of the write through hole 53 can correspond one-to-one to the read through hole 31, so that the subsequently formed write transistor 6 can be accurately formed on the read transistor 2, and other light may not be required, and the alignment can also be improved. When etching the write through hole 53, it can be etched at least to the surface of the read transistor 2, for example, it can be etched to stop at least to the surface of the first connection layer 24, or it can continue to etch downward into the first connection layer 24, that is, the write through hole 53 can be at least partially located in the first connection layer 24 to ensure that the write transistor 6 subsequently formed in the write through hole 53 can be connected to the first gate layer 23 of the read transistor 2.

[0072] like Figure 11 As shown, a second channel layer 61 can be formed on the inner wall surface of the write through hole 53, wherein the second channel layer 61 covers the bottom wall and side wall of the write through hole 63, the second channel layer 61 is located on the first connection layer 24 and is connected to the first connection layer 24, the second gate dielectric layer 62 is formed on the surface of the second channel layer 61, the second gate layer 63 is formed on the surface of the second gate dielectric layer 62, the second gate dielectric layer 62 is located between the second channel layer 61 and the second gate layer 63, and the second channel layer 61, the second gate dielectric layer 62 and the second gate layer 63 jointly fill the write through hole 53.

[0073] Thus, the second channel layer 61 is formed on the first connection layer 24 and is connected to the first gate layer 23 through the first connection layer 24. The write bit line 51 is located outside the second channel layer 61 and is connected to the second channel layer 61. The second channel layer can be formed with source and drain ends. The write bit line 51 and the second connection layer 24 are respectively connected to the source and drain ends. The second channel layer 61 surrounds the second gate layer 63, thereby enhancing the channel region area of ​​the write transistor 6, improving the gate's control over the channel, and thereby improving the performance and control capability of the write transistor 6, which is also conducive to further miniaturization of the semiconductor structure 100.

[0074] like Figure 12 As shown, step S5: forming a write word line 52 on the write transistor 6 , wherein the write word line 52 is connected to the second gate layer 63 .

[0075] Specifically, a sixth oxide layer 43 may be formed on the surface of the write transistor 6 and the surface of the fifth oxide layer 42, and then the sixth oxide layer 43 may be etched to form a write word line trench exposing the write transistor 6, and the write word line trench is filled to form a write word line 52, wherein the write word line trench may extend along a first direction and be spaced apart along a second direction, and the write word line 52 is formed in the write word line trench and located on the surface of the second gate layer 63. The second gate layer 63 is electrically connected to the write word line 52, as shown in FIG. Figure 12 In the illustrated example, the write word line ultimately covers the upper surfaces of the second channel layer 61 , the second gate dielectric layer 62 , and the second gate layer 63 .

[0076] In some embodiments of the present invention, the first channel layer 21 and the second channel layer 61 may form an indium gallium zinc oxide layer, and the first gate dielectric layer 22 and the second gate dielectric layer 62 may include a layer or a stacked layer. For example, the first gate dielectric layer 22 and the second gate dielectric layer 62 may each include at least one of a silicon oxide layer and a high-K dielectric layer. Exemplarily, the high-K dielectric layer may include but is not limited to an aluminum oxide layer, a lanthanum oxide layer, a hafnium oxide layer, etc., and the first gate layer 23 may be an indium zinc oxide layer.

[0077] The present invention further provides a semiconductor structure 100 , which can be formed by the method for forming the semiconductor structure 100 of any of the above embodiments.

[0078] According to an embodiment of the present invention, a semiconductor structure 100 may include a substrate 1, a write bit line 51 and a write word line 52, a read transistor 2 and a write transistor 6, wherein the substrate 1 has a read word line 13 and a read bit line 14; the read transistor 2 includes a first channel layer 21 and a first gate layer 23, wherein the first channel layer 21 at least partially surrounds the first gate layer 23 from the bottom to the top of the first gate layer, and the read transistor 2 is coupled to the read word line 13 and the read bit line 14 respectively; the write transistor 6 is located on the read transistor 2, and the write transistor 6 includes a second channel layer 61 and a second gate layer 63, wherein the second channel layer 61 at least partially surrounds the second gate layer 63 from the bottom to the top of the second gate layer 63, and the write transistor 6 is coupled to the write bit line 51, the write word line 52 and the first gate layer 23 respectively.

[0079] According to some embodiments of the present invention, a read via 31 is defined within substrate 1, extending through read bit line 14 and exposing read word line 13. Read transistor 2 is located within read via 31 and partially within the surface of substrate 1 surrounding read via 31. In this manner, read bit line 14 and read word line 12 form the sidewalls and bottom wall of read via 31. Positioning read transistor 2 within read via 31 facilitates coupling between read transistor 2 and read word line 13 and read bit line 14. Furthermore, embedding read transistor 2 within substrate 1 provides a more stable structure, thereby improving the performance of semiconductor structure 100.

[0080] According to some embodiments of the present invention, the semiconductor structure 100 further includes a first gate dielectric layer 22, a first channel layer 21, the first gate dielectric layer 22, and a first gate layer 23, which are stacked in sequence. The first channel layer 21 is located on the inner wall surface of the read through hole 31. Specifically, the first gate dielectric layer 22 is located between the first gate layer 23 and the first channel layer 21, the first gate dielectric layer 22 is located on the surface of the first channel layer 22, and the first gate layer 23 is located on the surface of the first gate dielectric layer 22.

[0081] According to some embodiments of the present invention, the read transistor 2 further includes a first connection layer 24 , which is located on the surface of the first gate layer 23 . The write transistor 6 is located on the first connection layer 24 , and the write transistor 6 is connected to the first gate layer 23 of the read transistor 2 through the first connection layer 24 .

[0082] According to some embodiments of the present invention, the semiconductor structure 100 further includes: a first isolation structure 37 and a second isolation structure 39, wherein the first isolation structure 37 extends along a first direction and is located between the read transistors 2, and extends downward to be located between adjacent read bit lines 14; the second isolation structure 39 extends along a second direction and is located on the substrate 1, so as to surround the read transistor 2 together with the first isolation structure 27, and multiple read transistors 2 can be separated by the first isolation structure 37 and the second isolation structure 39.

[0083] According to some embodiments of the present invention, it also includes: an isolation layer, the isolation layer is formed on the substrate, the write bit line 51 is located in the isolation layer, the isolation layer is provided with a write through hole 53 passing through the isolation layer and the write bit line 51, the write through hole 53 is located on the read transistor 2, and the write transistor 6 is located in the write through hole 53.

[0084] According to some embodiments of the present invention, the write transistor 6 further includes a second gate dielectric layer 62 , and the second channel layer 61 , the second gate dielectric layer 62 and the second gate layer 63 are sequentially stacked on the inner wall surface of the write through hole 53 .

[0085] According to some embodiments of the present invention, a write word line 52 is formed on the write transistor 6 and connected to the second gate layer 63 .

[0086] According to some embodiments of the present invention, the first channel layer 21 and the second channel layer 61 are both indium gallium zinc oxide layers.

[0087] Thus, according to the semiconductor structure 100 and its formation method according to an embodiment of the present invention, the first channel layer 21 at least partially surrounds the first gate layer 23 in a direction from the bottom to the top of the first gate layer 23, and the second channel layer 61 at least partially surrounds the second gate layer 63 in a direction from the bottom to the top of the second gate layer 63. The read transistor 2 and the write transistor 6 can both form a vertical ring channel device structure. The read word line 13 and the read bit line 14 are respectively coupled to the source and drain terminals of the read transistor 2, and the write transistor 6 is correspondingly formed on the read transistor 2, that is, the write transistor 6 and the read transistor 2 are stacked. The first gate layer 23 of the read transistor 2 is connected to the write transistor 6 through the first connection layer 24, so that the source and drain terminals of the write transistor are respectively coupled to the first connection layer 34 and the write bit line 51, and the second gate layer 63 is connected to the write word line 52. The semiconductor structure 100 can be formed into a semiconductor 2T0C structure. Both transistors are vertical ring channel structures, thereby increasing the effective channel area of ​​the two transistors, improving the channel control capability, and thereby improving the performance of the semiconductor structure 100, and also improving the semiconductor structure 100. The integration level is high, which is conducive to further miniaturization of the semiconductor structure 100.

[0088] The present invention also provides a three-dimensional memory.

[0089] A three-dimensional memory according to an embodiment of the present invention may include the semiconductor structure 100 of the above embodiment. Specifically, the three-dimensional memory may include a plurality of stacked semiconductor structures 100. For example, a device structure including a write bit line 51, a write word line 52, a read word line 13, and a read bit line 14, as well as a read transistor 2 and a write transistor 6 may be further stacked on the semiconductor structure 100. This improves the integration of the three-dimensional memory 1000, facilitates the miniaturization of the three-dimensional memory, and improves the stability and reliability of the three-dimensional memory.

[0090] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that include: a substrate having a read word line and a read bit line; a read transistor, the read transistor comprising a first channel layer and a first gate layer, the first channel layer at least partially surrounding the first gate layer from the bottom to the top of the first gate layer, the read transistor being coupled to the read word line and the read bit line respectively; write word lines and write bit lines; a write transistor, the write transistor being located on the read transistor, the write transistor comprising a second channel layer and a second gate layer, the second channel layer at least partially surrounding the second gate layer from the bottom to the top, the write transistor being coupled to the write bit line, the write word line, and the first gate layer, respectively; One end of the write transistor is connected to the gate of the read transistor.

2. The semiconductor structure according to claim 1, wherein: A read through hole is provided in the substrate, penetrating the read bit line and exposing the read word line. The read transistor is located in the read through hole and partially located on the substrate surface surrounding the read through hole.

3. The semiconductor structure according to claim 2, wherein: It also includes a first gate dielectric layer. The first channel layer, the first gate dielectric layer and the first gate layer are stacked in sequence. The first channel layer is located on the inner wall surface of the read through hole.

4. The semiconductor structure according to claim 1, wherein: The read transistor further includes a first connection layer, the first connection layer is located on a surface of the first gate layer, and the write transistor is located on the first connection layer.

5. The semiconductor structure according to claim 1, wherein: Also includes: a first isolation structure extending along a first direction and located between the read transistors, and extending downward to be located between adjacent read bit lines; A second isolation structure extends along a second direction and is located on the substrate to surround the read transistor together with the first isolation structure. The semiconductor structure according to claim 1 , wherein: Also includes: An isolation layer is formed on the substrate, the write bit line is located in the isolation layer, the isolation layer is provided with a write through hole penetrating the isolation layer and the write bit line, the write through hole is located on the read transistor, and the write transistor is located in the write through hole.

7. The semiconductor structure according to claim 6, wherein: The write transistor further includes a second gate dielectric layer. The second channel layer, the second gate dielectric layer and the second gate layer are sequentially stacked on the inner wall surface of the write through hole.

8. The semiconductor structure according to claim 1, wherein: The write word line is formed on the write transistor and connected to the second gate layer.

9. The semiconductor structure according to claim 1, wherein: The first channel layer and the second channel layer are both indium gallium zinc oxide layers.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate having a read word line and a read bit line; forming a read transistor having a first channel layer and a first gate layer, wherein the first channel layer at least partially surrounds the first gate layer from the bottom to the top of the first gate layer, and the read transistor is coupled to the read word line and the read bit line respectively; forming a write bit line on the read transistor; forming a write transistor having a second channel layer and a second gate layer, wherein the write transistor penetrates the write bit line, is located on the read transistor, and is connected to the first gate layer, and the second channel layer at least partially surrounds the second gate layer from the bottom to the top of the second gate layer; forming a write word line on the write transistor, wherein the write word line is connected to the second gate layer; One end of the write transistor is connected to the gate of the read transistor.

11. The method for forming a semiconductor structure according to claim 10, wherein: The steps of forming the substrate include: providing a substrate, and forming a first oxide layer on the substrate; etching the first oxide layer to form a read word line trench; filling the read word line trench to form the read word line; A second oxide layer, a read bit line and a third oxide layer are sequentially formed on the read word line and the first oxide layer.

12. The method for forming a semiconductor structure according to claim 10, wherein: The steps of forming the read transistor include: forming a plurality of read through holes to expose the read word lines; A first channel layer, a first gate dielectric layer and a first gate layer are sequentially formed in the read through hole and on the surface of the substrate surrounding the read through hole.

13. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: A first connection layer is formed on the first gate layer, and the first connection layer, the first channel layer, the first gate dielectric layer, and the first gate layer fill the read through hole.

14. The method for forming a semiconductor structure according to claim 12, wherein: The read via is at least partially located within the read word line.

15. The method for forming a semiconductor structure according to claim 13, wherein: The steps of forming a first channel layer, a first gate dielectric layer, a first gate layer and a first connection layer include: forming a first initial channel layer on the surface of the substrate and the inner wall surface of the reading through hole; forming a first initial gate dielectric layer, a first initial gate layer and a first initial connection layer in sequence on the surface of the first initial channel layer; The first initial channel layer, the first initial gate dielectric layer, the first initial gate layer and the first initial connection layer are patterned, and portions of the first initial channel layer, the first initial gate dielectric layer, the first initial gate layer and the first initial connection layer located within and surrounding the read through hole are retained to form a plurality of the read transistors separated from each other.

16. The method for forming a semiconductor structure according to claim 15, wherein: The step of patterning the first initial channel layer, the first initial gate dielectric layer, the first initial gate layer and the first initial connection layer includes: Etching the first initial channel layer, the first initial gate dielectric layer, the first initial gate layer, and the first initial connection layer to form a first isolation trench extending along a first direction; The first initial channel layer, the first initial gate dielectric layer, the first initial gate layer, the first initial connection layer and the first isolation structure are etched to form a second isolation trench extending along a second direction, the first isolation trench and the second isolation trench are both correspondingly located between the read through holes, and the second direction is perpendicular to the first direction.

17. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: filling the first isolation trench to form a first isolation structure; The second isolation trench is filled to form a second isolation structure.

18. The method for forming a semiconductor structure according to claim 16, wherein: The first isolation trench penetrates the read bit line and is located above the read word line.

19. The method for forming a semiconductor structure according to claim 10, wherein: The steps of forming a write bit line include: forming a fourth oxide layer on the read transistor; etching the fourth oxide layer to form a write bit line trench; The write bit line trench is filled to form the write bit line.

20. The method for forming a semiconductor structure according to claim 19, wherein: The steps of forming a write transistor include: forming a fifth oxide layer on the write bit line and the fourth oxide layer; Etching the fifth oxide layer, the write bit line, and the fourth oxide layer to form a write through hole exposing the read transistor; A second channel layer, a second gate dielectric layer and a second gate layer are sequentially formed on the inner wall of the write through hole, wherein the second channel layer at least partially surrounds the second gate layer, and the second gate dielectric layer is located between the second channel layer and the second gate layer.

21. The method for forming a semiconductor structure according to claim 20, wherein: The steps of forming a write word line include: forming a sixth oxide layer on a surface of the write transistor and a surface of the fifth oxide layer; etching the sixth oxide layer to form a write word line trench exposing the write transistor; The write word line trench is filled to form the write bit line.

22. A three-dimensional memory, characterized in that: A semiconductor structure comprising a plurality of stacked arrangements of claims 1 to 9.

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