Method for manufacturing image display device and image display device

Abstract

The present invention provides a method for manufacturing an image display device and an image display device. The method for manufacturing an image display device of an embodiment comprises: a process of preparing a second substrate having a semiconductor layer formed on a first substrate; a process of bonding the semiconductor layer to a first surface of a third substrate; a process of removing the first substrate; a process of etching the semiconductor layer to form a light-emitting element including a light-emitting surface opposite to a bottom surface on the first surface; a process of forming a first insulating film covering the first surface and the light-emitting element; a process of forming a circuit element on the first insulating film; a process of forming a second insulating film covering the circuit element and the first insulating film; a process of removing a portion of the first insulating film and the second insulating film to expose a surface including the light-emitting surface; a process of forming a via hole penetrating the first insulating film and the second insulating film; a process of forming a wiring layer on the second insulating film.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing an image display device and an image display device. Background Art

[0002] It is desired to realize a thin image display device with high brightness, wide viewing angle, high contrast, and low power consumption. In order to meet the above market demand, a display device using a self-luminous element is being developed.

[0003] As a self-luminous element, a display device using a fine light-emitting element, namely a micro-LED, is expected to appear. As a manufacturing method of a display device using a micro-LED, a method of sequentially transferring a single formed micro-LED to a drive circuit has been introduced. However, as the number of micro-LED elements increases with high image quality such as full HD, 4K, and 8K, the transfer process requires a lot of time in the process of forming a large number of micro-LEDs individually and sequentially transferring them to a substrate formed with a drive circuit, etc. In addition, poor connection between the micro-LED and the drive circuit, etc. may occur, resulting in a problem of reduced yield.

[0004] A technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board having a driving circuit formed thereon (see, for example, Patent Document 1).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: (Japanese) Patent Publication No. 2002-141492 Summary of the invention

[0008] Technical problem to be solved by the invention

[0009] One embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer process of a light-emitting element and improves the yield.

[0010] Technical solutions for solving technical problems

[0011] A method for manufacturing an image display device according to an embodiment of the present invention comprises: preparing a second substrate on which a semiconductor layer including a light-emitting layer is formed on a first substrate; bonding the semiconductor layer to a first surface of a third substrate; removing the first substrate; etching the semiconductor layer to form a light-emitting element including a bottom surface on the first surface and a light-emitting surface disposed opposite to the bottom surface; forming a first insulating film covering the first surface and the light-emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the circuit element and the first insulating film; removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light-emitting surface; forming a via hole penetrating the first insulating film and the second insulating film; and forming a wiring layer on the second insulating film. The light-emitting element includes a connection portion formed on the first surface. The via hole is disposed between the wiring layer and the connection portion to electrically connect the wiring layer and the connection portion.

[0012] An image display device according to one embodiment of the present invention comprises: a substrate having a first surface, a light-emitting element including a bottom surface on the first surface and a surface opposite to the bottom surface, i.e., a light-emitting surface, a first insulating film covering the side surface of the light-emitting element and the first surface, a circuit element provided on the first insulating film, a second insulating film covering the circuit element and the first insulating film, a via hole provided to penetrate the first insulating film and the second insulating film, and a wiring layer provided on the second insulating film. The light-emitting element includes a connection portion formed on the first surface. The via hole is provided between the wiring layer and the connection portion to electrically connect the wiring layer and the connection portion.

[0013] An image display device according to one embodiment of the present invention comprises: a substrate having a first surface, a semiconductor layer including a bottom surface on the first surface and a surface opposite to the bottom surface and including a plurality of light-emitting surfaces on the surface, a first insulating film covering the side surface of the semiconductor layer and the first surface, a plurality of transistors provided on the first insulating film, a second insulating film covering the plurality of transistors and the first insulating film, a plurality of vias provided to penetrate the first insulating film and the second insulating film, and a wiring layer provided on the second insulating film. The semiconductor layer includes a connection portion formed on the first surface. The plurality of vias are provided between the wiring layer and the connection portion to electrically connect the wiring layer and the connection portion.

[0014] Effects of the Invention

[0015] According to one embodiment of the present invention, it is possible to realize a method for manufacturing an image display device that can shorten the transfer process of a light-emitting element and improve the yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic cross-sectional view illustrating a part of the image display device according to the first embodiment.

[0017] Figure 2 This is a cross-sectional view schematically showing a part of a modification of the image display device according to the first embodiment.

[0018] Figure 3 is a schematic block diagram illustrating an image display device according to the first embodiment.

[0019] Figure 4 It is a schematic plan view illustrating a part of the image display device according to the first embodiment.

[0020] Figure 5A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0021] Figure 5B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0022] Figure 5C It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0023] Figure 6 This is a schematic perspective view illustrating the method for manufacturing the image display device according to the first embodiment.

[0024] Fig. 7A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0025] Figure 7B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0026] Figure 7C It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0027] Fig. 8A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0028] Figure 8B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0029] Fig. 9A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0030] Fig. 9BIt is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0031] Fig. 9C It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0032] Fig. 10A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0033] Fig. 10B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0034] Fig.11A It is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device according to the first embodiment.

[0035] Fig. 11B It is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device according to the first embodiment.

[0036] Fig.12 It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0037] Fig.13A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0038] Fig. 13B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0039] Fig. 13C It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0040] Fig.13D It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0041] Fig.14 It is a schematic perspective view illustrating the image display device according to the first embodiment.

[0042] Fig.15 is a schematic cross-sectional view illustrating a part of the image display device according to the second embodiment.

[0043] Fig.16 is a schematic block diagram illustrating an image display device according to the second embodiment.

[0044] Fig.17A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0045] Fig. 17B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0046] Fig. 17C It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0047] Fig.18A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0048] Fig.18B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0049] Fig.19A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0050] Fig.19B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0051] Fig. 20 is a schematic cross-sectional view illustrating a part of an image display device according to a third embodiment.

[0052] Fig.21A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the third embodiment.

[0053] Fig. 21B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the third embodiment.

[0054] Fig.22A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the third embodiment.

[0055] Fig. 22B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the third embodiment.

[0056] Fig.23 is a schematic cross-sectional view illustrating a part of an image display device according to a fourth embodiment.

[0057] Fig.24A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0058] Fig. 24B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0059] Fig.25 is a schematic cross-sectional view illustrating a portion of an image display device according to a fifth embodiment.

[0060] Fig.26A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fifth embodiment.

[0061] Fig.26B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fifth embodiment.

[0062] Fig.26C It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fifth embodiment.

[0063] Fig.27A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fifth embodiment.

[0064] Fig.27B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fifth embodiment.

[0065] Fig.28A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fifth embodiment.

[0066] Fig.28B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fifth embodiment.

[0067] Fig.29 This is a schematic cross-sectional view of a part of an image display device illustrating a modification example of the fifth embodiment.

[0068] Fig. 30A It is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modification example of the fifth embodiment.

[0069] Fig. 30B It is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modification example of the fifth embodiment.

[0070] Fig. 30C It is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modification example of the fifth embodiment.

[0071] Fig.31A It is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modification example of the fifth embodiment.

[0072] Fig.31B It is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modification example of the fifth embodiment.

[0073] Fig.32 is a graph illustrating the characteristics of a pixel LED element.

[0074] Fig.33is a block diagram illustrating an image display device according to the sixth embodiment.

[0075] Fig.34 This is a block diagram illustrating an image display device according to a modification of the sixth embodiment. DETAILED DESCRIPTION

[0076] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0077] It should be noted that the accompanying drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as the actual situation. In addition, even when representing the same part, sometimes the mutual size and ratio are represented differently due to the accompanying drawings.

[0078] It should be noted that in the present specification and each drawing, the same reference numerals are used for main components that are related to the drawings already shown and are the same as the components described above, and detailed descriptions thereof are appropriately omitted.

[0079] (First Embodiment)

[0080] Figure 1 This is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0081] Figure 1 The structure of the sub-pixel 20 of the image display device of this embodiment is schematically shown. A pixel constituting an image displayed in the image display device is constituted by a plurality of sub-pixels 20.

[0082] Below, the three-dimensional coordinate system of XYZ is sometimes used for explanation. Fig.14 As shown, the sub-pixels 20 are arranged in a two-dimensional plane. The two-dimensional plane in which the sub-pixels 20 are arranged is called an XY plane. The sub-pixels 20 are arranged along the X-axis and the Y-axis. Figure 1 Indicates the following description Figure 4 The sagittal section of the A-A' line is a cross-sectional view connecting the sections of multiple planes perpendicular to the XY plane on one plane. Figure 1 As shown in the figure, in the cross-sectional view of multiple planes perpendicular to the XY plane, the X-axis and the Y-axis are not shown, and the Z-axis perpendicular to the XY plane is shown. That is to say, in the above figure, the plane perpendicular to the Z-axis is taken as the XY plane. It should be noted that, for convenience, the positive direction of the Z-axis is sometimes referred to as "up" or "above", and the negative direction of the Z-axis is sometimes referred to as "down" or "below", but the direction along the Z-axis is not necessarily the direction in which gravity is applied. In addition, the length along the direction of the Z-axis is sometimes referred to as the height.

[0083] The sub-pixel 20 has a light emitting surface 153S that is substantially parallel to the XY plane. The light emitting surface 153S is a surface that mainly faces the positive direction of the Z axis that is perpendicular to the XY plane and emits light.

[0084] like Figure 1 As shown, the sub-pixel 20 of the image display device includes a substrate 102 , a light emitting element 150 , a first interlayer insulating film 156 , a transistor 103 , a second interlayer insulating film 108 , a via 161 k , and a wiring layer 110 .

[0085] In this embodiment, the substrate 102 on which the light-emitting element 150 is formed is a light-transmitting substrate, such as a glass substrate. The substrate 102 has a first surface 102a. The first surface 102a is a surface substantially parallel to the XY plane. The transistor 103 is a thin film transistor (TFT) formed on a first interlayer insulating film 156. The light-emitting element 150 is formed on the first surface 102a. The light-emitting element 150 is driven by the TFT provided via the first interlayer insulating film 156. The process of forming circuit elements including TFTs on a large glass substrate is established for the manufacture of liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing equipment.

[0086] The sub-pixel 20 further includes a color filter 180. The color filter (wavelength conversion member) 180 is provided on the surface resin layer 170 via a transparent thin film adhesive layer 188. The surface resin layer 170 is provided on the second interlayer insulating film 108 and the wiring layer 110.

[0087] Next, the structure of the sub-pixel 20 will be described in detail.

[0088] In this example, the light emitting element 150 is provided on the first surface 102a via a buffer layer 140. The buffer layer 140 is formed of an insulating material and is used in the growth of a semiconductor layer for forming the light emitting element 150, which will be described in detail later in the description of the manufacturing method.

[0089] The light emitting element 150 includes a light emitting surface 153S. The light emitting element 150 is a prismatic or cylindrical element having a bottom surface 151B on the first surface 102a. The light emitting surface 153S is a surface of the light emitting element 150 that is opposite to the bottom surface 151B. In this example, the bottom surface 151B of the light emitting element 150 is a surface that is in contact with the buffer layer 140.

[0090] The light emitting element 150 includes an n-type semiconductor layer 151, a light emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light emitting layer 152, and the p-type semiconductor layer 153 are stacked in this order from the bottom surface 151B to the light emitting surface 153S. Therefore, in this example, the n-type semiconductor layer 151 is provided in contact with the buffer layer 140.

[0091] The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided on the first surface 102a together with the buffer layer 140 so as to protrude in one direction from the n-type semiconductor layer 151. The height of the connection portion 151a is the same as that of the n-type semiconductor layer 151, or is lower than that of the n-type semiconductor layer 151, and the light emitting element 150 is formed in a stepped shape. The connection portion 151a is n-type and is electrically connected to the n-type semiconductor layer 151. The connection portion 151a is connected to one end of the via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connection portion 151a.

[0092] When the light emitting element 150 is prismatic, the shape of the light emitting element 150 when viewed from above in the XY plane is, for example, a substantially square or rectangular shape. When the shape of the light emitting element 150 when viewed from above in the XY plane is a polygon including a square, the corners of the light emitting element 150 may also be rounded. When the shape of the light emitting element 150 when viewed from above in the XY plane is cylindrical, the shape of the light emitting element 150 when viewed from above in the XY plane is not limited to a circle, and may be, for example, an ellipse. By appropriately selecting the shape and arrangement of the light emitting element when viewed from above, the degree of freedom of wiring design and the like is increased.

[0093] For example, InXAl Y Ga 1-X-Y N (0≦X, 0≦Y, X+Y<1) and the like include gallium nitride compound semiconductors of the light-emitting layer. Below, the above-mentioned gallium nitride compound semiconductors are sometimes simply referred to as gallium nitride (GaN). The light-emitting element 150 of one embodiment of the present invention is a so-called light-emitting diode. The wavelength of light emitted by the light-emitting element 150 can be a wavelength in the range of the near-ultraviolet region to the visible light region, for example, about 467nm±20nm. The wavelength of light emitted by the light-emitting element 150 can also be blue-violet light of about 410nm±20nm. The wavelength of light emitted by the light-emitting element 150 is not limited to the above-mentioned values ​​and can be an appropriate value.

[0094] The area of ​​the light-emitting layer 152 when viewed from above the XY plane is set according to the light-emitting colors of the red, green, and blue sub-pixels. In the following, the area when viewed from above the XY plane is sometimes simply referred to as the area. The area of ​​the light-emitting layer 152 can be appropriately set according to visibility, the conversion efficiency of the color conversion unit 182 of the color filter 180, etc. In other words, the area of ​​the light-emitting layer 152 of the sub-pixels 20 of each light-emitting color can be the same or different for each light-emitting color. It should be noted that the area of ​​the light-emitting layer 152 refers to the area of ​​the region surrounded by the periphery of the light-emitting layer 152 projected on the XY plane.

[0095] The first interlayer insulating film 156 (first insulating film) covers the first surface 102a. The first interlayer insulating film 156 covers the side surfaces of the buffer layer 140 and the side surfaces of the light-emitting element 150. The first interlayer insulating film 156 insulates the light-emitting elements 150 from each other. The first interlayer insulating film 156 insulates the light-emitting element 150 from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming the circuit 101 including the circuit elements such as the transistor 103. The first interlayer insulating film 156 protects the light-emitting element 150 from heat stress when forming the transistor 103, etc. by covering the light-emitting element 150.

[0096] The first interlayer insulating film 156 is formed of an organic insulating material. The organic insulating material used for the first interlayer insulating film 156 is preferably a white resin. Since the white resin reflects the lateral emission light of the light emitting element 150 and the return light generated by the interface of the color filter 180, etc., making the first interlayer insulating film 156 of a white resin helps to actually improve the light emitting efficiency of the light emitting element 150.

[0097] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin such as SOG (Spin On Glass) or a novolac-type phenolic-based resin. The scattering particles are colorless or white and have a diameter of about 1 / 10 to several times the wavelength of the light emitted by the light-emitting element 150. Suitable scattering particles have a diameter of about 1 / 2 of the wavelength of the light. For example, TiO2, Al2SO3, ZnO, etc. can be cited as the above-mentioned scattering particles.

[0098] Alternatively, the white resin may be formed by utilizing a large number of fine pores dispersed in the transparent resin. When the first interlayer insulating film 156 is whitened, it may be overlapped with SOG, for example, using a SiO2 film formed by ALD (Atomic-Layer-Deposition) or CVD.

[0099] The first interlayer insulating film 156 may also be made of black resin. By making the first interlayer insulating film 156 of black resin, scattering of light in the sub-pixel 20 is suppressed, and stray light is suppressed more effectively. An image display device with suppressed stray light can display a clearer image.

[0100] A TFT lower film 106 is formed over the first interlayer insulating film 156. The TFT lower film 106 is provided to ensure flatness when forming the transistor 103 and to protect the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower film 106 is an insulating film such as SiO2.

[0101] The transistor 103 is formed on the TFT lower film 106. In addition to the transistor 103, other transistors, capacitors and other circuit elements are formed on the TFT lower film 106, and the circuit 101 is formed by wiring and the like. For example, in the following description Figure 3 In FIG. 1 , transistor 103 corresponds to driving transistor 26. In addition, in Figure 3 In the circuit 101 , the transistor 24 , the capacitor 28 , etc. are selected as circuit elements. The circuit 101 includes a TFT channel 104 , an insulating layer 105 , a second interlayer insulating film 108 , vias 111 s and 111 d , and a wiring layer 110 .

[0102] In this example, the transistor 103 is a p-channel thin film transistor (Thin Film Transistor, TFT). The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature polysilicon (Low Temperature Poly Silicon, LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating a region of amorphous Si formed on the TFT lower film 106. For example, the polycrystallization and activation of the region of amorphous Si can be performed by laser annealing. The TFT formed by the LTPS process has a sufficiently high mobility.

[0103] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all disposed on the TFT lower layer film 106. The region 104i is disposed between the region 104s and the region 104d. The regions 104s and 104d are doped with boron ions (B + ) or boron fluoride ion (BF 2+ ) and other p-type impurities, and are ohmically connected to the vias 111s and 111d.

[0104] The gate electrode 107 is provided on the TFT channel 104 via the insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate electrode 107 and from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate electrode 107, a channel is formed in the region 104i, and the current flowing between the regions 104s and 104d can be controlled.

[0105] The insulating layer 105 is, for example, SiO 2. The insulating layer 105 may be a multilayer insulating layer containing SiO 2, Si 3 N 4, etc., depending on the area to be covered.

[0106] The gate 107 may be formed of, for example, polycrystalline Si, or may be formed of a high melting point metal such as W or Mo. The polycrystalline Si film of the gate 107 is formed by ordinary CVD or the like.

[0107] The second interlayer insulating film 108 is provided on the gate electrode 107 and the insulating layer 105. The second interlayer insulating film 108 is formed of, for example, the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of a white resin or an inorganic film such as SiO2. The second interlayer insulating film 108 is also used as a planarization film for forming the wiring layer 110.

[0108] Since the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 are formed as described above, no opening is provided on the upper portion of the light emitting surface 153S. That is, the light emitting surface 153S is exposed from the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 through the opening 158. As described later, the opening 158 is filled with the surface resin layer 170.

[0109] The via holes 111s and 111d are provided to penetrate the second interlayer insulating film 108 and the insulating layer 105. The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes a plurality of wirings having different potentials. In this example, the wiring layer 110 includes wirings 110s, 110d, and 110k.

[0110] A portion of the wiring 110s is provided above the region 104s. The other portion of the wiring 110s is, for example, Figure 3 The power supply line 3 shown is connected. A portion of the wiring 110d (second wiring) is provided above the region 104d. The other portion of the wiring 110d is connected to the surface including the light emitting surface 153S. The surface including the light emitting surface 153S is the same plane as the light emitting surface 153S, and one end of the other portion of the wiring 110d is connected to the surface other than the light emitting surface 153S on the surface. A portion of the wiring 110k (first wiring) is provided above the connection portion 151a. The other portion of the wiring 110k is connected to, for example, the surface described later. Figure 3 The ground wire 4 is shown connected.

[0111] exist Figure 1 In the wiring layer of the following cross-sectional views, unless otherwise specified, a mark of one wiring included in the wiring layer is shown next to the wiring for the purpose of marking the mark.

[0112] The via 111s is provided between the wiring 110s and the region 104s, and electrically connects the wiring 110s and the region 104s. The via 111d is provided between the wiring 110d and the region 104d, and electrically connects the wiring 110d and the region 104d.

[0113] The wiring 110s is connected to the region 104s through the via 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to the power supply line 3 through the via 111s and the wiring 110s.

[0114] The wiring 110d is connected to the region 104d through the via 111d. The region 104d is a drain region of the transistor 103. Therefore, the drain region of the transistor 103 is electrically connected to the p-type semiconductor layer 153 through the via 111d and the wiring 110d.

[0115] The via hole 161k is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via hole 161k is provided between the wiring 110k and the connecting portion 151a, and electrically connects the wiring 110k and the connecting portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to the ground line 4 via the connecting portion 151a, the via hole 161k, and the wiring 110k.

[0116] The wiring layer 110 and the vias 111s, 111d, and 161k are formed of, for example, Al or an Al alloy, a laminated film of Al and Ti, etc. For example, in the laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

[0117] The surface resin layer 170 covers the second interlayer insulating film 108 and the wiring layer 110. The surface resin layer 170 is also filled in the opening 158. The surface resin layer 170 covers the light emitting surface 153S. The surface resin layer 170 filled in the opening 158 covers the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105 and the side of the second interlayer insulating film 108. The surface resin layer 170 is a transparent resin, protects the interlayer insulating film 156 and the wiring layer 110, and provides a flattened surface for bonding the color filter 180.

[0118] The color filter 180 includes a light shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided just above the light emitting surface 153S of the light emitting element 150 in accordance with the shape of the light emitting surface 153S. In the color filter 180, the portion other than the color conversion portion 182 is the light shielding portion 181. The light shielding portion 181 is a so-called black matrix, and reduces blurring caused by color mixing of light emitted from adjacent color conversion portions 182, and can display a clear image.

[0119] The color conversion unit 182 has one layer or two or more layers. Figure 1The color conversion unit 182 is shown as a two-layer structure. Whether the color conversion unit 182 is a single layer or a double layer depends on the color, that is, the wavelength, of the light emitted by the sub-pixel 20. When the light emission color of the sub-pixel 20 is red, the color conversion unit 182 is preferably a two-layer structure consisting of a color conversion layer 183 and a filter layer 184 that allows red light to pass. When the light emission color of the sub-pixel 20 is green, the color conversion unit 182 is preferably a two-layer structure consisting of a color conversion layer 183 and a filter layer 184 that allows green light to pass. When the light emission color of the sub-pixel 20 is blue, a single layer is preferred.

[0120] When the color conversion section 182 is a two-layer structure, the first layer is the color conversion layer 183 and the second layer is the filter layer 184. The first color conversion layer 183 is disposed closer to the light emitting element 150. The filter layer 184 is laminated on the color conversion layer 183.

[0121] The color conversion layer 183 converts the wavelength of light emitted by the light emitting element 150 into a desired wavelength. In the case of a sub-pixel 20 emitting red light, the light of the light emitting element 150 having a wavelength of 467 nm ± 20 nm is converted into light of a wavelength of about 630 nm ± 20 nm, for example. In the case of a sub-pixel 20 emitting green light, the light of the light emitting element 150 having a wavelength of 467 nm ± 20 nm is converted into light of a wavelength of about 532 nm ± 20 nm, for example.

[0122] The filter layer 184 blocks the wavelength component of the blue light that remains without being color-converted by the color conversion layer 183 .

[0123] When the color of the light emitted by the sub-pixel 20 is blue, the sub-pixel 20 may output the light via the color conversion layer 183 or directly without the color conversion layer 183. When the wavelength of the light emitted by the light-emitting element 150 is about 467nm±20nm, the sub-pixel 20 may output the light without the color conversion layer 183. When the wavelength of the light emitted by the light-emitting element 150 is 410nm±20nm, in order to convert the wavelength of the output light to about 467nm±20nm, a color conversion layer 183 is preferably provided.

[0124] Even in the case of a blue sub-pixel 20, the sub-pixel 20 may include a filter layer 184. By providing the filter layer 184 through which blue light is transmitted in the blue sub-pixel 20, slight reflection of external light other than blue light generated on the surface of the light emitting element 150 is suppressed.

[0125] Figure 2 It is a cross-sectional view schematically showing a part of a modification example of the image display device according to the present embodiment.

[0126] exist Figure 2In the subsequent cross-sectional views of the sub-pixels, the surface resin layer 170, the transparent film adhesive layer 188, and the color filter 180 are not shown in order to avoid complication. In the subsequent drawings, except for the case of the cross-sectional view used to explain the manufacturing method, unless otherwise specified, the structure of the upper part of the surface resin layer 170 is provided on the second interlayer insulating film 108, the wiring layer 110, and the opening 158. The same is true for the other embodiments and their modified examples described later.

[0127] exist Figure 2 In the case of the above-mentioned first embodiment, the connection method between the light-emitting element 150 of the sub-pixel 20a and the wiring 110d1 is different from the connection method between the light-emitting element 150 and the wiring 110d in the first embodiment. In this modification, the difference from the first embodiment is that a translucent electrode 159s is provided over the wiring 110s. In other respects, this modification is the same as the first embodiment, and the same reference numerals are used for the same structural main components, and detailed descriptions are appropriately omitted.

[0128] like Figure 2 As shown, the sub-pixel 20a includes: a light-emitting element 150, a wiring 110d1, and a translucent electrode 159d. The wiring 110d1 is arranged above the region 104d and the via 111d. The wiring 110d1 is connected to the region 104d through the via 111d. The wiring 110d1 does not extend to the light-emitting surface 153S and is not directly connected to the light-emitting surface 153S.

[0129] The light-transmitting electrode 159d is provided over the wiring 110d1. The light-transmitting electrode 159d is provided over the light-emitting surface 153S. The light-transmitting electrode 159d is also provided between the wiring 110d1 and the light-emitting surface 153S, and electrically connects the wiring 110d1 and the light-emitting surface 153S.

[0130] The light-transmitting electrode 159s is provided over the wiring 110s. The light-transmitting electrode 159d and the light-transmitting electrode 159s are formed of a light-transmitting conductive film. The light-transmitting electrodes 159d and 159s are preferably made of an ITO film or a ZnO film. The light-transmitting electrode may also be provided on the wiring 110k.

[0131] The light emitting surface 153S is preferably roughened. When the light emitting surface 153S of the light emitting element 150 is roughened, light extraction efficiency can be improved.

[0132] By providing the light-transmitting electrode 159d on the light-emitting surface 153S, the connection area between the light-transmitting electrode 159d and the p-type semiconductor layer 153 can be increased, and the area of ​​the light-emitting surface 153S can be increased, so that the light-emitting efficiency can be improved. When the light-emitting surface 153S is a rough surface, the connection area between the light-emitting surface 153S and the light-transmitting electrode 159d is increased, and the contact resistance is reduced, thereby further improving the light-emitting efficiency.

[0133] In this embodiment, any structure of the sub-pixels 20 and 20a described above may be included.

[0134] Figure 3 : is a schematic block diagram illustrating an image display device according to this embodiment.

[0135] like Figure 3 As shown, the image display device 1 of this embodiment has a display area 2. Sub-pixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged in a grid pattern, for example. For example, n sub-pixels 20 are arranged along the X axis and m sub-pixels are arranged along the Y axis.

[0136] The pixel 10 includes a plurality of sub-pixels 20 that emit light of different colors. The sub-pixel 20R emits red light. The sub-pixel 20G emits green light. The sub-pixel 20B emits blue light. By emitting light at a desired brightness, the color and brightness of light emitted by one pixel 10 can be determined.

[0137] A pixel 10 includes three sub-pixels 20R, 20G, and 20B. Figure 3 As shown, the sub-pixels 20R, 20G, and 20B are arranged in a straight line on the X axis. In each pixel 10, sub-pixels of the same color may be arranged in the same column, or, as shown in this example, sub-pixels of different colors may be arranged in each column.

[0138] The image display device 1 further includes a power line 3 and a ground line 4. The power line 3 and the ground line 4 are arranged in a grid shape along the arrangement of the sub-pixels 20. The power line 3 and the ground line 4 are electrically connected to each sub-pixel 20, and power is supplied to each sub-pixel 20 from a DC power supply connected between a power terminal 3a and a GND terminal 4a. The power terminal 3a and the GND terminal 4a are respectively provided at the ends of the power line 3 and the ground line 4, and are connected to a DC power supply circuit provided outside the display area 2. The power terminal 3a supplies a positive voltage with reference to the GND terminal 4a.

[0139] The image display device 1 further includes a scanning line 6 and a signal line 8. The scanning line 6 is wired in a direction parallel to the X axis. That is, the scanning line 6 is wired along the arrangement of the sub-pixels 20 in the row direction. The signal line 8 is wired in a direction parallel to the Y axis. That is, the signal line 8 is wired along the arrangement of the sub-pixels 20 in the column direction.

[0140] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via the scanning lines 6, and supplies a selection signal to each sub-pixel 20.

[0141] The signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display region 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 of each row via the signal lines 8, and supplies a signal voltage to each sub-pixel 20.

[0142] The sub-pixel 20 includes a light emitting element 22, a selection transistor 24, a driving transistor 26, and a capacitor 28. Figure 3 And the following description Figure 4 In the diagram, the selection transistor 24 is sometimes represented as T1, the drive transistor 26 is sometimes represented as T2, and the capacitor 28 is sometimes represented as Cm.

[0143] The light emitting element 22 is connected in series with the driving transistor 26. In the present embodiment, the driving transistor 26 is a p-channel TFT, and the anode electrode of the light emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain electrode and the source electrode. The anode electrode of the light emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light emitting element 22 is connected to the n-type semiconductor layer. The series circuit of the light emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to Figure 1 The transistor 103 in the embodiment of the present invention corresponds to the light emitting element 22. Figure 1 The light emitting element 150 in the embodiment. The current flowing to the light emitting element 22 is determined by the voltage applied between the gate and the source of the driving transistor 26, and the light emitting element 22 emits light with a brightness corresponding to the flowing current.

[0144] The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to the scanning line 6. The capacitor 28 is connected between the gate electrode of the drive transistor 26 and the power supply line 3.

[0145] The row selection circuit 5 selects a row from the arrangement of the m rows of sub-pixels 20, and supplies a selection signal to the scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each sub-pixel 20 of the selected row. The signal voltage is applied between the gate and the source of the driving transistor 26 of the sub-pixel 20 of the selected row. The signal voltage is held by the capacitor 28. The driving transistor 26 flows a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light at a brightness corresponding to the current flowing in the light-emitting element 22.

[0146] The row selection circuit 5 sequentially switches the selected row and supplies the selection signal. That is, the row selection circuit 5 scans the row where the sub-pixels 20 are arranged. A current corresponding to the signal voltage flows to the light-emitting element 22 of the sequentially scanned sub-pixel 20, and emits light. Each pixel 10 emits light with the color and brightness determined by the color and brightness of the light emitted by the sub-pixel 20 of each RGB color, and displays an image in the display area 2.

[0147] Figure 4 This is a schematic plan view illustrating a part of the image display device according to this embodiment.

[0148] In this embodiment, if Figure 1 As described in the description, the light emitting element 150 and the driving transistor 103 are laminated in the Z-axis direction via the first interlayer insulating film 156. Figure 3 The driving transistor 103 corresponds to the light emitting element 22. Figure 3 The transistor T2 corresponds to the driving transistor 26, also referred to as T2.

[0149] like Figure 4 As shown, the cathode electrode of the light emitting element 150 is provided by the connection portion 151a. The connection portion 151a is provided at a lower layer than the transistor 103 and the wiring layer 110. The connection portion 151a is electrically connected to the wiring 110k via a via 161k. More specifically, one end of the via 161k is connected to the connection portion 151a. The other end of the via 161k is connected to the wiring 110k via a contact hole 161k1.

[0150] The anode electrode of the light emitting element 150 is Figure 1 The p-type semiconductor layer 153 shown is provided. The wiring 110d extends to the surface including the light emitting surface 153S through the opening 158. The p-type semiconductor layer 153 is connected to one end of the wiring 110d via the surface including the light emitting surface 153S. The surface including the light emitting surface 153S is a surface in the same plane as the light emitting surface 153S. One end of the wiring 110d is connected to the surface including the light emitting surface 153S, and the remaining surface is the light emitting surface 153S.

[0151] The other end of the wiring 110d is connected to the drain electrode of the transistor 103 through the via 111d. The drain electrode of the transistor 103 is Figure 1 The source electrode of the transistor 103 is connected to the wiring 110s through the via 111s. Figure 1 In this example, the wiring layer 110 includes the power supply line 3 , and the wiring 110 s is connected to the power supply line 3 .

[0152] In this example, the ground line 4 is provided in a layer higher than the wiring layer 110. Figure 1 Although not shown in the figure, an interlayer insulating film is further provided on the wiring layer 110. The ground line 4 is provided on the uppermost interlayer insulating film and is insulated from the power line 3.

[0153] Thus, the light emitting element 150 can be electrically connected to the wiring layer 110 provided above the light emitting element 150 by using the via hole 161k. In addition, the light emitting element 150 can be electrically connected to the wiring layer 110 provided above the light emitting element 150 by providing the opening 158 that exposes the light emitting surface 153S.

[0154] A method for manufacturing the image display device 1 according to the present embodiment will be described.

[0155] Figure 5A to Figure 5C This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0156] like Figure 5A As shown, in the manufacturing method of the image display device 1 of this embodiment, a plurality of semiconductor growth substrates 1194 are prepared. The plurality of semiconductor growth substrates 1194 respectively include a crystal growth substrate 1001, a buffer layer 1140, and a semiconductor layer 1150. The crystal growth substrate (first substrate) 1001 is, for example, a Si substrate or a sapphire substrate. Preferably, a Si substrate is used as the crystal growth substrate 1001. In addition, as described later, in the case of using a low-temperature crystal growth process such as a low-temperature sputtering method, a cheaper glass substrate or the like can also be used.

[0157] The buffer layer 1140 is formed on one surface of the crystal growth substrate 1001. Nitride such as AlN is preferably used for the buffer layer 1140. The semiconductor layer 1150 is crystal-grown via the buffer layer 1140, thereby alleviating the interface disconformity between the GaN crystal and the crystal growth substrate 1001.

[0158] The semiconductor layer 1150 is formed on the buffer layer 1140. The semiconductor layer 1150 includes: an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 are laminated in this order from the buffer layer 1140 side. The formation of the semiconductor layer 1150 can be achieved, for example, by using a chemical vapor deposition (CVD) method, and is preferably achieved by using a metal organic chemical vapor deposition (MOCVD) method. Alternatively, at a process temperature below 700°C, the semiconductor layer 1150 can also be epitaxially grown by a low-temperature sputtering method, thereby reducing the manufacturing cost by using a glass substrate or device with lower heat resistance. The semiconductor layer 1150 includes, for example, GaN, and more specifically, In. X Al Y Ga 1-X-Y N(0≦X, 0≦Y, X+Y<1), etc.

[0159] In the early stage of crystal growth, crystal defects may be generated due to the mismatch of lattice constants, and the crystal with crystal defects is n-type. Therefore, as in this example, when the semiconductor layer 1150 is formed from the n-type semiconductor layer 1151 on the crystal growth substrate 1001, the margin in the manufacturing process can be increased, so there is an advantage that the yield rate can be easily improved.

[0160] like Figure 5B As shown, after the semiconductor layer 1150 is formed on the buffer layer 1140, the support substrate 1190 is bonded to the exposed surface of the p-type semiconductor layer 1153. The support substrate 1190 is formed of, for example, quartz glass or Si. After the support substrate 1190 and the semiconductor layer 1150 are bonded, the crystal growth substrate 1001 is removed to form a substrate 1195 (second substrate). The crystal growth substrate 1001 can be removed by, for example, wet etching or laser stripping.

[0161] The process before forming the semiconductor growth substrate 1194 and the process after forming the substrate 1195 can be performed in the same device or in different devices. For example, the substrate 1195 can be manufactured in a first device, and the substrate 1195 can be transported to a second device different from the first device to perform the subsequent process.

[0162] like Figure 5C As shown, a plurality of substrates 1195 are bonded to a single substrate 102 (third substrate). The plurality of substrates 1195 are bonded to the first surface 102 a of the single substrate 102 with the semiconductor layer 1150 interposed between the buffer layer 1140 .

[0163] In the process of bonding the substrates, the surfaces of the substrates are bonded to each other. In this process, for example, the substrates are bonded to each other by heating and hot pressing each substrate. When hot pressing, a low melting point metal or a low melting point alloy may also be used. The low melting point metal may be, for example, Sn or In, and the low melting point alloy may be, for example, an alloy containing Zn, In, Ga, Sn, Bi, etc. as the main component.

[0164] In the substrate bonding step, in addition to the above, after the bonding surfaces of the substrates are flattened by chemical mechanical polishing (CMP) or the like, the bonding surfaces may be cleaned by plasma treatment in a vacuum and brought into close contact.

[0165] The substrate 102 is, for example, a roughly rectangular glass substrate of about 1500 mm×1800 mm. The substrate 1195 is a rectangular or square shape of about several 10 mm square to about 150 mm square, and when converted into a wafer size, it is, for example, about 4 inches to 6 inches in size. The size of the substrate 102 is appropriately selected according to the size of the image display device, etc. In the case where the size of the substrate 102 is, for example, a rectangular or square shape of about several 10 mm square to about 150 mm square, one semiconductor layer 1150 may be bonded to one substrate 102 as in the case of the second embodiment described later.

[0166] Figure 6 It is a perspective view illustrating a method for manufacturing the image display device according to this embodiment.

[0167] Figure 6 The figure above the arrows shows a situation where multiple substrates 1195 are arranged in a grid pattern. Figure 6 The figure below the arrow shows the case where the substrate 102 is configured. Figure 6 Arrows indicate that the plurality of substrates 1195 arranged in a grid pattern are bonded together at positions along two-dot chain lines as described later.

[0168] The crystal quality is reduced at the end of the semiconductor layer 1150 and its vicinity, so it is necessary to be careful not to form the light emitting element 150 at the end of the semiconductor layer 1150 and its vicinity.

[0169] like Figure 6 As shown, the end of the semiconductor layer 1150 is formed substantially in line with the end of the support substrate 1190. Figure 6 As shown by the solid line, the plurality of substrates 1195 are arranged in a grid pattern opposite to the substrate 102 so as to minimize the occurrence of gaps between adjacent substrates 1195. Figure 6As shown by the two-dot chain line, the semiconductor layer 1150 is attached to the substrate 102 via the buffer layer 1140 .

[0170] When a plurality of semiconductor layers 1150 are bonded to one substrate 102, the substrate 102 bonded to the plurality of semiconductor layers 1150 can be divided before or after the color filter is assembled to form image display devices of a number and size corresponding to the number of divisions. The end of the semiconductor layer 1150 with reduced crystal quality is preferably the end of the display area, so the division unit is preferably set in accordance with the shape of the substrate 1195. Fig.12 and FIG. 13A to FIG. 13D The relevant information will be described later.

[0171] Figures 7A to 8B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0172] exist Figures 7A to 8B In the embodiment of the present invention, two modifications related to the substrate bonding process are shown. Figure 5A to Figure 5C The process is Figure 7A to Figure 7C In addition, it can also replace Figure 5A to Figure 5C The process is Fig. 8A and Figure 8B process.

[0173] exist Figure 7A to Figure 7C In the manufacturing process shown, the semiconductor layer 1150 is not Figure 5A The buffer layer 1140 shown is formed on one surface of the crystal growth substrate 1001 .

[0174] like Fig. 7A As shown, replace Figure 5A The plurality of semiconductor growth substrates 1194 shown in the figure are prepared as a plurality of semiconductor growth substrates 1194a. The plurality of semiconductor growth substrates 1194a each include a crystal growth substrate 1001 and a semiconductor layer 1150. The semiconductor layer 1150 is directly formed on one surface of the crystal growth substrate 1001. The formation of the semiconductor layer 1150 is similar to Figure 5A The same situation is used, using CVD method or MOCVD method, etc.

[0175] like Figure 7B As shown, a support substrate 1190 is bonded to the exposed surface of the p-type semiconductor layer 1153. After the support substrate 1190 is bonded to the semiconductor layer 1150, the crystal growth substrate 1001 is removed by wet etching or laser lift-off to form a substrate 1195a.

[0176] like Figure 7CAs shown, the exposed surface of the n-type semiconductor layer 1151 is arranged to face the first surface 102a of the substrate 102. Thereafter, the exposed surface of the n-type semiconductor layer 1151 is bonded to the first surface 102a.

[0177] exist Fig. 8A and Figure 8B In the present invention, the semiconductor growth substrate 1294 is bonded to the substrate 102 without transferring to the support substrate. In the semiconductor growth substrate 1294, the lamination order of the semiconductor layers formed on the crystal growth substrate 1001 is the same as that of the semiconductor growth substrate 1294. Figure 5A and Fig. 7A The situation is different.

[0178] like Fig. 8A As shown, the plurality of semiconductor growth substrates 1294 respectively include a crystal growth substrate 1001 and a semiconductor layer 1150. The semiconductor layer 1150 is directly grown on one surface of the crystal growth substrate 1001. The semiconductor layer 1150 includes a p-type semiconductor layer 1153, a light emitting layer 1152, and an n-type semiconductor layer 1151. The p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 are laminated in this order from the crystal growth substrate 1001 side.

[0179] like Figure 8B As shown, the semiconductor growth substrate 1294 is turned upside down and the exposed surface of the n-type semiconductor layer 1151 is arranged to face the first surface 102a of the substrate 102. The exposed surface of the n-type semiconductor layer 1151 and the first surface 102a of the substrate 102 are bonded to each other.

[0180] Alternatively, a buffer layer may be formed on the crystal growth substrate 1001 instead of the semiconductor growth substrate 1294, and on the buffer layer, a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151 may be formed in this order from the buffer layer side. In this case, a step of removing the remaining buffer layer needs to be added in any of the steps before and after the step of processing the semiconductor layer 1150 to form a light-emitting element.

[0181] The method of bonding the semiconductor layer 1150 to the substrate 102 is not limited to the above description, and the following method may be used. That is, after the semiconductor layer 1150 is formed on the crystal growth substrate 1001, it is stored in a container, for example, by installing the support substrate 1190 in the container, with the crystal growth substrate 1001 removed. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the substrate 102. In addition, the semiconductor layer 1150 does not need to be installed on the support substrate 1190, but is stored in the container. After storage, the semiconductor layer 1150 is taken out of the container and directly bonded to the substrate 102.

[0182] The description will continue with the manufacturing process after the substrate bonding process.

[0183] Figures 9A to 10B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0184] like Fig. 9A As shown, Figure 5C The support substrate 1190 is shown being removed by wet etching, laser lift-off, or the like.

[0185] As in Figure 6 As described in , the plurality of substrates 1195 are arranged adjacent to each other and bonded to the substrate 102. The position X1 is a position where the ends of the adjacent substrates 1195 are arranged. At the position X1, the ends of the semiconductor layer 1150 are also adjacent to each other and close to each other.

[0186] like Fig. 9B As shown, Fig. 9A The semiconductor layer 1150 shown is processed into a desired shape by etching to form the light emitting element 150. The light emitting element 150 is formed at a position sufficiently away from the region including the position X1. The crystal quality near the end of the semiconductor layer 1150 is evaluated, and the region including the position X1 is determined based on the evaluation result.

[0187] In the light emitting element 150, the connection portion 151a is formed, and then other portions are formed by etching. Thus, the light emitting element 150 having the connection portion 151a protruding from the n-type semiconductor layer 151 in the positive direction of the X axis can be formed on the first surface 102a. The light emitting element 150 is formed by, for example, a dry etching process, preferably anisotropic plasma etching (Reactive Ion Etching, RIE). Fig. 9A The buffer layer 1140 shown is etched together with the semiconductor layer 1150 , and the buffer layer 140 remains between the first surface 102 a and the n-type semiconductor layer 151 .

[0188] like Fig. 9C As shown, a first interlayer insulating film 156 (first insulating film) is formed to cover the first surface 102a, the buffer layer 140, and the light emitting element 150. The TFT lower layer film 106 is formed on the first interlayer insulating film 156 by, for example, CVD or the like.

[0189] The TFT channel 104 is formed at a predetermined position on the TFT lower film 106. For example, in the LTPS process, the transistor 103 is formed as follows. First, an amorphous Si film is formed into the shape of the TFT channel 104. The amorphous Si film can be formed by, for example, CVD. The formed amorphous Si film is polycrystallized by laser annealing to form the TFT channel 104.

[0190] Thereafter, the source electrode and the drain electrode of the TFT channel 104 are formed by introducing B into the regions 104s and 104d, for example, by using ion implantation technology. + The source electrode and the drain electrode formation process may be performed after the gate electrode 107 formation process.

[0191] The insulating layer 105 is formed over the TFT lower film 106 and the TFT channel 104. The insulating layer 105 is formed, for example, by CVD. The gate 107 is formed at a position on the TFT channel 104 via the insulating layer 105. The gate 107 is formed by an appropriate formation method according to the material of the gate 107. For example, when the gate 107 is polycrystalline Si, it is formed by laser annealing amorphous Si to make it polycrystalline, similar to the TFT channel 104.

[0192] The second interlayer insulating film 108 (second insulating film) is provided to cover the insulating layer 105 and the gate electrode 107. The second interlayer insulating film 108 is formed by an appropriate method according to the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is formed of SiO2, a technique such as ALD or CVD can be used.

[0193] The flatness of the second interlayer insulating film 108 may be such that the wiring layer 110 can be formed, and the flattening process is not necessarily performed. In the case where the flattening process is not performed on the second interlayer insulating film 108, the number of processes can be reduced. For example, in the case where there is a position where the thickness of the second interlayer insulating film 108 is reduced around the light emitting element 150, since the depth of the via hole 162k becomes shallower, a sufficient opening diameter can be ensured. Therefore, it is easy to ensure electrical connection based on the via hole, and it is possible to suppress the reduction of the yield due to the problem of electrical characteristics.

[0194] like Fig. 10AAs shown, the via hole 162k is formed by penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 to reach the surface of the connection portion 151a. The opening 158 is formed by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower film 106, and a portion of the first interlayer insulating film 156 to reach the light emitting surface 153S. A portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower film 106, and a portion of the first interlayer insulating film 156 are formed at positions on the light emitting surface 153S among the above-mentioned insulating layers and insulating films. The via hole 112d is formed by penetrating the second interlayer insulating film 108 and the insulating layer 105 to reach the surface of the region 104d. The via hole 112s is formed by penetrating the second interlayer insulating film 108 and the insulating layer 105 to expose the surface of the region 104s. The via hole and the opening can be formed by, for example, RIE.

[0195] like Fig. 10B As shown, via 161k passes through Fig. 10A The via hole 162k is formed by filling the via hole 162k with a conductive material. Fig. 10A The via holes 112d and 112s are filled with conductive materials and formed respectively. Then, the wiring layer 110 is formed on the second interlayer insulating film 108, and the wirings 110k, 110d, and 110s are formed. The wiring layer 110 may be formed simultaneously with the formation of the via holes 161k, 111d, and 111s.

[0196] Fig.11A and Fig. 11B This is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device of the present embodiment.

[0197] Fig.11A and Fig. 11B Indicates the use to form Figure 2 In this modification, the same steps as the above steps are performed before the second interlayer insulating film 108 is formed and the via holes 162k, 112d, and 112s are formed. Fig. 10A Execute the process later Fig.11A and Fig. 11B The process will be explained below.

[0198] like Fig.11A As shown, vias 161k, 111d, 111s pass through Fig. 10AThe via holes 162k, 112d, and 112s shown are formed by filling a conductive material. After that, the wiring layer 110 is formed, and the wirings 110k, 110d1, and 110s are formed. Here, one end of the wiring 110d1 is connected to the via hole 111d. On the other hand, the other end of the wiring 110d1 is not directly connected to the light emitting surface 153S, but is located at a position away from the opening 158. The via holes 161k, 111d, and 111s and the wiring layer 110 can also be formed at the same time, which is the same as the case of the first embodiment.

[0199] like Fig. 11B As shown, a translucent electrode 159d is formed over the wiring 110d1 and the light-emitting surface 153S. The translucent electrode 159d is also formed between the wiring 110d1 and the light-emitting surface 153S to electrically connect the wiring 110d1 and the light-emitting surface 153S. The translucent electrode 159s is formed over the wiring 110s. The translucent electrodes 159d and 159s are formed at the same time. When a translucent electrode is formed on the wiring 110k, it is formed at the same time as the translucent electrodes 159d and 159s. It should be noted that the roughening treatment on the light-emitting surface 153S can be performed at any time after the opening 158 is provided and before the translucent electrode 159d is formed.

[0200] In this way, the sub-pixel 20 a of the modified example is formed.

[0201] For example Figure 3 The circuit is a driving circuit for driving the light emitting element 150 by the selection transistor 24, the driving transistor 26 and the capacitor 28. The driving circuit is formed in the sub-pixel 20, 20a. A part of the circuit other than the driving circuit is outside the sub-pixel 20, 20a, for example Figure 1 The peripheral portion of the display area 2 shown is formed. Figure 3 The row selection circuit 5 shown is formed simultaneously with the drive transistor, the selection transistor, etc., and is formed at the peripheral portion of the display region 2. That is, the row selection circuit 5 can be assembled simultaneously through the above-mentioned manufacturing steps.

[0202] The signal voltage output circuit 7 is preferably assembled in a semiconductor device manufactured by a manufacturing process that can be highly integrated through fine processing. The signal voltage output circuit 7 is mounted on another substrate together with the CPU and other main circuit components, for example, before assembling the color filter described later, or after assembling the color filter, and is connected to the sub-pixels 20 and 20a via a connector provided at the periphery of the display area.

[0203] In the image display device 1 of the present embodiment, each light emitting element 150 can form an image in the display area 2 by emitting light upward from the light emitting surface 153S. However, when light is scattered toward a lower direction than the light emitting surface 153S, the light emitting efficiency is actually reduced because the substrate 102 has light transmittance. Therefore, for example, by providing a light reflecting film or a light reflecting plate on one side of the surface of the substrate 102 opposite to the first surface 102a, the light scattered toward the substrate 102 can be reflected toward the light emitting surface 153S. The above-mentioned light reflecting film or the like can be provided on the substrate 102, or can be provided inside a housing or a frame, etc., that fixes the image display device 1.

[0204] Fig.12 This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0205] exist Fig.12 In the figure, the figure above the arrow shows the structure including the color filter 180, and the figure below the arrow shows the structure including the light emitting element 150 formed in the above process. Fig.12 The arrows indicate a step of bonding a color filter to a structure including the light emitting element 150 and the like.

[0206] exist Fig.12 In order to avoid complication, the main structural components other than the main structural components on the substrate 102 shown in the figure are omitted. The omitted main structural components are Figure 1 The buffer layer 140, the circuit 101 including the TFT channel 104 and the wiring layer 110, and the via 161k are shown. Fig.12 180 and other color conversion components. Figure 12 to Figure 13D In the related description, the light emitting element 150, the first interlayer insulating film 156, the circuit 101, the TFT lower film 106 and the surface resin layer 170 are referred to as the light emitting circuit portion 172, and the structure including the substrate 102, the light emitting circuit portion 172 and the omitted main structural components is referred to as the structure 1192. Fig.12 In FIG. 1 , among the main components constituting the circuit 101, the TFT channel 104, the vias 111s and 111d, and the wiring layer 110 are omitted.

[0207] like Fig.12 As shown, the color filter (wavelength conversion component) 180 is bonded to the structure 1192 on one side. The other side of the color filter 180 is bonded to the glass substrate 186. A transparent film adhesive layer 188 is provided on one side of the color filter 180, and the color filter 180 is bonded to the exposed side of the surface resin layer 170 of the structure 1192 via the transparent film adhesive layer 188.

[0208] In this example, the color filter 180 has color conversion sections arranged in the order of red, green, and blue in the positive direction of the X axis. For red, a red color conversion layer 183R is provided in the first layer, and for green, a green color conversion layer 183G is provided in the first layer. In either case, a filter layer 184 is provided in the second layer. For blue, a single-layer color conversion layer 183B may be provided, or a filter layer 184 may be provided. Although a light shielding section 181 is provided between each color conversion section, it is of course possible to change the frequency characteristics of the filter layer 184 for each color of the color conversion section.

[0209] The positions of the color conversion layers 183R, 183G, and 183B of the respective colors are aligned with the positions of the light emitting elements 150 , and the color filter 180 is attached to the structure 1192 .

[0210] FIG. 13A to FIG. 13D This is a schematic cross-sectional view showing a modified example of the method for manufacturing the image display device according to the present embodiment.

[0211] FIG. 13A to FIG. 13D A method of forming a color filter by an inkjet method is shown.

[0212] like Fig.13A As shown in FIG. 1 , a structure 1192 in which main components such as the light emitting element 150 are formed on the substrate 102 is prepared.

[0213] like Fig. 13B As shown in FIG. 1 , a light shielding portion 181 is formed on the structure 1192. The light shielding portion 181 is formed by, for example, screen printing or photolithography technology.

[0214] like Fig. 13C As shown, the phosphor corresponding to the luminous color is ejected from the inkjet nozzle to form a color conversion layer 183. The phosphor is colored in the area where the shading portion 181 is not formed. The phosphor can use a fluorescent paint, which uses, for example, a common fluorescent material, a perovskite fluorescent material, or a quantum dot fluorescent material. When a perovskite fluorescent material or a quantum dot fluorescent material is used, various luminous colors can be achieved, and the monochromaticity is increased, which can improve the color reproducibility, and is therefore preferred. After being drawn by the inkjet nozzle, a drying process is performed at an appropriate temperature and time. When coloring, the thickness of the coating is set to be thinner than the thickness of the shading portion 181.

[0215] As described above, for a sub-pixel emitting blue light, when a color conversion portion is not formed, the color conversion layer 183 is not formed. In addition, for a sub-pixel emitting blue light, when a blue color conversion layer is formed, when the color conversion portion may be a single layer, it is preferred that the coating thickness of the blue phosphor is about the same as the thickness of the light shielding portion 181a.

[0216] like Fig.13D As shown, the paint for the filter layer 184 is ejected from an inkjet nozzle. The paint is applied so as to overlap with the coating film of the fluorescent body 183a. The total thickness of the coating film of the fluorescent body and the paint is about the same as the thickness of the light shielding portion 181.

[0217] Regardless of whether it is a thin-film color filter or an inkjet color filter, in order to improve the color conversion efficiency, it is desirable that the color conversion layer 183 is as thick as possible. On the other hand, when the color conversion layer 183 is too thick, the emission light of the color-converted light is close to Lambertian, while the emission angle of the blue light that has not been color-converted is limited by the light shielding portion 181. Therefore, there is a problem that the display color of the displayed image depends on the viewing angle. In order to combine the light distribution of the sub-pixel provided with the color conversion layer 183 with the light distribution of the blue light that has not been color-converted, it is desirable that the thickness of the color conversion layer 183 is about half the opening size of the light shielding portion 181.

[0218] For example, in the case of a high-definition image display device with a resolution of about 250 ppi, the pitch of the sub-pixels 20 is about 30 μm, so the thickness of the color conversion layer 183 is preferably about 15 μm. Here, in the case where the color conversion material is formed of spherical phosphor particles, in order to suppress light leakage from the light-emitting element 150, it is preferably laminated into a dense structure. Therefore, the particle layer needs to be at least three layers. Therefore, the particle size of the phosphor material constituting the color conversion layer 183 is preferably, for example, about 5 μm or less, and more preferably about 3 μm or less.

[0219] Fig.14 It is a schematic perspective view illustrating the image display device according to this embodiment.

[0220] like Fig.14 As shown in FIG. 1 , the image display device of this embodiment has a light emitting circuit section 172 having a large number of sub-pixels 20 on a substrate 102. A color filter 180 is provided on the light emitting circuit section 172. Fig.14 The structure is the same as the structure shown.

[0221] Effects of the image display device 1 of the present embodiment will be described.

[0222] In the manufacturing method of the image display device 1 of the present embodiment, after the semiconductor layer 1150 and the substrate 102 are bonded together, the semiconductor layer 1150 is etched to form the light emitting element 150. Thereafter, the light emitting element 150 is covered with the first interlayer insulating film 156, and the circuit 101 including circuit elements such as the transistor 103 for driving the light emitting element 150 is implanted on the first interlayer insulating film 156. Therefore, compared with the case where the singulated light emitting elements are individually transferred on the substrate 102, the manufacturing process can be significantly shortened.

[0223] For example, in an image display device with 4K image quality, the number of sub-pixels exceeds 24 million, and in the case of an image display device with 8K image quality, the number of sub-pixels exceeds 99 million. It takes a lot of time to form such a large number of light-emitting elements individually and install them on a circuit substrate. Therefore, it is difficult to realize an image display device formed by micro-LEDs at a realistic cost. In addition, the individual installation of a large number of light-emitting elements will reduce the yield due to poor connection during installation, etc., and thus inevitably increase the cost, but in the manufacturing method of the image display device of this embodiment, the following effect can be obtained.

[0224] As described above, in the manufacturing method of the image display device 1 of the present embodiment, after the semiconductor layer 1150 is bonded to the substrate 102 as a whole, the light emitting element is formed by etching, so the transfer process is completed at one time. Therefore, in the manufacturing method of the image display device 1 of the present embodiment, the time of the transfer process can be shortened and the number of processes can be reduced compared to the existing manufacturing method.

[0225] In addition, there is no need to separate the semiconductor layer 1150 in advance or to form electrodes at positions corresponding to circuit elements. Instead, the semiconductor layer 1150 is bonded to the substrate 102 at the wafer level, so there is no need to perform alignment at the bonding stage. Therefore, the bonding process can be easily performed in a short time. Since there is no need to perform alignment during bonding, it is also easy to miniaturize the light emitting element 150, which is suitable for high-definition displays.

[0226] In this embodiment, for example, the glass substrate formed as described above can be covered with an interlayer insulating film, and a driving circuit and a scanning circuit including TFTs can be formed on the flattened surface by using an LTPS process, etc. Therefore, there is an advantage that the manufacturing process and equipment of existing flat panel displays can be used.

[0227] In this embodiment, the light emitting element 150 formed in a lower layer than the transistor 103 and the like can be electrically connected to the power supply line, ground line, driving transistor and the like formed in the upper layer by forming a via hole penetrating the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105 and the second interlayer insulating film 108. By using the technically established multi-layer wiring technology in this way, a uniform connection structure can be easily realized and the yield can be improved. Therefore, it is possible to suppress the reduction of the yield due to poor connection of the light emitting element and the like.

[0228] (Second Embodiment)

[0229] Fig.15 This is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0230] The difference between this embodiment and the other embodiments described above is that the light reflecting layer 120 including the light reflecting plate 120a is provided on the first surface 102a, and the light emitting element 250 is provided on the light reflecting plate 120a via the insulating layer 114. The difference between this embodiment and the other embodiments described above is that the n-type semiconductor layer 251 provides the light emitting surface 251S. The difference between this embodiment and the other embodiments described above is that there is a structure in which the light emitting element 250 is driven by the transistor 203. For the main components of the same structure as in the other embodiments, the same reference numerals are used, and detailed descriptions are appropriately omitted.

[0231] like Fig.15 As shown, the sub-pixel 220 of the image display device of this embodiment includes: a substrate 102, a light reflecting layer 120, a light emitting element 250, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via 261a, and a wiring layer 110.

[0232] The light reflecting layer 120 (a layer having light reflectivity) is provided on the first surface 102a. The light reflecting layer 120 includes a light reflecting plate 120a. The light reflecting plate 120a (first part) is a film-like, layer-like, or plate-like component having a square, arbitrary polygonal, elliptical, circular, or other shape when viewed from above the XY plane.

[0233] The light reflecting layer 120 includes a plurality of light reflecting plates 120a, and the light reflecting plates 120a are provided at each position where the light emitting element 250 is provided. In this example, the plurality of light reflecting plates 120a are separated from each other.

[0234] The periphery of the light reflecting plate 120a can be set to include the periphery of the light emitting element 250 when the light emitting element 250 is projected in the XY plane top view. The light reflecting plate 120a can be provided for each light emitting element 250, or can be provided every plurality of light emitting elements 250. The light reflecting plates 120a can also be connected and formed into a grid shape, for example, without being separated for each light emitting element 250. In this case, the light emitting element 250 is provided, for example, at the position of the grid crossed by the light reflecting plates 120a. The light reflecting layer 120 can also be a single light reflecting plate 120a. A single light reflecting plate 120a, for example, Figure 2 The entire surface of the display area 2 shown is set.

[0235] The light reflecting plate 120a is made of a material having light reflectivity. The light reflecting plate 120a is made of a metal material such as Ag or an alloy containing Ag, for example. Any material having light reflectivity can be used, not limited to Ag.

[0236] An insulating layer 114 is provided over the first surface 102a, the light reflecting layer 120, and the light reflecting plate 120a. The insulating layer 114 is formed of an oxide film such as SiO2. The insulating layer 114 is provided to insulate the light reflecting plate 120a from the light emitting element 250. In addition, as described later, the insulating layer 114 provides a flat surface when the substrate is bonded.

[0237] The light emitting element 250 is provided on the light reflecting plate 120a via the insulating layer 114. The light emitting element 250 is provided directly above the light reflecting plate 120a.

[0238] By setting the light reflecting plate 120a in this way, the light scattered downward from the light emitting element 250 is reflected upward by the light reflecting plate 120a. Therefore, the luminous efficiency of the light emitting element 250 is actually improved. It is preferred that the periphery of the light reflecting plate 120a is set so that when the transistor 203 is projected onto the plane including the light reflecting plate 120a in the XY plane top view, the periphery of the transistor 203 is not included. By setting it in this way, the transistor 203 is not easily received by the reflected light from the light reflecting plate 120a, and the probability of erroneous operation can be substantially reduced. The periphery of the transistor 203 in the XY plane top view refers to the periphery of the TFT channel in the XY plane top view.

[0239] The light emitting element 250 includes a light emitting surface 251S. The light emitting element 250 is a prism-shaped or cylindrical element having a bottom surface 253B on the first surface 102a, as in the other embodiments described above. The light emitting surface 251S is a surface opposite to the bottom surface 253B. The bottom surface 253B is a surface in contact with the insulating layer 114 in this example.

[0240] The light emitting element 250 includes a p-type semiconductor layer 253, a light emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light emitting layer 252, and the n-type semiconductor layer 251 are laminated in this order from the bottom surface 253B to the light emitting surface 251S. In this embodiment, the light emitting surface 251S is provided by the n-type semiconductor layer 251. Since the n-type semiconductor layer 251 can have a lower resistance value than the p-type semiconductor layer 253, the thickness can be increased. Therefore, it is easy to roughen the light emitting surface 251S.

[0241] The light emitting element 250 includes a connection portion 253a. The connection portion 253a is provided on the insulating layer 114 so as to protrude in one direction from the p-type semiconductor layer 253. The height of the connection portion 253a is the same as that of the p-type semiconductor layer 253, or is lower than that of the p-type semiconductor layer 253, and the light emitting element 250 is formed in a stepped shape. The connection portion 253a is p-type and is electrically connected to the p-type semiconductor layer 253. The connection portion 253a is connected to one end of the via 261a, and the p-type semiconductor layer 253 is electrically connected to the via 261a.

[0242] The light emitting element 250 has the same shape as the light emitting element 150 of the other embodiments described above when viewed from the XY plane. An appropriate shape is selected according to the design of the circuit element, etc. The shape of the light reflecting plate 120a when viewed from the XY plane can be any shape as described above, and an appropriate shape is selected according to the design of the circuit element, etc.

[0243] The light emitting element 250 is a light emitting diode similar to the light emitting element 150 of the other embodiments described above. That is, the wavelength of the light emitted by the light emitting element 250 is, for example, blue light of about 467nm±20nm, or blue-violet light of about 410nm±20nm. The wavelength of the light emitted by the light emitting element 250 is not limited to the above values, and can be any appropriate value.

[0244] The transistor 203 is disposed on the TFT lower film 106. The transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process, etc., as in the other embodiments described above. In this embodiment, the circuit 101 includes: a TFT channel 204, an insulating layer 105, a second interlayer insulating film 108, vias 111s, 111d, and a wiring layer 110.

[0245] The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are disposed on the TFT lower layer film 106. The regions 204s and 204d are doped with phosphorus ions (P - ) and other n-type impurities. The region 204s is ohmically connected to the via 111s. The region 204d is ohmically connected to the via 111d.

[0246] The gate electrode 107 is provided on the TFT channel 204 via the insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate electrode 107.

[0247] In the transistor 203, when a voltage higher than that of the region 204s is applied to the gate 107, a channel is formed in the region 204i. The current flowing between the regions 204s and 204d is controlled by the voltage of the region 204s by the gate 107. The TFT channel 204 and the gate 107 are formed using the same material and manufacturing method as the TFT channel 104 and the gate 107 in the case of the above-mentioned other embodiments.

[0248] The wiring layer 110 includes wirings 110s, 110d1, and 210a. Figure 2 The same as the case of the modified example of the first embodiment described above. A portion of the wiring 210a (first wiring) is provided above the connecting portion 253a. The other portion of the wiring 210a extends, for example, to the Fig.16The power cord 3 shown is connected to the power cord 3.

[0249] The via holes 111s and 111d are provided to penetrate the second interlayer insulating film 108. The via hole 111s is provided between the wiring 110s and the region 204s. The via hole 111s electrically connects the wiring 110s and the region 204s. The via hole 111d is provided between the wiring 110d1 and the region 204d. The via hole 111d electrically connects the wiring 110d1 and the region 204d. The via holes 111s and 111d are formed by the same material and manufacturing method as in the case of the other embodiments described above.

[0250] The via hole 261a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via hole 261a is provided between the wiring 210a and the connecting portion 253a, and electrically connects the wiring 210a and the connecting portion 253a.

[0251] The wiring 110s (second wiring) is, for example, the same as the wiring described later. Fig.16 The wiring 110d1 is electrically connected to the n-type semiconductor layer 251 via the light-transmitting electrode 159d.

[0252] In the present embodiment, the light-transmitting electrode 159d is provided over the roughened light-emitting surface 251S of the n-type semiconductor layer 251. The light-transmitting electrode 159d is provided over the wiring 110d1. The light-transmitting electrode 159d is also provided between the light-emitting surface 251S and the wiring 110d, and electrically connects the n-type semiconductor layer 251 and the wiring 110d.

[0253] As in the case of the other embodiments described above, Figure 1 In the example shown, the wiring 110 d may be extended to be directly connected to the n-type semiconductor layer 251 .

[0254] Fig.16 : is a schematic block diagram illustrating an image display device according to this embodiment.

[0255] like Fig.16 As shown, the image display device 201 of this embodiment includes a display region 2, a row selection circuit 205, and a signal voltage output circuit 207. As in the other embodiments described above, in the display region 2, sub-pixels 220 are arranged in a grid pattern on the XY plane.

[0256] The pixel 10 is the same as the other embodiments described above, and includes a plurality of sub-pixels 220 that emit light of different colors. The sub-pixel 220R emits red light. The sub-pixel 220G emits green light. The sub-pixel 220B emits blue light. The three sub-pixels 220R, 220G, and 220B emit light at a desired brightness, thereby determining the light color and brightness of one pixel 10.

[0257] One pixel 10 includes three sub-pixels 220R, 220G, and 220B, which are arranged in a straight line on the X axis as in this example. Each pixel 10 may arrange sub-pixels of the same color in the same column, or may arrange sub-pixels of different colors in each column as in this example.

[0258] The sub-pixel 220 includes a light emitting element 222, a selection transistor 224, a driving transistor 226, and a capacitor 228. Fig.16 In the diagram, the selection transistor 224 is sometimes represented as T1, the driving transistor 226 is sometimes represented as T2, and the capacitor 228 is sometimes represented as Cm.

[0259] In this embodiment, the light emitting element 222 is provided on the power supply line 3 side, and the driving transistor 226 connected in series with the light emitting element 222 is provided on the ground line 4 side. That is, the driving transistor 226 is connected to a lower potential side than the light emitting element 222. The driving transistor 226 is an n-channel transistor.

[0260] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the ground line 4.

[0261] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage having a different polarity from that of the other embodiments described above to the signal line 208 in order to drive the driving transistor 226 which is an n-channel transistor.

[0262] In this embodiment, since the polarity of the driving transistor 226 is an n-channel, the polarity of the signal voltage is different from that of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select a row from the arrangement of the sub-pixels 220 in the m rows. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each sub-pixel 220 in the selected row. The driving transistor 226 of the sub-pixel 220 in the selected row flows a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light at a brightness corresponding to the flowing current.

[0263] A method for manufacturing the image display device of this embodiment will be described.

[0264] Figures 17A to 19B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0265] like Fig.17A As shown, in the manufacturing method of the image display device of this embodiment, a semiconductor growth substrate (second substrate) 1194a is prepared and bonded to a substrate 102 (third substrate). As in the case of the above-mentioned other embodiments, a plurality of semiconductor growth substrates may be prepared and bonded to a substrate 102. With respect to the method of bonding the semiconductor layer 1150 to the substrate 102, the above-mentioned other embodiments and various variations thereof may be applied.

[0266] The semiconductor growth substrate 1194a has a semiconductor layer 1150 formed on a crystal growth substrate (first substrate) 1001. As already described, the crystal growth substrate 1001 is, for example, a Si substrate or a sapphire substrate, preferably a Si substrate. Alternatively, in the case of using a low-temperature crystallization process, a cheaper glass substrate may also be used.

[0267] The semiconductor layer 1150 includes an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 are laminated in the order of the n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 from the side of the crystal growth substrate 1001. The formation of the semiconductor layer 1150 is the same as that of the other embodiments described above, and can be epitaxially grown by CVD method, MOCVD method, or low-temperature sputtering method, and can be a low-temperature process of 700°C or less.

[0268] The light reflecting layer 120 (a layer having light reflectivity) is formed on the first surface 102a before the semiconductor layer 1150 is bonded to the substrate 102. The light reflecting layer 120 can be formed by sputtering or the like, or by applying Ag paste or the like in the shape of the light reflecting plate 120a and then firing it. The light reflecting plate 120a of the light reflecting layer 120 is set at a position where the light emitting element 250 is formed. The insulating layer 114 is formed over the first surface 102a, the light reflecting layer 120, and the light reflecting plate 120a before the semiconductor layer 1150 is bonded to the substrate 102. The insulating layer 114 is formed by CVD or the like. Since the exposed surface of the insulating layer 114 is the bonding surface with the substrate 102, it is flattened by CMP or the like.

[0269] The semiconductor growth substrate 1194a is arranged so that the exposed surface of the p-type semiconductor layer 1153 faces the planarized exposed surface of the insulating layer 114 provided on the substrate 102. The exposed surface of the p-type semiconductor layer 1153 and the exposed surface of the insulating layer 114 are bonded to each other.

[0270] like Fig. 17B As shown, Fig.17A The crystal growth substrate 1001 shown is removed by wet etching, laser lift-off or the like.

[0271] like Fig. 17C As shown, Fig. 17B The semiconductor layer 1150 is etched and molded into a desired shape to form the light emitting element 250. As in the first embodiment, the light emitting element 250 is formed after the connection portion 253a is formed, and then the remaining portion is formed. The light emitting element 250 can be formed by, for example, a dry etching process, preferably RIE.

[0272] like Fig.18A As shown, the first interlayer insulating film 156 is formed to cover the insulating layer 114 and the light emitting element 250 .

[0273] like Fig.18B As shown, a TFT lower film 106 is formed by CVD or the like over the first interlayer insulating film 156. A TFT channel 204 is formed on the planarized TFT lower film 106. An insulating layer 105 is formed to cover the TFT lower film 106 and the TFT channel 204. A gate electrode 107 is formed on the TFT channel 204 via the insulating layer 105. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate electrode 107.

[0274] like Fig.19A As shown, the via hole 162a is formed by penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 to reach the surface of the connection portion 253a. The opening 158 is formed by removing a portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower film 106, and a portion of the first interlayer insulating film 156 to reach the light emitting surface 251S. A portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower film 106, and a portion of the first interlayer insulating film 156 are positions formed on the light emitting surface 251S among the above-mentioned insulating layers and insulating films. The via hole 112d is formed by penetrating the second interlayer insulating film 108 and the insulating layer 105 to reach the surface of the region 204d. The via hole 112s is formed by penetrating the second interlayer insulating film 108 and the insulating layer 105 to reach the surface of the region 204s. The via hole and the opening can be formed by RIE, for example.

[0275] like Fig.19B As shown, via 261a passes through Fig.19A The via hole 162a shown is formed by filling the conductive material. The via holes 111d and 111s are also formed by Fig.19AThe via holes 112d and 112s shown are formed by filling the conductive material. After that, the wiring layer 110 is formed, and the wirings 210a, 110d1, and 110s are formed. The wiring layer 110 may be formed at the same time as the via holes 261a, 111d1, and 111s are formed.

[0276] A light-transmitting conductive film is formed to cover the second interlayer insulating film 108, the light-emitting surface 251S, and the wiring layer 110. By photolithography, desired light-transmitting electrodes 159d and 159s are formed.

[0277] A light-transmitting electrode 159d is formed over the light-emitting surface 251S and the wiring 110d1. A light-transmitting electrode 159d is also formed between the light-emitting surface 251S and the wiring 110d to electrically connect the light-emitting surface 251S and the wiring 110d. A light-transmitting electrode 159s is formed over the wiring 110s. The light-transmitting electrodes 159d and 159s are formed at the same time. A light-transmitting electrode may also be formed on the wiring 210a.

[0278] Thereafter, the sub-pixel 220 of the image display device 201 of this embodiment is formed by providing the color filter 180 (wavelength conversion member) and the like.

[0279] The effects of the image display device of this embodiment will be described.

[0280] In the image display device of this embodiment, as in the case of the other embodiments described above, the time of the transfer process for forming the light emitting element 250 can be shortened, the number of processes can be reduced, and in addition to this effect, by making the n-type semiconductor layer 251 the light emitting surface 251S, the light emitting surface 251S can be sufficiently roughened. Therefore, the light emitting efficiency can be improved, and the increase in loss due to contact resistance can be suppressed.

[0281] (Third Embodiment)

[0282] Fig. 20 This is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0283] This embodiment differs from the other embodiments in that the light emitting element 250 having the n-type semiconductor layer 251 as the light emitting surface 251S is driven by the p-type transistor 103. The same reference numerals are used for the same main components as those of the other embodiments, and detailed descriptions are omitted as appropriate.

[0284] like Fig. 20As shown, the sub-pixel 320 of the image display device of this embodiment includes: a substrate 102, a light-emitting element 250, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 361a, and a wiring layer 110. The transistor 103 is a p-channel TFT. The light-emitting element 250 provides a light-emitting surface 251S formed by an n-type semiconductor layer 251.

[0285] The light emitting element 250 is disposed on the light reflecting plate 120a via the insulating layer 114. The light reflecting plate 120a is disposed in the same structure as in the case of the other embodiments described above. The light reflecting plate 120a is disposed directly below the light emitting element 250. The periphery of the light reflecting plate 120a is set to include the periphery of the light emitting element 250 when the light emitting element 250 is projected in the XY plane top view. The light reflecting plate 120a reflects the scattered light of the light emitting element 250 downward toward the light emitting surface 251S side, which actually improves the light emitting efficiency.

[0286] The light emitting element 250 is a prism-shaped or cylindrical element having a bottom surface 253B on the first surface 102a. The light emitting surface 251S is a surface facing the bottom surface 253B. The bottom surface 253B is a surface in contact with the insulating layer 114 in this example.

[0287] The light emitting element 250 includes a p-type semiconductor layer 253, a light emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light emitting layer 252, and the n-type semiconductor layer 251 are laminated in this order from the bottom surface 253B to the light emitting surface 251S. The p-type semiconductor layer 253 includes a connecting portion 253a. The connecting portion 253a is provided on the insulating layer 114 to protrude in one direction from the p-type semiconductor layer 253. The connecting portion 253a is connected to one end of the via hole 361a, and the p-type semiconductor layer 253 and the via hole 361a are electrically connected.

[0288] The structure of the transistor 103 is the same as that of the first embodiment. The detailed description of the structure of the transistor 103 is omitted.

[0289] The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes wirings 310k, 310a, 110d1, and 110s. The wirings 310a and 310k are arranged above the light emitting element 250 and close to the light emitting element 250. The wiring 310a (third wiring) is arranged above the connecting portion 253a. The wiring 310k (fourth wiring) is arranged at a position that does not intersect with the wiring 310a.

[0290] The via hole 361a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via hole 361a is provided between the wiring 310a and the connecting portion 253a. The via hole 361a electrically connects the wiring 310a and the connecting portion 253a.

[0291] The via holes 111d and 111s are provided in the same manner as in the other embodiments described above.

[0292] The light-transmitting electrode 359k is provided over the wiring 310k. The light-transmitting electrode 359k is provided over the light-emitting surface 251S. The light-transmitting electrode 359k is also provided between the wiring 310k and the light-emitting surface 251S to electrically connect the wiring 310k and the light-emitting surface 251S. The wiring 310k and the light-transmitting electrode 359k are, for example, Figure 3 Therefore, the n-type semiconductor layer 251 is electrically connected to the ground line 4 via the light emitting surface 251S, the light-transmitting electrode 359k and the wiring 310k.

[0293] A light-transmitting electrode 359d is provided over the wiring 310a. A light-transmitting electrode 359d is provided over the wiring 110d1. A light-transmitting electrode 359k is also provided between the wiring 310a and the wiring 110d1 to electrically connect the wiring 310a and the wiring 110d1. Therefore, the p-type semiconductor layer 253 is electrically connected to the region 104d via the connection portion 253a, the via 361a, the wiring 310a, the light-transmitting electrode 359d, the wiring 110d1, and the via 111d.

[0294] The light-transmitting electrode 159s is provided over the wiring 110s. The wiring 110s and the light-transmitting electrode 159s are, for example, Figure 3 Therefore, the region 104s of the transistor 103 is electrically connected to the power line 3 through the via 111s, the wiring 110s, and the light-transmitting electrode 159s.

[0295] The vias 361 a , 111 d , and 111 s and the wirings 310 k , 310 a , 110 d 1 , and 110 s are formed using the same material and manufacturing method as those in the other embodiments and their modified examples described above.

[0296] In addition, a color filter 180 and the like are provided in the same manner as in the other embodiments described above.

[0297] A method for manufacturing the image display device of this embodiment will be described.

[0298] Figures 21A to 22B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0299] Before bonding the semiconductor layer 1150 formed on the crystal growth substrate 1001 to the substrate 102 formed with the light reflecting layer 120 and the insulating layer 114, the same process as in the second embodiment may be used. The substrate bonding method described in the first embodiment may also be used. Fig. 17B Execute in the following process Figures 21A to 22B The situation of the process is explained below.

[0300] like Fig.21A As shown, Fig. 17B The semiconductor layer 1150 shown is processed into a desired shape to form the light emitting element 250. After the connection portion 253a of the light emitting element 250 is formed, other parts are formed.

[0301] like Fig. 21B As shown, a first interlayer insulating film 156 is formed to cover the insulating layer 114 and the light emitting element 250. As in the case of the first embodiment, a TFT lower layer film 106 is formed, a TFT channel 104 is formed, an insulating layer 105 is formed, and a gate 107 is formed. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107.

[0302] like Fig.22A As shown, the via hole 362a is formed to pass through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106 and the first interlayer insulating film 156 and reach the surface of the connection portion 253a. The opening 158 and the via holes 112d and 112s are formed in the same manner as in the other embodiments described above.

[0303] like Fig. 22B As shown, Fig.22A The via holes 362a, 112d, and 112s are filled with a conductive material to form via holes 361a, 111d, and 111s. A wiring layer 110 is formed on the second interlayer insulating film 108. A light-transmitting conductive film is formed on the wiring layer 110, and light-transmitting electrodes 359k, 359d, and 159s are formed.

[0304] According to the image display device of this embodiment, the n-type semiconductor layer 251 can be used as the light-emitting surface 251S, and the circuit structure is such that the light-emitting element 250 is driven by the p-channel transistor 103. As a result, it is easy to roughen the light-emitting surface, as in the second embodiment. In addition, by roughening the light-emitting surface, it is also possible to improve the light-emitting efficiency and suppress the increase in loss due to contact resistance.

[0305] (Fourth Embodiment)

[0306] Fig.23 This is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0307] The image display device of this embodiment is configured with a flexible substrate 402 instead of a glass substrate. Light-emitting elements and circuit elements such as transistors are formed on the first surface 402a of the substrate 402. Other aspects are the same as those of the other embodiments described above. For the same structural main components, the same reference numerals are used, and detailed descriptions are appropriately omitted.

[0308] like Fig.23 As shown, the image display device of this embodiment has a sub-pixel 420. The sub-pixel 420 includes a substrate 402. The substrate 402 includes a first surface 402a. A layer 113 containing a silicon compound is formed on the first surface 402a. The layer 113 containing a silicon compound is made of, for example, SiO2 or SiN x The light reflecting layer 120 is formed on the layer 113 containing the silicon compound. The layer 113 containing the silicon compound is provided to improve the close contact with the light reflecting layer 120 formed of a metal material.

[0309] The insulating layer 114 is formed over the layer 113 containing the silicon compound and the light reflecting layer 120. The insulating layer 114 is planarized by CMP or the like.

[0310] The light emitting element 250 is provided on the light reflecting plate 120a via the insulating layer 114. In this example, the structure and main components above the insulating layer 114 are the same as those in the second embodiment, and detailed description thereof will be omitted.

[0311] The substrate 402 is flexible. The substrate 402 is formed of, for example, a polyimide resin. The first interlayer insulating film 156, the second interlayer insulating film 108, the wiring layer 110, etc. are preferably formed of a material having a certain degree of elasticity according to the flexibility of the substrate 402. It should be noted that the wiring layer 110 having the longest wiring length has the highest risk of being damaged when bent. Therefore, it is desirable to adjust the thickness, quality, and material of various films so that the neutral surface including a plurality of protective films added to the surface or the back is located at the position of the wiring layer 110 as required.

[0312] In this example, the structure and main components above the insulating layer 114 are the same as those in the second embodiment, but other embodiments or modified examples may also be used.

[0313] A method for manufacturing the image display device of this embodiment will be described.

[0314] Fig.24A and Fig. 24B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0315] like Fig.24AAs shown, in this embodiment, a substrate 1002 is prepared which is different from the case of the other embodiments described above. The substrate 1002 (fourth substrate) includes two layers of substrates 102 and 402. The substrate 102 is, for example, a glass substrate. The substrate 402 is disposed on the first surface 102a of the substrate 102. For example, the substrate 402 is formed by coating a polyimide material on the first surface 102a of the substrate 102 and firing it. Before forming the substrate 402, a SiN film may be formed on the first surface 102a. x In this case, the substrate 402 is formed by coating a polyimide material on the inorganic film and firing it. A layer 113 containing a silicon compound is formed over the first surface 402a of the substrate 402. The first surface 402a of the substrate 402 is a surface facing the surface on which the substrate 102 is provided.

[0316] By applying, for example, Figures 17A to 19B , Figure 12 to Figure 13D The upper structure of the sub-pixel 420 is formed by the process described in .

[0317] like Fig. 24B As shown, the substrate 102 is removed from the structure on which the upper structure including the color filter not shown is formed. The removal of the substrate 102 can be performed by laser stripping, for example. The removal of the substrate 102 is not limited to the above-mentioned time point, and can also be performed at other appropriate time points. For example, the substrate 102 can be removed after the substrate is bonded or before the color filter is formed. By removing the substrate 102 at an earlier time point, problems such as cracks and gaps in the manufacturing process can be reduced.

[0318] The effects of the image display device of this embodiment will be described.

[0319] Since the substrate 402 is flexible, it can be bent as an image display device, and can be attached to a curved surface or used in a wearable terminal without any discomfort.

[0320] (Fifth Embodiment)

[0321] Fig.25 This is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0322] In this embodiment, a plurality of light-emitting surfaces 551S1 and 551S2 are formed on a single semiconductor layer 550 including a light-emitting layer, thereby realizing an image display device with higher light-emitting efficiency. In the following description, the same reference numerals are used for the same structural main components as those in the above-mentioned other embodiments, and detailed descriptions are appropriately omitted.

[0323] like Fig.25As shown, the image display device of this embodiment has a sub-pixel group 520. The sub-pixel group 520 includes: a substrate 102, a semiconductor layer 550, a first interlayer insulating film 156, transistors 103-1, 103-2, a second interlayer insulating film 108, vias 561a1, 561a2, and a wiring layer 110. The semiconductor layer 550 is arranged on the first surface 102a side of the substrate 102. In this example, the light reflection layer 120 is arranged between the substrate 102 and the semiconductor layer 550. The light reflection layer 120 is arranged on the first surface 102a. The light reflection layer 120 includes a light reflection plate 120a. The insulating layer 114 covers the first surface 102a, the light reflection layer 120 and the light reflection plate 120a. The insulating layer 114 is flattened.

[0324] In this embodiment, holes are injected from one side of the semiconductor layer 550 through the wiring layer 110 and the vias 561a1 and 561a2 by turning on the p-channel transistors 103-1 and 103-2. Electrons are injected from the other side of the semiconductor layer 550 through the wiring layer 110. Holes and electrons are injected into the semiconductor layer 550, and the light-emitting layer 552 emits light due to the combination of holes and electrons. A driving circuit for driving the light-emitting layer 552 can be applied, for example. Figure 3 The circuit structure shown in the figure. The above other embodiments can also be used to replace the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer up and down, so that the semiconductor layer is driven by an n-channel transistor. In this case, the driving circuit can be applied Fig.16 Circuit structure.

[0325] The structure of the sub-pixel group 520 will be described in detail.

[0326] The semiconductor layer 550 is provided on the light reflecting plate 120a via the insulating layer 114. The periphery of the light reflecting plate 120a is set so as to include the periphery of the semiconductor layer 550 when the semiconductor layer 550 is projected onto the light reflecting plate 120a in the XY plane top view. It is preferred that the periphery of the light reflecting plate 120a is set so as not to include the periphery of the transistors 103-1 and 103-2 when the transistors 103-1 and 103-2 are projected onto the surface including the light reflecting plate 120a in the XY plane top view. The periphery of the transistors 103-1 and 103-2 in the XY plane top view is the periphery of the TFT channels 104-1 and 104-2 in the XY plane top view.

[0327] The semiconductor layer 550 includes a plurality of light-emitting surfaces 551S1 and 551S2. The semiconductor layer 550 is a prismatic or cylindrical laminate having a bottom surface 553B on the first surface 102a. The light-emitting surfaces 551S1 and 551S2 are surfaces opposite to the bottom surface 553B of the semiconductor layer 550. In this example, the bottom surface 553B is a surface in contact with the insulating layer 114. The light-emitting surfaces 551S1 and 551S2 are preferably surfaces within approximately parallel planes. The approximately parallel planes may be the same plane or different planes. The light-emitting surfaces 551S1 and 551S2 are arranged separately.

[0328] The semiconductor layer 550 includes a p-type semiconductor layer 553, a light emitting layer 552, and an n-type semiconductor layer 551. The p-type semiconductor layer 553, the light emitting layer 552, and the n-type semiconductor layer 551 are stacked in this order from the bottom surface 553B to the light emitting surfaces 551S1 and 551S2.

[0329] The p-type semiconductor layer 553 includes connection parts 553a1 and 553a2. The connection part 553a1 is provided on the insulating layer 114 to protrude from the p-type semiconductor layer 553 in one direction. The connection part 553a2 is provided on the insulating layer 114 to protrude from the p-type semiconductor layer 553 in a direction different from that of the connection part 553a1. The height of the connection parts 553a1 and 553a2 is lower than the height of the semiconductor layer 550, and as in this example, is the same as the height of the p-type semiconductor layer 553, or is lower than the height of the p-type semiconductor layer 553, and the semiconductor layer 550 is formed in a step shape.

[0330] The connection portion 553a1 is of p-type, and the via 561a1 having one end connected to the connection portion 553a1 is electrically connected to the p-type semiconductor layer 553. The connection portion 553a2 is of p-type, and the via 561a2 having one end connected to the connection portion 553a2 is electrically connected to the p-type semiconductor layer 553.

[0331] The n-type semiconductor layer 551 has two light-emitting surfaces 551S1 and 551S2 on the upper surface. The two light-emitting surfaces 551S1 and 551S2 are configured to be separated from each other. That is, one sub-pixel group 520 actually includes two sub-pixels. In this embodiment, as in the case of the other embodiments described above, the display area is formed by arranging the sub-pixel group 520 that actually includes two sub-pixels in a grid shape.

[0332] The connecting portions 553a1 and 553a2 are configured to protrude in a direction according to, for example, the configurations of the light-emitting surfaces 551S1 and 551S2. The connecting portion 553a1 is configured, for example, so that the distance from the light-emitting surface 551S1 is shorter than the distance from the light-emitting surface 551S2. That is, the connecting portion 553a1 is configured to be closer to the light-emitting surface 553S1 than the light-emitting surface 553S2. The connecting portion 553a2 is configured, for example, so that the distance from the light-emitting surface 551S2 is shorter than the distance from the light-emitting surface 551S1. That is, the connecting portion 553a2 is configured to be closer to the light-emitting surface 551S2 than the light-emitting surface 551S1.

[0333] The first interlayer insulating film 156 (first insulating film) covers the connecting portions 553a1, 553a2, the side surfaces of the p-type semiconductor layer 553, the side surfaces of the light-emitting layer 552, and the side surfaces of the n-type semiconductor layer 551. The first interlayer insulating film 156 covers a portion of the upper surface of the n-type semiconductor layer 551. The light-emitting surfaces 551S1, 551S2 of the n-type semiconductor layer 551 are not covered by the first interlayer insulating film 156. The first interlayer insulating film 156 is preferably a white resin as in the case of the other embodiments described above.

[0334] The TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is not provided on the light emitting surfaces 551S1 and 551S2. The TFT lower layer film 106 is planarized, and the TFT channels 104-1 and 104-2 are formed on the TFT lower layer film 106.

[0335] The insulating layer 105 covers the TFT lower film 106 and the TFT channels 104-1 and 104-2. The gate 107-1 is disposed on the TFT channel 104-1 via the insulating layer 105. The gate 107-2 is disposed on the TFT channel 104-2 via the insulating layer 105. The transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. The transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

[0336] The second interlayer insulating film 108 (second insulating film) covers the insulating layer 105 and the gate electrodes 107 - 1 and 107 - 2 .

[0337] TFT channels 104-1 and 104-2 include regions doped to p-type, and transistors 103-1 and 103-2 are p-channel TFTs. Transistor 103-1 is disposed closer to light emitting surface 551S1 than light emitting surface 551S2. Transistor 103-2 is disposed closer to light emitting surface 551S2 than light emitting surface 551S1.

[0338] An opening 558-1 is provided above the light emitting surface 551S1. An opening 558-2 is provided above the light emitting surface 551S2. The second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 are not provided in the openings 558-1 and 558-2, and the light emitting surfaces 551S1 and 551S2 are exposed from the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156.

[0339] A light-transmitting electrode 559 k is provided over the light-emitting surfaces 551S1 and 551S2 . Electrons are injected through the light-transmitting electrode 559 k and the light-emitting surfaces 551S1 and 551S2 . The light-emitting surfaces 551S1 and 551S2 are covered with the light-transmitting electrode 559 k , and the openings 558 - 1 and 558 - 2 are filled with the surface resin layer 170 .

[0340] The light-emitting surfaces 551S1 and 551S2 are square, rectangular, or other polygonal or circular shapes when viewed from above the XY plane. The shape of the top of the openings 558-1 and 558-2 may also be square, rectangular, or other polygonal or circular shapes. For the purpose of reflecting light from the wall surfaces of the openings 558-1 and 558-2 and reducing the loss, the openings 558-1 and 558-2 are preferably formed in a tapered shape so that the area is expanded upward, as in this example. When viewed from above the XY plane, the shape of the light-emitting surfaces 551S1 and 551S2 may be similar to or different from the shape of the top of the openings 558-1 and 558-2.

[0341] The wiring layer 110 is provided on the second interlayer insulating film 108. The wiring layer 110 includes wirings 510s1, 510d1, 510k, 510d2, 510s2.

[0342] The wiring 510k is provided between the light emitting surface 551S1 and the light emitting surface 551S2. A light-transmitting electrode 559k is provided over the wiring 510k. The wiring 510k and the light-transmitting electrode 559k are, for example, Figure 3 The ground wire 4 is connected.

[0343] The vias 111d1, 111s1, 111d2, and 111s2 are provided to penetrate the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106. The via 111d1 is provided between the region of the transistor 103-1 doped with the p-type on one side and the wiring 510d1. The via 111s1 is provided between the region of the transistor 103-1 doped with the p-type on the other side and the wiring 510s1. The via 111d2 is provided between the region of the transistor 103-2 doped with the p-type on one side and the wiring 510d2. The via 111s2 is provided between the region of the transistor 103-2 doped with the p-type on the other side and the wiring 510s2.

[0344] Wiring 510d1 is provided above connection portion 553a1. Wiring 510d1 is connected to the p-type region corresponding to the drain electrode of transistor 103-1 via via 111d1. Wiring 510s1 is connected to the p-type region corresponding to the source electrode of transistor 103-1 via via 111s1. Wiring 510d2 is provided above connection portion 553a2. Wiring 510d2 is connected to the region corresponding to the drain electrode of transistor 103-2 via via 111d2. Wiring 510s2 is connected to the region corresponding to the source electrode of transistor 103-2 via via 111s2.

[0345] The via hole 561a1 is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via hole 561a1 is provided between the connection portion 553a1 and the wiring 510d1, and electrically connects the connection portion 553a1 and the wiring 510d1.

[0346] The via hole 561a2 is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via hole 561a2 is provided between the connection portion 553a2 and the wiring 510d2, and electrically connects the connection portion 553a2 and the wiring 510d2.

[0347] The transistors 103-1 and 103-2 are driving transistors of adjacent sub-pixels and are driven sequentially. Holes supplied from one of the two transistors 103-1 and 103-2 are injected into the light-emitting layer 552, and electrons supplied from the wiring 510k are injected into the light-emitting layer 552, causing the light-emitting layer 552 to emit light.

[0348] In this embodiment, the drift current flowing in the direction parallel to the XY plane is suppressed by the resistance of the n-type semiconductor layer 551 and the p-type semiconductor layer 553. Therefore, the electrons injected from the light-emitting surfaces 551S1 and 551S2 and the holes injected from the vias 561a1 and 561a2 all travel along the lamination direction of the semiconductor layer 550. Since the light-emitting surfaces 551S1 and 551S2 are closer to the outside, there is almost no light source, so the multiple light-emitting surfaces 551S1 and 551S2 provided in one semiconductor layer 550 can be made to emit light respectively by using the transistors 103-1 and 103-2.

[0349] As described above, since the light sources are not emitted outside the light emitting surfaces 551S1 and 551S2, the light reflecting plate 120a may be provided for each of the light emitting surfaces 551S1 and 551S2.

[0350] A method for manufacturing the image display device of this embodiment will be described.

[0351] Figures 26A to 28B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0352] like Fig.26A As shown, a semiconductor growth substrate (second substrate) 1194a and substrate 102 (third substrate) are prepared. Substrate 102 is provided with a light reflection layer 120 including a light reflection plate 120a and an insulating layer 114 covering the light reflection layer 120 on the first surface 102a. Figure 6 The substrates shown in A are the same, and detailed description thereof is omitted. The substrates are bonded together by bonding the exposed surface of the p-type semiconductor layer 1153 formed on the semiconductor growth substrate 1194 a to the planarized insulating layer 114 .

[0353] like Fig.26B As shown, remove Fig.26A The crystal growth substrate 1001 is shown. The crystal growth substrate 1001 can be removed by, for example, wet etching or laser lift-off.

[0354] like Fig.26C As shown, Fig.26B The semiconductor layer 1150 shown is processed into a desired shape by etching to form a semiconductor layer 550 including connection parts 553a1 and 553a2. The desired shape is, for example, a square or a rectangle, or other polygonal shape, a circle, etc. in a top view of the XY plane.

[0355] like Fig.27A As shown, the first interlayer insulating film 156 is formed to cover the insulating layer 114 and the semiconductor layer 550 .

[0356] like Fig.27B As shown, a TFT lower film 106 is formed on the first interlayer insulating film 156, and TFT channels 104-1 and 104-2 are formed on the TFT lower film 106. An insulating layer 105 is formed over the TFT lower film 106 and the TFT channels 104-1 and 104-2. A gate 107-1 is formed on the TFT channel 104-1 via the insulating layer 105. A gate 107-2 is formed on the TFT channel 104-2 via the insulating layer 105. A second interlayer insulating film 108 is formed over the insulating layer 105 and the gates 107-1 and 107-2. The formation method and materials of the TFT channels 104-1 and 104-2, the insulating layer 105, the gates 107-1 and 107-2, etc. may be the same as those in the above-mentioned other embodiments.

[0357] like Fig.28AAs shown, via holes 112d1 and 112s1 are formed to reach the TFT channel 104-1 by penetrating the second interlayer insulating film 108, the insulating layer 105 and the TFT lower film 106. Via holes 112d2 and 112s2 are formed to reach the TFT channel 104-2 by penetrating the second interlayer insulating film 108, the insulating layer 105 and the TFT lower film 106. Via hole 562a1 is formed to reach the connection portion 553a1 by penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106 and the first interlayer insulating film 156. Via hole 562a2 is formed to reach the connection portion 553a2 by penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106 and the first interlayer insulating film 156. A portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower film 106, and a portion of the first interlayer insulating film 156 are removed to form an opening 558-1 that reaches the light-emitting surface 551S1. A portion of the second interlayer insulating film 108, a portion of the insulating layer 105, a portion of the TFT lower film 106, and a portion of the first interlayer insulating film 156 are removed to form an opening 558-2 that reaches the light-emitting surface 551S2.

[0358] like Fig.28B As shown, via holes 112d1, 112s1, 112d2, 112s2, 562a1, 562a2 are filled with a conductive material to form via holes 111d1, 111s1, 111d2, 111s2, 561a1, 561a2. A wiring layer 110 is formed, and wirings 510d1, 510s1, 510d2, 510s2, 510k are formed.

[0359] The light-emitting surfaces 551S1 and 551S2 are roughened. Then, a light-transmitting conductive film is provided to cover the wiring layer 110, and light-transmitting electrodes 559d1, 559s1, 559d2, 559s2, and 559k are formed. The light-transmitting electrode 559k is formed to cover the light-emitting surfaces 551S1 and 551S2, and electrically connects the light-emitting surfaces 551S1 and 551S2 and the wiring 510k.

[0360] In this way, a sub-pixel group 520 including a semiconductor layer 550 having two light emitting surfaces 551S1 and 551S2 is formed.

[0361] In this embodiment, two light emitting surfaces 551S1 and 551S2 are provided in one semiconductor layer 550, but the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces may be provided in one semiconductor layer 550. As an example, one or two columns of sub-pixels may be implemented by a single semiconductor layer 550. Thus, as described later, it is possible to reduce the recombination current that does not contribute to the light emission of each light emitting surface, and increase the effect of implementing a finer light emitting element.

[0362] (Variation Example)

[0363] Fig.29 This is a schematic cross-sectional view illustrating a portion of an image display device according to a modification of the present embodiment.

[0364] This modification is different from the fifth embodiment in that two n-type semiconductor layers 5551a1 and 5551a2 are provided on the light emitting layer 552. Other aspects are the same as those of the fifth embodiment, and the same reference numerals are used for the same structural main components, and detailed descriptions are appropriately omitted.

[0365] like Fig.29 As shown, the image display device of this variation has a sub-pixel group 520a. The sub-pixel group 520a includes a semiconductor layer 550a. The semiconductor layer 550a includes: a p-type semiconductor layer 553, a light-emitting layer 552, and n-type semiconductor layers 5551a1 and 5551a2. The p-type semiconductor layer 553 and the light-emitting layer 552 are laminated in this order from the insulating layer 114 side. The n-type semiconductor layers 5551a1 and 5551a2 are laminated on the light-emitting layer 552.

[0366] The n-type semiconductor layers 5551a1 and 5551a2 are arranged spaced apart from each other along the X-axis direction on the light emitting layer 552. A first interlayer insulating film 156 is provided between the n-type semiconductor layers 5551a1 and 5551a2, and the n-type semiconductor layers 5551a1 and 5551a2 are separated by the first interlayer insulating film 156.

[0367] The n-type semiconductor layers 5551a1 and 5551a2 have substantially the same shape in a plan view of the XY plane, and the shape is substantially square or rectangular, but may be other polygonal shapes, circular, or the like.

[0368] The n-type semiconductor layer 5551a1 has a light emitting surface 5551S1. The n-type semiconductor layer 5551a2 has a light emitting surface 5551S2. The light emitting surface 5551S1 is a surface of the n-type semiconductor layer 5551a1 exposed from the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108 through the opening 558-1. The light emitting surface 5551S2 is a surface of the n-type semiconductor layer 5551a2 exposed from the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108 through the opening 558-2.

[0369] The shape of the light-emitting surfaces 5551S1 and 5551S2 in the XY plane top view is the same as the shape of the light-emitting surface in the case of the fifth embodiment, and has a substantially same shape, such as a substantially square shape. The shape of the light-emitting surfaces 5551S1 and 5551S2 is not limited to the square shape of the present embodiment, and may also be a polygon such as a circle, an ellipse or a hexagon. The shape of the light-emitting surfaces 5551S1 and 5551S2 may be similar to the shape of the openings 558-1 and 558-2, or may be a different shape.

[0370] The light-transmitting electrode 559k is provided on each of the light-emitting surfaces 5551S1 and 5551S2. The light-transmitting electrode 559k is also provided on the wiring 510k. The light-transmitting electrode 559k is provided between the wiring 510k and the light-emitting surface 5551S1, and between the wiring 510k and the light-emitting surface 5551S2. The light-transmitting electrode 559k is electrically connected to the wiring 510k and the light-emitting surfaces 5551S1 and 5551S2.

[0371] The manufacturing method of this modification example will be described.

[0372] Figure 30A to Figure 31B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to this modification.

[0373] In this modification, before the step of bonding the substrates to each other, the above-mentioned fifth embodiment can be applied. Fig.26A and Fig.26B The following is the same process as described in Fig.26B The steps after the above steps will be described.

[0374] like Fig. 30A As shown, in this modification, Fig.26B The semiconductor layer 1150 is etched to form a light emitting layer 552 and a p-type semiconductor layer 553 including connecting portions 553a1 and 553a2. Further etching is performed to form two n-type semiconductor layers 5551a1 and 5551a2.

[0375] When forming the n-type semiconductor layers 5551a1 and 5551a2, further deep etching may be performed. For example, the etching for forming the n-type semiconductor layers 5551a1 and 5551a2 may be performed at a depth exceeding the depth reaching the light emitting layer 552 or the p-type semiconductor layer 553. In this way, when forming the n-type semiconductor layers by deep etching, it is desirable to compare Fig.29 The illustrated light emitting surfaces 5551S1 and 5551S2 are etched at a position 1 μm or more outside the periphery. By making the etching position farther outside than the periphery of the light emitting surfaces 5551S1 and 5551S2, the recombination current can be suppressed.

[0376] like Fig. 30B As shown, a first interlayer insulating film 156 is formed to cover the insulating layer 114 and the semiconductor layer 550a.

[0377] like Fig. 30C As shown, a TFT lower layer film 106 is formed on the first interlayer insulating film 156, and TFT channels 104-1 and 104-2 are formed on the TFT lower layer film 106. In addition, an insulating layer 105 is formed on the TFT channels 104-1 and 104-2, and gate electrodes 107-1 and 107-2 are formed on the insulating layer 105. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate electrodes 107-1 and 107-2.

[0378] like Fig.31A As shown, the via holes 112d1, 112s1, 112d2, 112s2, 562a1, and 562a2 are formed in the same manner as in the fifth embodiment. The opening 558-1 is formed by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 to reach the light emitting surface 5551S1. The opening 558-2 is formed by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 to reach the light emitting surface 5551S2.

[0379] like Fig.31B As shown, the wiring layer 110 is formed in the same manner as in the fifth embodiment, and a light-transmitting conductive film is formed.

[0380] In this way, a sub-pixel group 520a having two light-emitting surfaces 5551S1 and 5551S2 is formed.

[0381] The case of this variation is also the same as that of the fifth embodiment. The number of light emitting surfaces is not limited to two, and three or more light emitting surfaces may be provided in one semiconductor layer 550a.

[0382] The effects of the image display device of this embodiment will be described.

[0383] Fig.32 is a graph illustrating the characteristics of a pixel LED element.

[0384] Fig.32 The vertical axis represents the luminous efficiency [%], and the horizontal axis represents the current density flowing in the pixel LED element as a relative value.

[0385] like Fig.32As shown in FIG. 1 , in the region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is approximately constant or monotonically increasing. In the region where the relative value of the current density is greater than 1.0, the luminous efficiency decreases monotonically. That is, for the pixel LED element, there is an appropriate current density that maximizes the luminous efficiency.

[0386] It is expected that a highly efficient image display device can be realized by suppressing the current density to a level that can obtain sufficient brightness from the light-emitting element. Fig.32 It means that at low current density, the luminous efficiency tends to decrease as the current density decreases.

[0387] As described in the first to fourth embodiments, the light-emitting element is formed by individually separating the entire semiconductor layer 1150 including the light-emitting layer by etching, etc. At this time, the junction surface between the light-emitting layer and the n-type semiconductor layer is exposed at the end. Similarly, the junction surface between the light-emitting layer and the p-type semiconductor layer is exposed at the end.

[0388] In the case where the above-mentioned end exists, electrons and holes recombine at the end. On the other hand, the above-mentioned recombination does not contribute to luminescence. The recombination generated at the end has almost no relationship with the current flowing in the light-emitting element. It can be considered that the recombination is generated according to the length of the junction surface of the end that contributes to luminescence.

[0389] When two light emitting elements of the same size and in a cubic shape are made to emit light, since the four side surfaces of each light emitting element are ends, the two light emitting elements have eight ends in total, and recombination can occur at the eight ends.

[0390] In contrast, in the present embodiment, the semiconductor layers 550 and 550a have four side surfaces, and there are four side surfaces at the ends of the two light-emitting surfaces. However, since the injection of electrons or holes is small in the area between the openings 558-1 and 558-2, and it hardly helps to emit light, it can be considered that there are six ends that help to emit light. Thus, in the present embodiment, the number of ends of the semiconductor layer is actually reduced, thereby reducing the recombination that does not help to emit light. By reducing the recombination that does not help to emit light, the drive current of each light-emitting surface can be reduced.

[0391] In the case where the distance between sub-pixels is shortened for high definition or the like, or in the case where the current density is relatively high, in the sub-pixel group 520 of the fifth embodiment, the distance between the light-emitting surface 551S1 and the light-emitting surface 551S2 is shortened. In this case, as in the case of the fifth embodiment, when the n-type semiconductor layer is shared, part of the electrons injected into the driven light-emitting surface is diverted, and the light-emitting surface that is not driven may emit dim light. In the sub-pixel group 520a of the modified example, the n-type semiconductor layer is divided into two, and each n-type semiconductor layer has a light-emitting surface, so that the light-emitting surface on the undriven side can be reduced from emitting dim light.

[0392] In this embodiment, the semiconductor layer including the light emitting layer is laminated in the order of the p-type semiconductor layer, the light emitting layer, and the n-type semiconductor layer from the first interlayer insulating film 156 side, and the exposed surface of the n-type semiconductor layer is roughened, which is preferred from the perspective of improving the light emitting efficiency. As described above, the lamination order of the p-type semiconductor layer and the n-type semiconductor layer may be replaced, and the n-type semiconductor layer may be laminated in the order of the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer.

[0393] In the sub-pixels and sub-pixel groups of the image display devices in the above-mentioned embodiments, various specific examples are described. Each specific example is an example, and other structural examples can be formed by appropriately combining the structures or process sequences of the above-mentioned embodiments. For example, in the case of the first embodiment, the p-type semiconductor layer can be used as the light-emitting surface instead of the n-type semiconductor layer, or in the cases of the second to fourth embodiments, the n-type semiconductor layer can be used as the light-emitting surface instead of the p-type semiconductor layer.

[0394] (Sixth Embodiment)

[0395] The image display device may be an image display module having an appropriate number of pixels, and may be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0396] Fig.33 This is a block diagram illustrating an image display device according to this embodiment.

[0397] Fig.33 The main parts of the structure of a computer display are shown.

[0398] like Fig.33 As shown, the image display device 601 has an image display module 602. The image display module 602 is, for example, an image display device having the structure of the first embodiment described above. The image display module 602 includes: a display area 2 in which a plurality of sub-pixels including sub-pixels 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

[0399] The image display device 601 further includes a controller 670. The controller 670 receives a control signal separated and generated by an interface circuit (not shown) and controls the driving of each sub-pixel and the driving order thereof with respect to the row selection circuit 5 and the signal voltage output circuit 7.

[0400] (Variation Example)

[0401] The image display device may be an image display module having an appropriate number of pixels, and may be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0402] Fig.34 This is a block diagram illustrating an image display device according to a modified example of the present embodiment.

[0403] Fig.34 The structure of a high-definition flat-screen TV is shown.

[0404] like Fig.34 As shown, the image display device 701 has an image display module 702. The image display module 702 is, for example, the image display device 1 having the structure of the first embodiment described above. The image display device 701 has a controller 770 and a frame memory 780. The controller 770 controls the driving order of each sub-pixel of the display area 2 based on the control signal supplied by the bus 740. The frame memory 780 stores display data of one frame for processing such as smooth motion image reproduction.

[0405] The image display device 701 includes an I / O circuit 710. Fig.34 In the figure, the I / O circuit 710 is simply referred to as "I / O". The I / O circuit 710 provides an interface circuit for connecting to an external terminal, device, etc. The I / O circuit 710 includes, for example, a USB interface for connecting to an external hard disk device, an audio interface, etc.

[0406] The image display device 701 includes a receiving unit 720 and a signal processing unit 730. The receiving unit 720 is connected to an antenna 722, and separates and generates a required signal from the radio wave received by the antenna 722. The signal processing unit 730 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc. The signal separated and generated by the receiving unit 720 is separated and generated into image data, audio data, etc. by the signal processing unit 730.

[0407] By making the receiving unit 720 and the signal processing unit 730 a high-frequency communication module for transmitting / receiving, WiFi, GPS receiver, etc. of a mobile phone, it can also be formed into other image display devices. For example, an image display device with an image display module of appropriate screen size and resolution can be a portable information terminal such as a smart phone and a car navigation system.

[0408] The image display module in the present embodiment is not limited to the structure of the image display device in the first embodiment, and may also be a modified example or other embodiments. Fig.14 As shown, a structure including a large number of sub-pixels is shown.

[0409] According to the above-described embodiments, it is possible to realize a method for manufacturing an image display device and an image display device that shortens the transfer process of the light emitting element and improves the yield.

[0410] Several embodiments of the present invention are described above, but the above embodiments are mentioned as examples and are not intended to limit the scope of the invention. The above new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The above embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the scope of the technical solution and its equivalent. In addition, the above embodiments can be implemented in combination with each other.

[0411] Description of Reference Numerals

[0412] 1, 201, 601, 701 image display device; 2 display area; 3 power supply line; 4 ground line; 5, 205 row selection circuit; 6, 206 scanning line; 7, 207 signal voltage output circuit; 8, 208 signal line; 10 pixel; 20, 20a, 220, 320, 420 sub-pixel; 22, 222 light emitting element; 24, 224 selection transistor; 26, 226 driving transistor; 28, 228 capacitor; 101 circuit; 102, 402 substrate; 102a first surface; 103, 103-1, 103-2, 203 transistor; 104, 104-1, 104-2, 204 TFT channel; 105 insulating layer; 107, 107-1, 107-2 gate ; 108 second interlayer insulating film; 110 wiring layer; 120 light reflecting layer; 120a light reflecting plate; 150, 250 light emitting element; 153S, 251S, 551S1, 551S2, 5551S1, 5551S2 light emitting surface; 156 first interlayer insulating film; 159d, 159s, 359d, 359k, 559k light-transmitting electrode; 161k, 261a, 361a, 561a1, 561a2 via hole; 180 color filter; 520, 520a sub-pixel group; 1001 crystal growth substrate; 1140 buffer layer; 1150 semiconductor layer; 1190 supporting substrate; 1192 structure; 1194, 1194a, 1294 semiconductor growth substrate.

Claims

1. A method for manufacturing an image display device, characterized in that: have: A step of preparing a second substrate having a semiconductor layer including a light emitting layer formed on the first substrate; A step of bonding the semiconductor layer to the first surface of the third substrate; A step of removing the first substrate; A step of etching the semiconductor layer to form a light-emitting element including a bottom surface on the first surface and a light-emitting surface disposed opposite to the bottom surface; forming a first insulating film covering the first surface and the light emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the circuit element and the first insulating film; a step of removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light emitting surface; forming a via hole penetrating the first insulating film and the second insulating film; forming a wiring layer on the second insulating film; The light emitting element includes a connection portion formed on the first surface, The via hole is provided between the wiring layer and the connection portion to electrically connect the wiring layer and the connection portion.

2. The method for manufacturing an image display device according to claim 1, wherein: Also features: Before bonding the semiconductor layer to the first surface, forming a light-reflective layer on the first surface; A step of forming an insulating layer on the light-reflective layer.

3. The method for manufacturing an image display device according to claim 2, wherein: The layer having the light reflectivity includes a first portion having the light reflectivity, The light emitting element is formed on the first portion, The outer periphery of the first portion includes the outer periphery of the light emitting element when the light emitting element is projected onto the first portion in a plan view.

4. The method for manufacturing an image display device according to claim 1, wherein: The step of bonding the semiconductor layer to the third substrate includes bonding a plurality of the second substrates to one third substrate.

5. The method for manufacturing an image display device according to claim 1, wherein: The third substrate includes a light-transmitting substrate.

6. The method for manufacturing an image display device according to claim 5, wherein: The third substrate further includes a fourth substrate having flexibility and disposed on the light-transmitting substrate. The method further comprises a step of removing the light-transmitting substrate after bonding the semiconductor layer to the fourth substrate in the step of bonding the semiconductor layer to the third substrate.

7. The method for manufacturing an image display device according to claim 1, wherein: The semiconductor layers are stacked in order from the first substrate side, including a first semiconductor layer of a first conductivity type, the light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type. The second semiconductor layer includes the connecting portion, The first conductivity type is n-type, The second conductivity type is p-type.

8. The method for manufacturing an image display device according to claim 1, wherein: The method further comprises forming a light-transmitting electrode on the exposed light-emitting surface.

9. The method for manufacturing an image display device according to claim 1, wherein: The semiconductor layer includes a gallium nitride-based compound semiconductor.

10. The method for manufacturing an image display device according to claim 1, wherein: The method further includes forming a wavelength conversion member on the light emitting element.

11. An image display device, characterized in that: have: a substrate having a first surface; a light emitting element, comprising a bottom surface on the first surface, and a surface opposite to the bottom surface, namely, a light emitting surface; a first insulating film covering the side surfaces of the light emitting element and the first surface; a circuit element disposed on the first insulating film; a second insulating film covering the circuit element and the first insulating film; a via hole, which is provided to penetrate the first insulating film and the second insulating film; a wiring layer provided on the second insulating film; The light emitting element includes a connection portion formed on the first surface, The via hole is provided between the wiring layer and the connection portion to electrically connect the wiring layer and the connection portion.

12. The image display device according to claim 11, wherein: The substrate includes a light-transmitting substrate.

13. The image display device according to claim 11, wherein: The substrate includes a substrate having flexibility.

14. The image display device according to claim 11, wherein: Also features: A light-reflective layer disposed on the first surface; A layer having insulating properties covers the layer having light reflectivity.

15. The image display device according to claim 14, wherein: The layer having the light reflectivity comprises a first portion, The light emitting element is disposed on the first portion, The outer periphery of the first portion includes the outer periphery of the light emitting element when the light emitting element is projected onto the first portion in a plan view.

16. The image display device according to claim 11, wherein: The light emitting element is laminated in order from the first surface to the light emitting surface, including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type. The first semiconductor layer includes the connection portion.

17. The image display device according to claim 16, wherein: The wiring layer includes: a first wiring connected to the via hole, and a second wiring connected to a surface including the light emitting surface, The second semiconductor layer is electrically connected to the circuit element via a surface including the light emitting surface and the second wiring.

18. The image display device according to claim 16, wherein: The wiring layer includes: a third wiring connected to the via hole, and a fourth wiring connected to the surface including the light emitting surface, The first semiconductor layer is electrically connected to the circuit element through the via hole and the third wiring.

19. The image display device according to claim 16, wherein: The first conductivity type is p-type, The second conductivity type is n-type.

20. The image display device according to claim 16, wherein: It also has a light-transmitting electrode disposed on the light-emitting surface, The second semiconductor layer is connected to the wiring layer via the light-transmitting electrode.

21. The image display device according to claim 11, wherein: The light emitting element includes a gallium nitride-based compound semiconductor.

22. The image display device according to claim 11, wherein: The circuit element includes a thin film transistor.

23. The image display device according to claim 11, wherein: Furthermore, a wavelength conversion component is provided on the light emitting element.

24. An image display device, characterized in that: have: a substrate having a first surface; A semiconductor layer, comprising: a bottom surface on the first surface, and a surface opposite to the bottom surface, wherein the surface comprises a plurality of light-emitting surfaces; a first insulating film covering the side surfaces of the semiconductor layer and the first surface; a plurality of transistors disposed on the first insulating film; a second insulating film covering the plurality of transistors and the first insulating film; a plurality of via holes, which are provided to penetrate the first insulating film and the second insulating film; a wiring layer provided on the second insulating film; The semiconductor layer includes a connection portion formed on the first surface, The plurality of via holes are provided between the wiring layer and the connection portion to electrically connect the wiring layer and the connection portion.

25. The image display device according to claim 24, wherein: The semiconductor layers are stacked in order from the bottom surface to the plurality of light-emitting surfaces, including a first semiconductor layer of a first conductivity type, a light-emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type. The second semiconductor layer is separated by the first insulating film.

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