Pixel Circuit, Driving Method Thereof, and Display Device

Abstract

A pixel circuit, a driving method thereof, and a display device. The pixel circuit includes a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and a light-emitting element, wherein: The compensation sub-circuit writes the signal of the third node (N3) into the first node (N1) under the control of the third scan signal terminal (Gate3), and compensates the first node (N1) under the control of the third scan signal terminal (Gate3) and the first voltage terminal (VDD); The first reset sub-circuit writes the signal of the first initial signal terminal (INT1) into the third node (N3) under the control of the first scan signal terminal (Gate1) and the first light-emitting control signal terminal (EM1); The second light-emitting control sub-circuit provides the signal of the first voltage terminal (VDD) to the second node (N2) under the control of the second light-emitting control signal terminal (EM2); The first light-emitting control sub-circuit provides the signal of the third node (N3) to the fourth node (N4) under the control of the first light-emitting control signal terminal (EM1), and allows a driving current to pass between the third node (N3) and the fourth node (N4).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and particularly to a pixel circuit, a driving method thereof, and a display device. Background Art

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, etc., and has been widely used in display products such as mobile phones, tablet computers, digital cameras, etc. OLED display belongs to current drive, and it is necessary to output current to the OLED through a pixel circuit to drive the OLED to emit light. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0004] An exemplary embodiment of the present disclosure provides a pixel circuit, including a driving sub-circuit, a writing sub-circuit, a compensating sub-circuit, a first reset sub-circuit, a first light emitting control sub-circuit, a second light emitting control sub-circuit, and a light emitting element, wherein: the driving sub-circuit is respectively connected to a first node, a second node, and a third node, and is configured to provide a driving current to the third node under the control of signals of the first node and the second node; the writing sub-circuit is respectively connected to a second scan signal terminal, a data signal terminal, and the second node, and is configured to write the signal of the data signal terminal into the second node under the control of the signal of the second scan signal terminal; the compensating sub-circuit is respectively connected to a first voltage terminal, a third scan signal terminal, the first node, and the third node, and is configured to write the signal of the third node into the first node under the control of the signal of the third scan signal terminal, and compensate the first node under the control of the signals of the third scan signal terminal and the first voltage terminal; the first reset sub-circuit is respectively connected to a first scan signal terminal, a first light emitting control signal terminal, a first initial signal terminal, and the third node, and is configured to write the signal of the first initial signal terminal into the third node under the control of the signals of the first scan signal terminal and the first light emitting control signal terminal; the second light emitting control sub-circuit is respectively connected to the first voltage terminal, a second light emitting control signal terminal, and the second node, and is configured to provide the signal of the first voltage terminal to the second node under the control of the signal of the second light emitting control signal terminal; the first light emitting control sub-circuit is respectively connected to the first light emitting control signal terminal, the third node, and a fourth node, and is configured to provide the signal of the third node to the fourth node under the control of the signal of the first light emitting control signal terminal, and allow a driving current to pass between the third node and the fourth node; one end of the light emitting element is connected to the fourth node, and the other end is connected to a second voltage terminal.

[0005] In an exemplary embodiment, the first reset sub-circuit includes a first transistor and a seventh transistor; a control electrode of the first transistor is connected to a first scan signal terminal, a first electrode of the first transistor is connected to a first initial signal terminal, and a second electrode of the first transistor is connected to a first electrode of the seventh transistor; a control electrode of the seventh transistor is connected to the first light emission control signal terminal, and a second electrode of the seventh transistor is connected to the third node.

[0006] In an exemplary embodiment, the compensation sub-circuit includes a second transistor and a first capacitor, the driving sub-circuit includes a third transistor, and the writing sub-circuit includes a fourth transistor; a control electrode of the second transistor is connected to a third scan signal terminal, a first electrode of the second transistor is connected to the third node, and a second electrode of the second transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the first voltage terminal; a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the third node; a control electrode of the fourth transistor is connected to a second scan signal terminal, a first electrode of the fourth transistor is connected to the data signal terminal, and a second electrode of the fourth transistor is connected to the second node.

[0007] In an exemplary embodiment, the second light emission control sub-circuit includes a fifth transistor, and the first light emission control sub-circuit includes a sixth transistor; a control electrode of the fifth transistor is connected to the second light emission control signal terminal, a first electrode of the fifth transistor is connected to the first voltage terminal, and a second electrode of the fifth transistor is connected to the second node; a control electrode of the sixth transistor is connected to the first light emission control signal terminal, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor is connected to the fourth node.

[0008] In an exemplary embodiment, the first reset sub-circuit includes a first transistor and a seventh transistor, the compensation sub-circuit includes a second transistor and a first capacitor, the driving sub-circuit includes a third transistor, the writing sub-circuit includes a fourth transistor, the second light-emitting control sub-circuit includes a fifth transistor, and the first light-emitting control sub-circuit includes a sixth transistor; a control electrode of the first transistor is connected to a first scan signal terminal, a first electrode of the first transistor is connected to a first initial signal terminal, and a second electrode of the first transistor is connected to a first electrode of the seventh transistor; a control electrode of the seventh transistor is connected to the first light-emitting control signal terminal, and a second electrode of the seventh transistor is connected to the third node; a control electrode of the second transistor is connected to a third scan signal terminal, a first electrode of the second transistor is connected to the third node, and a second electrode of the second transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the first voltage terminal; a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the third node; a control electrode of the fourth transistor is connected to a second scan signal terminal, a first electrode of the fourth transistor is connected to the data signal terminal, and a second electrode of the fourth transistor is connected to the second node; a control electrode of the fifth transistor is connected to the second light-emitting control signal terminal, a first electrode of the fifth transistor is connected to the first voltage terminal, and a second electrode of the fifth transistor is connected to the second node; a control electrode of the sixth transistor is connected to the first light-emitting control signal terminal, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor is connected to the fourth node.

[0009] In an exemplary embodiment, the first transistor to the seventh transistor are all low-temperature polycrystalline silicon thin-film transistors, and signals of the third scan signal terminal and the first scan signal terminal are the same.

[0010] In an exemplary embodiment, the first transistor, the third transistor to the seventh transistor are all low-temperature polycrystalline silicon thin-film transistors, the second transistor is an indium gallium zinc oxide thin-film transistor, and signals of the third scan signal terminal and the first scan signal terminal are opposite.

[0011] In an exemplary embodiment, the pixel circuit further includes a second reset sub-circuit, wherein the second reset sub-circuit is respectively connected to the second scan signal terminal, a second initial signal terminal and the fourth node, and is configured to write a signal of the second initial signal terminal to the fourth node under the control of a signal of the second scan signal terminal.

[0012] In an exemplary embodiment, the second reset sub - circuit includes an eighth transistor. The control electrode of the eighth transistor is connected to the second scan signal terminal. The first electrode of the eighth transistor is connected to the second initial signal terminal. The second electrode of the eighth transistor is connected to the fourth node.

[0013] In an exemplary embodiment, the pixel circuit further includes a third reset sub - circuit. The third reset sub - circuit is respectively connected to the second scan signal terminal, the second voltage terminal, and the fourth node, and is configured to write the signal of the second voltage terminal to the fourth node under the control of the signal of the second scan signal terminal.

[0014] In an exemplary embodiment, the third reset sub - circuit includes a ninth transistor. The control electrode of the ninth transistor is connected to the second scan signal terminal. The first electrode of the ninth transistor is connected to the second voltage terminal. The second electrode of the ninth transistor is connected to the fourth node.

[0015] An exemplary embodiment of the present disclosure further provides a display device, including the pixel circuit described in any one of the foregoing items.

[0016] An exemplary embodiment of the present disclosure further provides a driving method for a pixel circuit, for driving the pixel circuit described in any one of the foregoing items. The driving method includes:

[0017] In the reset stage, the first reset sub - circuit writes the signal of the first initial voltage terminal to the third node under the control of the signals of the first scan signal terminal and the first light - emitting control signal terminal. The compensation sub - circuit writes the signal of the third node to the first node under the control of the signal of the third scan signal terminal. The first light - emitting control sub - circuit provides the signal of the third node to the fourth node under the control of the signal of the first light - emitting control signal terminal.

[0018] In the data writing stage, the writing sub - circuit writes the signal of the data signal terminal to the second node under the control of the signal of the second scan signal terminal. The compensation sub - circuit compensates the first node under the control of the signals of the third scan signal terminal and the first voltage terminal.

[0019] In the light - emitting stage, the second light - emitting control sub - circuit provides the signal of the first voltage terminal to the second node under the control of the signal of the second light - emitting control signal terminal. The driving sub - circuit provides a driving current to the third node under the control of the signals of the first node and the second node. The first light - emitting control sub - circuit allows the driving current to pass between the fourth node and the third node under the control of the signal of the first light - emitting control signal terminal.

[0020] In an exemplary embodiment, between the data writing stage and the light - emitting stage, the driving method further includes:

[0021] During one or more blank phases, at least one of the first light-emitting control sub-circuit and the second light-emitting control sub-circuit does not allow drive current to pass through. The one or more blank phases are used to make the pulse widths of the signals at the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal the same within one scan period.

[0022] Other aspects will be apparent after reading the accompanying drawings and the detailed description. Description of the Drawings

[0023] The accompanying drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure.

[0024] Figure 1 It is one of the structural schematic diagrams of the pixel circuit provided by the embodiment of the present disclosure;

[0025] Figure 2 It is the equivalent circuit diagram of the first reset sub-circuit provided by the embodiment of the present disclosure;

[0026] Figure 3 It is the equivalent circuit diagram of the compensation sub-circuit, the drive sub-circuit, and the write sub-circuit provided by the embodiment of the present disclosure;

[0027] Figure 4 It is the equivalent circuit diagram of the second light-emitting control sub-circuit and the first light-emitting control sub-circuit provided by the embodiment of the present disclosure;

[0028] Figure 5 It is one of the equivalent circuit diagrams of the pixel circuit provided by the embodiment of the present disclosure;

[0029] Figure 6 It is the second equivalent circuit diagram of the pixel circuit provided by the embodiment of the present disclosure;

[0030] Figure 7 It is one of the working timing diagrams of the pixel circuit provided by the embodiment of the present disclosure;

[0031] Figure 8 It is the second working timing diagram of the pixel circuit provided by the embodiment of the present disclosure;

[0032] Figure 9 It is the third working timing diagram of the pixel circuit provided by the embodiment of the present disclosure;

[0033] Figure 10 It is the fourth working timing diagram of the pixel circuit provided by the embodiment of the present disclosure;

[0034] Figure 11 One of the equivalent circuit diagrams of adjacent two - row sub - pixel pixel circuits provided by the embodiments of the present disclosure;

[0035] Figure 12 is Figure 11 the working timing diagram of the adjacent two - row sub - pixel pixel circuits shown;

[0036] Figure 13 The second structural schematic diagram of the pixel circuit provided by the embodiments of the present disclosure;

[0037] Figure 14 The third equivalent circuit diagram of the pixel circuit provided by the embodiments of the present disclosure;

[0038] Figure 15 The second equivalent circuit diagram of the adjacent two - row sub - pixel pixel circuits provided by the embodiments of the present disclosure;

[0039] Figure 16 The third equivalent circuit diagram of the adjacent two - row sub - pixel pixel circuits provided by the embodiments of the present disclosure;

[0040] Figure 17 The third structural schematic diagram of the pixel circuit provided by the embodiments of the present disclosure;

[0041] Figure 18 The fourth equivalent circuit diagram of the pixel circuit provided by the embodiments of the present disclosure;

[0042] Figure 19 The flow schematic diagram of the driving method of the pixel circuit provided by the embodiments of the present disclosure. Detailed implementation manners

[0043] In the following, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the embodiments can be implemented in multiple different forms. Those of ordinary skill in the art can easily understand the fact that the manner and content can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other arbitrarily.

[0044] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure belongs. The "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0045] In an embodiment of the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current mainly flows.

[0046] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes switch with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be switched with each other.

[0047] In this specification, "connection" includes cases where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0048] An embodiment of the present disclosure provides a pixel circuit. Figure 1 is a schematic structural diagram of the pixel circuit provided by the embodiment of the present disclosure, as Figure 1 shown, the pixel circuit includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and a light-emitting element.

[0049] Among them, the driving sub-circuit is respectively connected to the first node N1, the second node N2, and the third node N3, and is configured to provide a driving current to the third node N3 under the control of the signals of the first node N1 and the second node N2;

[0050] The writing sub-circuit is respectively connected to the second scan signal terminal Gate2, the data signal terminal Data, and the second node N2, and is configured to write the signal of the data signal terminal Data into the second node N2 under the control of the signal of the second scan signal terminal Gate2;

[0051] The compensation sub - circuit is respectively connected to the first voltage terminal VDD, the third scan signal terminal Gate3, the first node N1, and the third node N3, and is configured to write the signal of the third node N3 into the first node N1 under the control of the signal of the third scan signal terminal Gate3, and compensate the first node N1 under the control of the signals of the third scan signal terminal Gate3 and the first voltage terminal VDD;

[0052] The first reset sub - circuit is respectively connected to the first scan signal terminal Gate1, the first light - emitting control signal terminal EM1, the first initial signal terminal INT1, and the third node N3, and is configured to write the signal of the first initial signal terminal INT1 into the third node N3 under the control of the signals of the first scan signal terminal Gate1 and the first light - emitting control signal terminal EM1;

[0053] The second light - emitting control sub - circuit is respectively connected to the first voltage terminal VDD, the second light - emitting control signal terminal EM2, and the second node N2, and is configured to provide the signal of the first voltage terminal VDD to the second node N2 under the control of the signal of the second light - emitting control signal terminal EM2;

[0054] The first light - emitting control sub - circuit is respectively connected to the first light - emitting control signal terminal EM1, the third node N3, and the fourth node, and is configured to provide the signal of the third node N3 to the fourth node under the control of the signal of the first light - emitting control signal terminal EM1, and allow a driving current to pass between the third node N3 and the fourth node;

[0055] One end of the light - emitting element is connected to the fourth node N4, and the other end is connected to the second voltage terminal VSS.

[0056] The pixel circuit provided by the embodiment of the present disclosure writes the signal of the data signal terminal Data to the second node N2 under the control of the signal of the second scan signal terminal Gate2 through the writing sub-circuit. The compensation sub-circuit writes the signal of the third node N3 to the first node N1 under the control of the signal of the third scan signal terminal Gate3, and compensates the first node N1 under the control of the signals of the third scan signal terminal Gate3 and the first voltage terminal VDD. The first reset sub-circuit writes the signal of the first initial signal terminal INT1 to the third node N3 under the control of the signals of the first scan signal terminal Gate1 and the first light emission control signal terminal EM1. The first light emission control sub-circuit provides the signal of the third node N3 to the fourth node N4 under the control of the signal of the first light emission control signal terminal EM1, realizing the compensation of the control electrode voltage of the driving sub-circuit, avoiding the influence of the threshold voltage drift of the driving sub-circuit on the driving current of the light emitting element, and improving the uniformity of the displayed image and the display quality of the display panel. Moreover, the pixel circuit of the embodiment of the present disclosure has fewer leakage channels, improving the flashing effect at low frequencies. In addition, the pixel circuit of the embodiment of the present disclosure does not require a double-gate design, reducing the occupied space of the pixel circuit and improving the resolution of the screen.

[0057] In an exemplary embodiment, Figure 2 is the equivalent circuit diagram of the first reset sub-circuit provided by the embodiment of the present disclosure. As Figure 2 shown, the first reset sub-circuit provided by the embodiment of the present disclosure includes: a first transistor T1 and a seventh transistor T7.

[0058] Wherein, the control electrode of the first transistor T1 is connected to the first scan signal terminal Gate1, the first pole of the first transistor T1 is connected to the first initial signal terminal INT1, and the second pole of the first transistor T1 is connected to the first pole of the seventh transistor T7;

[0059] The control electrode of the seventh transistor T7 is connected to the first light emission control signal terminal EM1, and the second pole of the seventh transistor T7 is connected to the third node N3.

[0060] Figure 2 shows an exemplary structure of the first reset sub-circuit. It is easy for those skilled in the art to understand that the implementation manner of the first reset sub-circuit is not limited to this, as long as its function can be realized.

[0061] In an exemplary embodiment, Figure 3 is the equivalent circuit diagram of the compensation sub-circuit, the driving sub-circuit and the writing sub-circuit provided by the embodiment of the present disclosure. As Figure 3 shown, the compensation sub-circuit provided by the embodiment of the present disclosure includes a second transistor T2 and a first capacitor C1, the driving sub-circuit includes a third transistor (i.e., a driving transistor) T3, and the writing sub-circuit includes a fourth transistor T4.

[0062] Among them, the control electrode of the second transistor T2 is connected to the third scan signal terminal Gate3, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1;

[0063] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first voltage terminal VDD;

[0064] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3;

[0065] The control electrode of the fourth transistor T4 is connected to the second scan signal terminal Gate2, the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0066] Figure 3 An exemplary structure of the compensation sub-circuit, the driving sub-circuit, and the writing sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation manners of the compensation sub-circuit, the driving sub-circuit, and the writing sub-circuit are not limited thereto, as long as their respective functions can be realized.

[0067] In an exemplary embodiment, Figure 4 This is an equivalent circuit diagram of the second light-emitting control sub-circuit and the first light-emitting control sub-circuit provided by the embodiments of the present disclosure. As Figure 4 shown, the second light-emitting control sub-circuit provided by the embodiments of the present disclosure includes a fifth transistor T5, and the first light-emitting control sub-circuit includes a sixth transistor T6.

[0068] Among them, the control electrode of the fifth transistor T5 is connected to the second light-emitting control signal terminal EM2, the first electrode of the fifth transistor T5 is connected to the first voltage terminal VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2;

[0069] The control electrode of the sixth transistor T6 is connected to the first light-emitting control signal terminal EM1, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0070] Figure 4 An exemplary structure of the second light-emitting control sub-circuit and the first light-emitting control sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation manners of the second light-emitting control sub-circuit and the first light-emitting control sub-circuit are not limited thereto, as long as their respective functions can be realized.

[0071] Figure 5 and Figure 6Two equivalent circuit diagrams of the pixel circuit provided by the embodiments of the present disclosure are as follows Figure 5 and Figure 6 As shown, in the pixel circuit provided by the embodiments of the present disclosure, the first reset sub-circuit includes: a first transistor T1 and a seventh transistor T7, the compensation sub-circuit includes a second transistor T2 and a first capacitor C1, the driving sub-circuit includes a third transistor T3, the writing sub-circuit includes a fourth transistor T4, the second light-emitting control sub-circuit includes a fifth transistor T5, and the first light-emitting control sub-circuit includes a sixth transistor T6.

[0072] The control electrode of the first transistor T1 is connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is connected to the first initial signal terminal INT1, and the second electrode of the first transistor T1 is connected to the first electrode of the seventh transistor T7;

[0073] The control electrode of the seventh transistor T7 is connected to the first light-emitting control signal terminal EM1, and the second electrode of the seventh transistor T7 is connected to the third node N3;

[0074] The control electrode of the second transistor T2 is connected to the third scan signal terminal Gate3, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1;

[0075] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the first voltage terminal VDD;

[0076] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3;

[0077] The control electrode of the fourth transistor T4 is connected to the second scan signal terminal Gate2, the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the second node N2;

[0078] The control electrode of the fifth transistor T5 is connected to the second light-emitting control signal terminal EM2, the first electrode of the fifth transistor T5 is connected to the first voltage terminal VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2;

[0079] The control electrode of the sixth transistor T6 is connected to the first light-emitting control signal terminal EM1, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0080] Figure 5 and Figure 6An exemplary structure of a first reset sub-circuit, a compensation sub-circuit, a driving sub-circuit, a writing sub-circuit, a second light-emitting control sub-circuit, and a first light-emitting control sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation manners of the above sub-circuits are not limited thereto, as long as their respective functions can be realized.

[0081] In one exemplary embodiment, the light-emitting element EL may be an organic light-emitting diode (OLED) or any other type of light-emitting diode.

[0082] In one exemplary embodiment, as Figure 5 and Figure 7 shown, the first transistor to the seventh transistor are all N-type thin-film transistors, or all P-type thin-film transistors, and the signals of the third scan signal terminal Gate3 and the first scan signal terminal Gate1 are the same.

[0083] When the first transistor T1 to the seventh transistor T7 are all thin-film transistors of the same type, since the signals of the third scan signal terminal Gate3 and the first scan signal terminal Gate1 are exactly the same, at this time, the third scan signal terminal Gate3 and the first scan signal terminal Gate1 can be connected to the same scan signal line.

[0084] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0085] Compared with the traditional pixel circuit, there is only one leakage channel (i.e., the second transistor T2 connected to the control electrode of the third transistor T3) in the pixel circuit of the present disclosure embodiment. After the leakage channel is reduced, the generated leakage current is less, the brightness difference between the front and back of a frame of image is reduced, and the low-frequency flicker effect will be better. In addition, compared with the traditional pixel circuit, the first transistor T1 in the present disclosure embodiment is not connected to the control electrode of the third transistor T3 and will not generate leakage current. Therefore, the first transistor T1 does not need to be designed with a double gate, which reduces the occupied space of the pixel circuit and is beneficial to improving the resolution of the display panel.

[0086] In another exemplary embodiment, as Figure 6 and Figure 8As shown, the first transistor T1, the third transistor T3 to the seventh transistor T7 are all P-type thin film transistors, the second transistor T2 is an N-type thin film transistor, and the signals of the third scan signal terminal Gate3 and the first scan signal terminal Gate1 are opposite.

[0087] In an exemplary embodiment, the first transistor T1, the third transistor T3 to the seventh transistor T7 are all low temperature poly silicon (LTPS) thin film transistors (TFTs), and the second transistor T2 is an indium gallium zinc oxide (IGZO) thin film transistor.

[0088] In this embodiment, compared with the low temperature poly silicon thin film transistor, the indium gallium zinc oxide thin film transistor generates less leakage current. Therefore, setting the second transistor T2 as an indium gallium zinc oxide thin film transistor can significantly reduce the generation of leakage current. The first transistor T1 does not need to be set as an indium gallium zinc oxide thin film transistor. Since the size of the low temperature poly silicon thin film transistor is generally smaller than that of the indium gallium zinc oxide thin film transistor, the occupied space of the pixel circuit in the embodiment of the present disclosure is relatively small, which is beneficial to improving the resolution of the display panel.

[0089] Taking the example that the first transistor T1 to the seventh transistor T7 in the pixel circuit provided by the embodiment of the present disclosure are all P-type thin film transistors, combined with Figure 5 the pixel circuit unit shown in Figure 7 and the working timing diagram shown in Figure 5 the working process of a pixel circuit unit within one frame period will be described in detail. As shown in Figure 5 the pixel circuit provided by the embodiment of the present disclosure includes 7 transistor units (T1 to T7), 1 capacitor unit (C1), and 4 power supply terminals (VDD, VSS, Data, and INT1). Among them, the first power supply voltage terminal VDD continuously provides a high-level signal VGH, and the second power supply voltage terminal VSS continuously provides a low-level signal VGL. In an exemplary embodiment, its working process includes:

[0090] The first stage t1, called the reset stage, the signals of the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light emission control signal terminal EM1 are all low-level signals, and the signals of the second scan signal terminal Gate2 and the second light emission control signal terminal EM2 are all high-level signals. The low-level signals of the first scan signal terminal Gate1, the third scan signal terminal Gate3, and the first light emission control signal terminal EM1 turn on the first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7. The conduction of the first transistor T1 and the seventh transistor T7 enables the initial voltage Vint1 of the first initial signal terminal INT1 to be provided to the third node N3. The conduction of the second transistor T2 enables the initial voltage Vint1 of the third node N3 to be provided to the first node N1. The conduction of the sixth transistor T6 enables the initial voltage Vint1 of the third node N3 to be provided to the fourth node N4. At this time, the potentials of the first node N1, the third node N3, and the fourth node N4 are all the initial voltage Vint1 provided by the first initialization signal terminal INT1. This stage resets the storage capacitor C1, the voltage of the anodic terminal of the light-emitting element EL, and the gate voltage of the third transistor (i.e., the driving transistor) T3 to complete the initialization. The high-level signals of the second scan signal terminal Gate2 and the second light emission control signal terminal EM2 turn off the fourth transistor T4 and the fifth transistor T5, and the OLED does not emit light in this stage.

[0091] The second stage t2, called the data writing stage, the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are all low-level signals, the signals of the first light emission control signal terminal EM1 and the second light emission control signal terminal EM2 are all high-level signals, and the data signal terminal Data outputs a data voltage. In this stage, since the second terminal (i.e., the first node N1) of the first capacitor C1 is at a low level, the third transistor T3 is turned on. The low-level signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 turn on the first transistor T1, the second transistor T2, and the fourth transistor T4. The conduction of the second transistor T2 and the fourth transistor T4 enables the data voltage output by the data signal terminal Data to pass through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 to be provided to the first node N1, and charges the difference between the data voltage output by the data signal terminal Data and the threshold voltage of the third transistor T3 into the first capacitor C1. The voltage of the second terminal (the first node N1) of the first capacitor C1 is Vdata - Vth, where Vdata is the data voltage output by the data signal terminal Data and Vth is the threshold voltage of the third transistor T3. The high-level signals of the first light emission control signal terminal EM1 and the second light emission control signal terminal EM2 turn off the fifth transistor T5 and the sixth transistor T6 to ensure that the OLED does not emit light.

[0092] In the third stage t3, which is called the light-emitting stage, the signals of both the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 are low-level signals, and the signals of the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, and the third scanning signal terminal Gate3 are all high-level signals. The low-level signals of the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 turn on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first pole (i.e., the fourth node N4) of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting element EL to emit light.

[0093] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 (i.e., the driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage of the first node N1 is Vdata - Vth, the driving current of the third transistor T3 is:

[0094] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vdata + Vth) - Vth] 2 = K * [(Vdd - Vd)] 2

[0095] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output from the data signal terminal Data, and Vdd is the power supply voltage output from the first power supply terminal VDD.

[0096] It can be seen from the above formula that the current I flowing through the light-emitting element EL has nothing to do with the threshold voltage Vth of the third transistor T3, eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.

[0097] Based on the above working timing, the pixel circuit eliminates the residual positive charge of the light-emitting element EL after the previous light emission, realizes the compensation of the gate voltage of the driving transistor, avoids the influence of the threshold voltage drift of the driving transistor on the driving current of the light-emitting element EL, and improves the uniformity of the displayed image and the display quality of the display panel.

[0098] In some exemplary embodiments, such as Figure 9 and Figure 10As shown, one or more blank phases Bi can be added between the second phase t2 (data writing phase) and the third phase t3 (light emitting phase), where i is a natural number greater than or equal to 1. During the blank phase Bi, at least one of the signals of the first light emitting control signal terminal EM1 and the second light emitting control signal terminal EM2 is a high level signal, so that the light emitting element EL does not emit light during the blank phase Bi. By setting one or more blank phases in the embodiments of the present disclosure, the pulse widths of the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 are the same in one scan cycle, so that the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, and the third scan signal terminal Gate3 can be generated by cascading shift registers.

[0099] In an exemplary embodiment, as Figure 9 or Figure 10 shown, within one scan cycle, compared with the signal of the second scan signal terminal Gate2, the signal of the first scan signal terminal Gate1 has the same low level pulse period, and the starting moment only differs by one t1 phase. Therefore, the sub-pixel pixel circuits of adjacent rows can share the same scan signal line.

[0100] As Figure 11 shown, the fourth transistor T4 in the sub-pixels of the i-th row and the first transistor T1 in the sub-pixels of the (i + 1)-th row can share the same scan signal line. Therefore, during pixel layout design, the channel regions of the fourth transistor T4 in the sub-pixels of the i-th row and the first transistor T1 in the sub-pixels of the (i + 1)-th row can both extend along the first direction and be located on a straight line. In this embodiment, the first direction can be the extension direction of the scan signal line.

[0101] Figure 12 For Figure 11 a schematic diagram of a driving timing of the pixel circuit shown, in an exemplary embodiment, as Figure 12As shown, within one scan cycle, the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5,... The periods of the low-level pulses are the same, and the starting moments are successively different by one t1 stage. The corresponding signals can be generated through cascading shift registers. When the types of the first transistor T1 to the seventh transistor T7 are the same, the signal of the third scan signal terminal Gate3 is the same as the signal of the first scan signal terminal Gate1, and the signal of the sixth scan signal terminal Gate6 is the same as the signal of the second scan signal terminal Gate2. When the type of the second transistor T2 is different from that of other transistors, the signal of the third scan signal terminal Gate3 is opposite to the signal of the first scan signal terminal Gate1, and the signal of the sixth scan signal terminal Gate6 is opposite to the signal of the second scan signal terminal Gate2.

[0102] Assume that the entire display panel includes a total of 2N rows of sub-pixels, where N is a natural number greater than 1. The first transistor T1 in the sub-pixels of the (2i + 1)-th row is connected to the signal of the (3i + 1)-th scan signal terminal, and the fourth transistor T4 in the sub-pixels of the (2i + 1)-th row is connected to the signal of the (3i + 2)-th scan signal terminal; the first transistor T1 in the sub-pixels of the (2i + 2)-th row is connected to the signal of the (3i + 2)-th scan signal terminal, and the fourth transistor T4 in the sub-pixels of the (2i + 2)-th row is connected to the signal of the (3i + 4)-th scan signal terminal, where i is an integer between 0 and N - 1;

[0103] The second transistor T2 in the sub-pixels of the k-th row is connected to the signal of the (3k)-th scan signal terminal. The sixth transistor T6 and the seventh transistor T7 in the sub-pixels of the k-th row are connected to the signal of the (2k - 1)-th light emission control signal terminal. The fifth transistor T5 in the sub-pixels of the k-th row is connected to the signal of the (2k)-th light emission control signal terminal, where k is an integer between 1 and 2N.

[0104] For the entire display panel, the signals of the first scan signal terminal, the second scan signal terminal, the fourth scan signal terminal, the fifth scan signal terminal,... the signal of the (3i + 1)-th scan signal terminal, the signal of the (3i + 2)-th scan signal terminal,... the signal of the (3N - 2)-th scan signal terminal, the signal of the (3N - 1)-th scan signal terminal can be sequentially shifted and generated by a group of shift registers, that is, the signals of the first scan signal terminal, the second scan signal terminal, the fourth scan signal terminal, the fifth scan signal terminal, the seventh scan signal terminal, the eighth scan signal terminal,... are gradually shifted (the periods of the low-level pulses are the same, and the starting moments are successively different by one t1 stage).

[0105] Signals of the third scanning signal terminal, signals of the sixth scanning signal terminal... signals of the (3k)-th scanning signal terminal... signals of the (3N)-th scanning signal terminal can be sequentially shifted and generated by a group of shift registers. Optionally, when the types of the first transistor T1 to the seventh transistor T7 are the same, the control electrode of the second transistor T2 in the sub-pixels of the k-th row can share a scanning signal line with the control electrode of the first transistor T1 in the sub-pixels of this row, that is, the signal of the (3k)-th scanning signal terminal is the signal of the control electrode of the first transistor T1 in the sub-pixels of this row.

[0106] Signals of the first light emission control signal terminal, signals of the third light emission control signal terminal... signals of the (2k - 1)-th light emission control signal terminal... signals of the (4N - 1)-th scanning signal terminal can be sequentially shifted and generated by a group of shift registers.

[0107] Signals of the second light emission control signal terminal, signals of the fourth light emission control signal terminal... signals of the (2k)-th light emission control signal terminal... signals of the (4N)-th light emission control signal terminal can be sequentially shifted and generated by a group of shift registers.

[0108] In an exemplary embodiment, as Figure 13 shown, the pixel circuit further includes a second reset sub-circuit, wherein the second reset sub-circuit is respectively connected to the second scanning signal terminal Gate2, the second initial signal terminal INT2, and the fourth node N4, and is configured to write the signal of the second initial signal terminal INT2 to the fourth node N4 under the control of the signal of the second scanning signal terminal Gate2.

[0109] In an exemplary embodiment, as Figure 14 shown, the second reset sub-circuit includes an eighth transistor T8. The control electrode of the eighth transistor T8 is connected to the second scanning signal terminal Gate2, the first electrode of the eighth transistor T8 is connected to the second initial signal terminal INT2, and the second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0110] In this embodiment, a separate eighth transistor T8 is added to the fourth node N4 to separately reset the fourth node N4 (i.e., the anodic terminal of the light-emitting element EL), so that the reset voltages of the first node N1 and the fourth node N4 are different, achieving the effect of separate control.

[0111] In an exemplary embodiment, as Figure 14As shown, the control electrode of the eighth transistor T8 is connected to the second scan signal terminal Gate2, and the control electrode of the first transistor T1 is connected to the first scan signal terminal Gate1. In one scan cycle, compared with the signal of the second scan signal terminal Gate2, the signal of the first scan signal terminal Gate1 has the same low-level pulse period, and the starting moment only differs by a t1 stage. Therefore, as Figure 15 shown, the anodic terminal of the light-emitting element in the sub-pixel pixel circuit of the i-th row can be reset by using the eighth transistor T8 in the sub-pixel pixel circuit of the (i + 1)-th row, so as to facilitate sharing the same scan signal line by the eighth transistor T8 and the first transistor T1 in the sub-pixels of each row, which is beneficial to the spatial layout of the pixel circuit and improves the display resolution. When designing the pixel layout, the channel regions of the eighth transistor T8 and the first transistor T1 in the sub-pixels of each row can both extend along the first direction and be located on a straight line.

[0112] Figure 15 In , the eighth transistor T8 and the first transistor T1 in the sub-pixels of each row share the same initial signal line INT1. In other exemplary embodiments, the eighth transistor T8 and the first transistor T1 in the sub-pixels of each row can also use different initial signal lines respectively. For example, the first transistor T1 uses the first initial signal line INT1, and the eighth transistor T8 uses the second initial signal line INT2. The present disclosure does not limit this.

[0113] In an exemplary embodiment, as Figure 16 shown, the anodic terminal of the light-emitting element in the sub-pixel pixel circuit of the i-th row can also be reset by using the signal of the second pole (i.e., Figure 16 the fifth node in ) of the first transistor T1 in the sub-pixel pixel circuit of the (i + 1)-th row, so as to further reduce the number of thin-film transistors, which is beneficial to the spatial layout of the pixel circuit and improves the display resolution.

[0114] The fourth transistor T4 in the sub-pixels of the i-th row and the first transistor T1 in the sub-pixels of the (i + 1)-th row can share the same scan signal line. Therefore, when designing the pixel layout, the channel regions of the fourth transistor T4 in the sub-pixels of the i-th row and the first transistor T1 in the sub-pixels of the (i + 1)-th row can both extend along the first direction and be located on a straight line. In this embodiment, the first direction can be the extending direction of the scan signal line.

[0115] In another exemplary embodiment, as Figure 17As shown, the pixel circuit further includes a third reset sub-circuit. The third reset sub-circuit is respectively connected to the second scan signal terminal Gate2, the second voltage terminal VSS, and the fourth node N4, and is configured to write the signal of the second voltage terminal VSS to the fourth node N4 under the control of the signal of the second scan signal terminal Gate2.

[0116] In an exemplary embodiment, as Figure 18 shown, the third reset sub-circuit includes a ninth transistor T9. The control electrode of the ninth transistor T9 is connected to the second scan signal terminal Gate2, the first electrode of the ninth transistor T9 is connected to the second voltage terminal VSS, and the second electrode of the ninth transistor T9 is connected to the fourth node N4.

[0117] In this embodiment, a separate ninth transistor T9 is added to the fourth node N4. The fourth node N4 (i.e., the anodic terminal of the light-emitting element EL) is reset separately through the ninth transistor T9, and the reset voltage of the fourth node N4 is the same as the second voltage of the second voltage terminal VSS. In this way, the reset voltages of the first node N1 and the fourth node N4 are different, achieving the effect of separate control. In addition, since the second voltage terminal VSS can be dynamically set according to different gray levels, the reset voltage of the fourth node N4 also achieves the effect of dynamic reset.

[0118] Some embodiments of the present disclosure further provide a driving method for a pixel circuit, which is applied to the pixel circuit provided in the foregoing embodiments. The pixel circuit includes: a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, and a light-emitting element, as well as a first scan signal terminal, a second scan signal terminal, a third scan signal terminal, a first light-emitting control signal terminal, a second light-emitting control signal terminal, a first initial signal terminal, a data signal terminal, a first voltage terminal, and a second voltage terminal. Figure 19 is a flowchart of the driving method for the pixel circuit of the embodiments of the present disclosure. The pixel circuit has multiple scan cycles. In one scan cycle, as Figure 19 shown, the driving method includes the following steps:

[0119] Step S1: In the reset stage, the first reset sub-circuit writes the signal of the first initial voltage terminal to the third node under the control of the signals of the first scan signal terminal and the first light-emitting control signal terminal. The compensation sub-circuit writes the signal of the third node to the first node under the control of the signal of the third scan signal terminal. The first light-emitting control sub-circuit provides the signal of the third node to the fourth node under the control of the signal of the first light-emitting control signal terminal.

[0120] In this step, the third node is initialized by the first reset sub-circuit, the first node is initialized by the compensation sub-circuit, and the fourth node is initialized by the first light-emitting control sub-circuit. The storage capacitor, the voltage at the anode terminal of the light-emitting element, and the voltage at the control terminal of the driving sub-circuit are reset, eliminating the residual positive charge at the anode after the light-emitting element last emitted light and the residual charge in the storage capacitor.

[0121] In an exemplary embodiment, the pixel circuit further includes: a second reset sub-circuit, and the driving method further includes:

[0122] The second reset sub-circuit writes the signal at the second initial signal terminal to the fourth node under the control of the signal at the second scan signal terminal.

[0123] In another exemplary embodiment, the pixel circuit further includes: a third reset sub-circuit, and the driving method further includes:

[0124] The third reset sub-circuit writes the signal at the second voltage terminal to the fourth node under the control of the signal at the second scan signal terminal.

[0125] Step S2, in the data writing stage, the writing sub-circuit writes the signal at the data signal terminal to the second node under the control of the signal at the second scan signal terminal, and the compensation sub-circuit compensates the first node under the control of the signal at the third scan signal terminal and the signal at the first voltage terminal.

[0126] In this step, a data voltage signal is provided to the data signal terminal. When the first node is charged to Vdata - Vth, the driving transistor turns off, realizing the compensation for the threshold voltage of the driving transistor, thereby improving the uniformity of the displayed image.

[0127] Step S3, in the light-emitting stage, the second light-emitting control sub-circuit provides the signal at the first voltage terminal to the second node under the control of the signal at the second light-emitting control signal terminal, the driving sub-circuit provides a driving current to the third node under the control of the signals at the first node and the second node, and the first light-emitting control sub-circuit allows the driving current to pass between the fourth node and the third node under the control of the signal at the first light-emitting control signal terminal.

[0128] In this step, the generated driving current is:

[0129] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vdata + Vth) - Vth] 2 = K * [(Vdd - Vd)] 2

[0130] Wherein, I is the driving current flowing through the driving transistor, which is also the driving current for driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the driving transistor, Vth is the threshold voltage of the driving transistor, Vdata is the data voltage output from the data signal terminal, and Vdd is the power supply voltage output from the first power supply terminal.

[0131] In an exemplary embodiment, between the data writing stage and the light-emitting stage, the driving method further includes:

[0132] In one or more blank stages, at least one of the first light-emitting control sub-circuit and the second light-emitting control sub-circuit does not allow the driving current to pass through, and the one or more blank stages are used to make the pulse widths of the signals of the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal the same within one scan cycle.

[0133] The driving method of the pixel circuit provided by the embodiments of the present disclosure eliminates the residual positive charge after the last light emission of the light-emitting element, realizes the compensation of the gate voltage of the thin-film transistor, and improves the uniformity of the displayed image and the display quality of the display panel. Moreover, the driving method of the pixel circuit of the embodiments of the present disclosure has fewer leakage channels, improves the flash screen effect at low frequencies. In addition, the pixel circuit of the embodiments of the present disclosure does not require a double-gate design, reduces the occupied space of the pixel circuit, and improves the resolution of the screen.

[0134] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, which includes the pixel circuit provided by the above embodiments. The display device of the present disclosure can be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator. In an exemplary embodiment, the display device can be a wearable display device that can be worn on the human body in certain ways, such as a smart watch, a smart bracelet, etc.

[0135] The following points need to be explained:

[0136] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0137] Without conflict, the embodiments of the present disclosure, that is, the features in the embodiments can be combined with each other to obtain new embodiments.

[0138] Although the embodiments disclosed in the present disclosure are as above, the content described is only an embodiment adopted for facilitating the understanding of the present disclosure and is not intended to limit the present disclosure. Any person skilled in the art within the scope of the present disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present disclosure. However, the scope of patent protection of the present disclosure shall still be subject to the scope defined by the appended claims.

Claims

1. A pixel circuit, comprising a driving sub - circuit, a writing sub - circuit, a compensating sub - circuit, a first reset sub - circuit, a first light - emitting control sub - circuit, a second light - emitting control sub - circuit, and a light - emitting element. When the pixel circuit is driven, it includes a reset stage, a data writing stage, a blank stage, and a light - emitting stage arranged in sequence, where: The driving sub - circuit is respectively connected to a first node, a second node, and a third node, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node during the light - emitting stage; The writing sub - circuit is respectively connected to a second scan signal terminal, a data signal terminal, and the second node, and is configured to write the signal of the data signal terminal into the second node under the control of the signal of the second scan signal terminal during the data writing stage; The compensating sub - circuit is respectively connected to a first voltage terminal, a third scan signal terminal, the first node, and the third node, and is configured to write the signal of the third node into the first node under the control of the signal of the third scan signal terminal during the reset stage, and compensate the first node under the control of the signals of the third scan signal terminal and the first voltage terminal during the data writing stage; The first reset sub - circuit is respectively connected to a first scan signal terminal, a first light - emitting control signal terminal, a first initial signal terminal, and the third node, and is configured to write the signal of the first initial signal terminal into the third node under the control of the signals of the first scan signal terminal and the first light - emitting control signal terminal during the reset stage; The second light - emitting control sub - circuit is respectively connected to the first voltage terminal, a second light - emitting control signal terminal, and the second node, and is configured to provide the signal of the first voltage terminal to the second node under the control of the signal of the second light - emitting control signal terminal during the light - emitting stage; The first light - emitting control sub - circuit is respectively connected to the first light - emitting control signal terminal, the third node, and a fourth node, and is configured to provide the signal of the third node to the fourth node under the control of the signal of the first light - emitting control signal terminal, and allow a driving current to pass between the third node and the fourth node during the light - emitting stage; One end of the light - emitting element is connected to the fourth node, and the other end is connected to a second voltage terminal; During the blank stage, at least one of the first light - emitting control sub - circuit and the second light - emitting control sub - circuit does not allow a driving current to pass. The blank stage is used to make the pulse widths of the signals of the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal the same within one scan cycle, and make the pulse widths of the first light - emitting control signal terminal and the second light - emitting control signal terminal the same within one scan cycle.

2. The pixel circuit according to claim 1, wherein, The first reset sub - circuit includes a first transistor and a seventh transistor; The control electrode of the first transistor is connected to the first scan signal terminal, the first pole of the first transistor is connected to the first initial signal terminal, and the second pole of the first transistor is connected to the first pole of the seventh transistor; The control electrode of the seventh transistor is connected to the first light emission control signal terminal, and the second electrode of the seventh transistor is connected to the third node.

3. The pixel circuit according to claim 1, wherein, The compensation sub-circuit includes a second transistor and a first capacitor, the driving sub-circuit includes a third transistor, and the writing sub-circuit includes a fourth transistor; The control electrode of the second transistor is connected to the third scanning signal terminal, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the first node; One end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the first voltage terminal; The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; The control electrode of the fourth transistor is connected to the second scanning signal terminal, the first electrode of the fourth transistor is connected to the data signal terminal, and the second electrode of the fourth transistor is connected to the second node.

4. The pixel circuit according to claim 1, wherein The second light emission control sub-circuit includes a fifth transistor, and the first light emission control sub-circuit includes a sixth transistor; The control electrode of the fifth transistor is connected to the second light emission control signal terminal, the first electrode of the fifth transistor is connected to the first voltage terminal, and the second electrode of the fifth transistor is connected to the second node; The control electrode of the sixth transistor is connected to the first light emission control signal terminal, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node.

5. The pixel circuit according to claim 1, wherein, The first reset sub-circuit includes a first transistor and a seventh transistor, the compensation sub-circuit includes a second transistor and a first capacitor, the driving sub-circuit includes a third transistor, the writing sub-circuit includes a fourth transistor, the second light emission control sub-circuit includes a fifth transistor, and the first light emission control sub-circuit includes a sixth transistor; The control electrode of the first transistor is connected to the first scanning signal terminal, the first electrode of the first transistor is connected to the first initial signal terminal, and the second electrode of the first transistor is connected to the first electrode of the seventh transistor; The control electrode of the seventh transistor is connected to the first light emission control signal terminal, and the second electrode of the seventh transistor is connected to the third node; The control electrode of the second transistor is connected to the third scanning signal terminal, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the first node; One end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the first voltage terminal; The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; The control electrode of the fourth transistor is connected to the second scanning signal terminal, the first electrode of the fourth transistor is connected to the data signal terminal, and the second electrode of the fourth transistor is connected to the second node; The control electrode of the fifth transistor is connected to the second light emission control signal terminal, the first electrode of the fifth transistor is connected to the first voltage terminal, and the second electrode of the fifth transistor is connected to the second node; The control electrode of the sixth transistor is connected to the first light emission control signal terminal, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node.

6. The pixel circuit according to claim 5, wherein, The first transistor to the seventh transistor are all low-temperature polysilicon thin film transistors, and the signals of the third scan signal terminal and the first scan signal terminal are the same.

7. The pixel circuit according to claim 5, wherein, The first transistor, the third transistor to the seventh transistor are all low-temperature polysilicon thin film transistors, the second transistor is an indium gallium zinc oxide thin film transistor, and the signals of the third scan signal terminal and the first scan signal terminal are opposite.

8. The pixel circuit according to any one of claims 1 to 7 further includes a second reset sub-circuit, wherein, The second reset sub-circuit is respectively connected to the second scan signal terminal, the second initial signal terminal and the fourth node, and is configured to write the signal of the second initial signal terminal into the fourth node under the control of the signal of the second scan signal terminal.

9. The pixel circuit according to claim 8, wherein, The second reset sub-circuit includes an eighth transistor, the control electrode of the eighth transistor is connected to the second scan signal terminal, the first electrode of the eighth transistor is connected to the second initial signal terminal, and the second electrode of the eighth transistor is connected to the fourth node.

10. The pixel circuit according to any one of claims 1 to 7 further includes a third reset sub-circuit, wherein, The third reset sub-circuit is respectively connected to the second scan signal terminal, the second voltage terminal and the fourth node, and is configured to write the signal of the second voltage terminal into the fourth node under the control of the signal of the second scan signal terminal.

11. The pixel circuit according to claim 10, wherein, The third reset sub-circuit includes a ninth transistor, the control electrode of the ninth transistor is connected to the second scan signal terminal, the first electrode of the ninth transistor is connected to the second voltage terminal, and the second electrode of the ninth transistor is connected to the fourth node.

12. A display device, comprising the pixel circuit according to any one of claims 1 to 11.

13. A driving method for a pixel circuit, for driving the pixel circuit according to any one of claims 1 to 11, the driving method comprising: In the reset stage, the first reset sub-circuit writes the signal of the first initial voltage terminal into the third node under the control of the signals of the first scan signal terminal and the first light emission control signal terminal, the compensation sub-circuit writes the signal of the third node into the first node under the control of the signal of the third scan signal terminal, and the first light emission control sub-circuit provides the signal of the third node to the fourth node under the control of the signal of the first light emission control signal terminal; In the data writing stage, the writing sub-circuit writes the signal of the data signal terminal into the second node under the control of the signal of the second scan signal terminal, and the compensation sub-circuit compensates the first node under the control of the signals of the third scan signal terminal and the first voltage terminal; In the blank period, at least one of the first light-emitting control sub-circuit and the second light-emitting control sub-circuit does not allow a driving current to pass through. The blank period is used to make the pulse widths of the signals at the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal the same within one scan cycle, and to make the pulse widths of the signals at the first light-emitting control signal terminal and the second light-emitting control signal terminal the same within one scan cycle; In the light-emitting period, the second light-emitting control sub-circuit provides the signal of the first voltage terminal to the second node under the control of the signal at the second light-emitting control signal terminal. The driving sub-circuit provides a driving current to the third node under the control of the signals at the first node and the second node. The first light-emitting control sub-circuit allows a driving current to pass between the fourth node and the third node under the control of the signal at the first light-emitting control signal terminal.

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