Independent parallel plane access in multi-plane memory devices

Abstract

A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, where the second number is less than the first number, and a plane selection circuit to couple the second number of independent plane driver circuits to the first number of planes of the memory array. The memory device further includes control logic to perform receiving a first read command and identifying, among the first number of planes, a first plane to which the first read command is directed. The control logic further configures the plane selection circuit to couple a first independent plane driver of the second number of independent plane drivers to the first plane and cause the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems and, more particularly, to independent parallel plane access in multi-plane memory devices in a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, wherein:

[0004] Figure 1 An example computing system including a memory sub-system is described in accordance with some embodiments of the present disclosure.

[0005] Figure 2 A block diagram of a multi-plane memory device configured for independent parallel plane access in accordance with some embodiments of the present disclosure is described.

[0006] Figure 3 A flow diagram of an example method of independent parallel plane access in a multi-plane memory device in a memory sub-system in accordance with some embodiments of the present disclosure is described.

[0007] Figure 4 A block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0008] Aspects of the present disclosure are directed to independent parallel plane access in multi-plane memory devices in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0009] A memory sub-system can include high-density non-volatile memory devices in which data is expected to be retained when no power is supplied to the memory devices. One example of a non-volatile memory device is a "not- and" (NAND) memory device. Examples of storage devices and memory modules are described below in connection with Figure 1Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store binary information of one or more bits, and has various logical states related to the number of bits stored. The logical states can be represented by binary values (e.g., “0” and “1,” or combinations of such values).

[0010] A memory device can be composed of bits arranged in a two-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. In the following, a block refers to a unit of a memory device for storing data, and can include a set of memory cells, a set of word lines, a word line, or a single memory cell. One or more blocks can be combined together to form a plane of a memory device in order to allow concurrent operations to occur on each plane. A memory device can include circuitry to perform concurrent memory page accesses of two or more memory planes. For example, a memory device can include a plurality of access line driver circuits and power supply circuits that can be shared by the planes of the memory device to facilitate concurrent access of pages including two or more memory planes of different page types. For ease of description, these circuits can be collectively referred to as independent plane driver circuits.

[0011] In certain memory devices, there can be fewer independent plane driver circuits than there are memory planes. For example, in one case, a memory device can have four separate memory planes, but only two independent plane driver circuits. In such a case, the planes are typically divided into multiple plane groups, each plane group being associated with a separate independent plane driver circuit. For example, the first two planes of the memory device can be part of a first plane group, which is associated with a first independent plane driver circuit, and the last two planes of the memory device can be part of a second plane group, which is associated with a second independent plane driver circuit. The two independent plane driver circuits allow memory access operations (e.g., read operations) to be performed in parallel (i.e., at least partially overlapping in time) on multiple planes of the memory device. Because the multiple planes are grouped into plane groups, each plane group being associated with a separate independent plane driver circuit, there is a limitation on which planes can be accessed in parallel. For example, if memory access operations are received that are directed to multiple planes in the same plane group, the memory access operations cannot be performed in parallel because there is only a single independent plane driver circuit associated with the plane group. Even if the memory device can include another independent plane driver circuit that is not being used, the independent plane driver circuit cannot be used to access the planes of the first plane group. Thus, at any time that a memory access operation is being performed on a given plane of the memory device, at least some other portion of the memory device is inaccessible. Thus, any subsequent memory access operations directed to planes in the same plane group are queued and processed at a later time (e.g., once the associated independent plane driver circuit completes processing of a previous memory access operation and becomes available). This increases the overall latency, reduces the number of read input / output operations per second (RIOPS) that can be processed by the memory device, and degrades the quality of service of a host system utilizing the memory subsystem.

[0012] Aspects of the disclosure address the above and other deficiencies by implementing plane selection circuitry in a memory device to selectively couple any of a first number of memory planes in the memory device to any of a second number of independent plane driver circuits. The independent plane driver circuits are configured to concurrently provide signals to access a block of a plane of the memory device during a memory access operation. In one embodiment, the plane selection circuitry includes a multiplexer circuit corresponding to each of the planes of the memory device. Each of the multiplexer circuits is configured to route a signal from any of the independent plane driver circuits to a corresponding one of the memory planes based on a control signal received from control logic in the memory device. In this way, the restriction on which planes can be accessed in parallel is eliminated. Thus, if one independent plane driver circuit is configured to perform a memory access operation on a given plane, a second independent plane driver circuit can be configured to perform a memory access operation on any other plane of the memory device in parallel, without any restriction based on a plane group.

[0013] Advantages of this approach include, but are not limited to, a reduction in total latency, an increase in the number of RIOPS that can be handled by the memory device, and an improvement in quality of service for a host system utilizing the memory subsystem. The approach described herein provides many benefits compared to adding additional independent plane driver circuits, such as one independent plane driver circuit corresponding to each plane of the memory device. For example, the second number of independent plane driver circuits can be less than the first number of memory planes in the memory device in order to reduce circuit area, amount of noise generated, and power consumption in the memory subsystem, while still providing the benefits described herein.

[0014] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated in accordance with some embodiments of the disclosure. The memory subsystem 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or such combinations.

[0015] The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0016] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial appliance), or such computing device that includes a memory and a processing device.

[0017] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 One example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0018] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 writes data to and reads data from the memory sub-system 110, for example, using the memory sub-system 110.

[0019] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize a Non-Volatile Memory express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0020] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory device 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0021] Some examples of non-volatile memory devices (e.g., the memory device 130) include “not- and” (NAND) type flash memory and in-place write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. For example, NAND type flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0022] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, e.g., a single-level cell (SLC), can store one bit of data per cell. Other types of memory cells, e.g., a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a penta-level cell (PLC), can store multiple bits of data per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, e.g., SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device can include SLC, MLC, TLC, QLC, or PLC portions of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to a logical unit of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0023] Although 3D cross-point arrays of non-volatile memory components, such as non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), “not- or” (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0024] Memory sub-system controller 115 (or, for simplicity, controller 115) can communicate with memory devices 130 to perform operations such as reading data, writing data, or erasing data at memory devices 130, among other such operations. Memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. Memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0025] Memory sub-system controller 115 can be a processing device, such as including one or more processors (processors 117), configured to execute instructions stored in local memory 119. In the illustrated example, local memory 119 of memory sub-system controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control operation of memory sub-system 110, including handling communications between memory sub-system 110 and host system 120.

[0026] In some embodiments, local memory 119 can include memory registers that store memory pointers, fetched data, and the like. Local memory 119 can also include read-only memory (ROM) for storing microcode. Although Figure 1 The example memory sub-system 110 in FIG. 1 has been illustrated as including memory sub-system controller 115, but in another embodiment of the disclosure, memory sub-system 110 does not include memory sub-system controller 115 and instead can rely on external control (e.g., by an external host, or provided by a processor or controller separate from the memory sub-system).

[0027] Generally, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to effectuate desired accesses to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access memory devices 130, as well as convert responses associated with memory devices 130 into information for host system 120.

[0028] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive addresses from memory sub-system controller 115 and decode the addresses to access memory devices 130.

[0029] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory sub-system 110 is a managed memory device that includes raw memory devices 130 with control logic (e.g., local media controller 135) on-die and a controller for media management (e.g., memory sub-system controller 115) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] In one embodiment, the memory device 130 includes a plane selection circuit 150 that can selectively couple any of a first number of memory planes in the memory device 130 to any of a second number of independent plane driver circuits in the memory device 130. In one embodiment, the local media controller 135 receives a first read command associated with the memory device 130, e.g., from the memory sub-system controller 115, the host system 120, or some other component, and identifies a first plane of a memory array of the memory device 130 to which the first read command is directed. The local media controller 135 configures the plane selection circuit 150 to couple a first independent plane driver of the memory device 130 to the first plane and cause the first independent plane driver to perform a first read operation on the first plane corresponding to the first read command. If the local media controller 135 receives a second read command while still performing the first read operation, the local media controller 135 can determine whether the second read command is directed to the first plane (i.e., the same plane as the currently active first read operation). If the second read command is directed to the first plane, the local media controller can maintain an indication of the second read command in a queue corresponding to the first plane until the first read operation completes, and then cause the first independent plane driver to perform a second read operation on the first plane corresponding to the second read command.

[0031] However, if the second read command is not directed to the first plane, the local media controller 135 can identify a second plane of the first number of planes to which the second read command is directed. The local media controller 135 can configure the plane selection circuit 150 to couple a second independent plane driver to the second plane and cause the second independent plane driver to perform a second read operation on the second plane corresponding to the second read command. The second read operation can be performed concurrently with (i.e., at least partially overlapping in time with) the first read operation. The second plane can be any of the first number of planes in the memory device 130 without any restriction based on plane group. In one embodiment, the local media controller 135 tracks the status of the first number of planes of the memory array (i.e., whether each plane is currently being accessed or available) and the second number of independent plane driver circuits (i.e., whether each independent plane driver circuit is currently performing a memory access operation), and routes / schedules memory access operations in the memory device 130 based on those statuses. Further details regarding the operation of the local media controller 135 and the plane selection circuit 150 are described below.

[0032] In some embodiments, the memory sub-system controller 115 includes at least a portion of the plane selection circuit 150. For example, the memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in local memory 119 to perform the operations described herein. In other embodiments, the memory device 130 includes a local media controller 135 and at least a portion of the plane selection circuit 150, and is configured to perform the functions described herein. In such embodiments, the plane selection circuit 150 can be implemented using hardware or as firmware stored on the memory device 130, executed by control logic (e.g., the local media controller 135) to perform the operations related to independent and parallel plane accesses described herein.

[0033] Figure 2 A block diagram of a multi-plane memory device 130 configured for independent and parallel plane accesses according to some embodiments of the present disclosure is illustrated. The memory device 130 includes a memory array 270 that is partitioned into memory planes 272(0) through 272(3) each including a respective number of memory cells. The multi-plane memory device 130 can further include a local media controller 135 that includes power control circuitry and access control circuitry for concurrently performing memory access operations to different memory planes 272(0) through 272(3). The memory cells can be non-volatile memory cells (e.g., NAND flash memory cells), or generally can be any type of memory cell.

[0034] The memory planes 272(0) through 272(3) can each be partitioned into data blocks, where two or more different, relative data blocks from the memory planes 272(0) through 272(3) can be concurrently accessed during a memory access operation. For example, two or more of data block 282 of memory plane 272(0), data block 283 of memory plane 272(1), data block 284 of memory plane 272(2), and data block 285 of memory plane 272(3) can each be concurrently accessed during a memory access operation.

[0035] Each of the memory planes 272(0) through 272(3) can be coupled to a respective page buffer 276(0) through 276(3). Each page buffer 276(0) through 276(3) can be configured to provide data to or receive data from the respective memory plane 272(0) through 272(3). The page buffers 276(0) through 276(3) can be controlled by the local media controller 135. Data received from the respective memory plane 272(0) through 272(3) can be respectively locked at the page buffers 276(0) through 276(3) and retrieved by the local media controller 135 and provided to the memory sub-system controller 115 via the NVMe interface.

[0036] Each of the memory planes 272(0) through 272(3) can be further coupled to one of a plurality of independent plane driver circuits 274(0) through 274(1), such as an access line driver circuit. The driver circuits 274(0) through 274(1) can be configured to condition pages of a respective block of one of the memory planes 272(0) through 272(3) for memory access operations, such as programming data (i.e., writing data), reading data, or erasing data. Each of the driver circuits 274(0) through 274(1) can be coupled to a global access line associated with any of the memory planes 272(0) through 272(3) in the memory array 270 via the plane selection circuit 150. During a memory access operation associated with a page within a block, the plane selection circuit 150 can selectively couple each of the global access lines to a respective local access line within a block of a plane. The driver circuits 274(0) through 274(1) can be controlled based on signals from the local media controller 135. Each of the driver circuits 274(0) through 274(1) can include or be coupled to a respective power circuit and can provide a voltage to a respective access line based on a voltage provided by the respective power circuit. The voltage provided by the power circuit can be based on a signal received from the local media controller 135. In Figure 2 In the embodiment illustrated in FIG. 1, the memory device 130 includes four planes 272(0) through 272(3) and two independent plane driver circuits 274(0) through 274(1). It should be appreciated that in other embodiments, the memory device 130 can include some other number of planes and some other number of independent plane driver circuits, where the number of independent plane driver circuits is generally less than the number of planes.

[0037] The local media controller 135 can control the driver circuits 274(0)-274(1) and page buffers 276(0)-276(3) to concurrently perform memory access operations associated with each of a set of memory command and address pairs (e.g., received from the memory sub-system controller 115). For example, the local media controller 135 can control the driver circuits 274(0)-274(1) and page buffers 376(0)-376(3) to perform concurrent memory access operations. The local media controller 135 can include a power control circuit that configures two or more of the driver circuits 274(0)-274(1) in parallel to perform concurrent memory access operations, and an access control circuit that is configured to control two or more of the page buffers 276(0)-276(3) to sense and latch data from, or program data to, the respective memory planes 272(0)-272(3) to perform concurrent memory access operations.

[0038] In operation, the local media controller 135 can receive a set of memory command and address pairs via the NVMe bus, where each pair arrives in parallel or serially. In some examples, the set of memory command and address pairs can each be associated with a different respective memory plane 272(0)-272(3) of the memory array 270. The local media controller 135 can be configured to perform concurrent memory access operations (e.g., read operations or program operations) on two or more different memory planes 272(0)-272(3) of the memory array 270 in response to the set of memory command and address pairs. For example, a power control circuit of the local media controller 135 can serially configure driver circuits 274(0)-274(1) for two or more memory planes 272(0)-272(3) associated with the set of memory command and address pairs for concurrent memory access operations based on respective page types (e.g., UP, MP, LP, XP, SLC / MLC / TLC / QLC pages). After the access line driver circuits 274(0)-274(1) have been configured, an access control circuit of the local media controller 135 can concurrently control page buffers 276(0)-276(3) to access respective pages (e.g., retrieve data or write data) of each of the two or more memory planes 272(0)-272(3) associated with the set of memory command and address pairs during the concurrent memory access operations. For example, the access control circuit can concurrently (e.g., in parallel and / or simultaneously) control the page buffers 276(0)-276(3) to charge / discharge bit lines, sense data from, and / or latch data from the two or more memory planes 272(0)-272(3).

[0039] Based on signals received from the local media controller 135, driver circuits 274(0) through 274(1) coupled to memory planes 272(0) through 272(3) associated with the set of memory command and address command pairs can select memory or memory cell blocks from the associated memory planes 272(0) through 272(3) for memory operations (e.g., read operations, program operations, and / or erase operations). The driver circuits 274(0) through 274(1) can drive different respective global access lines associated with the respective memory planes 272(0) through 272(3). As an example, driver circuit 274(0) can drive a first voltage on a first global access line associated with memory plane 272(0), driver circuit 274(1) can drive a second voltage on a third global access line associated with memory plane 272(1), driver circuit 274(2) can drive a third voltage on a seventh global access line associated with memory plane 272(2), and so on, and other voltages can be driven on each of the remaining global access lines. In some examples, a pass voltage can be provided on all access lines except for the access lines associated with the pages of the memory planes 272(0) through 272(3) to be accessed. The local media controller 135, driver circuits 274(0) through 274(1) can allow concurrent access to different respective pages and page buffers 276(0) through 276(3) within different respective memory cell blocks. For example, a first page of a first block of a first memory plane can be concurrently accessed with a second page of a second block of a second memory plane, regardless of page type.

[0040] The page buffers 276(0) through 276(3) can provide data to or receive data from the local media controller 135 during memory access operations in response to signals from the local media controller 135 and the respective memory planes 272(0) through 272(3). The local media controller 135 can provide the received data to the memory sub-system controller 115.

[0041] It will be appreciated that the memory device 130 can include more or less than four memory planes, driver circuits, and page buffers. It will also be appreciated that the respective global access lines can include 8, 16, 32, 64, 128, etc. global access lines. The plane selection circuit 150 enables the local media controller 135 and the driver circuits 274(0) through 274(1) to concurrently access different respective pages within different respective blocks of any two of the memory planes 272(0) through 272(3). In one embodiment, the plane selection circuit 150 includes a plurality of bidirectional multiplexer circuits 252(0) through 252(3), each corresponding to one of the memory planes 272(0) through 272(3). Each of the bidirectional multiplexer circuits 252(0) through 252(3) can be an N: 1 multiplexer, where N represents the number of independent plane driver circuits 274(0) through 274(1) in the memory device 130. The bidirectional multiplexer circuits 252(0) through 252(3) are controlled by control signals received from the local media controller 135 to selectively couple any of the independent plane driver circuits 274(0) through 274(1) to a corresponding one of the memory planes 272(0) through 272(3). For example, depending on the control signals, the multiplexer circuit 252(0) can couple any of the independent plane driver circuits 274(0) through 274(1) to the memory plane 272(0). Similarly, depending on the control signals, the multiplexer circuit 252(1) can couple any of the independent plane driver circuits 274(0) through 274(1) to the memory plane 272(1), the multiplexer circuit 252(2) can couple any of the independent plane driver circuits 274(0) through 274(1) to the memory plane 272(2), or the multiplexer circuit 252(3) can couple any of the independent plane driver circuits 274(0) through 274(1) to the memory plane 272(3). Thus, the plane selection circuit 150 can concurrently couple two independent plane driver circuits 274(0) through 274(1) to any two of the memory planes 272(0) through 272(3), allowing the local media controller 135 to perform concurrent memory access operations. Any received read command can include an associated address of a plane / block / page of the memory device 130 to be read, so the location of the data is fixed. However, the data from the fixed location can be read using any of the independent plane driver circuits 274(0) through 274(1), depending on which plane driver circuit is available.

[0042] Figure 3A flow diagram illustrating an example method of independent parallel plane access in a multi-plane memory device in a memory sub-system in accordance with some embodiments of the present disclosure is described. The method 300 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by the local media controller 135 and the plane selection circuit 150 of the memory device 130. Figure 1 Although shown in a particular sequence or order, unless otherwise specified, steps can be modified, supplemented, or re-ordered. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0043] At operation 305, a memory access command is received. For example, processing logic (e.g., the local media controller 135) can receive a first memory access command directed to a memory device (e.g., the memory device 130). In one embodiment, the first memory access command is a read command, which can be received from a controller (e.g., the memory sub-system controller 115), some other component of the memory sub-system 110, or from an external component (e.g., the host system 120). In one embodiment, the read command specifies at least one of a logical or physical address associated with data to be read from the memory device 130.

[0044] At operation 310, a corresponding plane of the memory device is identified. For example, processing logic can identify a first plane of a first number of planes (e.g., memory planes 272(0) through 272(3)) of a memory array 270 of the memory device to which the read command is directed. In one embodiment, the processing logic identifies the first plane as one of the memory planes 272(0) through 272(3) that stores a data block corresponding to the logical or physical address included in the received read command. For example, the local media controller 135 can maintain a mapping of memory addresses to each of the memory planes 272(0) through 272(3). In one embodiment, the first memory plane can be any one of the memory planes 272(0) through 272(3), and is not necessarily limited to memory plane 272(0).

[0045] At operation 315, the plane selection circuit is configured. For example, the processing logic can configure the plane selection circuit 150 to couple a first independent plane driver (e.g., driver 274(0)) of a second number of independent plane drivers of the memory device 130 to the first plane identified at operation 310. In one embodiment, the memory device includes independent plane drivers 274(0) through 274(1) configured to currently provide signals used to access blocks of memory planes 272(0) through 272(3) during memory access operations. In one embodiment, the plane selection circuit 150 includes a first number of multiplexer circuits 252(0) through 252(3), each corresponding to one of the first number of planes 272(0) through 272(3). Each multiplexer circuit 252(0) through 252(3) is configured to route signals from any of the independent plane driver circuits 274(0) through 274(1) to a corresponding one of the memory planes 272(0) through 272(3) based on control signals received from control logic (e.g., local media controller 135). Thus, to configure the plane selection circuit 150, the processing logic can send a control signal to one of the multiplexer circuits 252(0) through 252(3) corresponding to the first plane identified at operation 310 to cause the multiplexer circuit to couple a selected one of the independent plane drivers 274(0) through 274(1) to the identified plane. In one embodiment, the first independent plane driver can be any of the drivers 274(0) through 274(1) and is not necessarily limited to driver 274(0). In one embodiment, any of the available drivers 274(0) through 274(1) can be selected as the first driver independent plane driver. To identify available drivers, the processing logic can track the status (e.g., ready / busy status) of the drivers 274(0) through 274(1) and the memory planes 272(0) through 272(3) and can route memory access operations based on those statuses. If more than one of the drivers 274(0) through 274(1) is available, the processing logic can select a default driver to use as the first driver or can select a driver to use as the first driver according to some selection algorithm (e.g., round robin).

[0046] At operation 320, a memory access operation is performed. For example, the processing logic can cause the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane. In one embodiment, the processing logic can apply a signal to a selected one of the independent plane drivers 274(0) through 274(1) to cause the driver to provide a signal to access a block of the identified one of the planes 272(0) through 272(3) that corresponds to an address included in the received memory access command. The signal reads the charge level stored at the memory cells of the accessed block, which can be interpreted as a data value. The processing logic can return those data values to the component that issued the memory access command as a response.

[0047] At operation 325, a memory access command is received. For example, the processing logic can receive a second memory access command directed to the memory device 130. In one embodiment, the second memory access command is a read command, which can be received from a controller (e.g., the memory sub-system controller 115), some other component of the memory sub-system 110, or from an external component (e.g., the host system 120). In one embodiment, the read command specifies at least one of a logical or physical address associated with data to be read from the memory device 130. In one embodiment, the second memory access command is received concurrently with the first memory access command, such that the second memory access command is received prior to the first read operation being performed or while the first read operation is still being performed at operation 320.

[0048] At operation 330, a determination is made. For example, the processing logic can determine whether the second read command is directed to the first plane (i.e., the same plane to which the first read command is directed). If the second read command is not directed to the first plane (i.e., the second read command is directed to a different one of the planes 272(0) through 272(3)), then the processing logic proceeds to operation 335. However, if the second read command is directed to the first plane, then the processing logic proceeds to operation 345.

[0049] At operation 335, the memory access command is queued. For example, the processing logic can maintain an indication of the second read command in a queue corresponding to the first plane until the first read operation is completed. In one embodiment, each of the planes 272(0) through 272(3) has an associated queue (e.g., buffer, FIFO, etc.) in which commands / operations can be stored. Since only one operation can be performed on a given plane at a time, any additional operations can be stored in the associated queue until the previous command has been completed.

[0050] At operation 340, a memory access operation is performed. For example, the processing logic can cause the first independent plane driver to perform a second read operation corresponding to the second read command on the first plane. In one embodiment, the processing logic can apply a signal to a selected one of the independent plane drivers 274(0) through 274(1) to cause the driver to provide a signal to access a block of the identified one of the planes 272(0) through 272(3) that corresponds to an address included in the received memory access command. The signal reads the charge levels stored at the memory cells of the accessed block, which can be interpreted as data values. The processing logic can return those data values to the component that issued the memory access command as a response.

[0051] At operation 345, a corresponding plane of the memory device is identified. For example, the processing logic can identify a second one of the first number of planes (e.g., memory planes 272(0) through 272(3)) to which the read command is directed. In one embodiment, the processing logic identifies the second plane as one of the memory planes 272(0) through 272(3) that stores a data block corresponding to a logical or physical address included in the received read command. For example, the local media controller 135 can maintain a mapping of memory addresses to each of the memory planes 272(0) through 272(3). In one embodiment, the second memory plane can be any of the memory planes 272(0) through 272(3), and is not necessarily limited to memory plane 272(1).

[0052] At operation 350, the plane selection circuit is configured. For example, the processing logic can configure the plane selection circuit 150 to couple a second independent plane driver (e.g., driver 274(1)) to the second plane identified at operation 345. To configure the plane selection circuit 150, the processing logic can send a control signal to one of the multiplexer circuits 252(0) through 252(3) corresponding to the second plane identified at operation 345 to cause the multiplexer circuit to couple a selected one of the independent plane drivers 274(0) through 274(1) to the identified plane. In one embodiment, the second independent plane driver can be any of the drivers 274(0) through 274(1), and is not necessarily limited to driver 274(1). In one embodiment, any of the drivers 274(0) through 274(1) that is available can be selected as the second driver independent plane driver. For example, if driver 274(0) is currently in use, then the processing logic can select driver 274(1).

[0053] In operation 355, a memory access operation is performed. For example, the processing logic may cause a second independent plane driver to perform a second read operation on a second plane corresponding to a second read command. In one embodiment, the processing logic may apply a signal to a selected one of the independent plane drivers 274(0) to 274(1) such that the driver provides a signal for accessing a block in planes 272(0) to 272(3) corresponding to an address contained in the received memory access command. The signal reads the charge level stored at the memory cell of the accessed block, which can be interpreted as a data value. The processing logic may return those data values ​​to the component that issued the memory access command in response.

[0054] Figure 4 An example machine illustrating computer system 400 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 400 may correspond to a host system (e.g., Figure 1 The host system 120 includes a memory subsystem coupled to, or utilizing, a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the local media controller 135). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0055] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be performed by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as encompassing any collection of machines that individually or jointly execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0056] The example computer system 400 includes a processing device 402 that communicates with each other via a bus 430, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418.

[0057] Processing device 402 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 402 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. The computer system 400 can further include a network interface device 408 to communicate over the network 420.

[0058] The data storage system 418 can include a machine-readable storage medium 424 (also known as a computer-readable medium, e.g., a non-transitory computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methodologies or functions described herein. The instructions 426 can also reside, completely or at least partially, within the main memory 404 and / or within the processing device 402 during execution thereof by the computer system 400, the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable storage medium 424, data storage system 418, and / or main memory 404 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0059] In one embodiment, the instructions 426 include instructions to implement functionality corresponding to the local media controller 135 of FIG. 1. While the machine-readable storage medium 424 is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media. Figure 1

[0060] ​​Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self- consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0061] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0062] The disclosure also relates to an apparatus for performing the operations presented herein. This apparatus can be specially constructed for the required purposes, or it can comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as follows. In addition, the disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0064] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.).

[0065] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples thereof. It is evident, however, that various modifications can be made thereto without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory device comprising: a memory array comprising a first number of planes; a second number of independent plane driver circuits, wherein the second number is less than the first number; plane selection circuitry to couple the second number of independent plane driver circuits to the first number of planes of the memory array; and control logic operatively coupled with the memory array, the second number of independent plane driver circuits, and the plane selection circuitry, the control logic to perform operations comprising: receiving a first read command and a second read command; identifying, among the first number of planes, a first plane to which the first read command is directed and a second plane to which the second read command is directed; configuring the plane selection circuitry to couple a first independent plane driver of the second number of independent plane drivers to the first plane and a second independent plane driver of the second number of independent plane drivers to the second plane; and concurrently causing the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane and causing the second independent plane driver to perform a second read operation corresponding to the second read command.

2. The memory device of claim 1, wherein the second number of independent plane driver circuits are configured to concurrently provide signals to access blocks of the first number of planes during memory access operations.

3. The memory device of claim 1, wherein the plane selection circuitry comprises a first number of multiplexer circuits, each multiplexer circuit corresponding to one of the first number of planes, and wherein each of the first number of multiplexer circuits is configured to route a signal from any of the second number of independent plane driver circuits to the corresponding one of the first number of planes based on a control signal received from the control logic.

4. The memory device of claim 1, wherein the control logic is to perform further operations comprising: receiving the second read command while still performing the first read operation; and determining whether the second read command is directed to the first plane.

5. The memory device of claim 4, wherein the control logic is to perform further operations comprising: in response to determining that the second read command is directed to the first plane, maintaining an indication of the second read command in a queue corresponding to the first plane until the first read operation is complete; and causing the first independent plane driver to perform a second read operation corresponding to the second read command on the first plane.

6. The memory device of claim 4, wherein the control logic is to perform further operations comprising: in response to determining that the second read command is not directed to the first plane, identifying, among the first number of planes, the second plane to which the second read command is directed; ​ ​ configuring the plane selection circuitry to couple the second independent plane driver of the second number of independent plane drivers to the second plane; and causing the second independent plane driver to perform the second read operation on the second plane corresponding to the second read command.

7. The memory device of claim 1, wherein the control logic is to perform further operations, the operations comprising: tracking a state of the first number of planes of the memory array and the second number of independent plane driver circuits; and routing memory access operations in the memory device based on the state.

8. A method comprising: receiving a first read command and a second read command associated with a memory device; identifying, among a first number of planes of a memory array of the memory device, a first plane to which the first read command is directed and a second plane to which the second read command is directed; configuring plane selection circuitry to couple a first independent plane driver of a second number of independent plane drivers of the memory device to the first plane and a second independent plane driver of the second number of independent plane drivers to the second plane; and concurrently causing the first independent plane driver to perform a first read operation on the first plane corresponding to the first read command and the second independent plane driver to perform a second read operation corresponding to the second read command.

9. The method of claim 8, wherein the second number of independent plane driver circuits are configured to concurrently provide signals to access blocks of the first number of planes during memory access operations.

10. The method of claim 8, wherein the plane selection circuitry comprises a first number of multiplexer circuits, each multiplexer circuit corresponding to one of the first number of planes, and wherein each of the first number of multiplexer circuits is configured to route a signal from any of the second number of independent plane driver circuits to the corresponding one of the first number of planes based on a control signal received from control logic.

11. The method of claim 8, further comprising: receiving the second read command while still performing the first read operation; and determining whether the second read command is directed to the first plane.

12. The method of claim 11, further comprising: in response to determining that the second read command is directed to the first plane, maintaining an indication of the second read command in a queue corresponding to the first plane until the first read operation is complete; and causing the first independent plane driver to perform a second read operation on the first plane corresponding to the second read command.

13. The method of claim 11, further comprising: in response to determining that the second read command is not directed to the first plane, identifying the second plane to which the second read command is directed among the first number of planes; the second number of independent plane drivers to the second plane; and causing the second independent plane driver to perform the second read operation on the second plane corresponding to the second read command.

14. The method of claim 8, further comprising: tracking a state of the first number of planes of the memory array and the second number of independent plane driver circuits; and routing memory access operations in the memory device based on the state.

15. A memory device, comprising: a memory array comprising a first number of planes; a second number of independent plane driver circuits, wherein the second number is less than the first number; plane selection circuitry to couple any of the second number of independent plane driver circuits to any of the first number of planes of the memory array; and control logic operatively coupled with the memory array, the second number of independent plane driver circuits, and the plane selection circuitry, the control logic to cause the second number of independent plane driver circuits to concurrently perform first and second memory access operations on at least two of the first number of planes.

16. The memory device of claim 15, wherein the second number of independent plane driver circuits are configured to concurrently provide signals to access blocks of the first number of planes during the memory access operations.

17. The memory device of claim 15, wherein the plane selection circuitry comprises a first number of multiplexer circuits, each multiplexer circuit corresponding to one of the first number of planes.

18. The memory device of claim 17, wherein each of the first number of multiplexer circuits is configured to route a signal from any of the second number of independent plane driver circuits to the corresponding one of the first number of planes based on a control signal received from the control logic.

19. The memory device of claim 15, wherein the first and second memory access operations comprise read operations.

20. The memory device of claim 15, wherein the control logic is further to: track a state of the first number of planes of the memory array and the second number of independent plane driver circuits; and route memory access operations in the memory device based on the state.

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