A regression neural network used to identify the threshold voltage during reads in a flash memory device.

Abstract

A method and apparatus for reading from a flash memory device are disclosed. A regressive neural network (RNN) inference model is stored on a flash memory controller. The RNN inference model is configured to identify at least one threshold voltage offset read error (TVS-RE) curve, which identifies the number of errors dependent on a threshold voltage offset compensation (TVSO) value. Operation of the flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic value. The inputs to the neural network operation include the usage characteristic value. The minimum value corresponding to the TVS-RE curve is used to identify the TVSO value. A read from the flash memory device is performed using a threshold voltage offset read at the TVSO value.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 057,278, filed July 27, 2020, and U.S. Non-Provisional Patent Application Serial No. 17 / 089,891, filed November 5, 2020, the contents of which are incorporated herein by reference in their entirety. Background Technology

[0003] Characterizing flash memory devices is an expensive and time-consuming process. Furthermore, the characteristics of flash memory devices change over their lifetime, making accurate characterization difficult.

[0004] Standard read instructions (e.g., read or read page instructions) perform reads of memory cells at a default threshold voltage within each threshold voltage region required to define the bits of the memory cell. Single-level cell (SLC) flash memory devices store unit information in each cell and require reads only within a single threshold voltage region (a region extending between the center of a voltage distribution of 1s and the center of a voltage distribution of 0s) to identify the bit value (regardless of whether the cell stores 1 or 0). Multi-level cell (MLC) flash memory devices store two bits of information per cell, three-level cell (TLC) flash memory devices store three bits of information per cell, and four-level cell (QLC) flash memory devices store four bits of information per cell. MLC, TLC, and QLC flash memory devices require reads at more than one threshold voltage to identify the value of a specific bit.

[0005] Some solid-state drives (SSDs) use threshold voltage offset reads to read flash memory devices to achieve the low levels of uncorrectable bit error rate (UBER) required for client and enterprise SSDs. A threshold voltage offset read is performed by sending a threshold voltage offset read command to the flash memory device to be read. One or more threshold-voltage-offset compensation (TVSO) values ​​are sent along with the threshold voltage offset read command. The TVSO value indicates the amount of compensation between the threshold voltage used to perform the read and the corresponding default threshold voltage specified by the flash memory device manufacturer. Threshold voltage offset read commands for MLC, TLC, and QLC flash memory devices include two or more TVSO values, one of which identifies each threshold voltage region required to identify the specific bit being read.

[0006] For systems that use threshold voltage offset read commands to read flash memory devices, it is necessary to identify the TVSO value used in each read of the flash memory device in order to keep the UBER within an acceptable level during the lifespan of the SSD. Summary of the Invention

[0007] A method for reading a flash memory device is disclosed, comprising storing a regressive neural network (RNN) inference model on a flash controller coupled to the flash memory device, the RNN inference model being configured to identify at least one threshold voltage offset read error (TVS-RE) curve, each TVS-RE curve identifying an error number dependent on a TVSO value. The operation of the flash memory device is monitored to identify one or more usage characteristic values ​​of the flash memory device. Usage characteristic values ​​are values ​​indicating the age and / or physical degradation of the flash memory device over time and values ​​indicating current transient characteristics of the flash memory device or a specific structure (e.g., word lines or blocks) of the flash memory device. In one example, the number of program and erase cycles (P / E cycles) of the flash memory device or the number of P / E cycles for a specific structure (e.g., word lines or blocks) of the flash memory device is used as a usage characteristic value indicating the age and / or physical degradation of the flash memory device over time.

[0008] The stored RNN inference model is executed as a neural network to generate a TVS-RE curve corresponding to the identified usage characteristic values. The inputs to the neural network operation include one or more identified usage characteristic values ​​and one or more values ​​identifying the page to be read. The minimum value of the TVSO corresponding to the generated TVS-RE curve is then identified. A read of the flash memory device is performed using a threshold voltage offset read at the identified TVSO value.

[0009] An SSD is disclosed, comprising a flash memory controller and a plurality of flash memory devices. The flash memory controller includes write circuitry, read circuitry configured to perform reads of the flash memory devices using a threshold voltage offset read operation, and a decoder configured to decode the results of the reads. The flash memory controller includes state circuitry for monitoring the operation of the flash memory devices to identify one or more usage characteristic values ​​of the flash memory devices and a data storage device configured to store an RNN inference model. The RNN inference model is configured to identify at least one TVS-RE curve. Each TVS-RE curve identification depends on the number of errors in the TVSO value.

[0010] The flash memory controller further includes a neural processing module coupled to the data storage device. The neural processing module is configured to perform neural network operations on the stored RNN inference model to generate TVS-RE curves corresponding to the identified usage characteristic values. The inputs for the neural network operations include one or more identified usage characteristic values ​​and one or more values ​​identifying the page to be read. The value identifying the page to be read can be a value indicating one or more of the word lines, blocks, planes, and devices to be read (i.e., indicating the physical structure of the flash memory device to be read).

[0011] The flash memory controller includes a minimum functional module coupled to the neural processing module. This minimum functional module is configured to determine the minimum value of the generated TVS-RE curve and identify the TVSO value corresponding to the determined minimum value. Threshold voltage offset read operations use the identified TVSO value to perform reads.

[0012] The method and apparatus of this invention model multiple factors affecting UBER and generate TVS-RE curves on the flash memory controller. These TVS-RE curves accurately reflect the physical characteristics of the location to be read, the structural characteristics of the location (e.g., word lines and blocks to be read), the current age / physical degradation of the location (e.g., number of P / E cycles), and the current transient characteristics of the location (e.g., closed-block read interference and closed-block retention time). Because the generated TVS-RE curve accurately represents the factors affecting UBER, the TVSO value generated corresponding to the minimum value of the TVS-RE curve will be the appropriate TVSO value for performing the read (corresponding to the TVSO value that provides the minimum number of errors during device characterization). Using an appropriate TVSO value to perform the read results in a reduction in the number of read errors at the flash memory controller. During the lifespan of the SSD, the reduction in the number of read errors by the method and apparatus of this invention effectively maintains the UBER at an acceptable level. Attached Figure Description

[0013] This document includes accompanying drawings to provide a further understanding of the invention, and the drawings are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0014] Figure 1 This is a block diagram illustrating an SSD according to one embodiment of the present invention.

[0015] Figure 2 This is a diagram illustrating a flash controller and an exemplary NAND flash memory device according to an embodiment of the present invention, and illustrating the communication between the flash controller and the flash memory device.

[0016] Figure 3 This is a block diagram illustrating a method for reading a flash memory device according to an embodiment of the present invention.

[0017] Figure 4A This is a diagram illustrating an RNN inference model according to an embodiment of the present invention, which includes multiple programming and erasing cycles as inputs and can be used throughout the lifetime of a flash memory device.

[0018] Figure 4BThis is a diagram illustrating an RNN inference model according to one embodiment of the present invention, wherein the output neurons include output neurons for each TVSO value.

[0019] Figure 5 This is a graph illustrating the time cycles during the lifespan of an exemplary flash memory device according to an embodiment of the present invention.

[0020] Figure 6 This is a graph illustrating an RNN inference model for a specific time period during the lifespan of a flash memory device according to an embodiment of the present invention.

[0021] Figure 7 This is a diagram illustrating a test and model generation system according to one embodiment of the present invention.

[0022] Figure 8 This is a block diagram illustrating a method for generating a neural network model according to one embodiment of the present invention.

[0023] Figure 9 It is a graph showing the number of errors on the horizontal axis according to one embodiment of the invention, and the threshold voltage offset compensation on the horizontal axis for reading errors in an exemplary flash memory device.

[0024] Figure 10 This is a graph illustrating an exemplary threshold voltage offset readout error curve generated from an exemplary threshold voltage offset readout training dataset according to an embodiment of the present invention.

[0025] Figure 11 This is a graph illustrating an exemplary smooth threshold voltage offset read error curve generated from an exemplary smooth threshold voltage offset read training dataset according to an embodiment of the present invention.

[0026] Figures 12A to 12J This is a block diagram illustrating an exemplary RNN inference model according to one embodiment of the present invention. Detailed Implementation

[0027] Figure 1The image shows an SSD 10, which includes a flash controller 3 coupled to a plurality of flash memory devices 9 for storing data. In this embodiment, the flash memory devices 9 are NAND devices, and the SSD 10 includes one or more circuit boards on which a host connector socket 14, the flash controller 3, and the flash memory devices 9 are attached. The SSD 10 may also include one or more memory devices 13 (such as dynamic random access memory (DRAM)), which may be separate integrated circuit devices attached to the circuit board on which the flash controller 3 is mounted and directly electrically connected.

[0028] The flash memory controller 3 is configured to receive read and write instructions from a host computer via the host connector socket 14, and to perform programming, erasing, and read operations on the memory cells of the flash memory device 9 to fulfill the instructions from the host computer. For example, when a write instruction is received from the host via the host connector socket 14, the flash memory controller 3 is operable to program codewords into one or more flash memory devices 9 to store data in the SSD 10 by performing programming operations (and, when necessary, erasing operations).

[0029] The flash memory controller 3 includes a write circuit 8, a read circuit 6, a decoder 7, a state circuit 5, and a data storage device 4. The flash memory controller 3 also includes a neural processing module 11 connected to the data storage device 4 and a minimum functional module 2 connected to the neural processing module 11. The flash memory controller 3 may optionally include one or more tables 15, 15a connected to the minimum functional module 2, optionally included within the data storage device 4. The read circuit 6 is connected to the decoder 7, the state circuit 5, the minimum functional module 2, the data storage device 4, and the neural processing module 11. The state circuit 5 is connected to the write circuit 8, the minimum functional module 2, the neural processing module 11, and the data storage device 4. One or more regressive neural network (RNN) inference models 12 are included within the data storage device 4.

[0030] Each flash memory device 9 may be a packaged semiconductor die or "chip" connected to the flash memory controller 3 via a conductive path that connects each flash memory device 9 to the flash memory controller 3 for instructions, data, and other information. Figure 2In the illustrated embodiment, each flash memory device 9 (e.g., a NAND device) includes a register 31, a microcontroller 32, and a memory array 33, and is coupled to the flash controller 3 via a chip enable signal line (CE#), a command latch enable signal line (CLE), a read enable signal line (RE#), an address latch enable signal line (ALE), a write enable signal line (WE#), a read / busy signal line (R / B), and input / output signal lines (DQ). Upon receiving a write instruction from a host computer, the write circuit 8 is operable to encode the received data into a codeword, which is sent to the register 31 along with the corresponding programming instruction. The microcontroller 32 is operable to execute the requested write instruction and retrieve the codeword from the register 31 and store the codeword in the memory array 33 via cells of the programmable memory array 33 (e.g., as logical pages).

[0031] In one example, each flash memory device 9 comprises NAND memory cells organized into blocks and pages, wherein each block consists of NAND strings sharing the same word line. Each logical page consists of cells belonging to the same word line. The number of logical pages within each logical block is typically a plurality of 16 (e.g., 64, 128). In this embodiment, a logical page is the smallest addressable unit for reading and writing to the NAND memory cells of each flash memory device 9, and a logical block is the smallest erasable unit. However, it should be understood that in embodiments of the invention, programming smaller than a whole logical page may be possible, depending on the structure of the NAND array. Although the flash memory device 9 is shown as a NAND device, it should be understood that the flash memory device 9 can be any type of memory storage device that uses a threshold voltage to read the memory cells of the flash memory device 9.

[0032] In response to receiving a read command from the host computer, the read circuit 6 is configured to perform a read operation on the corresponding flash memory device 9 using a threshold voltage offset read operation. More specifically, the read circuit 6 is operable to send a threshold voltage offset read command 34 to the flash memory device 9. The microcontroller 32 reads the corresponding memory array 33 in response to the threshold voltage offset read command and outputs the read result at register 31. The read result is sent to the decoder 7, which is operable to decode the read result to obtain the stored codeword.

[0033] The flash memory device 9 can be an SLC, MLC, TLC, or QLC NAND device. In this embodiment, the flash memory device 9 is capable of performing a wide range of threshold voltage offset reads, including reads specified by the entire digital compensation value (such as -n...-2, -1, 0, +1, +2, ...n) without limitation.

[0034] The erase blocks of flash memory device 9 can be referred to as "free blocks". When data is programmed into an erased block, the block is called an "open block" until all pages of the block have been programmed. Once all pages of a block have been programmed, the block is called a "closed block" until it is erased again.

[0035] Figure 3 A method 100 for reading a flash memory device is illustrated. In the following discussion, reference is made to... Figure 1 Method 100 is discussed in relation to the flash memory controller 3. Method 100 includes generating (101) an RNN inference model. The RNN inference model is configured to identify at least one TVS-RE curve, wherein each TVS-RE curve is identified based on the number of errors depending on the TVSO value. Preferably, the generation of the RNN inference model (step 101) is performed before the sale and use of the SSD 10 and before the flash memory controller 3 is delivered to the customer for manufacturing the SSD 10. Depending on the computing power of the flash memory controller, the generation of the RNN inference model can be performed on the SSD 10 or using a testing and model generation system (such as... Figure 7 The test and model generation system 70 shown is used to perform the operation, as will be discussed in more detail below, and the data is stored in the data storage device 4 of the SSD 10. When the generation of the RNN inference model is performed using the test and model generation system 70, it is performed exclusively on the test and model generation system 70 and not on the SSD 10.

[0036] The RNN inference model is stored (102) on a flash controller coupled to a flash memory device or on a memory device directly coupled to the flash controller. In one example, one or more RNN inference models 12 are stored in a data storage device 4 of the flash controller 3, preferably before the flash controller 3 is delivered to a customer. The RNN inference model 12 may also be stored in a memory device 13. Each RNN inference model 12 is configured to identify at least one TVS-RE curve, wherein each TVS-RE curve identification depends on the number of errors of the TVSO value.

[0037] The operation of the flash memory device (103) is monitored to identify one or more usage characteristic values ​​of the flash memory device. In one example, the state circuit 5 is operable to monitor the operation of each flash memory device 9 to identify one or more usage characteristic values ​​of the flash memory device 9. The determined usage characteristic values ​​may be stored in a register of the flash controller 3, in a data storage device 4 in the flash memory device 9 or the memory device 13. As used herein, the term "usage characteristic value" is a value determined during the use of a flash memory device that may affect the threshold voltage distribution, such as a value indicating the current age / physical degradation of the location to be read (e.g., the number of P / E cycles or the bit error rate (BER)) or an indication of the current transient characteristics of the location to be read (e.g., block read interference and block retention time).

[0038] The use of characteristic values ​​can include read interference values. In one example, whenever a block is closed, state circuit 5 is operable to count the number of reads of the block when the block is closed, and stores the number of reads of the block when the block is closed as a read interference value. When the block is erased, the read interference value of the erased block is reset to zero.

[0039] The characteristic value can include the closed block retention time. In one example, each time the block is closed, state circuit 5 is operable to start a timer to determine the amount of time that has elapsed since the block was closed. The elapsed time determined by the timer at any point in time is defined as the closed block retention time value. When the block is erased, the timer for that block stops, and the closed block retention time value for the erased block is reset to zero.

[0040] The characteristic value can include a number indicating the number of programming and erase operations for each block. In one example, state circuit 5 is operable to count the number of programming and erase cycles for each block of the flash memory device over the entire lifetime of the flash memory device and to store the count in data storage device 4 or DRAM 13.

[0041] The characteristic values ​​can also include the BER of a block or a set of blocks. In one example, state circuit 5 is operable to periodically determine the BER of each block, and the BER of each block is stored as a BER value. In one example, each time a BER value is calculated, it is stored in data storage device 4 or DRAM 13 to overwrite the previously stored BER value for a particular block.

[0042] Optionally, when generating and storing more than one RNN inference model, method 100 includes selecting (104) one of the stored RNN inference models. In one example, one of the stored RNN inference models corresponding to the current cycle in the lifetime of the flash memory device is selected.

[0043] The neural network operation (105) of the stored RNN inference model is executed to generate a TVS-RE curve corresponding to the identified usage characteristic values. The inputs for the neural network operation include one or more identified usage characteristic values ​​and one or more values ​​identifying the page to be read (e.g., values ​​identifying the physical location of the page to be read, such as values ​​identifying one or more word lines, blocks, planes, or flash memory devices to be read). In one example, the neural processing module 11 is configured to execute the neural network operation of the stored RNN inference model 12 to generate a TVS-RE curve corresponding to the identified usage characteristic values, wherein the inputs for the neural network operation include one or more identified usage characteristic values ​​and one or more values ​​identifying the page to be read. In one example, the neural processing module 11 includes a specialized hardware module (e.g., a specialized configurable accelerator) specifically configured to perform neural network operations, and this specialized hardware module may also be referred to hereinafter as a "neural network engine". In one implementation, step 105 is performed in response to receiving a read command from the host computer (e.g., each time a read command is received), wherein the value identifying the page to be read is a value indicating a physical location in the flash memory device 9 corresponding to the read address included in the read command. Step 105 may also be performed on internal controller events (such as by a timer or counter) or events by the flash controller 3 (e.g., background reads) to monitor the reliability status of the flash memory device 9.

[0044] Identify the TVSO value corresponding to the minimum value of the generated TVS-RE curve (106). In one example, the minimum functional module 2 is configured to determine the minimum value of the generated TVS-RE curve and identify the TVSO value corresponding to the determined minimum value. The minimum functional module 2 may include software, hardware, and / or firmware for receiving the coefficients of the generated TVS-RE curve, identifying the minimum point of the curve, and outputting the TVSO value corresponding to the identified minimum point of the curve.

[0045] Then, a read of the flash memory device is performed using the threshold voltage offset read at the TVSO value identified in step 106 (107). The neural network operation of step 105 is executed each time a read command is received from the host computer. More specifically, in response to receiving a read command at the host connector socket 14, steps 103, optionally 104, and steps 105 through 106 are executed to identify the TVSO value, and the read circuit 6 uses the TVSO value identified in step 106 to perform the read.

[0046] In another example, steps 105 to 106 are performed periodically, and the results (TVSO values) are stored in a table (e.g., including an optional table 15a of the usage characteristics and corresponding TVSO values ​​that may be referred to as the "TVSO table"). In this example, when the read in step 107 is performed, the usage characteristics identified in step 103 are used to find the corresponding TVSO value used in the read in step 107.

[0047] Example 1: Stored Single RNN Inference Model

[0048] In one example, a single RNN inference model is stored in step 102, which predicts TVS-RE curves at different points in the lifetime of the flash memory device. Step 103 includes monitoring the operation of the flash memory device to determine the current point in the lifetime of the flash memory device, and the input for the neural network operation includes identifying the value of the current point determined in the lifetime of the flash memory device. In one example, the value of the current point in the lifetime of the flash memory device is multiple programming and erasing loops. Alternatively, the value of the current point in the lifetime of the flash memory device is the BER of a block of pages to be read.

[0049] Figure 4A A diagram of an exemplary RNN inference model 40a is shown, comprising layers 42 to 44 containing multiple input neurons 41, multiple output neurons 45a, and hidden neurons. The inputs to the RNN inference model include reference values ​​that identify one or more characteristics of the flash memory device to be read, such as, but not limited to, manufacturer, part number, and / or manufacturing batch number. By including reference values ​​that identify the type of flash memory device, an RNN inference model capable of identifying TVS-RE curves for different types of flash memory devices can be used.

[0050] The input includes one or more values ​​that identify the page to be read. In this example, the values ​​include a block value that identifies the block of the page to be read in step 107 and a word line value that indicates the word line of the page to be read. In one exemplary embodiment of the SSD 10, which includes 128 flash memory devices 9, each flash memory device includes 2048 blocks, which can be assigned numbers from 0 to 262,143, where the block value is the block number of the page to be read in step 107.

[0051] In this example, step 103 includes counting multiple closed block reads, and the input for the neural network operation includes a value indicating the number of closed block reads of the block containing the page to be read (i.e., read interference value). Step 103 also includes determining the closed block retention time, and the input for the neural network operation includes a value indicating the retention time of the closed block containing the page to be read (i.e., retention time value). Additionally, step 103 includes counting the number of programming and erase cycles for each block of the flash memory device, and the current point in the lifetime of the flash memory device is determined as the current number of programming and erase cycles of the block containing the page to be read (i.e., programming / erase value).

[0052] In this example, step 103 identifies the following usage characteristic values: retention time value, readout disturbance value, programming / erasing value, and other exemplary usage characteristic values ​​that can be any measurement that can affect the threshold voltage distribution, such as, for example, but not limited to, temperature values. The inputs for neural network operation include the usage characteristic values: retention time value, readout disturbance value, programming / erasing value, and other usage characteristic values.

[0053] Output neuron 45a generates an output that defines the TVS-RE curve in the form of exponential values. An exemplary output of the RNN inference model 40a is shown as including six exponents, indicated as the first, second, third, fourth, fifth, and sixth exponents. It should be understood that the RNN inference model 40a can have any number of exponents, and the number of exponents can be varied to achieve a balance between processing time and accuracy.

[0054] exist Figure 4BIn the example shown, output neuron 45b generates a value indicating the number of errors at the location corresponding to the TVSO value. In this example, output neuron 45b includes output neurons for each TVSO value (for n TVSO values), such as, for example, an output neuron predicting the error using a first TVSO value (PRED-ERR TVSO1), an output neuron predicting the error using a second TVSO value (PRED-ERR TVSO2), an output neuron predicting the error using a third TVSO value (PRED-ERR TVSO3), an output neuron predicting the error using a fourth TVSO value (PRED-ERR TVSO4), an output neuron predicting the error using a fifth TVSO value (PRED-ERR TVSO5), and so on, up to an output neuron predicting the error using the nth TVSO value (PRED-ERR TVSOn). In a specific example, TVSO values ​​from -32...0...+32 are used, and when using a TVSO of -32, PRED-ERR TVSO1 is the prediction error; when using a TVSO of -31, PRED-ERR TVSO2 is the prediction error; when using a TVSO of -30, PRED-ERR TVSO3 is the prediction error; when using a TVSO of -29, PRED-ERR TVSO4 is the prediction error; when using a TVSO of -28, PRED-ERR TVSO5 is the prediction error; and when using a TVSO of +32, PRED-ERR TVSOn is the prediction error.

[0055] When the output is an instruction, such as Figure 4B When determining the magnitude of the error at the location of the indicated TVSO value, in step 106, the minimum measuring procedure 83 needs to identify only which output produces the lowest error to determine the TVSO value corresponding to the minimum value of the TVSE curve, since the TVSO value is known to correspond to each output neuron. However, when the output neurons produce outputs exponentially, the minimum measuring procedure 83 includes an algorithm for identifying where the minimum value is (e.g., its location on the x-axis) and identifying the TVSO value corresponding to the identified minimum point on the curve (e.g., the integer TVSO value closest to the identified minimum point on the curve).

[0056] Example 2: Storing multiple RNN inference models corresponding to the period

[0057] In this exemplary step 102, it further includes storing a plurality of RNN inference models 12, each of which identifies a TVS-RE curve for different periods during the lifetime of the flash memory device 9.

[0058] Figure 5Exemplary cycles P1 to P9 are shown during the lifetime of an exemplary flash memory device 9, beginning at an initial time T0 and ending at an end time TN of the lifetime of the flash memory device 9. In this example, each cycle P1 to P9 is represented by multiple programming and erasing cycles (PE1 to PE8). For example, an exemplary cycle P2 begins with multiple programming and erasing cycles, shown as PE1, and ends with PE2 in multiple programming and erasing cycles. As the flash memory device 9 ages, shorter cycles may be required to ensure that the number of read errors is minimized. Although threshold voltage offset read operations used throughout the lifetime of the flash memory device 9 are disclosed, it should be understood that regular read instructions such as page read instructions can be used early in the lifetime of the flash memory device 9, since reads at the default threshold voltage are unlikely to cause read errors early in the lifetime of the flash memory device 9.

[0059] In one example, multiple RNN inference models are stored in step 102, each corresponding to Figure 5 One of the exemplary periods P1 to P9 is shown. Therefore, a first RNN inference model corresponding to P1 will be stored, a second RNN model corresponding to P2 will be stored, and so on.

[0060] In this example, step 103 includes monitoring the operation of the flash memory device 9 to determine the current cycle in the lifetime of the flash memory device 9, and in step 104 selecting one of a plurality of RNN inference models 12 corresponding to the current cycle in the lifetime of the flash memory device. In this example, step 103 may include counting the number of programming and erase cycles for each block of the flash memory device 9, and determining the current cycle in the lifetime of the flash memory device 9 as the cycle corresponding to the current number of programming and erase cycles for the block containing the pages to be read (e.g., one of cycles P1 to P9). In one example, state circuit 5 is operable to determine the current number of programming and erase cycles for the block containing the pages to be read, and identify the current cycle in the lifetime of the flash memory device that is read using the identified current number of programming and erase cycles (e.g., by storing a table indicating cycles and corresponding numbers of programming and erase cycles, and performing a lookup operation on the table using the current number of programming and erase cycles for the block containing the pages to be read).

[0061] In one example, the neural processing module 11 is operable upon receiving input from the state circuit 5, identifies the current cycle to select the corresponding RNN inference model 12 and performs (105) the neural network operation of the selected RNN inference model to generate a TVS-RE curve. Figure 6A diagram of an exemplary RNN inference model 50 that can be used according to this embodiment is shown. The RNN inference model 50 includes layers 52 to 54 of multiple input neurons 51, multiple output neurons 55, and hidden neurons. It can be seen that the RNN inference model 50 does not include neurons for receiving multiple programming and erasing cycles (programming / erasing values), as done by RNN inference models 40a to 40b. In this example, the number of programming and erasing cycles is not required as input because the error characteristics related to the use / age of the flash memory device are characteristic of the selected RNN inference model 50. Although the RNN inference model 50 shows output neurons 55 generating TVSO curve coefficients, the output neurons 55 can also indicate, for example... Figure 4B The error values ​​at different TVSO values ​​are shown.

[0062] Example 3: Generating a Neural Network Model (Step 101)

[0063] Figure 7 An exemplary testing and model generation system 70, which can be used to generate RNN inference models according to one embodiment of the present invention, is shown. The system includes an input 71, an output 72, a processor 74, a data storage device 79, and a minimum tester program 83 connected via a network 80. The minimum tester program 83 is a software program operable on the processor 74 and therefore can represent electronically readable instructions, which can be communicated with... Figure 1 The minimum functional module 2 shown uses the same program, which is operable to identify the minimum value of a function. The testing and model generation system 70 includes a bench test program 82, which may represent electronically readable instructions operable on the processor 74 to test the representative flash memory device 73 in a manner that identifies the number of errors occurring as a representative flash memory device 73's age. The representative flash memory device 73 may be inserted into one or more test fixtures coupled to the testing and model generation system 70. The representative flash memory device 73 is a device similar to or identical to the flash memory device 9, and may be a device of the same type (e.g., a NAND device of the same type) manufactured by the same manufacturer as the flash memory device 9. The machine learning module 81 may represent electronically readable instructions operable on the processor 74 to generate neural networks, such as... Figure 4A , Figure 4B and Figure 6 The neural network shown is 40a, 40b, or 50, and may include a computer program operable on processor 74.

[0064] exist Figure 8One embodiment shown discloses a method 200 for generating an RNN inference model, which includes performing flash characterization tests (201) on a representative flash memory device 73 to obtain one or more threshold voltage offset readout test result sets. Figure 7 In one example shown, a number of representative flash memory devices 73 are tested under different conditions to obtain one or more threshold voltage offset read test result sets 83 that can be stored in data storage device 79. The test result sets represent different characteristic points or cycles in the lifetime of the characterized flash memory devices and different operating conditions of the characterized flash memory devices because different test conditions were applied during the testing of the flash memory devices 73.

[0065] In one example step 201, a test is performed on a representative flash memory device 73, which identifies the number of errors and test characteristic values ​​for each of a plurality of identification features of the respective representative flash memory device 73 being tested, such as, for example, a reference value for the respective representative flash memory device 73 being tested, a block value identifying the block of pages read in the test, a word line value indicating the word line of the pages read in the test, a read interference value indicating the number of closed block reads of the block containing the pages read in the test, a retention time value indicating the retention time of the closed block of the block containing the pages read in the test, and a programming / erasing value of the block containing the pages read in the test.

[0066] Figure 9 A graph representing an exemplary flash memory characterization test of an exemplary memory cell is shown, illustrating different TVSO values ​​on the x-axis and the number of errors on the y-axis. The result of this process, namely the set of error numbers at different VT offset values ​​(point 91), is a curve, a portion of which is shaped into "troughs". The RNN inference model 78 of the present invention generates curves that include these troughs for each condition simulated during the test in step 201.

[0067] One or more profiles defining the initial RNN inference model are received as input (202). In one example, one or more profiles are received via input 71 and temporarily stored in data storage device 79. When the operation of machine learning module 81 is initiated, the profiles received in step 202 define the architecture of the initial RNN inference model (e.g., the number of input neurons, hidden neurons, and output neurons, and the connections between neurons) and the inputs required to control and define the operation of machine learning module 81 during the process of steps 202 to 215. In one example, the one or more profiles received in step 202 define the features of the initial RNN inference model (e.g., reference number, block, word line, number of closed block reads, closed block retention time, programming / erasing values), and include an initial parameter set and hyperparameters. In one example, the initial parameter set includes the initial weights and biases for each neuron in the initial RNN model (e.g., the initial weights and biases may all be set to zero or random numbers).

[0068] One or more threshold voltage offset readout test result sets are received as input (203). In one example, one or more sets of threshold voltage offset readout test results 83 created in step 201 are input into machine learning module 81.

[0069] Method 200 further includes creating (204) a threshold voltage offset readout training dataset, a threshold voltage offset readout validation dataset, and a threshold voltage offset readout test dataset. In one example, machine learning module 81 is operable to separate (e.g., via a random process) threshold voltage offset readout test results 83 into a training database 75, which includes a threshold voltage offset readout training dataset, a validation database 76, which includes a threshold voltage offset readout validation dataset, and a test database 77, which includes a threshold voltage offset readout test dataset.

[0070] An initial RNN inference model is trained (206) using a threshold voltage offset readout training dataset to obtain a trained RNN model. In one example, machine learning module 81 is operable to perform training of the initial RNN inference model to generate an RNN inference model 78 that can be stored in data storage device 79. In one example, the number of errors at each test TVSO value is loaded into the input neuron, the feature values ​​from the test are input into the corresponding neuron, and a backpropagation algorithm is performed to identify a new set of parameters for the RNN model. This process is repeated until all records in the threshold voltage offset readout training dataset have been processed. The trained RNN inference model incorporates word-to-word and block-to-block variability of the tested representative flash memory device 73 to identify TVS-RE curves reflecting word-to-word and block-to-block variability and variability corresponding to usage characteristics. Figure 10 An example of a TVS-RE curve generated from a training dataset read from an exemplary threshold voltage offset is shown. More specifically, the number of errors is shown on the y-axis, and TVSO is shown on the x-axis. (As in...) Figure 10 As can be seen, due to the nature of the NAND flash memory read circuit, there are fluctuations (noise) in the number of errors in each trough. This noise negatively impacts the learning process of the RNN inference model, potentially affecting the actual location of the minimum trough and leading to incorrectly calculated TVSO values. To avoid this problem, as shown in step 205, in step 206, before training the RNN, a smoothing algorithm such as moving average or multinomial interpolation is optionally applied to the training dataset to generate a smoothed threshold voltage offset read training dataset (where the shape of the troughs represented by the target dataset is smoothed). Figure 11 An example of a TVS-RE curve generated from an exemplary smoothed threshold voltage offset readout training dataset is shown. Therefore, since the smoothing function (205) is performed prior to training (206), instead of training an RNN inference model to predict the exact number of TVS-RE curves corresponding to the errors measured during the device characterization step (executed in step 201 and input in step 203), an RNN inference model is trained to predict the TVS-RE curves corresponding to the smoothed threshold voltage offset readout training dataset.

[0071] The trained RNN inference model is compared to a predetermined training criterion (207). If the trained RNN inference model does not meet the predetermined training criterion, the initial RNN inference model is updated (213), and the training process is repeated to generate a new trained RNN inference model (206). Step 213 may include adding additional parameters, hyperparameters, and / or neurons. Additionally, step 213 may also include adding additional threshold voltage offset readout test data to the threshold voltage offset readout training dataset.

[0072] If the trained RNN inference model meets a predetermined training criterion, the RNN inference model is validated using a threshold voltage offset readout validation dataset (208). In one example, machine learning module 81 is operable to perform validation using the threshold voltage offset readout validation dataset to generate trained and validated RNN inference models that can be temporarily stored in data storage device 79. The trained and validated RNN inference models are compared to predetermined validation criteria (209). If the trained and validated RNN inference models do not meet the predetermined validation criteria, the initial RNN model is updated (214), and the processes of training (206), testing (207), and validation (208) are repeated. Step 214 may include adding additional parameters, hyperparameters, and / or neurons. Additionally, step 214 may also include adding additional threshold voltage offset readout test data to the threshold voltage offset readout training dataset.

[0073] If the trained and validated RNN inference model meets the predetermined validation criteria, the RNN inference model is tested using a threshold voltage offset readout test dataset (210). The trained, validated, and tested RNN inference model is compared with the predetermined test criteria (211). If the test fails (215), the process ends and must be restarted with a new initial RNN model.

[0074] If the trained, validated, and tested RNN inference model meets the testing criteria of step 211, the trained, validated, and tested RNN model is trimmed by removing unnecessary elements (212) to obtain an RNN inference model 78 that can be stored in data storage device 79. An example step 212 includes removing those portions of the configuration file related to the training / testing and validation phases of method 200 and converting the remaining elements of the RNN model to a different data format to accelerate the inference time of the resulting final RNN inference model. This example step 212 includes converting the remaining elements of the RNN model from floating-point to fixed-point, such as 40-bit fixed-point. In one example, step 212 produces... Figure 1 The TVS-RE inference model 12 is shown. The conversion from floating-point to fixed-point enables the neural processing module 11 to have a lower gate count and reduced latency.

[0075] The criteria used in steps 207, 209, and 211 can be a cost function for determining the "degree" of the training process. In one example, the mean squared error (MSE) function is used, with the aim of having the lowest possible overall MSE. Therefore, the MSE is calculated at 207 to identify the MSE achieved by training using a threshold voltage offset reading of the training dataset. To proceed to step 208, the MSE calculated using the threshold voltage offset reading of the training dataset must be below a predetermined threshold. The MSE is calculated at 209 to identify the MSE achieved using a threshold voltage offset reading of the validation dataset. To proceed to step 210, the MSE calculated using the threshold voltage offset reading of the validation dataset must be below a predetermined threshold and must be close to the MSE calculated using the threshold voltage offset reading of the training dataset (e.g., within a predetermined tolerance). Therefore, the MSE is calculated at step 211 to identify the MSE achieved using a threshold voltage offset reading of the test dataset. In order to proceed to step 212, the MSE calculated using the threshold voltage offset reading test dataset must be lower than a predetermined threshold and must be close to the MSE calculated using the threshold voltage offset reading training dataset and the MSE calculated using the threshold voltage offset reading validation dataset (e.g., within a predetermined tolerance).

[0076] In one example, after characterization in step 201, an optimal threshold voltage offset value, which may be referred to as the "golden VT-opt value," is calculated (and is separate from any of steps 202 through 209). The golden VT-opt value is the optimal threshold voltage offset value calculated without using the RNN inference model generated by method 200. In one embodiment, the golden VT-opt value is calculated to identify the golden VT-opt values ​​for various test samples by using a test bench procedure 82 and generating error curves using a minimum measuring instrument procedure 83.

[0077] In this example, step 211 includes operating a trained and validated RNN inference model (e.g., on processor 74) to identify the coefficients of the exemplary TVS-RE curve, and inputting the identified coefficients into a minimum measurer procedure 83 to identify the predicted minimum TVSO value (e.g., by running the RNN inference model on the entire training dataset and running the minimum measurer procedure 83 on the result to compute the predicted minimum TVSO value). The predicted minimum TVSO value is then compared with the corresponding gold VT-opt value, and the method proceeds to step 212 when the predicted TVSO value computed using the RNN inference model is within the range of the corresponding gold VT-opt value (e.g., within a predetermined tolerance).

[0078] When generating a single RNN inference model (e.g., the RNN inference model used in Example 1 above) to be used for the lifetime of a flash memory device, the RNN inference model uses a value indicating the current point in the lifetime of the flash memory device (e.g., the number of PE cycles) to generate an output representing the usage and age of the flash memory device. Generating a single RNN inference model used over the lifetime of the flash memory is advantageous because it eliminates the need to store and manipulate multiple RNN inference models. However, training and validation are more extensive and time-consuming because test data representing the complete lifetime of the flash memory device must be used.

[0079] When multiple RNN inference models are generated to represent a specific flash memory device, more factors affecting the threshold voltage can be accurately modeled, leading to increased accuracy. However, the time required to load each of the different models into the neural processing module 11 can cause system latency.

[0080] Grouping Examples

[0081] Multiple RNN inference models can be created in step 101 and stored. Figure 1 In step 102, each of the multiple RNN inference models identifies a threshold voltage offset read error curve corresponding to one or more groups of factors affecting the threshold voltage. The one or more groups of factors affecting the threshold voltage may be, but are not limited to, a set of word lines of the flash memory device, a set of blocks of the flash memory device, a time period, a set of read interferences, and a set of retention times.

[0082] In the following example, characterization is performed for a single type of flash memory device, such that each RNN interference model is tailored to that single type of flash memory device. Therefore, no reference values ​​are needed as input, as the RNN interference model will be trained using only test data associated with the single type of flash memory device connected to the flash controller 3. The following groupings are exemplary, and it should be understood that many other combinations of groupings can also be used according to one embodiment of the invention. In the following example, retention time, read interference, and the number of programming and erase cycles are determined for each block to identify one or more usage characteristic values. However, it should be understood that retention time, read interference, and the number of programming and erase cycles can also be determined on a word line basis.

[0083] A. Periodic grouping

[0084] In one example, the lifetime of the flash memory device is grouped into periods based on the number of programming and erasing cycles, and an RNN inference model (which may be referred to as a "P / E-classified RNN inference model") is generated for each of the multiple periods in the lifetime of the flash memory device. In this example, each of the P / E-classified RNN inference models is stored on the flash controller 3 in step 102, and in step 104, a P / E-classified RNN inference model is selected corresponding to the current time period. For example, a grouping table 15 may be stored in a data storage device 4, which includes programming / erasing values ​​and corresponding values, or pointers, to identify the specific P / E-classified RNN inference model to be used. In step 104, a lookup operation is performed on the grouping table 15 using the current number of programming and erasing cycles of the word lines or blocks to be read in step 107 (or based on the total number of current programming and erasing cycles for the flash memory device) to identify the P / E-classified RNN inference model to be used. Figure 12A The diagram shows an RNN inference model 60a for P / E classification. Since the RNN inference model 60a for P / E classification corresponds to a specific time period, it does not have programmed / erased values ​​as inputs to input neurons 61a.

[0085] In one example, the lifetime of the flash memory device is divided into seven distinct cycles: the first cycle consists of 1,000 P / E cycles; the second cycle consists of 1,001 to 2,000 P / E cycles; the third cycle consists of 2,001 to 3,000 P / E cycles; the fourth cycle consists of 3,001 to 4,000 P / E cycles; the fifth cycle consists of 4,001 to 5,000 P / E cycles; the sixth cycle consists of 5,001 to 6,000 P / E cycles; and the seventh cycle consists of 6,001 to 7,000 P / E cycles (at which point the lifetime ends). This allows the RNN inference model for the seven P / E cycles to be stored in step 102.

[0086] B. Word line grouping

[0087] In one example, word lines are grouped, and an RNN inference model (which may be referred to as a "W-classified RNN inference model") is generated for each of the multiple word line groups. In this example, in step 102, each of the W-classified RNN inference models is stored on a flash memory controller, and in step 104, a W-classified RNN inference model is selected corresponding to the word line to be read in step 107. For example, a grouping table 15 may be stored in a data storage device 4, which includes word line values ​​and corresponding values ​​or pointers identifying a specific W-classified RNN inference model to be used. In step 104, a lookup operation is performed on the word line table using the word line to be read in step 107 to identify the W-classified RNN model to be used. Figure 12B The diagram shows an RNN inference model 60b for W-classification. Since the RNN inference model 60b for W-classification corresponds to a specific word line group, it does not include word line values ​​as input to the input neuron 61b.

[0088] In one example, word lines are grouped by their physical location on the chip (e.g., word lines in the first nth layer are in the first category, and word lines in the next nth layer are in the second category, and so on), wherein word lines are divided into ten different word line categories, such that 10 W-class RNN inference models are stored in step 102.

[0089] C. Word lines and periodic grouping

[0090] In one example, word lines are grouped and the lifetime of the flash memory device is grouped into periods based on the number of programming and erasing cycles. An RNN inference model (which may be referred to as a "WP / E-classified RNN inference model") is generated for each of the multiple word lines and for each of the multiple periods within the lifetime of the flash memory device. In this example, in step 102, each of the WP / E-classified RNN inference models is stored on the flash controller, and in step 104, a WP / E-classified RNN inference model is selected corresponding to the word line to be read in step 107 and the current time period. For example, a grouping table 15 may be stored in a data storage device 4, which includes word line values, programming / erasing values, and corresponding values ​​identifying the specific WP / E-classified RNN inference model to be used. In step 104, a lookup operation is performed on the WP / E table using the word line to be read in step 107 and the programming / erasing value corresponding to the current number of programming / erasing cycles for the block to be read in step 107 to identify the WP / E-classified RNN inference model to be used. Figure 12CThe diagram shows an RNN inference model 60c for WP / E classification. Since the RNN inference model 60c for WP / E classification corresponds to a specific word line group and a specific time period, it does not include word line values ​​or programming / erasing values ​​as inputs to input neurons 61c.

[0091] In one example, word lines are grouped into ten different word line categories based on their physical location on the chip, as discussed in Example B above, and the lifespan of the flash memory device is divided into seven different cycles, as discussed in Example A above, such that 70 W / P / E classification RNN inference models are stored in step 102.

[0092] D. Block grouping

[0093] In one example, blocks are grouped and an RNN inference model (which may be referred to as a "B-class RNN inference model") is generated for each of the multiple block groups. In this example, in step 102, each of the B-class RNN inference models is stored on a flash memory controller, and in step 104, a B-class RNN inference model is selected based on the block value corresponding to the block to be read in step 107. For example, a grouping table 15 may be stored in a data storage device 4, which includes block values ​​and corresponding values ​​or pointers that identify the specific B-class RNN inference model to be used. In step 104, a lookup operation is performed on the block table using the block value of the block to be read in step 107 to identify the B-class RNN inference model to be used. Figure 12D The diagram shows an RNN inference model 60d for B-class classification. Since the RNN inference model 60d for B-class classification corresponds to a specific block group, it does not have block values ​​as inputs to the input neuron 61d.

[0094] In one example, blocks are grouped by their physical location on the chip (e.g., n adjacent blocks are in the first category, then the next n adjacent blocks are in the second category, and so on), with the blocks divided into ten different block groups, such that 10 B-class RNN inference models are stored in step 102.

[0095] E. Block and Periodic Grouping

[0096] In one example, blocks are grouped and the lifetime of the flash memory device is grouped into periods based on the number of programming and erasing cycles. An RNN inference model (which may be referred to as a "BP / E-classified RNN inference model") is generated for each of the multiple groups of blocks and for each of the multiple periods within the lifetime of the flash memory device. In this example, in step 102, each of the BP / E-classified RNN inference models is stored on the flash controller, and in step 104, a BP / E-classified RNN inference model is selected corresponding to the block value of the block to be read in step 107 and the current time period. For example, a grouping table 15 may be stored in a data storage device 4, which includes block values, programming / erasing values, and corresponding values ​​identifying the specific BP / E-classified RNN inference model to be used. In step 104, a lookup operation is performed on the BP-E table using the block value of the block to be read in step 107 and the programming / erasing value for the block to be read in step 107 to identify the BP / E-classified RNN interference model to be used. Figure 12E The diagram shows an RNN inference model 60e for BP / E classification. Since the RNN inference model 60e for BP / E classification corresponds to a specific block group and a specific time period, it does not include block values ​​or programmed / erased values ​​as inputs to input neurons 61e.

[0097] In one example, the block categories are grouped into ten different block groups based on their physical location on the chip, as discussed in Example B above, and the lifespan of the flash memory device is divided into seven different cycles, as discussed in Example A above, such that 70 BP / E classification RNN inference models are stored in step 102.

[0098] F. Block and word lines and periodic grouping

[0099] In one example, blocks and word lines are grouped; and the lifetime of the flash memory device is grouped into cycles based on the number of programming and erasing cycles; and an RNN inference model (which may be referred to as a "BWP / E classification RNN inference model") is generated for each of the multiple groups of blocks, for each of the multiple groups of word lines, and for each of the multiple cycles in the lifetime of the flash memory device. In this example, in step 102, each of the BWP / E classification RNN inference models is stored on the flash controller, and in step 104, a BWP / E classification RNN inference model is selected corresponding to the block value to be read in step 107, the word line to be read in step 107, and the current time cycle. For example, a grouping table 15 may be stored in a data storage device 4, which includes block values, word line values, programming / erasing values, and corresponding values ​​identifying the specific BWP / E classification RNN inference model to be used. In step 104, a lookup operation is performed on the BWP / E table using the block value of the block to be read in step 107, the word line to be read in step 107, and the current number of P / E loops for the block to be read in step 107, to identify the RNN inference model for the BWP / E classification to be used. Figure 12F The diagram shows an RNN inference model 60f for BWP / E classification. Since the RNN inference model 60f for BWP / E classification corresponds to a specific block group, a specific word line group, and a specific time period, the RNN inference model 60f for BWP / E classification will not have block values, word line values, or programmed / erased values ​​as inputs to the input neurons 61f.

[0100] In one example, word lines are grouped into ten different word line groups based on their physical location on the chip, as discussed above in Example B; blocks are grouped into ten groups based on their physical location on the chip, as discussed above in Example D; and the lifetime of the flash memory device is divided into seven different cycles, as discussed above in Example A, such that 700 BWP / E classification RNN inference models are stored in step 102.

[0101] G. Retention Time Grouping

[0102] In one example, retention times are grouped and an RNN inference model (which may be referred to as a "RT-classified RNN inference model") is generated for each of the multiple retention time groups. In this example, in step 102, each of the RT-classified RNN inference models is stored on the flash memory controller, and in step 104, an RT-classified RNN inference model is selected corresponding to the closing block retention time of the block to be read in step 107. For example, a retention time (RT) table may be stored in a data storage device 4, which includes closing block retention time values ​​and corresponding values ​​that identify the specific RT-classified RNN inference model to be used. In step 104, a lookup operation is performed on the retention time table using the current closing block retention time for the block to be read in step 107 to identify the RT-classified RNN inference model to be used. Figure 12G The diagram shows an RNN inference model 60g for RT classification. Since the RNN inference model 60g for RT classification corresponds to a specific retention time group, it does not have a retention time value as the input to the input neuron 61g.

[0103] In one example, retention times are grouped into different periods based on the closure block retention time, with some or all of these periods having the same duration. In one example, the retention times are grouped into 50 periods, each with a duration of 40 hours (e.g., the first group has a closure block retention time of less than or equal to 40 hours, the second group has a closure block retention time of greater than 40 hours and less than or equal to 80 hours, the third group has a closure block retention time of greater than 80 hours and less than or equal to 120 hours, and so on), such that 50 RNN inference models for RT classification are stored in step 102.

[0104] H. Retention Time and Periodic Grouping

[0105] In one example, retention time and the lifetime of the flash memory device are grouped into periods based on the number of programming and erasing cycles, and an RNN inference model (which may be referred to as an "RT-P / E classified RNN inference model") is generated for each of multiple retention time groups and for each of multiple periods within the lifetime of the flash memory device. In this example, in step 102, each of the RT-P / E classified RNN inference models is stored on the flash controller, and in step 104, an RT-P / E classified RNN inference model is selected corresponding to the closed block retention time of the block to be read in step 107 and the current time period. For example, a grouping table 15 may be stored in a data storage device 4, which includes retention time values, programming / erasing values, and corresponding values ​​or pointers identifying the specific RT-P / E classified RNN inference model to be used. In step 104, a lookup operation is performed on grouping table 15 using the current closed block retention time of the block to be read in step 107 and the current number of programming and erasing cycles of the block to be read in step 107 to identify the RNN model to be used for RT-P / E classification. Figure 12H The diagram shows an RNN inference model 60h for RT-P / E classification. Since the RNN inference model 60h for RT-P / E classification corresponds to a specific retention time group and a specific time period, it does not have the number of retention times or programmed / erased values ​​that are used as inputs to the input neurons 61h.

[0106] In one example, as discussed in Example G above, the retention time is grouped into 50 different cycles based on the closed block retention time, and the lifetime of the flash memory device is divided into seven different cycles, as discussed in Example A above, such that 350 RNN inference models for RT-P / E classification are stored in step 102.

[0107] I. Reading interference packets

[0108] In one example, read interference is grouped and an RNN inference model (which may be referred to as an "RD-classified RNN inference model") is generated for each of the multiple read interference groups. In this example, in step 102, each of the RD-classified RNN inference models is stored on the flash memory controller, and in step 104, an RD-classified RNN inference model is selected corresponding to the current number of read interferences for the block to be read in step 107. For example, a grouping table 15 may be stored in a data storage device 4, which includes read interference values ​​and corresponding values ​​or pointers that identify the specific RD-classified RNN inference model to be used. In step 104, a lookup operation is performed on the grouping table 15 using the current number of closed block reads for the block to be read in step 107 to identify the RD-classified RNN inference model to be used. Figure 12I The diagram shows an RNN inference model 60i for RD classification. Since the RNN inference model 60i for RD classification corresponds to a specific read disturbance group, it does not have read disturbance values ​​as inputs to the input neuron 61i.

[0109] In one example, reading interference is classified based on the number of closed block reads of the block to be read in step 107, where the first category includes 0 to 100,000 closed block reads, the second category includes 100,001 to 200,000 closed block reads, the third category includes 200,001 to 300,000 closed block reads, and the fourth category includes more than 300,001 closed block reads, so that the RNN inference model with 4 RD categories is stored in step 102.

[0110] J. Reading Interference and Periodic Grouping

[0111] In one example, read interference is grouped; the lifetime of the flash memory device is grouped into cycles based on the number of programming and erasing cycles; and an RNN inference model (which may be referred to as an "RD-P / E classification RNN inference model") is generated for each of the multiple read interference groups and for each of the multiple cycles of the flash memory device's lifetime. In this example, in step 102, each of the RD-P / E classification RNN inference models is stored on the flash controller, and in step 104, an RD-P / E classification RNN inference model is selected based on the current number of closed block reads corresponding to the block to be read in step 107 and the current time cycle. For example, a grouping table 15 may be stored in a data storage device 4, which includes read interference values, programming / erasing values, and corresponding values ​​or pointers identifying the specific RD-P / E classification RNN inference model to be used. In step 104, a lookup operation is performed on grouping table 15 using the current number of currently closed block reads of the block to be read in step 107 and the programming / erasing value corresponding to the current number of programming and erasing cycles of the block to be read in step 107, to identify the RNN inference model for the RD-P / E classification to be used. Figure 12J The diagram shows an RNN inference model 60j for RD-P / E classification. Since the RNN inference model 60j for RD-P / E classification corresponds to a specific read disturbance group and a specific time period, the RNN inference model for RD-P / E classification will not have read disturbance values ​​or programming / erasing values ​​as inputs to the input neurons 61jj.

[0112] In one example, read interference is grouped into four different groups, as discussed in Example I above, and the lifespan of the flash memory device is divided into seven different cycles, as discussed in Example A above, such that 28 RNN inference models for RD-P / E classification are stored in step 102.

[0113] K. Retention time and read interference groups

[0114] In one example, retention time and read interference are grouped and an RNN inference model is generated for each of the multiple retention time groups and for each of the multiple read interference groups (which can be referred to as "RT-RD classification RNN inference model").

[0115] In one example, the retention time is grouped into 50 groups, as discussed in Example G, and the reading interference is grouped into 4 different groups, as discussed in Example I, such that 200 RT-RD-classification RNN inference models are stored in step 102.

[0116] L. Retention time, blocks, and read interference groups

[0117] In one example, retention time, blocks, and read interference are grouped, and an RNN inference model is generated for each of the multiple retention time groups, for each of the multiple block groups, and for each of the multiple read interference groups (which can be referred to as "RT-B-RD classification RNN inference model").

[0118] In one example, retention times are grouped into 50 groups, and blocks are grouped into 10 groups as discussed in Example G, as discussed in Example D, and read interference is grouped into 4 distinct groups as discussed in Example I, such that 2000 RT-B-RD classification RNN inference models are stored in step 102.

[0119] M. Retention time, word lines, and read interference groups

[0120] In one example, retention time, word lines, and read interference are grouped, and an RNN inference model is generated for each of the multiple retention time groups, for each of the multiple word line groups, and for each of the multiple read interference groups (which can be called "RT-W-RD classification RNN inference model").

[0121] In one example, retention times are grouped into 50 groups, word lines are grouped into 10 groups as discussed in Example G, and read interference is grouped into 4 distinct groups as discussed in Example I, such that 2000 RT-W-RD classification RNN inference models are stored in step 102.

[0122] N. Retention time, word lines, read interference, and periodic grouping

[0123] In one example, retention time, word lines, and read interference are grouped; the lifetime of the flash memory device is grouped into periods based on the number of programming and erasing cycles; and an RNN inference model (which may be referred to as "RT-WP / E classification RNN inference model") is generated for each of the multiple retention time groups, for each of the multiple word line groups, for each of the multiple read interference groups, and for each of the multiple periods in the lifetime of the flash memory device.

[0124] In one example, retention times are grouped into 50 groups, word lines are grouped into 10 groups as discussed in Example G, read interferences are grouped into 4 distinct groups as discussed in Example I, and P / E cycles are divided into 7 cycles as discussed in Example A, such that 14,000 RNN inference models for RT-W-RD-P / E classifications are stored in step 102.

[0125] Although the above examples A to N and Figures 12A to 12J The output is described as being generated in the form of coefficients from a TVS-RE curve, but alternatively, the output neuron generation indicator is as follows: Figure 4B The output values ​​of the error at different TVSO values ​​are shown.

[0126] The method and apparatus of this invention model multiple factors affecting UBER and generate TVS-RE curves on the flash memory controller. These TVS-RE curves accurately reflect the physical characteristics of the location to be read, the structural characteristics of the location (e.g., word lines and blocks to be read), the current age / physical degradation of the location (e.g., number of P / E cycles), and the current transient characteristics of the location (e.g., closed-block read interference and closed-block retention time). Because the generated TVS-RE curve accurately represents the factors affecting UBER, the TVSO value generated corresponding to the minimum value of the TVS-RE curve will be the appropriate TVSO value for performing the read (corresponding to a TVSO value that provides the minimum number of errors during device characterization). Using the TVSO value to perform the read results in a reduction in the number of read errors at the flash memory controller. During the lifespan of the SSD, the reduction in the number of read errors by the method and apparatus of this invention effectively maintains the UBER at an acceptable level.

[0127] Furthermore, numerous specific details have been set forth in this specification for the purpose of explanation in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the invention. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention, and it should be understood that other embodiments can be utilized, and logical, mechanical, electrical, and other changes can be made, without departing from the scope of the invention.

Claims

1. A method for reading a flash memory device, comprising: Multiple regressive neural network (RNN) inference models are stored on a flash controller connected to the flash memory device or on a memory device connected to the flash controller. The corresponding RNN inference model among the multiple RNN inference models identifies threshold voltage offset read error curves for different periods during the lifetime of the flash memory device. The identification of the corresponding threshold voltage offset read error curve depends on the number of errors of the threshold voltage offset compensation value. Monitoring the operation of the flash memory device to identify one or more usage characteristic values ​​of the flash memory device, the monitoring including monitoring the operation of the flash memory device to determine the current cycle in the lifetime of the flash memory device; Select one RNN inference model from the plurality of RNN inference models that corresponds to the current period determined in the lifetime of the flash memory device; Execute a neural network operation of a selected RNN inference model from the stored RNN inference models to generate a threshold voltage offset read error curve corresponding to the identified usage characteristic value, wherein the input to the neural network operation includes one or more identified usage characteristic values; Identify the threshold voltage offset compensation value corresponding to the minimum value of the generated threshold voltage offset read error curve; as well as The read of the flash memory device is performed using a threshold voltage offset read at the identified threshold voltage offset compensation value.

2. The method of claim 1, wherein the input for the operation of the neural network includes one or more values ​​identifying the page to be read.

3. The method of claim 1, wherein the current cycle in the lifetime of the flash memory device corresponds to the current number of programming and erasing cycles.

4. The method of claim 1, wherein the operation of monitoring the flash memory device includes counting the number of programming and erasing cycles of corresponding blocks of the flash memory device, and the determined current cycle in the lifetime of the flash memory device includes the counted number of programming and erasing cycles of blocks containing pages to be read.

5. The method of claim 1, wherein the operation of monitoring the flash memory device includes counting the number of closed block reads, and the input for the neural network operation includes a value indicating the counted number of closed block reads containing a block of pages to be read.

6. The method of claim 1, wherein the operation of monitoring the flash memory device includes determining a closed block retention time, and the input for the neural network operation includes a value indicating the determined closed block retention time of a block containing a page to be read.

7. The method of claim 1, further comprising: The RNN inference model is generated and configured to perform regression to identify coefficients of at least one of the threshold voltage offset readout error curves.

8. A method for reading a flash memory device, comprising: Generate a regressive neural network (RNN) inference model, the RNN inference model being used to perform regression to identify coefficients of at least one threshold voltage offset readout error curve, the at least one threshold voltage offset readout error curve being identified depending on the number of errors of the threshold voltage offset compensation value, wherein generating the RNN inference model includes: It receives one or more configuration files that define the initial RNN inference model as input; Receive one or more threshold voltage offset read test result sets as input; Create a threshold voltage offset reading training dataset, a threshold voltage offset reading validation dataset, and a threshold voltage offset reading test dataset based on one or more threshold voltage offset reading test result sets received as input; A smoothing function is performed on the threshold voltage offset readout training dataset to obtain a smoothed threshold voltage offset readout training dataset; The initial RNN inference model is trained using the smoothed threshold voltage offset to read the training dataset to obtain the trained RNN inference model; The trained RNN inference model was validated using the threshold voltage offset readout validation dataset. The trained and validated RNN inference model was tested using the threshold voltage offset to read the test dataset. The trained, validated, and tested RNN inference model is stored on a flash controller connected to the flash memory device or on a memory device connected to the flash memory controller; Monitor the operation of the flash memory device to identify one or more usage characteristic values ​​of the flash memory device; The stored RNN inference model is executed to generate a threshold voltage offset read error curve corresponding to the identified usage characteristic value. The input to the neural network operation includes one or more identified usage characteristic values. Identify the threshold voltage offset compensation value corresponding to the minimum value of the generated threshold voltage offset readout error curve; and The read of the flash memory device is performed using a threshold voltage offset read at the identified threshold voltage offset compensation value.

9. A method for reading a flash memory device, comprising: Multiple regressive neural network (RNN) inference models are stored on a flash controller coupled to the flash memory device or on a memory device coupled to the flash controller. A corresponding RNN inference model among the multiple RNN inference models identifies one or more threshold voltage offset read error curves. These one or more threshold voltage offset read error curves identify the number of errors dependent on the threshold voltage offset compensation value. Each RNN inference model corresponds to one or more groups of factors selected from the following: a set of word lines of the flash memory device, a set of blocks of the flash memory device, a time period, a set of read interferences, and a set of retention times. Monitor the operation of the flash memory device to identify one or more usage characteristic values ​​of the flash memory device; Select one of the multiple RNN inference models; Perform a neural network operation on a selected RNN inference model to generate a threshold voltage offset readout error curve corresponding to the identified usage characteristic values, wherein the input to the neural network operation includes one or more identified usage characteristic values; Identify the threshold voltage offset compensation value corresponding to the minimum value of the generated threshold voltage offset read error curve; as well as The read of the flash memory device is performed using a threshold voltage offset read at the identified threshold voltage offset compensation value.

10. The method of claim 9, wherein the input for the operation of the neural network includes one or more values ​​identifying the page to be read.

11. A flash memory controller, the flash memory controller including write circuitry, read circuitry configured to perform reads of a flash memory device using a threshold voltage offset read operation, and a decoder configured to decode the result of the reads, the flash memory controller comprising: A status circuit for monitoring the operation of the flash memory device to identify one or more usage characteristic values; A data storage device for storing multiple regressive neural network (RNN) inference models, the multiple RNN inference models identifying one or more threshold voltage offset read error curves, the one or more threshold voltage offset read error curves identifying the number of errors depending on the threshold voltage offset compensation value, and a corresponding RNN inference model in the multiple RNN inference models corresponding to one or more groups of factors, the one or more groups of factors being selected from a set of: a set of word lines of the flash memory device, a set of blocks of the flash memory device, a time period, a set of read interferences, and a set of retention times; A neural processor, comprising at least one of software, hardware, and firmware, coupled to the data storage device, the neural processor being configured to select one of a plurality of stored RNN inference models and execute a neural network operation on the selected RNN inference model to generate a threshold voltage offset read error curve corresponding to identified usage characteristic values, wherein the input to the neural network operation includes one or more identified usage characteristic values; and A minimum functional module, comprising at least one of software, hardware, and firmware, is coupled to the neural processor. The minimum functional module is configured to determine a minimum value for a generated threshold voltage offset readout error curve and identify a threshold voltage offset compensation value corresponding to the determined minimum value. The threshold voltage offset read operation is performed using the identified threshold voltage offset compensation value.

12. The flash memory controller of claim 11, wherein a corresponding RNN inference model among the plurality of RNN inference models identifies a threshold voltage offset read error curve for a word line group of the flash memory device. The neural processor is used to select one of the plurality of RNN inference models in accordance with the word line of the read to be performed.

13. The flash memory controller of claim 11, wherein a corresponding RNN inference model among the plurality of RNN inference models identifies a threshold voltage offset read error curve for a block group of the flash memory device. The neural processor is used to select one of the plurality of RNN inference models corresponding to the block of the read to be performed.

14. The flash memory controller of claim 11, wherein the corresponding RNN inference model among the plurality of RNN inference models identifies a threshold voltage offset read error curve for a read interference group of the flash memory device. The neural processor is used to select one of the plurality of RNN inference models from multiple closed block reads corresponding to blocks of the page to be read.

15. A solid-state drive (SSD), comprising: Multiple flash memory devices; A flash memory controller, coupled to the plurality of flash memory devices, includes: A writing circuit, the writing circuit being used to program codewords into the respective flash memory devices of the plurality of flash memory devices; A read circuit, the read circuit being configured to perform read operations on the plurality of flash memory devices using a threshold voltage offset read operation; A decoder, connected to the reading circuit, is used to decode the reading result; A status circuit is used to monitor the operation of the plurality of flash memory devices to identify one or more usage characteristic values ​​for each flash memory device. A data storage device for storing multiple regressive neural network (RNN) inference models, the multiple RNN inference models identifying one or more threshold voltage offset read error curves, the one or more threshold voltage offset read error curves identifying the number of errors depending on the threshold voltage offset compensation value, and the corresponding RNN inference model in the multiple RNN inference models identifying the threshold voltage offset read error curve for one or more of a set of word lines of the flash memory device, a set of blocks of the flash memory device, a time period, a set of read interferences and a set of retention times; A neural processor, comprising at least one of software, hardware, and firmware, coupled to the data storage device, wherein the neural processor selects one of a plurality of stored RNN inference models and executes a neural network operation on the selected RNN inference model to generate a threshold voltage offset read error curve corresponding to identified usage characteristic values, wherein the input to the neural network operation includes one or more identified usage characteristic values; and A minimum functional module, comprising at least one of software, hardware, and firmware, is coupled to the neural processor. The minimum functional module is configured to determine a minimum value for a generated threshold voltage offset readout error curve and identify a threshold voltage offset compensation value corresponding to the determined minimum value. The threshold voltage offset read operation is performed using the identified threshold voltage offset compensation value.

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