Semiconductor device and power conversion device

Abstract

Mitigation of adverse effects on a surface electrode of a semiconductor device. The semiconductor device includes a first well region formed in a surface layer of an upper surface of a drift layer; a gate electrode; a second well region surrounding the first well region in plan view; and a gate portion covering an interlayer insulating film and the gate electrode exposed from the interlayer insulating film. Furthermore, an outer end portion of the gate electrode is farther from the first well region than an outer end portion of the gate portion and is closer to the first well region than an outer end portion of the second well region.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a power conversion device. Background Art

[0002] Conventionally, in vertical semiconductor devices used in power devices, a technique is known to provide a p-type guard ring region (termination well region) in the so-called termination region at the periphery of an n-type semiconductor layer in order to ensure withstand voltage performance (see, for example, Patent Document 1).

[0003] In a semiconductor device having a guard ring region, the electric field generated when a reverse voltage is applied to the main electrode of the semiconductor device is mitigated by the depletion layer formed by the pn junction between the n-type semiconductor layer and the p-type guard ring region, thereby avoiding avalanche breakdown below the rated voltage or damage at the electrode end.

[0004] In the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) disclosed in Patent Document 1, p + The impurity region is formed so as to extend further outward than the gate pad electrode and gate wiring electrode located at the outermost periphery of the surface electrode. In semiconductor devices such as MOSFETs, the surface electrode is typically covered with a surface protective film such as polyimide, excluding the area where wire bonding is performed. The surface electrode is sometimes sealed with a sealing material such as gel.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2008-85188 Summary of the Invention

[0008] Surface protective films such as polyimide and sealing materials such as gel are susceptible to moisture in high-humidity environments. Moisture contained in the surface protective films and sealing materials can adversely affect the surface electrodes. Specifically, this moisture can dissolve the surface electrodes, or the reaction between the moisture and the surface electrodes can cause precipitation reactions.

[0009] In such cases, the surface electrode and the surface protective film may crack, or the surface protective film may peel off at the interface between the surface electrode and the surface protective film. If the voids formed by the cracks in the surface electrode and the surface protective film or the peeling of the surface protective film act as leakage paths, there is a possibility that the insulation reliability of the semiconductor device will be impaired.

[0010] The technology disclosed in this specification has been accomplished in view of the above-described problems, and is a technology for alleviating adverse effects on surface electrodes of semiconductor devices.

[0011] The first scheme of the technology disclosed in the present application specification relates to a semiconductor device, comprising: a drift layer of a first conductivity type; a first well region of a second conductivity type, formed in a surface layer of an upper surface of the drift layer; a source region of a first conductivity type, formed in a surface layer of the first well region; a gate insulating film, formed in contact with the first well region sandwiched by the source region and the drift layer; a gate electrode, formed in contact with the gate insulating film; an interlayer insulating film, covering the gate electrode; a source electrode, covering the source region exposed on the upper surface of the drift layer and the interlayer insulating film; a back electrode, formed on the lower surface side of the drift layer; a second well region of a second conductivity type, formed in the surface layer of the upper surface of the drift layer, and Surrounding the first well region when viewed from above; and a field insulating film partially covering the second well region, the gate electrode is formed to extend to the upper surface of the field insulating film, the interlayer insulating film partially covers the gate electrode in the upper surface of the field insulating film, the semiconductor device also has a gate portion, which overlaps with the field insulating film when viewed from above, is separated from the source electrode, and covers the interlayer insulating film and the gate electrode exposed from the interlayer insulating film, and the end in the direction of leaving the first well region when viewed from above is set as an outer end, the outer end of the gate electrode is farther away from the first well region than the outer end of the gate portion, and is closer to the first well region than the outer end of the second well region.

[0012] The second scheme of the technology disclosed in this application specification relates to a power conversion device, comprising: a conversion circuit, which has the above-mentioned semiconductor device, and the conversion circuit converts the input power and outputs it; a drive circuit, which outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit, which outputs a control signal for controlling the drive circuit to the drive circuit.

[0013] A first aspect of the technology disclosed in the specification of the present application relates to a semiconductor device including: a drift layer of a first conductivity type; a first well region of a second conductivity type formed in a surface layer of an upper surface of the drift layer; a source region of the first conductivity type formed in a surface layer of the first well region; a gate insulating film formed in contact with the first well region sandwiched by the source region and the drift layer; a gate electrode formed in contact with the gate insulating film; an interlayer insulating film covering the gate electrode; a source electrode covering the source region exposed on the upper surface of the drift layer and the interlayer insulating film; a back surface electrode formed on a lower surface side of the drift layer; a second well region of the second conductivity type formed in the surface layer of the upper surface of the drift layer and surrounding the first well region in plan view; and a field insulating film partially covering the second well region, the gate electrode being formed so as to extend to an upper surface of the field insulating film, the interlayer insulating film partially covering the gate electrode in the upper surface of the field insulating film, the semiconductor device further including a gate portion overlapping the field insulating film in plan view, being separated from the source electrode, and covering the interlayer insulating film and the gate electrode exposed from the interlayer insulating film, an outer end portion of the gate portion being set in a direction away from the first well region in plan view, the outer end portion of the gate electrode being farther away from the first well region than the outer end portion of the gate portion and being closer to the first well region than the outer end portion of the second well region. According to such a structure, it is possible to suppress generation of an exudate at an end portion of the gate portion in a terminal region. Therefore, cracking or peeling of the gate portion is suppressed. Thus, it is possible to suppress an increase in leakage current and gas discharge caused by cracking or peeling of the gate portion, so it is possible to improve insulation reliability of the semiconductor device.

[0014] A second aspect of the technology disclosed in the specification of the present application relates to a power conversion device including: a conversion circuit having the semiconductor device described above and converting input power to output; a drive circuit outputting a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit outputting a control signal for controlling the drive circuit to the drive circuit. According to such a structure, it is possible to moderate electric field concentration at an outer peripheral end portion of a gate portion of a semiconductor device provided in a power conversion device, suppress an increase in leakage current and gas discharge caused by cracking or peeling of the gate portion, so it is possible to improve insulation reliability of the power conversion device.

[0015] In addition, the objects, features, means, and advantages of the technology associated with the specification of the present application will become more apparent from the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1It is a cross-sectional view showing an example of the structure of a MOSFET as a semiconductor device according to the embodiment.

[0017] Figure 2 This is a top view of the MOSFET.

[0018] Figure 3 is shown formed as Figure 1 1 is a cross-sectional view showing an example of the structure of a cell which is the minimum unit structure of a MOSFET, in a region inside the active region shown.

[0019] Figure 4 It is a cross-sectional view showing a modified example of the structure of the MOSFET according to the embodiment.

[0020] Figure 5 It is a cross-sectional view showing a modified example of the structure of the MOSFET according to the embodiment.

[0021] Figure 6 It is a cross-sectional view showing a modified example of the structure of the MOSFET according to the embodiment.

[0022] Figure 7 It is a plan view showing an example of the structure of a MOSFET as a semiconductor device according to the embodiment.

[0023] Figure 8 It is a cross-sectional view of a MOSFET.

[0024] Figure 9 It is a plan view showing an example of the structure of a MOSFET as a semiconductor device according to the embodiment.

[0025] Figure 10 It is a cross-sectional view of a MOSFET.

[0026] Figure 11 It is a plan view showing an example of the structure of a MOSFET as a semiconductor device according to the embodiment.

[0027] Figure 12 It is a cross-sectional view of a MOSFET.

[0028] Figure 13 This is a diagram conceptually showing an example of the configuration of a power conversion system including a power conversion device according to an embodiment.

[0029] (Explanation of Symbols)

[0030] 1: drift layer; 2: termination well region; 3: low concentration well region; 4: field insulation film; 6: surface protective film; 8: back electrode; 9: element well region; 11: source region; 12: gate insulation film; 13, 113, 313, 413: gate electrode; 14, 114, 214, 314, 414: interlayer insulation film; 19: contact region; 20: high concentration portion; 30: epitaxial substrate; 31: single crystal substrate; 32: epitaxial layer; 50: surface electrode; 51: source electrode; 52, 252, 352, 452: gate portion; 52p, 152p: gate pad; 52w, 252w, 352w, 452w: gate wiring; 100, 200, 300, 400: MOSFET; 2100: power supply; 2200: power conversion device; 2201: conversion circuit; 2202: drive circuit; 2203: control circuit; 2300: load. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, detailed features and the like are also shown for the purpose of technical explanation, but they are examples, and all of them are not necessarily essential features for making the embodiments practicable.

[0032] In the following description, "active region" of a semiconductor device means a region through which a main current flows when the semiconductor device is in an on state, and "termination region" of the semiconductor device means a region around the active region. In addition, "outer side" of the semiconductor device means a direction from a central portion toward an outer peripheral portion of the semiconductor device, and "inner side" of the semiconductor device means a direction opposite to the "outer side". In addition, the conduction type of impurities will be described assuming that "first conduction type" is n-type and "second conduction type" is p-type, but it can be opposite, assuming that "first conduction type" is p-type and "second conduction type" is n-type.

[0033] In addition, the term "MOS" has been used as a term indicating a stacked structure of metal-oxide-semiconductor, using the initials of Metal-Oxide-Semiconductor. However, particularly in a field effect transistor having a MOS structure (hereinafter, simply referred to as "MOS transistor"), the material of the gate insulation film or the gate electrode is improved in view of recent integration or improvement of manufacturing processes. For example, in the MOS transistor, polysilicon is used as the material of the gate electrode instead of metal mainly in view of forming the source-drain self-aligned. In addition, a material having a high dielectric constant is used in the gate insulation film in view of improving the electrical characteristics, but the material is not necessarily limited to an oxide.

[0034] Therefore, the term "MOS" is not necessarily limited to metal-oxide-semiconductor stacked structures, and this applies throughout this specification. That is, based on common technical knowledge, "MOS" is defined not only as an abbreviation for Metal-Oxide-Semiconductor but also broadly encompasses conductor-insulator-semiconductor stacked structures.

[0035] In addition, in the following description, even if it is described as "on (upper surface) of A" and "covering -", it does not prevent the presence of spacers between the components. For example, even if it is described as "B provided on (upper surface) of A" or "B covering A", other components may be provided between A and B. In addition, in the following description, sometimes the terms "upper", "lower", "left", "right", "side", "bottom", "front", or "back" are used to imply specific positions or directions, but these terms are used for convenience of description and have nothing to do with the directions in actual use.

[0036] The accompanying drawings are schematic diagrams, and for ease of explanation, some structures may be omitted or simplified as appropriate. Furthermore, the sizes and positions of structures shown in different drawings are not necessarily accurately depicted and may be modified as appropriate. Furthermore, in drawings such as top views that are not cross-sectional views, hatching may be added to facilitate understanding of the embodiments.

[0037] In the following description, the same components are denoted by the same reference numerals and their names and functions are the same, and therefore, detailed description thereof may be omitted to avoid duplication.

[0038] In the following description, when a certain component is described as “having,” “including,” or “having,” it is not intended to be an exclusive expression excluding the presence of other components unless otherwise specified.

[0039] In the following description, even when ordinal numbers such as "first" or "second" are used, these terms are merely examples used appropriately to facilitate understanding of the contents of the embodiment and are not limited to the order that can be generated by these ordinal numbers.

[0040] In addition, in the descriptions recorded below, expressions indicating equal states, such as "same", "equal", "uniform" or "homogeneous", unless otherwise specified, include situations where a strictly equal state is indicated and situations where a difference occurs within a tolerance or a range that can achieve the same degree of function.

[0041] <First embodiment>

[0042] Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described.

[0043] <Regarding the Structure of Semiconductor Device>

[0044] Figure 1 : is a cross-sectional view showing an example of the structure of a MOSFET 100 as a semiconductor device according to this embodiment. Figure 2 is a top view of MOSFET 100. Figure 2 The cross section of line A-A' is Figure 1 In addition, Figure 3 is shown formed as Figure 1 The cross-sectional view of the structure of the unit cell UC as the minimum unit structure of the MOSFET 100 in the inner region RI of the active region is shown. In the inner region RI of the MOSFET 100, a plurality of Figure 3 The unit UC is shown. Figure 1 The structure shown on the left end of is the outermost unit UC in the inner region RI.

[0045] like Figure 1 For example, MOSFET 100 is formed using an epitaxial substrate 30 composed of a single crystal substrate 31 and an epitaxial layer 32 formed on the upper surface of the single crystal substrate 31. The single crystal substrate 31 is a semiconductor substrate composed of n-type (first conductivity type) silicon carbide (SiC), and the epitaxial layer 32 is an n-type semiconductor layer composed of SiC epitaxially grown on the upper surface of the single crystal substrate 31. In other words, MOSFET 100 is a SiC-MOSFET. In this embodiment, an epitaxial substrate 30 having a 4H polytype is used.

[0046] A p-type (second conductivity type) element well region 9 is selectively formed on the surface portion of the upper surface of the epitaxial layer 32 in the active region (i.e., inner region RI). Furthermore, an n-type source region 11 and a p-type contact region 19 having a higher impurity concentration than the element well region 9 are selectively formed on the surface portion of the element well region 9.

[0047] A p-type termination well region 2 is selectively formed in the surface portion of the upper surface of the epitaxial layer 32 in the termination region (i.e., the outer region RO surrounding the inner region RI) so as to surround the active region (i.e., surround the device well region 9 in a plan view). A p-type high-concentration portion 20 having a relatively high impurity concentration is formed in the surface portion of the termination well region 2. High-concentration portion 20 is not limited to p-type and may also be n-type.

[0048] Figure 4 : is a cross-sectional view showing a modified example of the structure of the MOSFET of this embodiment. Figure 4For example, a p-type low-concentration well region 3 is provided on the periphery of the termination well region 2. The low-concentration well region 3 is formed in the surface layer of the upper surface of the drift layer 1 and surrounds the termination well region 2 when viewed from above. Furthermore, the impurity concentration of the low-concentration well region 3 is lower than that of the termination well region 2. Alternatively, multiple low-concentration well regions 3 may be provided circumferentially, spaced apart from each other.

[0049] like Figure 1 as well as Figure 4 For example, the n-type region of the epitaxial layer 32, excluding the aforementioned impurity regions (element well region 9, source region 11, contact region 19, termination well region 2, and low-concentration well region 3), is the drift layer 1 through which current flows due to drift. The impurity concentration of the drift layer 1 is lower than that of the single crystal substrate 31. Therefore, the single crystal substrate 31 has a lower resistivity than the drift layer 1. Here, the impurity concentration of the drift layer 1 is, for example, 1×10 14 / cm 3 Above and 1×10 17 / cm 3 the following.

[0050] The termination well region 2 is a frame-shaped (ring-shaped) region surrounding the active region in a plan view, and functions as a so-called guard ring. Figure 1 as well as Figure 4 For example, the inner (inner peripheral) end of the termination well region 2 is used as a boundary, the inner side is defined as an inner region RI as an active region, and the outer side is defined as an outer region RO as a termination region.

[0051] like Figure 1 as well as Figure 4 For example, a gate insulating film 12 is formed on the upper surface S2 of the epitaxial substrate 30 in the active region so as to span the device well region 9, which is sandwiched between the source region 11 and the drift layer 1 when viewed from above. Furthermore, a gate electrode 13 is formed on the upper surface of the gate insulating film 12. The surface portion of the device well region 9 covered by the gate insulating film 12 and the gate electrode 13, that is, the portion of the device well region 9 sandwiched between the source region 11 and the drift layer 1, is the channel region that forms an inversion channel when the MOSFET 100 is in the on state.

[0052] In the active region, the gate electrode 13 is covered by an interlayer insulating film 14, and a source electrode 51 is formed on the upper surface of the interlayer insulating film 14. Furthermore, the interlayer insulating film 14 contains, for example, boron or phosphorus. Therefore, the gate electrode 13 and the source electrode 51 are electrically insulated by the interlayer insulating film 14.

[0053] The source electrode 51 is connected to the source region 11 and the contact region 19 via contact holes formed in the interlayer insulating film 14 and the gate insulating film 12. The source electrode 51 and the contact region 19 form an ohmic contact. Furthermore, a surface protective film 6 is formed to cover the source electrode 51, the gate pad 52p, and the exposed portion of the interlayer insulating film 14 not covered by the source electrode 51 and the gate pad 52p. Furthermore, a back surface electrode 8 is formed on the lower surface S1 of the epitaxial substrate 30, functioning as a drain electrode.

[0054] like Figure 1 as well as Figure 4 For example, the gate insulating film 12, gate electrode 13, interlayer insulating film 14, and a portion of the source electrode 51 in the inner region RI extend across the boundary between the inner region RI and the outer region RO and into the outer region RO. The source electrode 51 extended to the outer region RO is connected to the high-concentration portion 20 of the termination well region 2 via a contact hole formed in the interlayer insulating film 14 to form an ohmic contact or a Schottky contact.

[0055] A field insulating film 4 having a thickness thicker than the gate insulating film 12 is provided on the upper surface S2 of the epitaxial substrate 30 in the termination region. Furthermore, a portion of the gate electrode 13, which is extended to the outer region RO, is supported on the upper surface of the field insulating film 4 and is disposed above the termination well region 2 via the gate insulating film 12 or the field insulating film 4.

[0056] Field insulating film 4 covers a portion of termination well region 2 and extends beyond the outer periphery of termination well region 2 to the outside of termination well region 2. Furthermore, field insulating film 4 is not provided in inner region RI. In other words, field insulating film 4 has an opening that includes inner region RI in a plan view.

[0057] In this embodiment, the interlayer insulating film 14 covering the gate electrode 13 extends to the outside of the termination well region 2 and is formed on the upper surface of the field insulating film 4 .

[0058] Furthermore, along Figure 2 A gate pad 52p is formed in the terminal region at the position of the AA' line. The gate pad 52p is formed on the upper surface of the interlayer insulating film 14 covering the gate electrode 13 extended to the outer region RO, and is connected to the gate electrode 13 via a contact hole formed in the interlayer insulating film 14.

[0059] Figure 5 1 is a cross-sectional view showing a modified example of the structure of the MOSFET of this embodiment. The above-mentioned contact hole may be formed in multiples or in a plurality of ways. Figure 5 For example, a contact hole is formed in the interlayer insulating film 114 at the outermost periphery of the gate pad 152 p , and the gate pad 152 p and the gate electrode 13 are connected at the outermost periphery of the gate pad 152 p .

[0060] In addition, if Figure 2 For example, gate wiring 52w connected to gate pad 52p extends to the center of MOSFET 100. Gate pad 52p is arranged to be partially surrounded by source electrode 51 (entering a region surrounded by a region where source electrode 51 is formed) in a plan view.

[0061] The gate portion 52 (i.e., the gate pad 52p and the gate wiring 52w) functions as an electrode that receives a gate control signal for suppressing the electrical path between the source electrode 51 and the back electrode 8. The gate portion 52 (i.e., the gate pad 52p and the gate wiring 52w) is separated from the source electrode 51 and is also electrically insulated from the source electrode 51.

[0062] exist Figure 1 、 Figure 4 as well as Figure 5 In the figure, the field insulating film 4 is formed outside the connection portion between the high-concentration portion 20 of the termination well region 2 and the source electrode 51. However, the field insulating film 4 may be formed inside the connection portion between the high-concentration portion 20 and the source electrode 51. In this case, the source electrode 51 is connected to the high-concentration portion 20 of the termination well region 2 via a contact hole that penetrates both the interlayer insulating film 14 and the field insulating film 4.

[0063] In the MOSFET 100 of this embodiment, Figure 2 At the position of the AA' line, the outer peripheral end of the gate electrode 13 is located between the outer peripheral end of the gate pad 52p (or the gate pad 152p) and the outer peripheral end of the terminal well region 2. Figure 2 The position of the A-A' line can also be in all areas of the peripheral end of the gate pad 52p (or gate pad 152p), and the peripheral end of the gate electrode 13 is located between the peripheral end of the gate pad 52p (or gate pad 152p) and the peripheral end of the terminal well region 2.

[0064] Figure 6 : is a cross-sectional view showing a modified example of the structure of the MOSFET of this embodiment. Figure 6 For example, the gate electrode 113 may not necessarily be formed in the entire area below the gate pad 52p. The gate electrode 113 is formed at a position corresponding to the outer peripheral end of the gate pad 52p, but is not formed at a position corresponding to other parts of the gate pad 52p (i.e., an opening is formed when viewed from above). An interlayer insulating film 214 is formed in this area. The gate electrode 113 is formed at Figure 6 A position not shown in the figure is connected to the gate pad 52p or the gate wiring 52w.

[0065] In the present embodiment, SiC is assumed as the material of the epitaxial substrate 30 . However, the material of the epitaxial substrate 30 is not limited to SiC, and may be other wide-bandgap semiconductors such as gallium nitride (GaN).

[0066] In addition, the semiconductor device of this embodiment may be a transistor other than a MOSFET, such as a JFET (Junction FET) or an IGBT (Insulated Gate Bipolar Transistor). Furthermore, in this embodiment, a planar transistor is exemplified, but a trench transistor may also be used.

[0067] <About Operation of Semiconductor Device>

[0068] about Figure 1 as well as Figure 2 The operation of MOSFET 100 according to the embodiment shown as an example is divided into two states, which will be described below.

[0069] The first state is a state in which a positive voltage above the threshold is applied to the gate electrode 13, and this state is hereinafter referred to as the "on-state". When the MOSFET 100 is in the on-state, an inversion channel is formed in the channel region. The inversion channel becomes a path for electrons, which are carriers, to flow between the source region 11 and the drift layer 1. In the on-state, when a high voltage is applied to the back electrode 8 with the potential of the source electrode 51 as a reference, current flows through the single crystal substrate 31 and the drift layer 1. At this time, the voltage between the source electrode 51 and the back electrode 8 is called the "on-voltage", and the current flowing between the source electrode 51 and the back electrode 8 is called the "on-current". The on-current flows only in the active region where the channel exists, and does not flow to the terminal region.

[0070] The second state is a state in which a voltage less than the threshold value is applied to the gate electrode 13. This state is hereinafter referred to as the "off state." When the MOSFET 100 is in the off state, an inversion channel is not formed in the channel region. Therefore, no on-current flows. Therefore, when a high voltage is applied between the source electrode 51 and the back electrode 8, this high voltage is maintained. At this time, the voltage between the gate electrode 13 and the source electrode 51 is very small compared to the voltage between the source electrode 51 and the back electrode 8, so a high voltage is also applied between the gate electrode 13 and the back electrode 8.

[0071] In the off state, even in the termination region, a high voltage is applied between each of gate pad 52p, gate wiring 52w, and gate electrode 13, and back electrode 8. However, just as electrical contact is formed between device well region 9 and source electrode 51 in the active region, electrical contact is formed between termination well region 2 and source electrode 51 in the termination region. Therefore, a high electric field is prevented from being applied to gate insulating film 12, field insulating film 4, and interlayer insulating film 14.

[0072] When MOSFET 100 is in the off state, a large electric field is applied near the interfaces of the pn junctions between the drift layer 1 and the device well region 9, and between the drift layer 1 and the termination well region 2. The voltage applied to the back electrode 8 when this electric field reaches the critical electric field and causes avalanche breakdown is defined as the maximum voltage (avalanche voltage) of MOSFET 100. Typically, the rated voltage of MOSFET 100 is determined so that it can be used within a voltage range that does not cause avalanche breakdown.

[0073] In the off state of the MOSFET 100, the depletion layer extends from the pn junction interface between the drift layer 1 and the element well region 9 and between the drift layer 1 and the termination well region 2 toward the single crystal substrate 31 ( Figure 1 ) and the direction toward the periphery of the drift layer 1 ( Figure 1 The depletion layer expands from the inner region RI toward the outer region RO in the drift layer 1. Furthermore, the depletion layer also expands from the pn junction interface between the drift layer 1 and the termination well region 2 into the termination well region 2, and the extent of this expansion greatly depends on the impurity concentration of the termination well region 2. Specifically, when the impurity concentration of the termination well region 2 is increased, the expansion of the depletion layer in the termination well region 2 is suppressed, and the front end of the depletion layer is located near the boundary between the termination well region 2 and the drift layer 1.

[0074] Furthermore, the position of the leading end of the depletion layer can be checked by TCAD (Technology CAD) simulation, etc. In the outer region RO, a potential difference occurs from the outer periphery toward the center of the epitaxial layer 32 in the depletion layer (depleted region) within the epitaxial layer 32. Furthermore, the non-depleted region within the termination well region 2 can be considered to be at approximately the same potential as the source electrode 51.

[0075] In semiconductor devices using materials such as SiC, which has a particularly high electric field strength in the off state, if the end of the electrode material is located in a depleted portion of the upper surface of the epitaxial layer 32, a high electric field may be applied to the end of the electrode material, sometimes causing damage to the electrode material. Therefore, in MOSFET 100 of this embodiment, the impurity concentration of the termination well region 2 is generally set to an impurity concentration that does not deplete the interior of the termination well region 2 below the gate electrode 13 and the gate pad 52p.

[0076] Here, consider the situation where MOSFET100 is in the off state under high humidity. The sealing resin provided in a manner covering the semiconductor chip may contain moisture. For example, when the surface protection film 6 (upper surface film) is composed of a resin material with high water absorption such as polyimide, the surface protection film 6 contains a large amount of moisture under high humidity, and there is a possibility that this moisture reaches the upper surface of the epitaxial layer 32 and the gate pad 52p. In addition, even if the surface protection film 6 is composed of a material with high moisture resistance such as SiN, cracks are easily generated in the surface protection film 6 due to stress generated in the process, and there is a possibility that the epitaxial layer 32 and the gate pad 52p are exposed to moisture via these cracks.

[0077] In this state, when a voltage is applied to the MOSFET 100 in the off state, the end of the epitaxial layer 32 functions as an anode in the termination region, and the gate pad 52p functions as a cathode. Furthermore, when a negative voltage is applied to the gate pad 52p relative to the source electrode 51, the gate pad 52p also functions as a cathode for the source electrode 51 and the termination well region 2 connected to the source electrode 51. Near the gate pad 52p, which functions as a cathode, moisture causes an oxygen reduction reaction represented by the following equation (1) and a hydrogen generation reaction represented by equation (2).

[0078] [Formula 1]

[0079] O2+2H2O+4e - →4OH - ···(1)

[0080] [Formula 2]

[0081] H2O+e - →OH - +1 / 2H2···(2)

[0082] As a result, the concentration of hydroxide ions increases near gate pad 52p. These hydroxide ions chemically react with gate pad 52p. For example, if gate pad 52p is made of aluminum, the aluminum may be converted into aluminum hydroxide due to the chemical reaction.

[0083] The reaction between aluminum and hydroxide ions is accelerated by the surrounding electric field strength. A potential gradient is generated in the depleted region within the semiconductor layer. Therefore, in MOSFET 100 of this embodiment, a potential gradient occurs along upper surface S2 in the region where the depletion layer reaches the upper surface of epitaxial substrate 30. This potential gradient is transferred to field insulating film 4 and interlayer insulating film 14 formed on upper surface S2 of epitaxial layer 32, generating an electric field around the end of gate pad 52p. Consequently, when the electric field strength at the end of gate pad 52p exceeds a certain level, a reaction to form aluminum hydroxide is initiated, and this reaction is accelerated as the electric field strength increases.

[0084] Furthermore, when a negative voltage is applied to gate pad 52p relative to source electrode 51, the electric field intensity below gate pad 52p increases due to the potential difference between gate pad 52p and termination well region 2. In particular, electric field concentration tends to occur at the outer peripheral edge of the lower portion of gate pad 52p, accelerating the formation of aluminum hydroxide.

[0085] When the interlayer insulating film 14 contains boron (B) or phosphorus (P), as the concentration increases, the interlayer insulating film 14 tends to absorb moisture. For example, when the boron concentration exceeds 2% or the phosphorus concentration exceeds 5%, this tendency becomes significant, accelerating the formation of aluminum hydroxide.

[0086] As described above, when aluminum hydroxide is generated on the surface of gate pad 52p, the gate pad 52p and surface protection film 6 may be cracked or peeled off due to volume expansion, forming a cavity on the upper surface of interlayer insulating film 14. Moisture entering the cavity may cause excessive leakage current to flow, or gas discharge may be caused in the cavity, potentially destroying MOSFET 100.

[0087] In contrast, in the MOSFET 100 of the present embodiment, Figure 2 At the position of the line AA′, the outer peripheral end of the gate pad 52 p is located further inward than the outer peripheral end of the termination well region 2 , so the electric field intensity around the gate pad 52 p is relaxed.

[0088] Here, if the impurity concentration of termination well region 2 is kept above a certain level, the depletion layer in termination well region 2 hardly expands, effectively reducing the electric field intensity around gate pad 52p. Therefore, the generation of aluminum hydroxide can be effectively suppressed.

[0089] Furthermore, if Figure 4For example, by providing a low-concentration well region 3 in the peripheral portion of the terminal well region 2, the electric field strength around the gate pad 52p can be effectively mitigated, and the electric field strength of the epitaxial layer 32 around the peripheral end portion of the terminal well region 2 can be mitigated, thereby increasing the avalanche voltage of the MOSFET 100.

[0090] Furthermore, in the MOSFET 100 of this embodiment, Figure 2 At the position of line A-A', the outer peripheral end of gate electrode 13 is located further outward than the outer peripheral end of gate pad 52p. Therefore, when a negative voltage is applied to gate pad 52p relative to source electrode 51, a potential difference between gate pad 52p and termination well region 2 occurs only within field insulating film 4 below gate electrode 13 in the region between gate pad 52p and termination well region 2. Consequently, the electric field strength around gate pad 52p is mitigated.

[0091] Thus, in the MOSFET 100 of this embodiment, the gate electrode 13 is provided below the outer peripheral end of the gate pad 52p where the electric field is easily concentrated. This can alleviate the electric field concentration at the lower outer peripheral end of the gate pad 52p and suppress the generation of aluminum hydroxide.

[0092] On the other hand, when gate electrode 13 is not provided between gate pad 52p and termination well region 2, the potential difference between gate pad 52p and termination well region 2 is shared by field insulating film 4 and interlayer insulating film 14. Therefore, the electric field strength inside field insulating film 4 is relaxed, thereby suppressing a decrease in yield caused by dust or the like entering during the manufacture of MOSFET 100.

[0093] Therefore, if Figure 6 For example, in addition to being formed in the area spanning the outer peripheral end of the gate pad 52p, the gate electrode 113 is opened in a portion of the lower part of the gate pad 52p, thereby alleviating the electric field concentration at the outer peripheral end of the lower part of the gate pad 52p where the electric field is easily concentrated, and also suppressing the reduction in yield.

[0094] In addition, not limited to Figure 2 The position of the A-A' line is such that, in all areas of the peripheral end portion of the gate pad 52p, the peripheral end portion of the gate electrode 13 is located between the peripheral end portion of the gate pad 52p and the peripheral end portion of the terminal well region 2. This can alleviate the electric field concentration in all areas of the peripheral end portion of the lower part of the gate pad 52p and suppress the generation of aluminum hydroxide.

[0095] In addition, if Figure 5For example, a contact hole is formed in the interlayer insulating film 114 at the outermost periphery of the gate pad 152p, and the gate pad 152p and the gate electrode 13 are connected via the contact hole at the outermost periphery of the gate pad 152p, thereby fully suppressing the electric field concentration at the outer peripheral end of the lower part of the gate pad 152p and suppressing the generation of aluminum hydroxide.

[0096] As described above, in MOSFET 100 of this embodiment, the formation of aluminum hydroxide at the end of gate pad 52p (or gate pad 152p) is suppressed. As a result, an increase in leakage current and gas discharge caused by cracking or peeling of gate pad 52p (or gate pad 152p) and surface protection film 6 can be suppressed.

[0097] <About the Manufacturing Method of Semiconductor Device>

[0098] Next, a method for manufacturing MOSFET 100 as a semiconductor device according to this embodiment will be described.

[0099] First, prepare a relatively high concentration (n + A low-resistance single crystal substrate 31 containing n-type impurities (a polytype) is used. In this embodiment, the single crystal substrate 31 is a SiC substrate having a 4H polytype and a separation angle of 4° or 8°.

[0100] Next, by epitaxially growing SiC on the upper surface of the single crystal substrate 31, an n-type SiC with an impurity concentration of 1×10 14 / cm 3 Above and 1×10 17 / cm 3 The following epitaxial layer 32 is formed. In this way, the epitaxial substrate 30 composed of the single crystal substrate 31 and the epitaxial layer 32 can be obtained.

[0101] Next, by repeating a photolithography step of forming a resist mask and an ion implantation step of implanting ions using the resist mask as an implantation mask, an impurity region is formed in the surface portion of the epitaxial layer 32. Thus, the termination well region 2, the element well region 9, the contact region 19, the high-concentration portion 20, and the source region 11 are formed in the surface portion of the epitaxial layer 32. Similarly, the low-concentration well region 3 can also be formed.

[0102] In the ion implantation process, N (nitrogen) or the like is used as an n-type impurity, and Al or B or the like is used as a p-type impurity. Furthermore, the termination well region 2 and the element well region 9 can be formed simultaneously in the same ion implantation process. Furthermore, the contact region 19 and the high-concentration portion 20 of the termination well region 2 can be formed simultaneously in the same ion implantation process.

[0103] The impurity concentration of the device well region 9 is, for example, 1.0×10 18 / cm 3 Above and 1.0×10 20 / cm 3 the following.

[0104] The impurity concentration of the source region 11 and the impurity concentration of the contact region 19 are higher than the impurity concentration of the device well region 9, for example, 1.0×10 19 / cm 3 Above and 1.0×10 22 / cm 3 the following.

[0105] The terminal well region 2 needs to have an impurity content that makes it difficult for the depletion layer to extend into the interior of the terminal well region 2 in the off state. Therefore, the dose of the terminal well region 2 is preferably 2.0×10 13 / cm 2 Above, for example, 5.0×10 13 / cm 2 .

[0106] The dose of the low concentration well region 3 is preferably 0.5×10 13 / cm 2 Above and 5×10 13 / cm 2 Below, for example, it becomes 1.0×10 13 / cm 2 .

[0107] The implantation energy of ion implantation is, for example, 100 keV or more and 700 keV or less when the impurity is Al. In this case, the above-mentioned dose [cm -2 ] The impurity concentration of the low-concentration well region 3 is converted to 1×10 17 / cm 3 Above and 1×10 19 / cm 3 In addition, when the impurity is N, the implantation energy of the ion implantation is, for example, 20 keV or more and 300 keV or less.

[0108] Thereafter, annealing is performed using a heat treatment apparatus at a temperature of 1500° C. or higher. This activates the impurities added by ion implantation.

[0109] Next, a SiO2 film having a thickness of not less than 0.5 μm and not more than 2 μm is formed on the upper surface S2 of the epitaxial substrate 30, for example, by chemical vapor deposition (CVD). The SiO2 film is then patterned using photolithography and etching to form the field insulating film 4. The field insulating film 4 is patterned to partially cover the termination well region 2 and extend beyond the end of the termination well region 2 to the outer periphery of the termination well region 2.

[0110] Next, the upper surface of the epitaxial layer 32 not covered by the field insulating film 4 is thermally oxidized to form a SiO2 film serving as the gate insulating film 12. Furthermore, a conductive polysilicon film is formed on the upper surface of the gate insulating film 12 by a reduced pressure CVD method. Furthermore, the polysilicon film is patterned by photolithography and etching to form the gate electrode 13.

[0111] At this time, in the termination region, the gate electrode 13 is formed to be supported on the upper surface of the field insulating film 4 , and the outer peripheral end of the gate electrode 13 is located further inward than the outer peripheral end of the termination well region 2 .

[0112] After that, a SiO2 film is formed as the interlayer insulating film 14 by CVD. Furthermore, contact holes are formed by photolithography and etching, penetrating the gate insulating film 12 and the interlayer insulating film 14 and reaching the contact region 19, the source region 11, and the high-concentration portion 20 in the terminal region. In this process, a contact hole is formed in the terminal region, penetrating the interlayer insulating film 14 and reaching the gate electrode 13.

[0113] The interlayer insulating film 14 can also be boron phosphorsilicate glass (BPSG), which is SiO2 doped with boron and phosphorus, or a multilayer film containing SiO2, SiN, and BPSG. For example, BPSG can be annealed at 1000°C to smoothen the step shape. This improves the embedding of the electrode into the contact hole, enabling the formation of fine structures.

[0114] Next, a material layer for the surface electrode 50, including the source electrode 51 and the gate portion 52 (i.e., the gate pad 52p and the gate wiring 52w), is formed on the upper surface S2 of the epitaxial substrate 30 by sputtering or evaporation. Furthermore, a material layer for the back surface electrode 8 is formed on the lower surface S1 of the epitaxial substrate 30 by the same method.

[0115] The surface electrode 50 is formed of, for example, a base layer containing any one or more of Ti, Ni, W, Mo and Au for making electrical contact with the epitaxial substrate 30 and a thick film layer containing any one or more of Al and Cu or an Al alloy such as Al-Si.

[0116] As the material of the back electrode 8, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au can be used. Alternatively, a silicide film may be formed in advance by heat treatment on the portion of the epitaxial substrate 30 that contacts the surface electrode 50 or the back electrode 8. Furthermore, the back electrode 8 may be formed at the end of all the steps.

[0117] Next, the surface electrode 50 is patterned by a photolithography process and an etching process, and then the surface electrode 50 is separated into a source electrode 51 and a gate portion 52 (ie, a gate pad 52p and a gate wiring 52w).

[0118] At this time, along Figure 2 The outer peripheral end of the gate pad 52p is formed in a manner such that it is located on the inner peripheral side than the outer peripheral end of the gate electrode 13 at the position of the AA' line. Figure 2 The position of the AA′ line may be located in the entire region of the outer peripheral end of the gate pad 52 p , and the outer peripheral end of the gate pad 52 p may be formed so as to be located further inward than the outer peripheral end of the gate electrode 13 .

[0119] Finally, a portion of the surface electrode 50 is opened, and a surface protection film 6 is formed so as to cover the end of the surface electrode 50 and at least a portion of the outer region RO of the epitaxial substrate 30. Figure 1 Example MOSFET100.

[0120] The surface protection film 6 is processed into a desired shape by, for example, a polyimide coating process, a photolithography process, and an etching process. Alternatively, the surface protection film 6 may be formed by depositing a SiN film by CVD and performing photolithography and etching processes.

[0121] As described above, according to MOSFET 100 of this embodiment, the formation of aluminum hydroxide at the end of gate pad 52p in the terminal region can be suppressed. Consequently, cracking or peeling of gate pad 52p and surface protection film 6 is suppressed. Consequently, an increase in leakage current and gas discharge caused by cracking or peeling of gate pad 52p and surface protection film 6 can be suppressed, thereby improving the insulation reliability of MOSFET 100.

[0122] <Second embodiment>

[0123] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals, and their detailed descriptions are omitted as appropriate.

[0124] <Regarding the Structure of Semiconductor Device>

[0125] Figure 7 : is a top view showing an example of the structure of a MOSFET 200 as a semiconductor device according to this embodiment. Figure 8 is a cross-sectional view of MOSFET 200 . Figure 8 Along with Figure 7 The cross section of the BB' line is equivalent.

[0126] In the MOSFET 200 of the present embodiment, a gate wiring 252 w connected to the gate pad 52 p is provided in the terminal region (ie, the outer region RO) so as to surround the source electrode 51 in a plan view.

[0127] The gate wiring 252w is connected to the gate electrode 13 via a contact hole formed in the interlayer insulating film 314. Alternatively, the gate pad 52p may be provided at a corner of the terminal region (ie, a bent portion of the gate wiring 252w in a plan view).

[0128] In the MOSFET 200 of this embodiment, similarly to the MOSFET 100 of the first embodiment, in the region having the gate pad 52p, the outer peripheral end of the gate electrode 13 is located between the outer peripheral end of the gate pad 52p and the outer peripheral end of the termination well region 2. Figure 7 At the position of the BB' line, the outer peripheral end of the gate electrode 13 is located between the outer peripheral end of the gate wiring 252w and the outer peripheral end of the terminal well region 2. Figure 7 The position of the BB′ line may be located in all regions of the outer peripheral end of the gate wiring 252 w , and the outer peripheral end of the gate electrode 13 may be located between the outer peripheral end of the gate wiring 252 w and the outer peripheral end of the termination well region 2 .

[0129] In this embodiment, it is also possible to Figure 4 The p-type low-concentration well region 3 , which has an impurity concentration lower than that of the termination well region 2 , is provided on the outer periphery of the termination well region 2 .

[0130] In addition, in this embodiment, it is also possible to Figure 5 As in the illustrated gate pad 152 p , a contact hole is formed in the interlayer insulating film 314 at the outermost periphery of the gate wiring 252 w , and the gate wiring 252 w and the gate electrode 13 are connected at the outermost periphery of the gate wiring 252 w .

[0131] The other structures are the same as those of MOSFET 100 in the first embodiment.

[0132] <About Operation of Semiconductor Device>

[0133] Next, the operation of MOSFET 200 according to this embodiment will be described.

[0134] In the MOSFET 200 of this embodiment, as in the first embodiment, it operates in an on state where a positive voltage equal to or higher than the threshold is applied to the gate electrode 13 and in an off state where a voltage less than the threshold is applied to the gate electrode 13 .

[0135] In semiconductor devices using materials such as SiC, which exhibits particularly high electric field strength in the off state, if the end of the electrode material is located in a depleted portion of the upper surface of epitaxial layer 32, a high electric field may also be generated at the end of the electrode material, sometimes causing damage to the electrode material. Therefore, in MOSFET 200 of this embodiment, the impurity concentration of the termination well region 2 is generally set to an impurity concentration that does not deplete the interior of the termination well region 2 below gate electrode 13, gate pad 52p, and gate wiring 252w.

[0136] Here, consider the case where MOSFET 200 is turned off under high humidity. The sealing resin provided to cover the semiconductor chip may contain moisture. For example, if the surface protection film 6 is made of a highly water-absorbent resin material such as polyimide, the surface protection film 6 may contain a large amount of moisture under high humidity, and there is a possibility that this moisture may reach the upper surface of the epitaxial layer 32, the gate pad 52p, and the gate wiring 252w. In addition, even if the surface protection film 6 is made of a highly moisture-resistant material such as SiN, cracks are likely to form in the surface protection film 6 due to stress generated during the process, and there is a possibility that the epitaxial layer 32, the gate pad 52p, and the gate wiring 252w may be exposed to moisture through these cracks.

[0137] In this state, when a voltage is applied to the off-state MOSFET 200, the end of the epitaxial layer 32 functions as an anode in the termination region, and the gate portion 252 (gate pad 52p and gate wiring 252w) functions as a cathode. Furthermore, when a negative voltage is applied to the gate portion 252 (gate pad 52p and gate wiring 252w) relative to the source electrode 51, the gate portion 252 (gate pad 52p and gate wiring 252w) also functions as a cathode for the source electrode 51 and the termination well region 2 connected to the source electrode 51. In the vicinity of the gate portion 252 (gate pad 52p and gate wiring 252w), which functions as a cathode, the concentration of hydroxide ions increases, similar to the first embodiment. These hydroxide ions chemically react with the gate portion 252 (gate pad 52p and gate wiring 252w). For example, when the gate portion 252 (gate pad 52 p and gate wiring 252 w ) is made of aluminum, the aluminum may become aluminum hydroxide due to a chemical reaction.

[0138] The reaction between aluminum and hydroxide ions is accelerated by the surrounding electric field strength. A potential gradient is generated in the depleted region within the semiconductor layer. Therefore, in the MOSFET 200 of this embodiment, a potential gradient is generated along the upper surface S2 in the region where the depletion layer reaches the upper surface of the epitaxial substrate 30. This potential gradient is transferred to the field insulating film 4 and the interlayer insulating film 314 formed on the upper surface S2 of the epitaxial layer 32, generating an electric field around the end of the gate portion 252 (gate pad 52p and gate wiring 252w). Consequently, when the electric field strength at the end of the gate portion 252 (gate pad 52p and gate wiring 252w) exceeds a certain level, a reaction to generate aluminum hydroxide is initiated, and this reaction is accelerated as the electric field strength increases.

[0139] Furthermore, when a negative voltage is applied to gate portion 252 (gate pad 52p and gate wiring 252w) relative to source electrode 51, the electric field intensity below gate portion 252 (gate pad 52p and gate wiring 252w) increases due to the potential difference between gate portion 252 (gate pad 52p and gate wiring 252w) and termination well region 2. In particular, electric field concentration tends to occur at the outer peripheral edge below gate pad 52p, accelerating the formation of aluminum hydroxide.

[0140] As described above, when aluminum hydroxide is generated on the surface of gate portion 252 (gate pad 52p and gate wiring 252w), volume expansion causes cracks or peeling of gate pad 52p, gate wiring 252w, and surface protection film 6, forming voids on the upper surface of interlayer insulating film 314. Moisture entering these voids may cause excessive leakage current to flow, or gas discharge may occur in these voids, potentially damaging MOSFET 200.

[0141] In contrast, in MOSFET 200 of the present embodiment, similarly to MOSFET 100 in the first embodiment, the outer peripheral end of the gate portion 252 (gate pad 52p and gate wiring 252w) is located further inward than the outer peripheral end of the terminal well region 2, so the electric field strength around the gate portion 252 (gate pad 52p and gate wiring 252w) is mitigated.

[0142] Here, if the impurity concentration of the termination well region 2 is kept above a certain level, the depletion layer in the termination well region 2 will hardly expand, effectively mitigating the electric field strength around the gate portion 252 (gate pad 52p and gate wiring 252w). Therefore, the generation of aluminum hydroxide can be effectively suppressed.

[0143] Furthermore, if Figure 4 For example, by providing a low-concentration well region 3 in the peripheral portion of the terminal well region 2, the electric field strength around the gate portion 252 (gate pad 52p and gate wiring 252w) can be effectively mitigated, and the electric field strength of the epitaxial layer 32 in the peripheral end portion of the terminal well region 2 can be mitigated, so that the avalanche voltage of MOSFET200 can be increased.

[0144] Furthermore, in the MOSFET 200 of the present embodiment, similarly to the case of the MOSFET 100 of the first embodiment, the outer peripheral end of the gate electrode 13 is located further toward the outer peripheral side than the outer peripheral end of the gate pad 52p. Figure 7 At the position of the line BB′, the outer peripheral end of the gate electrode 13 is located on the outer peripheral side than the outer peripheral end of the gate wiring 252 w.

[0145] When a negative voltage is applied to gate portion 252 (gate pad 52p and gate wiring 252w) relative to source electrode 51, a potential difference between gate portion 252 (gate pad 52p and gate wiring 252w) and termination well region 2 occurs only within field insulating film 4 below gate electrode 13, in a region where gate electrode 13 is provided between gate portion 252 (gate pad 52p and gate wiring 252w) and termination well region 2. Therefore, the electric field intensity around gate portion 252 (gate pad 52p and gate wiring 252w) is mitigated.

[0146] Thus, in the MOSFET 200 of the present embodiment, the gate electrode 13 exists at the lower portion of the outer peripheral end portion of the gate portion 252 (the gate pad 52p and the gate wiring 252w) where the electric field is likely to concentrate, and thus the electric field concentration at the outer peripheral end portion of the lower portion of the gate portion 252 (the gate pad 52p and the gate wiring 252w) can be moderated, and the generation of aluminum hydroxide can be suppressed.

[0147] In addition, the position of the gate electrode 13 is not limited to the position along the B-B' line, but in the case where the outer peripheral end portion of the gate electrode 13 is positioned between the outer peripheral end portion of the gate wiring 252w and the outer peripheral end portion of the termination well region 2 in all regions of the outer peripheral end portion of the gate wiring 252w, the electric field concentration can be moderated in all regions of the outer peripheral end portion of the lower portion of the gate wiring 252w, and the generation of aluminum hydroxide can be suppressed. Figure 7 In addition, as described above, in the MOSFET 200 of the present embodiment, the generation of aluminum hydroxide at the end portion of the gate portion 252 (the gate pad 52p and the gate wiring 252w) is suppressed. As a result, the increase in the leakage current and the gas discharge caused by the breakage or peeling of the gate portion 252 and the surface protective film 6 can be suppressed.

[0148] Figure 5 In the example, a contact hole is formed in the interlayer insulating film 314 at the position of the outermost periphery of the gate pad 52p and the gate wiring 252w, and the gate pad 52p and the gate wiring 252w and the gate electrode 13 are connected via the contact hole at the outermost periphery of the gate pad 52p and the gate wiring 252w, and thus the electric field concentration at the outer peripheral end portion of the lower portion of the gate pad 52p and the gate wiring 252w can be sufficiently suppressed, and the generation of aluminum hydroxide can be suppressed.

[0149] As described above, in the MOSFET 200 of the present embodiment, the generation of aluminum hydroxide at the end portion of the gate portion 252 (the gate pad 52p and the gate wiring 252w) is suppressed. As a result, the increase in the leakage current and the gas discharge caused by the breakage or peeling of the gate portion 252 and the surface protective film 6 can be suppressed.

[0150] <Method for manufacturing semiconductor device>

[0151] Next, the method for manufacturing the MOSFET 200 of the present embodiment as a semiconductor device will be described.

[0152] As for the MOSFET 200 of the present embodiment, as well as in the case of the MOSFET 100 in the first embodiment, it is manufactured by repeating a photolithography process of forming a resist mask, an ion implantation process of performing ion implantation with the resist mask as an implant mask, and further a film formation process, an etching process.

[0153] ​In the MOSFET 200 of this embodiment, when the surface electrode 50 is patterned and separated into the source electrode 51 and the gate portion 252 (the gate pad 52p and the gate wiring 252w), the outer peripheral end of the gate pad 52p is formed so as to be located further inward than the outer peripheral end of the gate electrode 13. Figure 7 At the position of the BB' line, the outer peripheral end of the gate wiring 252w is formed so as to be located on the inner peripheral side than the outer peripheral end of the gate electrode 13. Figure 7 The position of the BB′ line may be located in all regions of the outer peripheral end portion of the gate wiring 252 w , and the outer peripheral end portion of the gate wiring 252 w may be formed so as to be located further inward than the outer peripheral end portion of the gate electrode 13 .

[0154] The other steps are the same as those of the MOSFET 100 in the first embodiment.

[0155] As described above, according to MOSFET 200 of this embodiment, the formation of aluminum hydroxide at the end of gate portion 252 (gate pad 52p and gate wiring 252w) in the terminal region can be suppressed. Consequently, cracking or peeling of gate pad 52p, gate wiring 252w, and surface protective film 6 is suppressed. Consequently, an increase in leakage current and gas discharge caused by cracking or peeling of gate pad 52p, gate wiring 252w, and surface protective film 6 can be suppressed, thereby improving the insulation reliability of MOSFET 200.

[0156] <Third embodiment>

[0157] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals, and their detailed descriptions are omitted as appropriate.

[0158] <Regarding the Structure of Semiconductor Device>

[0159] Figure 9 : is a top view showing an example of the structure of a MOSFET 300 as a semiconductor device according to this embodiment. Figure 10 is a cross-sectional view of MOSFET 300 . Figure 10 Along with Figure 9 The cross section of the C-C' line is equivalent.

[0160] In the MOSFET 300 of this embodiment, in the terminal region (i.e., the outer region RO), the gate wiring 352w is separated from the gate pad 52p and is arranged in a manner that is partially surrounded by the source electrode 51 when viewed from above (in a manner that enters the area surrounded by the area where the source electrode 51 is formed, similar to the gate pad 52p).

[0161] The gate wiring 352w is connected to the gate electrode 313 via a contact hole formed in the interlayer insulating film 314. The gate electrode 313 is partially opened in a region between the gate pad 52p and the gate wiring 352w.

[0162] In addition, the gate electrode 313 is along Figure 9 The terminal region of the CC' line is not connected to the gate pad 52p. The gate electrode 313 is connected to the gate pad 52p along the CC' line. Figure 9 The gate pad 52p and the gate wiring 352w are electrically connected to each other via a contact hole formed in the interlayer insulating film 314 in a portion of the terminal region other than the position of the CC' line. Alternatively, the gate pad 52p may be provided at a corner of the terminal region (i.e., a bent portion of the gate wiring 352w in a plan view).

[0163] Alternatively, a portion of gate electrode 313 may be separated in the terminal region and connected to gate pad 52p and gate wiring 352w via a contact hole formed in interlayer insulating film 314. In this case, gate electrode 313 of unit UC extends to the terminal region but is not connected to gate pad 52p but only to gate wiring 352w.

[0164] In the MOSFET 300 of this embodiment, similarly to the MOSFET 100 of the first embodiment, Figure 9 At the position of the CC' line, the outer peripheral end of the gate electrode 313 is located between the outer peripheral end of the gate pad 52p and the outer peripheral end of the termination well region 2. Furthermore, in a region where the gate pad 52p is not formed, the outer peripheral end of the gate electrode 313 is located between the outer peripheral end of the gate wiring 352w and the outer peripheral end of the termination well region 2, similar to the MOSFET 200 in the second embodiment.

[0165] In addition, not limited to Figure 9 The position of the CC' line may be such that the outer peripheral end of the gate electrode 313 is located between the outer peripheral end of the gate pad 52p and the outer peripheral end of the termination well region 2 in all regions of the outer peripheral end of the gate pad 52p. In addition, in a region where the gate pad 52p is not formed, the outer peripheral end of the gate electrode 313 may be located between the outer peripheral end of the gate wiring 352w and the outer peripheral end of the termination well region 2 in all regions of the outer peripheral end of the gate wiring 352w.

[0166] The gate electrode 313 located below the outer peripheral end portion of the gate pad 52 p may extend from a region connected to the gate pad 52 p or from a region connected to the gate wiring 352 w .

[0167] In this embodiment, it is also possible to Figure 4 The p-type low-concentration well region 3 , which has an impurity concentration lower than that of the termination well region 2 , is provided on the outer periphery of the termination well region 2 .

[0168] In addition, in this embodiment, it is also possible to Figure 5 As shown in the example gate pad 52p, a contact hole is formed in the interlayer insulating film 314 at the outermost position of the gate pad 52p and the gate wiring 352w, and the gate pad 52p and the gate wiring 352w are connected to the gate electrode 313 at the outermost position of the gate pad 52p and the gate wiring 352w.

[0169] In addition, you can also Figure 6 Like the gate electrode 113 exemplified above, the gate electrode 313 is not necessarily provided on the entire region below the gate pad 52 p .

[0170] The other structures are the same as those of the MOSFET 200 in the second embodiment.

[0171] <About Operation of Semiconductor Device>

[0172] Next, the operation of MOSFET 300 according to this embodiment will be described.

[0173] In the MOSFET 300 of this embodiment, as in the first and second embodiments, it operates in an on-state in which a positive voltage greater than a threshold value is applied to the gate electrode 313 and in an off-state in which a voltage less than a threshold value is applied to the gate electrode 313.

[0174] In the MOSFET 300 of this embodiment, the gate electrode 313 is partially open in the area between the gate pad 52p and the gate wiring 352w. Therefore, the gate electrode 313 electrically connecting the gate pad 52p and the gate wiring 352w via the contact hole exists only in a portion of the periphery of the gate pad 52p. In other words, the MOSFET 300 of this embodiment has a built-in parasitic gate resistance based on the gate electrode 313, which suppresses self-oscillation during switching between the on and off states. The resistance value of this parasitic gate resistance can be controlled by changing the shape of the gate electrode 313 electrically connecting the gate pad 52p and the gate wiring 352w via the contact hole.

[0175] In semiconductor devices using materials such as SiC, which exhibits particularly high electric field strength in the off state, if the end of the electrode material is located in a depleted portion of the upper surface of epitaxial layer 32, a high electric field may also be generated at the end of the electrode material, sometimes causing damage to the electrode material. Therefore, in MOSFET 300 of this embodiment, the impurity concentration of termination well region 2 is generally set to an impurity concentration that does not deplete the interior of termination well region 2 below gate electrode 313, gate pad 52p, and gate wiring 352w.

[0176] Here, consider the case where MOSFET 300 is turned off under high humidity. The sealing resin provided to cover the semiconductor chip may contain moisture. For example, if the surface protection film 6 is made of a highly water-absorbent resin material such as polyimide, the surface protection film 6 may contain a large amount of moisture under high humidity, and there is a possibility that this moisture may reach the upper surface of the epitaxial layer 32, the gate pad 52p, and the gate wiring 352w. In addition, even if the surface protection film 6 is made of a highly moisture-resistant material such as SiN, cracks are likely to form in the surface protection film 6 due to stress generated during the process, and there is a possibility that the epitaxial layer 32, the gate pad 52p, and the gate wiring 352w may be exposed to moisture through these cracks.

[0177] In this state, when a voltage is applied to the off-state MOSFET 300, the edge of the epitaxial layer 32 in the termination region functions as an anode, and the gate portion 352 (gate pad 52p and gate wiring 352w) functions as a cathode. Furthermore, when a negative voltage is applied to the gate portion 352 (gate pad 52p and gate wiring 352w) relative to the source electrode 51, the gate portion 352 (gate pad 52p and gate wiring 352w) also functions as a cathode for the source electrode 51 and the termination well region 2 connected to the source electrode 51. Near the gate portion 352 (gate pad 52p and gate wiring 352w), which functions as a cathode, the concentration of hydroxide ions increases, similar to the first embodiment. These hydroxide ions chemically react with the gate portion 352 (gate pad 52p and gate wiring 352w). For example, when the gate portion 352 (gate pad 52 p and gate wiring 352 w ) is made of aluminum, the aluminum may become aluminum hydroxide due to a chemical reaction.

[0178] The reaction of aluminum and hydroxide ions is accelerated according to the strength of the electric field around. In the interior of the semiconductor layer, a potential gradient is generated in the region where depletion occurs, so in the MOSFET 300 of the present embodiment, a potential gradient along the upper surface S2 occurs in the region where the depletion layer reaches the upper surface of the epitaxial substrate 30. This potential gradient is transferred to the field insulating film 4 formed on the upper surface S2 of the epitaxial layer 32 and the interlayer insulating film 314, so an electric field is generated around the end portion of the gate portion 352 (the gate pad 52p and the gate wiring 352w). Thus, when the electric field strength at the end portion of the gate portion 352 (the gate pad 52p and the gate wiring 352w) becomes a certain value or more, a generation reaction of aluminum hydroxide occurs, which is accelerated as the electric field strength increases.

[0179] In addition, in the case where a negative voltage is applied to the gate portion 352 (the gate pad 52p and the gate wiring 352w) with respect to the source electrode 51, the electric field strength of the lower portion of the gate portion 352 (the gate pad 52p and the gate wiring 352w) increases due to the potential difference between the gate portion 352 (the gate pad 52p and the gate wiring 352w) and the termination well region 2. In addition, when the gate voltage fluctuates due to self-oscillation at the time of switching or a sharp change in drain voltage occurs, the electric field strength of the lower portion of the gate portion 352 (the gate pad 52p and the gate wiring 352w) increases. In particular, an electric field concentration is easily caused at the outer peripheral end portion of the lower portion of the gate portion 352 (the gate pad 52p and the gate wiring 352w), and the generation of aluminum hydroxide is accelerated.

[0180] As described above, when aluminum hydroxide is generated on the surface of the gate portion 352 (the gate pad 52p and the gate wiring 352w), cracking or peeling of the gate pad 52p, the gate wiring 352w, and the surface protective film 6 occurs due to volume expansion, and a cavity is formed on the upper surface of the interlayer insulating film 314. Since moisture enters this cavity and flows through the excess leakage current or gas discharge occurs in this cavity, there is a possibility that the MOSFET 300 causes element destruction.

[0181] In contrast, in the MOSFET 300 of the present embodiment, as with the MOSFET 200 in the second embodiment, the outer peripheral end portion of the gate portion 352 (the gate pad 52p and the gate wiring 352w) is located more on the inner peripheral side than the outer peripheral end portion of the termination well region 2, so the electric field strength around the gate portion 352 (the gate pad 52p and the gate wiring 352w) is moderated.

[0182] Here, if the impurity concentration of the termination well region 2 is kept above a certain level, the depletion layer in the termination well region 2 will hardly expand, effectively mitigating the electric field strength around the gate portion 352 (gate pad 52p and gate wiring 352w). Therefore, the generation of aluminum hydroxide can be effectively suppressed.

[0183] Furthermore, MOSFET 300 of this embodiment has a built-in parasitic gate resistor. Therefore, the parasitic gate resistor suppresses self-oscillation during switching between the on and off states, thereby suppressing electric field concentration around gate portion 352 (gate pad 52p and gate wiring 352w) caused by gate voltage fluctuations or sudden changes in drain voltage, thereby suppressing the generation of aluminum hydroxide.

[0184] Furthermore, if Figure 4 For example, by providing a low-concentration well region 3 in the peripheral portion of the terminal well region 2, the electric field strength around the gate portion 352 (gate pad 52p and gate wiring 352w) can be effectively mitigated, and the electric field strength of the epitaxial layer 32 around the peripheral end portion of the terminal well region 2 can be mitigated, thereby increasing the avalanche voltage of the MOSFET 300.

[0185] Furthermore, in the MOSFET 300 of this embodiment, similarly to the case of the MOSFET 100 in the first embodiment, Figure 9 At the position of the CC' line, the outer peripheral end of the gate electrode 313 is located further outward than the outer peripheral end of the gate pad 52p. In addition, in the area where the gate pad 52p is not formed, the outer peripheral end of the gate electrode 313 is located further outward than the outer peripheral end of the gate wiring 352w.

[0186] When a negative voltage is applied to gate portion 352 (gate pad 52p and gate wiring 352w) relative to source electrode 51, a potential difference between gate portion 352 (gate pad 52p and gate wiring 352w) and termination well region 2 occurs only within field insulating film 4 below gate electrode 313, in a region where gate electrode 313 is provided between gate portion 352 (gate pad 52p and gate wiring 352w) and termination well region 2. Therefore, the electric field intensity around gate portion 352 (gate pad 52p and gate wiring 352w) is mitigated.

[0187] Thus, in the MOSFET 300 of this embodiment, a gate electrode 313 is present at the lower portion of the peripheral end portion of the gate portion 352 (gate pad 52p and gate wiring 352w) where the electric field is particularly easily concentrated, thereby alleviating the electric field concentration at the peripheral end portion of the lower portion of the gate portion 352 (gate pad 52p and gate wiring 352w) and suppressing the generation of aluminum hydroxide.

[0188] On the other hand, when gate electrode 313 is not provided between gate pad 52p and termination well region 2, the potential difference between gate pad 52p and termination well region 2 is shared by field insulating film 4 and interlayer insulating film 314. Therefore, the electric field strength inside field insulating film 4 is relaxed, and a decrease in yield caused by dust, etc., that enters during the manufacture of MOSFET 300 can be suppressed.

[0189] In addition, in addition to being formed in the area that spans the outer peripheral end of the gate pad 52p when viewed from above, the gate electrode 313 is opened in a portion of the lower part of the gate pad 52p, thereby alleviating the electric field concentration at the outer peripheral end of the lower part of the gate pad 52p where the electric field is easily concentrated, and also suppressing the reduction in yield.

[0190] In addition, not limited to Figure 9 At the position of the CC' line, if the outer edge of gate electrode 313 is located between the outer edge of gate pad 52p and the outer edge of termination well region 2 in all regions of the outer edge of gate pad 52p, electric field concentration can be relaxed in all regions of the lower outer edge of gate pad 52p, thereby suppressing the generation of aluminum hydroxide. Similarly, in an area where gate pad 52p is not formed, if the outer edge of gate electrode 313 is located between the outer edge of gate wiring 352w and the outer edge of termination well region 2 in all regions of the outer edge of gate wiring 352w, electric field concentration can be relaxed in all regions of the lower outer edge of gate wiring 352w, thereby suppressing the generation of aluminum hydroxide.

[0191] In addition, if Figure 5 For example, a contact hole is formed in the interlayer insulating film 314 at the outermost periphery of the gate pad 52p and the gate wiring 352w, and the gate pad 52p and the gate wiring 352w are connected to the gate electrode 313 via the contact hole at the outermost periphery of the gate pad 52p and the gate wiring 352w, thereby fully suppressing the electric field concentration at the outer peripheral end of the lower part of the gate pad 52p and the gate wiring 352w, and suppressing the generation of aluminum hydroxide.

[0192] As described above, in MOSFET 300 of this embodiment, the formation of aluminum hydroxide is suppressed at the gate pad 52p and at the end of gate wiring 352w in the region where gate pad 52p is not formed. As a result, an increase in leakage current and gas discharge caused by cracking or peeling of gate portion 352 and surface protection film 6 can be suppressed.

[0193] <About the Manufacturing Method of Semiconductor Device>

[0194] Next, a method for manufacturing MOSFET 300 as a semiconductor device according to this embodiment will be described.

[0195] Regarding MOSFET300 of this embodiment, similarly to MOSFET100 in the first embodiment and MOSFET200 in the second embodiment, it is manufactured by repeatedly forming a photolithography process of a resist mask, an ion implantation process of implanting ions using the resist mask as an implantation mask, and then a film forming process and an etching process.

[0196] In MOSFET 300 of this embodiment, a portion of the region between gate pad 52p and gate wiring 352w is opened, and gate electrode 313 is patterned so that gate electrode 313 is not formed. Alternatively, a configuration may be employed in which a portion of gate electrode 313 is removed from the terminal region, so that the gate electrode 313 of each cell UC extends to the terminal region and is connected only to gate wiring 352w, not to gate pad 52p. Furthermore, even when the opening of gate electrode 313 overlaps at least one of gate pad 52p and gate wiring 352w, parasitic gate resistance can be reduced by thinning gate electrode 313.

[0197] In the MOSFET 300 of this embodiment, when the surface electrode 50 is patterned and separated into the source electrode 51 and the gate portion 352 (the gate pad 52p and the gate wiring 352w), Figure 9 At the position of the CC' line, the outer peripheral end of the gate pad 52p is formed so as to be located on the inner peripheral side than the outer peripheral end of the gate electrode 313. Furthermore, in the area where the gate pad 52p is not formed, the outer peripheral end of the gate wiring 352w is formed so as to be located on the inner peripheral side than the outer peripheral end of the gate electrode 313. Figure 9 The position of the C-C' line can also be in all areas of the outer peripheral end of the gate pad 52p and all areas of the outer peripheral end of the gate wiring 352w in the area where the gate pad 52p is not formed, and the outer peripheral end of the gate pad 52p and the gate wiring 352w are formed in a manner that is located closer to the inner side than the outer peripheral end of the gate electrode 313.

[0198] The other steps are the same as those of the MOSFET 100 in the first embodiment.

[0199] As described above, according to the MOSFET 300 of this embodiment, the formation of aluminum hydroxide at the end of the gate portion 352 (gate pad 52p and gate wiring 352w) in the terminal region can be suppressed. Consequently, cracking or peeling of the gate pad 52p, gate wiring 352w, and surface protection film 6 is suppressed. Consequently, an increase in leakage current and gas discharge caused by cracking or peeling of the gate pad 52p, gate wiring 352w, and surface protection film 6 can be suppressed, thereby improving the insulation reliability of the MOSFET 300.

[0200] <Fourth embodiment>

[0201] In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals, and their detailed descriptions are omitted as appropriate.

[0202] <Regarding the Structure of Semiconductor Device>

[0203] Figure 11 : is a top view showing an example of the structure of a MOSFET 400 as a semiconductor device according to this embodiment. Figure 12 is a cross-sectional view of MOSFET 400 . Figure 12 Along with Figure 11 The cross section of the D-D' line is equivalent.

[0204] In the MOSFET 400 of this embodiment, in the terminal region (ie, the outer region RO), the gate wiring 452w is separated from the gate pad 52p and provided so as to surround the source electrode 51 and the gate pad 52p in a plan view.

[0205] The gate wiring 452w is connected to the gate electrode 413 via a contact hole formed in the interlayer insulating film 414. The gate electrode 413 is partially opened in a region between the gate pad 52p and the gate wiring 452w.

[0206] In addition, the gate electrode 413 is along Figure 11 The terminal region of the position of the DD' line is not connected to the gate pad 52p. The gate electrode 413 is connected to the gate pad 52p along the line Figure 11 The gate pad 52p and the gate wiring 452w are electrically connected to a portion of the terminal region other than the position of the DD' line via a contact hole formed in the interlayer insulating film 414. Alternatively, the gate pad 52p may be provided at a corner of the terminal region (i.e., a bent portion of the gate wiring 452w in a plan view).

[0207] Alternatively, a portion of the gate electrode 413 may be separated in the terminal region and connected to the gate pad 52p and the gate wiring 452w via a contact hole formed in the interlayer insulating film 414. In this case, the gate electrode 413 of the unit UC extends to the terminal region but is not connected to the gate pad 52p but only to the gate wiring 452w.

[0208] In the MOSFET 400 of this embodiment, similarly to the MOSFET 200 of the second embodiment, Figure 11 At the position of the line DD′ of FIG. 1 , the outer peripheral end of the gate electrode 413 is located between the outer peripheral end of the gate wiring 452 w and the outer peripheral end of the termination well region 2 .

[0209] In addition, not limited to Figure 11 The position of the DD′ line may be located at all regions of the outer peripheral end of the gate wiring 452 w , and the outer peripheral end of the gate electrode 413 may be located between the outer peripheral end of the gate wiring 452 w and the outer peripheral end of the termination well region 2 .

[0210] The gate electrode 413 located below the outer peripheral end portion of the gate wiring 452w may extend from a region connected to the gate pad 52p or a region connected to the gate wiring 452w.

[0211] In this embodiment, it is also possible to Figure 4 The p-type low-concentration well region 3 , which has an impurity concentration lower than that of the termination well region 2 , is provided on the outer periphery of the termination well region 2 .

[0212] In addition, in this embodiment, it is also possible to Figure 5 As in the illustrated gate pad 52 p , a contact hole is formed in the interlayer insulating film 414 at the outermost periphery of the gate wiring 452 w , and the gate wiring 452 w and the gate electrode 413 are connected at the outermost periphery of the gate wiring 452 w .

[0213] In addition, you can also Figure 6 Like the gate electrode 113 shown as an example, the gate electrode 413 is not necessarily provided on the entire region below the gate pad 52 p .

[0214] The other structures are the same as those of the MOSFET 200 in the second embodiment.

[0215] <About Operation of Semiconductor Device>

[0216] Next, the operation of MOSFET 400 according to this embodiment will be described.

[0217] In the MOSFET 400 of this embodiment, as in the first, second and third embodiments, it operates in an on-state in which a positive voltage greater than a threshold value is applied to the gate electrode 413 and in an off-state in which a voltage less than a threshold value is applied to the gate electrode 413.

[0218] In MOSFET 400 of this embodiment, similar to MOSFET 300, gate electrode 413 is partially open in the region between gate pad 52p and gate wiring 452w. Therefore, gate electrode 413 electrically connecting gate pad 52p and gate wiring 452w via a contact hole exists only in a portion of the periphery of gate pad 52p. In other words, MOSFET 400 of this embodiment has a built-in parasitic gate resistance based on gate electrode 413, which suppresses self-oscillation during switching between the on and off states. The resistance value of this parasitic gate resistance can be controlled by changing the shape of gate electrode 413, which electrically connects gate pad 52p and gate wiring 452w via a contact hole.

[0219] In semiconductor devices using materials such as SiC, which has a particularly high electric field strength in the off state, if the end of the electrode material is located in a depleted portion of the upper surface of the epitaxial layer 32, a high electric field may also be generated at the end of the electrode material, sometimes causing damage to the electrode material. Therefore, in the MOSFET 400 of this embodiment, the impurity concentration of the termination well region 2 is generally set to an impurity concentration that does not deplete the interior of the termination well region 2 below the gate electrode 413, the gate pad 52p, and the gate wiring 452w.

[0220] Here, consider the case where MOSFET 400 is turned off under high humidity. The sealing resin provided to cover the semiconductor chip may contain moisture. For example, if the surface protection film 6 is made of a highly water-absorbent resin material such as polyimide, the surface protection film 6 may contain a large amount of moisture under high humidity, and there is a possibility that this moisture may reach the upper surface of the epitaxial layer 32 and the gate wiring 452w. Furthermore, even if the surface protection film 6 is made of a highly moisture-resistant material such as SiN, cracks may easily form in the surface protection film 6 due to stress generated during the process, and there is a possibility that the epitaxial layer 32 and the gate wiring 452w may be exposed to moisture through these cracks.

[0221] In this state, when a voltage is applied to the off-state MOSFET 400, the edge of the epitaxial layer 32 in the terminal region functions as an anode, and the gate wiring 452w functions as a cathode. Furthermore, when a negative voltage is applied to the gate wiring 452w relative to the source electrode 51, the gate wiring 452w also functions as a cathode for the source electrode 51 and the terminal well region 2 connected to the source electrode 51. Near the gate wiring 452w, which functions as a cathode, the concentration of hydroxide ions increases, similar to the first embodiment. These hydroxide ions chemically react with the gate wiring 452w. For example, if the gate wiring 452w is made of aluminum, the aluminum may be converted into aluminum hydroxide due to the chemical reaction.

[0222] The reaction between aluminum and hydroxide ions is accelerated by the surrounding electric field strength. A potential gradient is generated in the depleted region within the semiconductor layer. Therefore, in the MOSFET 400 of this embodiment, a potential gradient is generated along the upper surface S2 in the region where the depletion layer reaches the upper surface of the epitaxial substrate 30. This potential gradient is transferred to the field insulating film 4 and the interlayer insulating film 414 formed on the upper surface S2 of the epitaxial layer 32, generating an electric field around the end of the gate wiring 452w. Consequently, when the electric field strength at the end of the gate wiring 452w exceeds a certain level, a reaction to form aluminum hydroxide is initiated, and this reaction is accelerated as the electric field strength increases.

[0223] Furthermore, when a negative voltage is applied to the gate wiring 452w relative to the source electrode 51, the electric field intensity at the lower portion of the gate wiring 452w increases due to the potential difference between the gate wiring 452w and the termination well region 2. Furthermore, when the gate voltage fluctuates due to self-oscillation during switching or when a sudden change in drain voltage occurs, the electric field intensity at the lower portion of the gate wiring 452w increases. In particular, electric field concentration tends to occur at the outer peripheral edge of the lower portion of the gate wiring 452w, accelerating the formation of aluminum hydroxide.

[0224] As described above, when aluminum hydroxide forms on the surface of gate wiring 452w, volume expansion causes cracks or peeling of gate wiring 452w and surface protection film 6, forming voids on the upper surface of interlayer insulating film 414. Moisture entering these voids could cause excessive leakage current to flow, or gas discharge could occur in these voids, potentially damaging MOSFET 400.

[0225] In contrast, in the MOSFET 400 of this embodiment, similarly to the MOSFET 200 of the second embodiment, the outer peripheral end of the gate wiring 452 w is located further inward than the outer peripheral end of the termination well region 2 , so the electric field strength around the gate wiring 452 w is relaxed.

[0226] Here, if the impurity concentration of the termination well region 2 is kept above a certain level, the depletion layer in the termination well region 2 hardly expands, and the electric field intensity around the gate wiring 452w can be effectively relaxed. Therefore, the generation of aluminum hydroxide can be effectively suppressed.

[0227] Furthermore, the MOSFET 400 of this embodiment has a built-in parasitic gate resistor. Therefore, the parasitic gate resistor suppresses self-oscillation during switching between the on and off states, thereby suppressing electric field concentration around the gate wiring 452w caused by gate voltage fluctuations or sudden changes in drain voltage, thereby suppressing the generation of aluminum hydroxide.

[0228] Furthermore, if Figure 4 For example, by providing a low-concentration well region 3 in the peripheral portion of the terminal well region 2, the electric field strength around the gate wiring 452w can be effectively mitigated, and the electric field strength of the epitaxial layer 32 around the peripheral end of the terminal well region 2 can be mitigated, thereby increasing the avalanche voltage of the MOSFET 400.

[0229] Furthermore, in the MOSFET 400 of this embodiment, similarly to the case of the MOSFET 200 in the second embodiment, Figure 11 At the position of the line DD′, the outer peripheral end of the gate electrode 413 is located on the outer peripheral side than the outer peripheral end of the gate wiring 452w.

[0230] When a negative voltage is applied to the gate wiring 452w relative to the source electrode 51, a potential difference between the gate wiring 452w and the termination well region 2 occurs only within the field insulating film 4 below the gate electrode 413 in the region between the gate wiring 452w and the termination well region 2. Therefore, the electric field intensity around the gate wiring 452w is reduced.

[0231] Thus, in the MOSFET 400 of this embodiment, the gate electrode 413 is located below the outer peripheral end of the gate wiring 452w where the electric field is easily concentrated, thereby alleviating the electric field concentration at the lower outer peripheral end of the gate wiring 452w and suppressing the generation of aluminum hydroxide.

[0232] On the other hand, when gate electrode 413 is not provided between gate pad 52p and termination well region 2, the potential difference between gate pad 52p and termination well region 2 is shared by field insulating film 4 and interlayer insulating film 414. Therefore, the electric field strength inside field insulating film 4 is relaxed, and a decrease in yield caused by dust, etc., that enters during the manufacture of MOSFET 400 can be suppressed.

[0233] In addition, the gate electrode 413 is opened in a portion of the lower portion of the gate pad 52p in addition to the area formed in the position spanning the outer peripheral end portion of the gate pad 52p when viewed from above, thereby alleviating the electric field concentration at the outer peripheral end portion of the lower portion of the gate pad 52p where the electric field is easily concentrated, and also suppressing the reduction in yield.

[0234] In addition, not limited to Figure 11 The position of the D-D' line is in all areas of the peripheral end of the gate wiring 452w, and when the peripheral end of the gate electrode 413 is located between the peripheral end of the gate wiring 452w and the peripheral end of the terminal well region 2, it is possible to alleviate the electric field concentration in all areas of the peripheral end of the lower part of the gate wiring 452w and suppress the generation of aluminum hydroxide.

[0235] In addition, if Figure 5 For example, a contact hole is formed in the interlayer insulating film 414 at the outermost position of the gate wiring 452w, and the gate wiring 452w and the gate electrode 413 are connected at the outermost portion of the gate wiring 452w, thereby fully suppressing the electric field concentration at the outer peripheral end portion of the lower portion of the gate wiring 452w and suppressing the generation of aluminum hydroxide.

[0236] As described above, in the MOSFET 400 of this embodiment, the generation of aluminum hydroxide at the end of the gate wiring 452w is suppressed. As a result, an increase in leakage current and gas discharge caused by cracking or peeling of the gate wiring 452w and the surface protection film 6 can be suppressed.

[0237] <About the Manufacturing Method of Semiconductor Device>

[0238] Next, a method for manufacturing MOSFET 400 as a semiconductor device according to this embodiment will be described.

[0239] In the MOSFET400 of this embodiment, as with the MOSFET100 in the first embodiment, the MOSFET200 in the second embodiment, and the MOSFET300 in the third embodiment, it is manufactured by repeatedly forming a photolithography process of a resist mask, an ion implantation process of implanting ions using the resist mask as an implantation mask, and then a film forming process and an etching process.

[0240] In the MOSFET 400 of this embodiment, a portion of the region between the gate pad 52p and the gate wiring 452w is opened, and the gate electrode 413 is patterned so that no gate electrode 413 is formed. Alternatively, a configuration may be employed in which a portion of the gate electrode 413 is separated from the terminal region, so that the gate electrode 413 of the unit cell UC extends to the terminal region and is connected only to the gate wiring 452w, not to the gate pad 52p. Furthermore, even when the opening of the gate electrode 413 overlaps at least one of the gate pad 52p and the gate wiring 452w, a parasitic gate resistance can be reduced by thinning the gate electrode 413.

[0241] In the MOSFET 400 of this embodiment, when the surface electrode 50 is patterned and separated into the source electrode 51 and the gate portion 452 (the gate pad 52p and the gate wiring 452w), Figure 11 At the position of the DD' line, the outer peripheral end of the gate wiring 452w is formed so as to be located on the inner peripheral side than the outer peripheral end of the gate electrode 413. Figure 11 The position of the DD′ line may be located in all regions of the outer peripheral end portion of the gate wiring 452 w , and the outer peripheral end portion of the gate wiring 452 w may be formed so as to be located further inward than the outer peripheral end portion of the gate electrode 413 .

[0242] The other steps are the same as those of the MOSFET 100 in the first embodiment.

[0243] As described above, according to the MOSFET 400 of this embodiment, the formation of aluminum hydroxide at the end of the gate wiring 452w in the terminal region can be suppressed. Consequently, cracking or peeling of the gate wiring 452w and the surface protection film 6 is suppressed. Consequently, an increase in leakage current and gas discharge caused by cracking or peeling of the gate wiring 452w and the surface protection film 6 can be suppressed, thereby improving the insulation reliability of the MOSFET 400.

[0244] <Fifth embodiment>

[0245] In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and their detailed descriptions are omitted as appropriate.

[0246] <About the Structure of the Power Converter>

[0247] This embodiment is an example in which the semiconductor device of the above-described embodiment is applied to a power conversion device. The power conversion device to which it is applied is not limited to a specific application, but the following describes a case in which it is applied to a three-phase inverter.

[0248] Figure 13 This is a diagram conceptually showing an example of the configuration of a power conversion system including the power conversion device according to the present embodiment.

[0249] like Figure 13 As an example, the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. Power supply 2100 is a DC power supply and supplies DC power to power conversion device 2200. Power supply 2100 can be configured from various power sources, such as a DC system, a solar cell, or a battery. Furthermore, power supply 2100 can be configured from a rectifier circuit or an AC-DC converter connected to an AC system. Furthermore, power supply 2100 can be configured from a DC-DC converter that converts DC power output from the DC system into a predetermined power.

[0250] Power conversion device 2200 is a three-phase inverter connected between power source 2100 and load 2300 . Power conversion device 2200 converts DC power supplied from power source 2100 into AC power, and supplies the AC power to load 2300 .

[0251] In addition, the power conversion device 2200 is as follows Figure 13 For example, it comprises: a conversion circuit 2201 that converts DC power into AC power and outputs it; a drive circuit 2202 that outputs a drive signal for driving each switching element of the conversion circuit 2201; and a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

[0252] Load 2300 is a three-phase electric motor driven by the AC power supplied from power conversion device 2200. Load 2300 is not limited to a specific application and may be a motor mounted on various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0253] The power converter 2200 is described in detail below. The converter circuit 2201 includes a switching element and a freewheeling diode (not shown). The switching element performs switching operations to convert DC power supplied from the power supply 2100 into AC power, which is then supplied to the load 2300.

[0254] The specific circuit configuration of the conversion circuit 2201 has various examples, but the conversion circuit 2201 of this embodiment is a two-level three-phase full-bridge circuit including six switching elements and six freewheeling diodes connected in anti-parallel to the respective switching elements.

[0255] The semiconductor device described in any of the above-described embodiments is employed in at least one of the switching elements and freewheeling diodes in conversion circuit 2201. Six switching elements are connected in series, with two switching elements each forming upper and lower branches. Each upper and lower branch forms a phase (i.e., U-phase, V-phase, and W-phase) of the full-bridge circuit. The output terminals of each upper and lower branch (i.e., the three output terminals of conversion circuit 2201) are connected to load 2300.

[0256] The drive circuit 2202 generates a drive signal for driving the switching elements of the conversion circuit 2201 and supplies the drive signal to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on a control signal output from the control circuit 2203 described later, the drive signal for turning on the switching element and the drive signal for turning off the switching element are output to the control electrodes of the respective switching elements.

[0257] When the switching element is maintained in the on state, the driving signal is a voltage signal above the threshold voltage of the switching element (i.e., an on signal); when the switching element is maintained in the off state, the driving signal becomes a voltage signal below the threshold voltage of the switching element (i.e., an off signal).

[0258] Control circuit 2203 controls the switching elements of converter circuit 2201 so that the desired power is supplied to load 2300. Specifically, control circuit 2203 calculates the time for which each switching element of converter circuit 2201 should be in the on state (i.e., the on-time) based on the power to be supplied to load 2300. For example, converter circuit 2201 can be controlled using pulse width modulation (PWM) control, which modulates the on-time of the switching elements based on the voltage to be output.

[0259] Furthermore, the control circuit 2203 outputs a control instruction (i.e., a control signal) to the driver circuit 2202 such that, at each point in time, it outputs an on signal to the switching element that is in the on state, and an off signal to the switching element that is in the off state. Based on this control signal, the driver circuit 2202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0260] In the power conversion device 2200 of this embodiment, the semiconductor device according to any of the above-described embodiments is applied as a switching element of the conversion circuit 2201 , so that the on-resistance after a power-on cycle can be stabilized.

[0261] In the power conversion device 2200 of this embodiment, the semiconductor device of the above-described embodiment can be applied as the freewheeling diode of the conversion circuit 2201 .

[0262] Thus, when the semiconductor device according to the above-described embodiment is used in power conversion device 2200, it is typically embedded in a gel or resin. However, even these sealing materials cannot completely block moisture, so it is important to maintain insulation protection of the semiconductor device using the structure shown in the above-described embodiment. By using the semiconductor device structure shown in the above-described embodiment, the reliability of power conversion device 2200 can be improved.

[0263] In addition, in this embodiment, an example of applying the semiconductor device in any of the above-described embodiments in a 2-level three-phase inverter is described, but the application example is not limited to this, and the semiconductor device in any of the above-described embodiments can be applied to various power conversion devices.

[0264] In addition, although a two-level power conversion device is described in this embodiment, the semiconductor device in any of the above-described embodiments can also be applied to a three-level or multi-level power conversion device. In addition, when supplying power to a single-phase load, the semiconductor device in any of the above-described embodiments can also be applied to a single-phase inverter.

[0265] Furthermore, when supplying power to a DC load or the like, the semiconductor device in any of the above-described embodiments can also be applied to a DC-DC converter or an AC-DC converter.

[0266] Furthermore, a power conversion device using a semiconductor device in any of the above-described embodiments is not limited to the case where the load is a motor. For example, it can also be used as a power supply device for an electrical discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system. Furthermore, a power conversion device using a semiconductor device in any of the above-described embodiments can also be used as a power conditioner in, for example, a solar power generation system or a power storage system.

[0267] <About the Manufacturing Method of the Power Converter>

[0268] Next, a method for manufacturing the power conversion device according to this embodiment will be described.

[0269] First, a semiconductor device is manufactured using the manufacturing method described in the above embodiment. Furthermore, a conversion circuit 2201 including the semiconductor device is provided as a power conversion device. The conversion circuit 2201 is a circuit for converting input power and outputting it.

[0270] Furthermore, a drive circuit 2202 is provided as a component of the power conversion device. Drive circuit 2202 is a circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device. Furthermore, a control circuit 2203 is provided as a component of the power conversion device. Control circuit 2203 is a circuit for outputting a control signal for controlling drive circuit 2202 to drive circuit 2202.

[0271] The semiconductor switching elements used in the above-described embodiments are not limited to those formed of a silicon (Si) semiconductor. For example, the semiconductor switching elements may be formed of a non-Si semiconductor material having a wider band gap than that of a Si semiconductor.

[0272] Examples of non-Si semiconductor materials, namely wide bandgap semiconductors, include silicon carbide, gallium nitride-based materials, and diamond.

[0273] Switching elements made of wide-bandgap semiconductors can be used even in high-voltage regions where unipolar operation of Si semiconductors is difficult, significantly reducing switching losses during switching operations. Consequently, power loss can be significantly reduced.

[0274] Furthermore, switching elements made of wide-bandgap semiconductors have low power loss and high heat resistance. Therefore, when configuring a power module with a cooling unit, the heat sink fins can be miniaturized, further miniaturizing the semiconductor module.

[0275] Furthermore, switching elements made of wide-bandgap semiconductors are suitable for high-frequency switching operations. Therefore, when used in converter circuits requiring high frequencies, the increased switching frequency can also reduce the size of reactors and capacitors connected to the converter circuit.

[0276] Therefore, even when the semiconductor switching element in the above-described embodiment is a switching element made of a wide-bandgap semiconductor such as silicon carbide, the same effects can be obtained.

[0277] <Regarding the Effects Produced by the Embodiments Described Above>

[0278] Next, examples of the effects produced by the above-described embodiments are shown. In addition, in the following description, the effects are described based on the specific structures exemplified in the above-described embodiments, but they can also be replaced with other specific structures exemplified in the present specification within the scope of producing the same effects.

[0279] Furthermore, this substitution may be performed across multiple embodiments. In other words, the same effects may be produced by combining various configurations exemplified in different embodiments.

[0280] According to the embodiment described above, the semiconductor device includes a drift layer 1 of a first conductivity type (n-type), a first well region of a second conductivity type (p-type), an n-type source region 11, a gate electrode, an interlayer insulating film, a source electrode 51, a back electrode 8, a p-type second well region, a field insulating film 4, and a gate portion. Here, the first well region corresponds to, for example, the element well region 9. Furthermore, the gate electrode corresponds to, for example, any one of the gate electrodes 13, 113, 313, and 413 (hereinafter, for convenience, these may be referred to as corresponding). Furthermore, the interlayer insulating film corresponds to, for example, any one of the interlayer insulating films 14, 114, 214, and 414 (hereinafter, for convenience, these may be referred to as corresponding). Furthermore, the second well region corresponds to, for example, the termination well region 2. Furthermore, the gate portion corresponds to, for example, any one of gate portion 52, gate portion 252, gate portion 352, and gate portion 452 (hereinafter, for convenience, any one of these may be described as corresponding). The device well region 9 is formed in the surface layer of the upper surface of the drift layer 1. The source region 11 is formed in the surface layer of the device well region 9. The gate insulating film 12 is formed in contact with the device well region 9 sandwiched between the source region 11 and the drift layer 1. The gate electrode 13 is formed in contact with the gate insulating film 12. The interlayer insulating film 14 covers the gate electrode 13. The source electrode 51 covers the source region 11 exposed on the upper surface of the drift layer 1 and the interlayer insulating film 14. The back electrode 8 is formed on the lower surface side of the drift layer 1. The termination well region 2 is formed in the surface layer of the upper surface of the drift layer 1 and surrounds the device well region 9 when viewed from above. The field insulating film 4 partially covers the termination well region 2. Furthermore, the gate electrode 13 is formed so as to extend to the upper surface of the field insulating film 4. Furthermore, the interlayer insulating film 14 partially covers the gate electrode 13 on the upper surface of the field insulating film 4. Furthermore, the semiconductor device includes a gate portion 52. Gate portion 52 overlaps with the field insulating film 4 in a plan view, is spaced apart from the source electrode 51, and covers the interlayer insulating film 14 and the gate electrode 13 exposed from the interlayer insulating film 14. Furthermore, when the end in the direction away from the device well region 9 in a plan view is defined as the outer end, the outer end of the gate electrode 13 is farther away from the device well region 9 than the outer end of the gate portion 52, and is closer to the device well region 9 than the outer end of the termination well region 2.

[0281] This structure can alleviate electric field concentration at the outer peripheral end of gate portion 52, thereby suppressing the formation of precipitates at the end of gate portion 52 in the terminal region. Consequently, cracking or peeling of gate portion 52 is suppressed. Consequently, an increase in leakage current and gas discharge caused by cracking or peeling of gate portion 52 can be suppressed, thereby improving the insulation reliability of MOSFET 100.

[0282] Furthermore, when other structures exemplified in the present specification are appropriately added to the above-mentioned structure, that is, when other structures not mentioned as the above-mentioned structure in the present specification are appropriately added, the same effects can be produced.

[0283] Furthermore, according to the embodiment described above, the outer end of the gate electrode 13, which is formed to extend to the upper surface of the field insulating film 4, is located farther from the device well region 9 than the outer end of the gate portion 52, and closer to the device well region 9 than the outer end of the termination well region 2, all around the device well region 9. This structure can alleviate electric field concentration in the entire region around the outer peripheral end of the lower portion of the gate portion 52, thereby suppressing the generation of precipitates such as aluminum hydroxide.

[0284] Furthermore, according to the embodiment described above, an opening is formed in gate electrode 113, which is formed to extend to the upper surface of field insulating film 4. This structure allows gate electrode 113 to be located below the outer peripheral edge of gate pad 52p, where electric field concentration is particularly likely. This alleviates electric field concentration at the outer peripheral edge below gate pad 52p, thereby suppressing the generation of aluminum hydroxide. On the other hand, gate electrode 113 is not provided between gate pad 52p and termination well region 2. Therefore, the potential difference between gate pad 52p and termination well region 2 is shared by field insulating film 4 and interlayer insulating film 14. Consequently, the electric field strength within field insulating film 4 is mitigated, thereby suppressing yield reductions caused by dust, etc., that enter during the manufacture of MOSFET 100.

[0285] Furthermore, according to the embodiment described above, interlayer insulating film 114 exposes at least a portion of the outer end portion of gate electrode 13 on the upper surface of field insulating film 4 and partially covers gate electrode 13. Furthermore, the gate portion covers at least a portion of the outer end portion of gate electrode 13 exposed from interlayer insulating film 114. With this structure, a contact hole is formed in interlayer insulating film 114 at the outermost periphery of gate pad 152p, and gate pad 152p and gate electrode 13 are connected via this contact hole at the outermost periphery of gate pad 152p. This effectively suppresses electric field concentration at the lower outer peripheral end portion of gate pad 152p, thereby preventing the generation of aluminum hydroxide.

[0286] Furthermore, according to the embodiment described above, the drift layer 1 comprises silicon carbide. This structure, even in a silicon carbide semiconductor device where the use of silicon carbide easily results in a high electric field strength being applied to the termination region, can suppress increases in leakage current and gas discharge caused by cracking or delamination of the gate portion 52, thereby improving the insulation reliability of the MOSFET 100. This eliminates the need for measures such as increasing the width of the termination region or thickening the insulating film around the surface electrode to mitigate the electric field strength. Consequently, increases in semiconductor chip manufacturing costs can be suppressed.

[0287] Further, according to the above-described embodiment, the film thickness of the field insulating film 4 is thicker than the film thickness of the gate insulating film 12. According to such a structure, the electric field concentration at the outer peripheral end portion of the gate portion 52 can be mitigated, so generation of precipitates at the end portion of the gate portion 52 in the termination region can be suppressed. Thus, the breakage or peeling of the gate portion 52 is suppressed.

[0288] Further, according to the above-described embodiment, the source electrode 51 and the gate portion 52 are made of a metal or an Al alloy containing at least one of Al, Cu, Mo, Ni, and Ti. According to such a structure, the electric field concentration at the outer peripheral end portion of the gate portion 52 can be mitigated, so generation of precipitates at the end portion of the gate portion 52 in the termination region can be suppressed. Thus, the breakage or peeling of the gate portion 52 is suppressed.

[0289] Further, according to the above-described embodiment, the interlayer insulating film 14 has an element component of boron or phosphorus. According to such a structure, even in the case where the shape of the step of the interlayer insulating film 14 is smoothed, generation of precipitates can be suppressed and the insulating reliability of the semiconductor device can be improved.

[0290] Further, according to the above-described embodiment, the impurity concentration per unit area of the termination well region 2 is 2 x 10 13 cm -2 The above. According to such a structure, in the off state, the depletion layer is difficult to extend to the inside of the termination well region 2.

[0291] Further, according to the above-described embodiment, the semiconductor device is provided with a third well region of the second conductive type (p-type). Here, the third well region corresponds to, for example, a low-concentration well region 3 or the like. The low-concentration well region 3 is formed in a surface layer of the upper surface of the drift layer 1 and surrounds the termination well region 2 in plan view. Further, the impurity concentration of the low-concentration well region 3 is lower than the impurity concentration of the termination well region 2. According to such a structure, the electric field concentration at the outer peripheral end portion of the gate portion 52 can be mitigated, so generation of precipitates at the end portion of the gate portion 52 in the termination region can be suppressed. Thus, the breakage or peeling of the gate portion 52 is suppressed.

[0292] Further, according to the above-described embodiment, the gate portion 52 (or the gate portion 252) is provided with a gate pad 52p (or a gate pad 152p) and a gate wire 52w (or a gate wire 252w) connected to the gate pad 52p (or the gate pad 152p). According to such a structure, the electric field concentration at the outer peripheral end portion of the gate portion 52 can be mitigated, so generation of precipitates at the end portion of the gate portion 52 in the termination region can be suppressed. Thus, the breakage or peeling of the gate portion 52 is suppressed.

[0293] Furthermore, according to the embodiment described above, the gate wiring 252w is provided so as to surround the source electrode 51 in a plan view. This structure can alleviate electric field concentration at the outer peripheral end of the gate wiring 252w surrounding the source electrode 51, thereby suppressing the formation of precipitates at the end of the gate wiring 252w in the terminal region. Consequently, cracking or peeling of the gate wiring 252w is suppressed.

[0294] Furthermore, according to the embodiment described above, gate portion 352 (or gate portion 452) includes gate pad 52p (or gate pad 152p) and gate wiring 352w (or gate wiring 452w) separated from gate pad 52p (or gate pad 152p). This structure can alleviate electric field concentration at the outer peripheral end of gate portion 352, thereby suppressing the formation of precipitates at the end of gate portion 352 in the terminal region. Consequently, cracking or peeling of gate portion 352 is suppressed.

[0295] Furthermore, according to the embodiment described above, the gate wiring 352w (or gate wiring 452w) is provided so as to surround the source electrode 51 in a plan view. This structure can alleviate electric field concentration at the outer peripheral end of the gate wiring 352w surrounding the source electrode 51, thereby suppressing the formation of precipitates at the end of the gate wiring 352w in the terminal region. Consequently, cracking or peeling of the gate wiring 352w is suppressed.

[0296] Furthermore, according to the embodiment described above, gate electrode 313 (or gate electrode 413), formed so as to extend to the upper surface of field insulating film 4, has an opening formed in a portion of the region that does not overlap with gate pad 52p (or gate pad 152p) and gate wiring 352w (or gate wiring 452w) when viewed from above. This structure mitigates electric field concentration at the outer peripheral end of gate wiring 452w surrounding source electrode 51, even in the presence of parasitic gate resistance. This suppresses the formation of precipitates at the end of gate wiring 452w in the terminal region. Consequently, cracking or peeling of gate wiring 452w is suppressed.

[0297] Furthermore, according to the embodiment described above, the power conversion device includes: a conversion circuit 2201 having the semiconductor device described above and converting input power and outputting the converted power; a drive circuit 2202 outputting a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit 2203 outputting a control signal for controlling the drive circuit 2202 to the drive circuit 2202. This configuration can alleviate electric field concentration at the outer peripheral end of the gate portion 52, thereby suppressing an increase in leakage current and gas discharge caused by cracking or peeling of the gate portion 52, thereby improving the insulation reliability of the power conversion device.

[0298] <Regarding Modifications of the Embodiments Described Above>

[0299] In the above-described embodiments, the materials, dimensions, shapes, relative arrangement relationships, or implementation conditions of each component may be described, but these are merely examples and are not restrictive in all respects.

[0300] Therefore, within the scope of the technology disclosed in this specification, numerous modifications and equivalents not shown are contemplated, including, for example, modifications, additions, or omissions of at least one component, and further, extraction of at least one component from at least one embodiment and combination with components from other embodiments.

[0301] In the above-described embodiments, when a material name is described without specifying it, other additives, such as alloys, are included in the material unless there is any inconsistency.

[0302] Furthermore, in the above-described embodiments, a component described as including “one” may also include “one or more” unless there is any contradiction.

[0303] Furthermore, the various constituent elements in the embodiments described above are conceptual units, and within the scope of the technology disclosed in this application specification, include situations where one constituent element is composed of multiple structures, situations where one constituent element corresponds to a part of a certain structure, and further situations where multiple constituent elements are arranged in one structure.

[0304] Furthermore, as long as the components in the above-described embodiments exhibit the same function, components having other structures or shapes are also included.

[0305] In addition, the descriptions in the present application specification are incorporated by reference for all purposes related to the present technology and are not to be regarded as prior art.

Claims

1. A semiconductor device comprising: A drift layer of a first conductivity type; a first well region of a second conductivity type formed in a surface layer of an upper surface of the drift layer; a source region of the first conductivity type formed on a surface layer of the first well region; a gate insulating film formed in contact with the first well region sandwiched between the source region and the drift layer; a gate electrode formed in contact with the gate insulating film; an interlayer insulating film covering the gate electrode; a source electrode covering the source region exposed on the upper surface of the drift layer and the interlayer insulating film; a back electrode formed on the lower surface side of the drift layer; a second well region of a second conductivity type, formed in the surface layer of the upper surface of the drift layer and surrounding the first well region in a plan view; as well as a field insulating film partially covering the second well region, The gate electrode is formed to extend to the upper surface of the field insulating film, The interlayer insulating film partially covers the gate electrode in the upper surface of the field insulating film, The semiconductor device further includes a gate portion that overlaps with the field insulating film in a plan view, is separated from the source electrode, and covers the interlayer insulating film and the gate electrode exposed from the interlayer insulating film. The end in the direction away from the first well region in a plan view is defined as an outer end. The outer end of the gate electrode is farther from the first well region than the outer end of the gate portion and closer to the first well region than the outer end of the second well region. The gate electrode formed to extend to the upper surface of the field insulating film has an opening formed at a lower portion of the gate portion.

2. A semiconductor device comprising: A drift layer of a first conductivity type; a first well region of a second conductivity type formed in a surface layer of an upper surface of the drift layer; a source region of the first conductivity type formed on a surface layer of the first well region; a gate insulating film formed in contact with the first well region sandwiched between the source region and the drift layer; a gate electrode formed in contact with the gate insulating film; an interlayer insulating film covering the gate electrode; a source electrode covering the source region exposed on the upper surface of the drift layer and the interlayer insulating film; a back electrode formed on the lower surface side of the drift layer; a second well region of a second conductivity type, formed in the surface layer of the upper surface of the drift layer and surrounding the first well region in a plan view; as well as a field insulating film partially covering the second well region, The gate electrode is formed to extend to the upper surface of the field insulating film, The interlayer insulating film partially covers the gate electrode in the upper surface of the field insulating film, The semiconductor device further includes a gate portion that overlaps with the field insulating film in a plan view, is separated from the source electrode, and covers the interlayer insulating film and the gate electrode exposed from the interlayer insulating film. The end in the direction away from the first well region in a plan view is defined as an outer end. The outer end of the gate electrode is farther from the first well region than the outer end of the gate portion and closer to the first well region than the outer end of the second well region. The interlayer insulating film exposes the gate electrode at the outermost periphery of the gate portion and partially covers the gate electrode. The gate portion is connected to at least a portion of the gate electrode exposed from the interlayer insulating film at an outermost periphery of the gate portion.

3. The semiconductor device according to claim 1 or 2, wherein The gate portion includes: a gate pad; and A gate wiring is connected to the gate pad.

4. The semiconductor device according to claim 3, wherein The gate wiring is provided so as to surround the source electrode in a plan view.

5. A semiconductor device comprising: A drift layer of a first conductivity type; a first well region of a second conductivity type formed in a surface layer of an upper surface of the drift layer; a source region of the first conductivity type formed on a surface layer of the first well region; a gate insulating film formed in contact with the first well region sandwiched between the source region and the drift layer; a gate electrode formed in contact with the gate insulating film; an interlayer insulating film covering the gate electrode; a source electrode covering the source region exposed on the upper surface of the drift layer and the interlayer insulating film; a back electrode formed on the lower surface side of the drift layer; a second well region of a second conductivity type, formed in the surface layer of the upper surface of the drift layer and surrounding the first well region in a plan view; as well as a field insulating film partially covering the second well region, The gate electrode is formed to extend to the upper surface of the field insulating film, The interlayer insulating film partially covers the gate electrode in the upper surface of the field insulating film, The semiconductor device further includes a gate portion that overlaps with the field insulating film in a plan view, is separated from the source electrode, and covers the interlayer insulating film and the gate electrode exposed from the interlayer insulating film. The end in the direction away from the first well region in a plan view is defined as an outer end. The outer end of the gate electrode is farther from the first well region than the outer end of the gate portion and closer to the first well region than the outer end of the second well region. The gate portion includes: a gate pad; and The gate wiring is separated from the gate pad. The semiconductor device according to claim 5 , wherein: The gate wiring is provided so as to surround the source electrode in a plan view.

7. The semiconductor device according to claim 5 or 6, wherein: The gate electrode formed to extend to the upper surface of the field insulating film has an opening formed in a portion of a region that does not overlap with the gate pad and the gate wiring in a plan view.

8. The semiconductor device according to claim 1, 2, 4, 5 or 6, wherein: The outer end portion of the gate electrode formed to extend to the upper surface of the field insulating film is farther away from the first well region than the outer end portion of the gate portion over the entire circumference surrounding the first well region, and closer to the first well region than the outer end portion of the second well region.

9. The semiconductor device according to claim 1, 2, 4, 5 or 6, wherein: The drift layer includes silicon carbide.

10. The semiconductor device according to claim 1, 2, 4, 5 or 6, wherein: The field insulating film has a thickness thicker than that of the gate insulating film.

11. The semiconductor device according to claim 1, 2, 4, 5 or 6, wherein: The source electrode and the gate portion are made of a metal containing at least one of Al, Cu, Mo, Ni, and Ti, or an Al alloy.

12. The semiconductor device according to claim 1, 2, 4, 5 or 6, wherein: The interlayer insulating film has an elemental component of boron or phosphorus.

13. The semiconductor device according to claim 1, 2, 4, 5 or 6, wherein: The impurity concentration per unit area of ​​the second well region is 2×10 13 cm -2 above.

14. The semiconductor device according to claim 1, 2, 4, 5 or 6, wherein: further comprising a third well region of the second conductivity type, the third well region being formed in the surface layer of the upper surface of the drift layer and surrounding the second well region in a plan view, The impurity concentration of the third well region is lower than the impurity concentration of the second well region.

15. A power conversion device comprising: A conversion circuit comprising the semiconductor device according to any one of claims 1 to 14, wherein the conversion circuit converts input power and outputs the converted power; a driving circuit for outputting a driving signal for driving the semiconductor device to the semiconductor device; as well as The control circuit outputs a control signal for controlling the driving circuit to the driving circuit.

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