Method for forming a contact structure, contact structure and semiconductor device

Abstract

The present application discloses a method for forming a contact structure, a contact structure, and a semiconductor device, comprising: providing a substrate having a plurality of isolation regions therein, wherein the isolation regions isolate a plurality of active regions from the substrate; simultaneously etching the active regions and the isolation regions for a first time to form a first contact via, wherein a raised active region is formed at the bottom of the first contact via at the location of the active region; depositing a first dielectric layer to cover the sidewalls and bottom of the first contact via; and etching the bottom of the first contact via for a second time to form a contact structure having a target depth. By backfilling the bottom of the first contact via with the first dielectric layer and etching again to reach the target depth, the height difference between the bottom of the first contact via at different dielectric layers is reduced, thereby avoiding the problem of the conductive material required to fill the contact structure subsequently not being fully filled, thereby improving the electrical performance of the subsequently formed semiconductor structure and thereby improving the yield rate.

Description

Technical Field

[0001] The present application relates to, but is not limited to, the technical field of semiconductors, and in particular to a method for forming a contact structure, a contact structure, and a semiconductor device. Background Art

[0002] As the line width of dynamic random access memory (DRAM) gradually decreases, the size of the structure to be formed decreases, resulting in a decrease in the size of the contact structure to be formed.

[0003] In semiconductor manufacturing, when different materials need to be etched in the same process, due to the different etching rates of different materials, an uneven step structure will form at the interface of the different materials after etching. This is especially true at the bottom of the contact structure. If an uneven step structure is formed, and the size of the contact structure is reduced, the conductive material that needs to be filled into the contact structure will find it difficult to completely fill the uneven step structure, thereby affecting the electrical performance of the subsequently formed semiconductor structure and reducing the yield of the semiconductor structure. In more serious cases, voids will form, causing the wafer to be scrapped. Summary of the Invention

[0004] The purpose of the present application is to provide a method for forming a contact structure, a contact structure and a semiconductor device, in order to solve the problem in the prior art that due to the different etching rates of different materials in etching, in the process of etching different materials at the same time, an uneven step structure will be formed at the junction of different materials after etching, resulting in that it is difficult for the conductive material that needs to be filled into the contact structure later to completely fill the uneven step structure, thereby affecting the electrical performance of the semiconductor structure formed subsequently, and further resulting in a reduced yield of the semiconductor structure.

[0005] To solve the above technical problems, according to some embodiments, the present application provides a method for forming a contact structure, comprising:

[0006] A substrate is provided, wherein the substrate has a plurality of isolation regions, wherein the isolation regions isolate a plurality of active regions from the substrate; the active regions and the isolation regions are simultaneously etched for a first time to form a first contact hole, wherein a raised active region is formed at the bottom of the first contact hole at the location of the active region; a first dielectric layer is deposited to cover the sidewalls and bottom of the first contact hole; and the bottom of the first contact hole is etched for a second time to form a contact structure having a target depth.

[0007] Preferably, the etching rate of the isolation region is greater than the etching rate of the active region.

[0008] Preferably, a first height difference is formed between the top of the raised active region at the bottom of the first contact hole and the bottom of the first contact hole.

[0009] Preferably, the distance from the top of the active region at the bottom of the contact structure to the surface of the isolation region at the bottom of the contact structure is a second height difference, and the second height difference is smaller than the first height difference.

[0010] Preferably, in the first contact hole formed by one etching, the depth of the first contact hole corresponding to the raised active area is smaller than the target depth of the first contact hole.

[0011] Preferably, the etching depth of the active area in the first etching is three quarters of the target depth.

[0012] Preferably, the raised active area is located at the center of the bottom of the first contact hole, and the distances from both sides of the raised active area to the corresponding sidewalls of the first contact hole are both the first width.

[0013] Preferably, the deposition thickness of the first dielectric layer is greater than or equal to half of the first width.

[0014] Preferably, the distance from the top of the raised active area to the bottom surface of the first contact hole is a first height, and the first height is greater than the deposition thickness.

[0015] Preferably, the etching rate of the isolation region in the first etching is the same as the etching rate of the first dielectric layer in the second etching; and the etching rate of the active region in the first etching is the same as the etching rate of the active region in the second etching.

[0016] Preferably, the isolation region material and / or the first dielectric layer material includes silicon oxide; and the active region material includes silicon.

[0017] Preferably, the first etching of the active area and the isolation area includes: forming a protection layer on the surface of the substrate, and forming a patterned mask layer above the protection layer, wherein the patterned mask layer is used to define the position of the first contact hole.

[0018] According to other embodiments, the present application provides a contact structure, which is formed using the above-mentioned forming method.

[0019] According to some other embodiments, the present application also provides a semiconductor device including the contact structure.

[0020] The embodiments disclosed herein have at least the following advantages: during the first etching, due to the inconsistent etching rates of the active area and the isolation area, a raised active area is formed at the active area position at the bottom of the first contact hole. The thickness of the deposited first dielectric layer is adjusted according to the first height difference between the raised active area formed after the first etching and the bottom of the first contact hole. By covering the sidewalls and bottom of the first contact hole with a layer of the first dielectric layer and etching again to reach the target depth, the height difference between the bottom of the first contact hole at different dielectric levels is reduced, thereby avoiding the problem of the conductive material that needs to be filled into the contact structure subsequently not being able to be completely filled, improving the electrical performance of the subsequently formed semiconductor structure, and thereby improving the yield rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 is a flow chart of a method for forming a contact structure in one embodiment of the present application;

[0023] Figure 2-Figure 8 A schematic diagram of the cross-sectional structure corresponding to each step in the method for forming a contact structure provided in one embodiment of the present application. DETAILED DESCRIPTION

[0024] In semiconductor manufacturing, when different materials need to be etched in the same process, due to the different etching rates of different materials, the process of etching different materials simultaneously will form an uneven step structure at the interface of the different materials after etching. This is particularly true at the bottom of the contact structure. If the uneven step structure forms, while the contact structure size is reduced, the conductive material required to fill the contact structure will find it difficult to completely fill the uneven step structure, thus affecting the electrical performance of the subsequent semiconductor structure and reducing the yield of the semiconductor structure.

[0025] To solve the above-mentioned problem, an embodiment of the present application provides a method for forming a contact structure, comprising: providing a substrate having a plurality of isolation regions therein, wherein the isolation regions isolate a plurality of active regions from the substrate; simultaneously etching the active regions and the isolation regions for a first time to form a first contact through-hole, wherein a raised active region is formed at the bottom of the first contact through-hole at the position of the active region; depositing a first dielectric layer to cover the sidewalls and bottom of the first contact through-hole; and etching the bottom of the first contact through-hole for a second time to form a contact structure having a target depth.

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in each embodiment of the present application, many technical details are proposed to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.

[0027] Figure 1 is a flow chart of a method for forming a contact structure in one embodiment of the present application. Figure 2-Figure 8 The cross-sectional structural diagram corresponding to each step in the method for forming a contact structure provided in one embodiment of the present application is further described in detail below in conjunction with the accompanying drawings. The specific steps are as follows:

[0028] like Figure 1 、 2 As shown, in step S11 , a substrate is provided; the substrate 1 includes an isolation region 11 , an active region 12 and a word line structure 13 .

[0029] The material of the substrate 1 may include a semiconductor substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a single crystal metal oxide substrate, etc. In this embodiment, the substrate 1 is made of silicon. This embodiment uses silicon as the substrate 1 to facilitate those skilled in the art to understand the subsequent formation method and does not constitute a limitation. In actual application, a suitable material for the substrate 1 can be selected according to requirements.

[0030] Specifically, multiple active regions 12 are arranged parallel to each other and spaced apart within the substrate 1. It should be noted that the substrate 1 also includes other memory structures besides the isolation region 11, active region 12, and wordline structure 13. Since these other memory structures do not relate to the core technology of this application, they will not be described in detail here. Those skilled in the art will understand that the substrate 1 also includes other memory structures besides the isolation region 11, active region 12, and wordline structure 13 to ensure the normal operation of the memory.

[0031] refer to Figure 2 A plurality of deep trenches 111 are formed in the surface area of ​​the substrate 1, and isolation materials are filled in the deep trenches 111 to form isolation regions 11. The isolation regions 11 isolate a plurality of active regions 12 from the substrate 1. The isolation regions 11 can isolate a plurality of active regions 12 distributed in an array or other distribution types on the substrate 1. The active regions 12 can be formed by implanting impurities into the substrate 1, for example, by an ion implantation process.

[0032] In other embodiments, the isolation material may include silicon oxide, tetraethyl silicate, borophosphosilicate glass, or the like.

[0033] refer to Figure 2 and Figure 3 As shown, in step S12, a protection layer is formed on the surface area of ​​the substrate.

[0034] A protective layer 4 is covered on the surface of the substrate 1 . The protective layer 4 can be formed on the substrate 1 using oxide, nitride, oxynitride, etc.

[0035] In one example, the protective layer 4 may include silicon oxide, silicon nitride, silicon oxynitride, etc. For example, the protective layer 4 may be formed using undoped silicate glass (USG), spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-phosphosilicate glass (BPSG), flowable oxide (FOX), tetraethoxysilane (tetraethylorthosilicate, TEOS), plasma-enhanced TEOS (PE-TEOS), Tonen's silazane (TOSZ), high-density plasma chemical vapor deposition (HDP-CVD) oxide, etc. These may be used alone or in combination. In addition, the protective layer 4 may be formed by a spin coating process, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDP-CVD) process, etc.

[0036] In other embodiments, the protective layer 4 may have a multi-layer structure including an oxide film, a nitride film, and / or an oxynitride film sequentially formed on the substrate 1 .

[0037] refer to Figure 2 and Figure 4 As shown, in step S13, a patterned mask layer is formed on the protection layer, and the patterned mask layer is used to define the position of the first contact hole.

[0038] In detail, the patterned mask layer 41 includes a first opening 411 that penetrates the thickness of the mask layer. The patterned mask layer 41 and the first opening 411 are used to define the position of the first contact hole 5 .

[0039] In one example, forming the first opening 411 having a thickness extending through the mask layer includes forming a patterned photoresist (not shown) on top of the mask layer, and forming the first opening 411 in the mask layer based on the patterned photoresist, thereby forming a patterned mask layer 41. It should be noted that the patterned mask layer 41 may have a single-layer mask structure or a multi-layer mask structure.

[0040] refer to Figure 2 and Figure 5 As shown, in step S14, a second opening is formed to expose a portion of the isolation region and the active region on the substrate.

[0041] Specifically, using the mask layer 41 patterned in step S13 as a mask, an appropriate etching process is used, for example, wet etching using phosphoric acid (H3PO4) as an etching solution or dry etching using N2 plasma as an etching gas, to etch the protective layer 4 exposed by the first opening 411 until a second opening 42 is formed passing through the protective layer 4. The second opening 42 can expose part of the isolation region 11 and the active region 12 on the substrate 1.

[0042] refer to Figure 2 、 Figure 5 and Figure 6 As shown, in step S15, a first contact hole is formed at the bottom of the second opening by a first etching.

[0043] Specifically, the active area 12 and the isolation area 11 exposed at the bottom of the second opening 42 are etched for the first time to form a first contact hole 5. In a direction parallel to the surface of the substrate 1, the width of the first contact hole 5 is equal to the width of the second opening 42. A raised active area 121 is formed at the position of the active area 12 at the bottom of the first contact hole 5. Figure 7 As shown, the width of the raised active region 121 is d.

[0044] In one example, in a direction perpendicular to the surface of the substrate 1 , the depth of the first contact hole 5 is 20 nm to 40 nm, for example, 20 nm, 30 nm or 40 nm.

[0045] In this embodiment, in the first etching, the silicon oxide filled in the isolation region 11 and the material of the active region 12 have different etching selectivities, and the etching rate of the isolation region 11 is greater than the etching rate of the active region 12. Therefore, in the first etching, within the same etching time, the depth of the etching of the isolation region 11 is deeper than that of the active region 12, that is, the filling material in the isolation region 11 is removed faster. Therefore, when the first etching process stops, the bottom of the first contact through hole 5 at the position of the active region 12 will protrude from the bottom of the isolation region 11 to form a protruding active region 121, that is, a first height difference is formed between the top of the protruding active region 121 at the bottom of the first contact through hole 5 and the upper surface of the isolation region 11 at the bottom of the first contact through hole 5, as shown in FIG. Figure 7 As shown, the first height difference is b.

[0046] refer to Figure 7 and Figure 8 As shown, the first contact via 5 formed by the first etching process has a depth corresponding to the raised active area 121 within the first contact via 5 that is less than the target depth of the first contact via 5. For example, the first etching process etches the active area 12 to a depth H1 that is three-quarters of the target depth H0. Because the raised active area 121 protrudes from the bottom of the first contact via 5, a trench 6 is formed between the sidewalls of the raised active area 121 and the sidewalls of the first contact via 5.

[0047] In some embodiments, the formed raised active region 121 is located at the bottom center of the first contact hole 5, and the distances from both sides of the raised active region 121 to the corresponding sidewalls of the first contact hole 5 are both the first width. Figure 7 As shown, the first width is c.

[0048] The presence of the first height difference b makes it difficult for the conductive material subsequently filled into the contact structure to completely fill the uneven step structure, thereby affecting the electrical performance of the subsequently formed semiconductor structure and further reducing the yield of the semiconductor structure. Therefore, a second etching process is performed to reduce the first height difference b.

[0049] refer to Figure 2 and Figure 7 As shown, in step S16, the first contact hole is backfilled and etched a second time.

[0050] According to an embodiment of the present application, a first dielectric layer 7 is conformally deposited on the sidewalls and bottom of the first contact hole 5 and the raised active area 121 using a chemical vapor deposition (CVD) process or other suitable process. According to an embodiment of the present application, the first dielectric layer 7 conformally covers the surface area of ​​the protective layer 4, the sidewalls and bottom of the first contact hole 5, and the raised active area 121. Figure 7 As shown, the thickness of the first dielectric layer 7 deposited on the raised active area 121 is a.

[0051] In one example, when the thickness a of the first dielectric layer 7 deposited on the raised active area 121 is greater than or equal to half of the first width c, the first dielectric layer 7 is conformally deposited on the sidewalls and bottom of the first contact hole 5 and the raised active area 121 to fill the trench 6.

[0052] refer to Figure 7 and Figure 8As shown, an anisotropic etching process is used to simultaneously perform a second etching on the sidewalls and the first dielectric layer 7 at the bottom of the first contact through hole 5 and the bottom raised active area 121, thereby forming a contact structure with a target depth H0, and the distance from the top of the active area 12 at the bottom of the contact structure to the surface of the isolation area 11 at the bottom of the contact structure is a second height difference, which is less than the first height difference b, and the second height difference is preferably 0.

[0053] In one example, the distance from the top of the raised active area 121 to the bottom surface of the first contact through hole 5 is a first height, i.e., a first height difference b. The first height is greater than the thickness a of the first dielectric layer 7 deposited on the raised active area 121, and the width d of the raised active area 121 is greater than the first width c.

[0054] In this embodiment, the etching rate of the active region 12 in the second etching is the same as the etching rate of the active region 12 in the first etching.

[0055] It should be noted that the etching rate of the first dielectric layer 7 in the second etching process is the same as the etching rate of the isolation region 11 in the first etching process. For example, the material of the first dielectric layer 7 can be the same as or different from the filling material in the isolation region 11. In the embodiment of the present application, the material of the first dielectric layer 7 and the filling material in the isolation region 11 are the same, both being silicon oxide.

[0056] For ease of understanding, this embodiment compares the height differences between the active area and the isolation area after direct etching and step etching;

[0057] Assume that the target depth H0 of the active area is 40nm, the etching rate of the material in the isolation area is 1.5 times that of the active area material, and the surface is completely flat when filling the first dielectric layer:

[0058] If direct etching to the target depth is used:

[0059] The target depth of the active region is 40 nm, and the target depth of the isolation region is 60 nm, so the height difference between the two is 20 nm.

[0060] If step etching is used to the target depth:

[0061] The first etching is 3 / 4 of the target depth. The target depth of the active area is 30nm, and the target depth of the isolation area is 45. Then, the height difference between the active area and the isolation area after the first etching is 15nm.

[0062] The thickness of the first dielectric layer on the backfilled active area is set to 5nm. The target depth of the active area becomes 25nm. The bottom of the active area and the isolation area are made flush. At this time, the target depth of the isolation area needs to be backfilled by 20nm. This is mainly due to the height difference of 15nm between the active area and the isolation area plus the thickness of the first dielectric layer of 5nm. At this time, the depth of the isolation area becomes 45nm minus the backfill of 20nm, which equals 25nm.

[0063] In the second etching, the active area is further etched to a target depth of 40 nm. Specifically, the target depth after the first etching and backfilling is 25 nm, and an additional 15 nm to 40 nm depth is etched. The depth etched away mainly includes the thickness of the first dielectric layer (5 nm) and the active area (10 nm).

[0064] The target depth of the isolation area after backfilling is continued to be etched from 25nm to 45nm. The etched depth is mainly the thickness of the first dielectric layer filled, 20nm. Therefore, the height difference between the active area and the isolation area is 5nm. It can be seen that step-by-step etching can reduce the height difference between the active area and the isolation area.

[0065] Compared with related technologies, the thickness of the deposited first dielectric layer is adjusted according to the first height difference between the raised active area and the bottom of the first contact hole formed by the first etching. By covering the sidewall and bottom of the first contact hole with a layer of the first dielectric layer, the height difference caused by the raised active area is eliminated. By etching again to reach the target depth, the height difference between the bottom of the first contact hole at different dielectric levels is reduced, avoiding the problem of the conductive material that needs to be filled in the contact structure later not being able to be completely filled, improving the electrical performance of the subsequently formed semiconductor structure, and thereby improving the yield.

[0066] Correspondingly, another embodiment of the present application relates to a contact structure that can be manufactured using any of the above-mentioned formation methods.

[0067] Correspondingly, another embodiment of the present application also relates to a semiconductor device including the contact structure.

[0068] It should be understood that the above-mentioned specific embodiments of the present application are merely illustrative or explain the principles of the present application and do not constitute a limitation of the present application. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present application should be included in the scope of protection of the present application. In addition, the claims attached hereto are intended to cover all variations and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. A method for forming a contact structure, characterized in that: include: Providing a substrate, wherein the substrate has a plurality of isolation regions, wherein the isolation regions isolate a plurality of active regions from the substrate; Simultaneously performing a first etching on the active region and the isolation region to form a first contact hole, wherein a raised active region is formed at the bottom of the first contact hole at the location of the active region, wherein a depth corresponding to the raised active region within the first contact hole formed by the first etching is less than a target depth of the first contact hole, the raised active region is located at the center of the bottom of the first contact hole, and a distance from both sides of the raised active region to corresponding sidewalls of the first contact hole is a first width; Depositing a first dielectric layer to cover the sidewalls and bottom of the first contact hole, wherein the deposition thickness of the first dielectric layer is greater than or equal to half of the first width, and the distance from the top of the raised active area to the bottom surface of the first contact hole is a first height, and the first height is greater than the deposition thickness; The bottom of the first contact hole is etched for the second time to form a contact structure with the target depth.

2. The forming method according to claim 1, wherein: An etching rate of the isolation region is greater than an etching rate of the active region.

3. The forming method according to claim 1, wherein: A first height difference is formed between the top of the raised active region at the bottom of the first contact hole and the bottom of the first contact hole.

4. The forming method according to claim 3, wherein: A distance from the top of the active region at the bottom of the contact structure to the surface of the isolation region at the bottom of the contact structure is a second height difference, and the second height difference is smaller than the first height difference.

5. The forming method according to claim 1, wherein: The etching depth of the active area by the first etching is three quarters of the target depth.

6. The forming method according to claim 1, wherein: The etching rate of the isolation region in the first etching is the same as the etching rate of the first dielectric layer in the second etching; the etching rate of the active region in the first etching is the same as the etching rate of the active region in the second etching.

7. The forming method according to claim 1, wherein: The isolation region material and / or the first dielectric layer material include silicon oxide; the active region material includes silicon.

8. The forming method according to claim 1, wherein: Performing the first etching on the active area and the isolation area includes: forming a protection layer on the surface of the substrate, and forming a patterned mask layer above the protection layer, wherein the patterned mask layer is used to define the position of the first contact hole.

9. A contact structure, characterized in that: The contact structure is formed by the forming method according to any one of claims 1 to 8.

10. A semiconductor device, characterized in that: Comprising the contact structure according to claim 9.

Images