Semiconductor structure and manufacturing method thereof

Abstract

An embodiment of the present invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate; a bit line located on the substrate; and a semiconductor channel located on the surface of the bit line. The semiconductor channel includes a first doped region, a channel region, and a second doped region arranged sequentially along the substrate toward the bit line. The first doped region contacts the bit line, and the first, channel, and second doped regions are doped with a first type of dopant ion. The channel region is also doped with a second type of dopant ion, such that the majority carrier concentration in the channel region is lower than the majority carrier concentration in the first and second doped regions. The first type of dopant ion is either an N-type ion or a P-type ion, and the second type of dopant ion is either an N-type ion or a P-type ion. Embodiments of the present invention facilitate reducing the majority carrier concentration in the channel region to a lower concentration than in the first and second doped regions, thereby improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the integration density of dynamic memory develops towards a higher direction, while studying the arrangement of transistors in the dynamic memory array structure and how to reduce the size of a single functional device in the dynamic memory array structure, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When a vertical gate-all-around (GAA) transistor structure is used as a dynamic memory select transistor (access transistor), the area occupied by it can reach 4F. 2 (F: the minimum pattern size obtainable under given process conditions). In principle, higher density efficiency can be achieved. However, due to the limitations of the doping process, the concentrations of majority carriers in various regions of the GAA transistor structure are consistent or slightly different. It is difficult to adjust the concentrations of majority carriers in various regions of the GAA transistor structure, making it difficult to further improve the electrical performance of the GAA transistor structure and dynamic memory. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a bit line located on the substrate; and a semiconductor channel located on a surface of the bit line. In a direction along the substrate pointing to the bit line, the semiconductor channel comprises a first doping region, a channel region, and a second doping region arranged in sequence, the first doping region being in contact with the bit line, and the first doping region, the channel region, and the second doping region being doped with first-type doping ions, and the channel region being further doped with second-type doping ions, such that the majority carrier concentration in the channel region is lower than the majority carrier concentration in the first doping region and the second doping region, the first-type doping ions being one of N-type ions or P-type ions, and the second-type doping ions being the other of N-type ions or P-type ions.

[0005] Correspondingly, an embodiment of the present invention also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming an initial bit line on the substrate, and forming a semiconductor channel on a surface of the initial bit line away from the substrate, wherein in a direction along the substrate pointing to the initial bit line, the semiconductor channel includes a first doping region, a channel region and a second doping region arranged in sequence, and the first doping region, the channel region and the second doping region are doped with first type doping ions of the same doping concentration, and the first type doping ions are one of N-type ions or P-type ions; forming a sacrificial layer doped with second type doping ions on the sidewalls of the channel region, and the sacrificial layer at least covers the sidewalls of the channel region, and the second type doping ions are the other of N-type ions or P-type ions; using an annealing process to diffuse the second type doping ions into the channel region to reduce the majority carrier concentration in the channel region; and removing the sacrificial layer to expose the sidewalls of the channel region.

[0006] The technical solution provided by the embodiment of the present invention may have the following advantages:

[0007] In the above technical solution, the channel region is doped not only with the first type of dopant ions but also with the second type of dopant ions, so that the majority carrier concentration in the channel region is lower than the majority carrier concentration in the first doping region and also lower than the majority carrier concentration in the second doping region. On the one hand, the lower majority carrier concentration in the channel region is beneficial to improving the on / off ratio of the channel region, thereby improving the sensitivity of controlling the on / off of the channel region to ensure that the channel region can be quickly turned on and off; on the other hand, the concentration of majority carriers in both the first doping region and the second doping region is relatively high, which is beneficial to reducing the resistance of the first doping region and the second doping region themselves, thereby reducing the threshold voltage of the transistor composed of the first doping region, the channel region, and the second doping region and increasing the saturation current of the transistor. Therefore, the embodiments of the present invention are beneficial to improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] One or more embodiments are exemplarily described by the figures in the corresponding drawings. Unless otherwise stated, the figures in the drawings are not limited to scale.

[0009] Figures 1 to 36 This is a schematic structural diagram corresponding to each step in the method for forming a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] As can be seen from the background art, the electrical performance of current semiconductor structures needs to be improved.

[0011] Analysis has revealed that in GAA transistors, the first doping region, channel region, and second doping region are stacked in sequence, making it difficult to perform the self-aligned doping process for the first and second doping regions after the gate structure is formed using an ion implantation process, as in planar transistors. Therefore, the first doping region, channel region, and second doping region in GAA transistors are typically formed using the same doping process. This results in the majority carrier concentrations in the first, channel, and second doping regions being essentially the same, and the majority carrier concentration in the channel region should not be too high. A high majority carrier concentration in the channel region reduces the on / off ratio of the channel region, making it difficult for the gate to control the channel region's shutdown. However, while ensuring that the majority carrier concentration in the channel region meets the high on / off ratio required for the channel region, the majority carrier concentrations in the first and second doping regions are low, resulting in a high resistance. This increases the threshold voltage of the GAA transistor and reduces its saturation current, adversely affecting its electrical performance.

[0012] To address the above-mentioned problems, embodiments of the present invention provide a semiconductor structure and a method for fabricating the same. In the semiconductor structure, a channel region is doped with both a first type of dopant ion and a second type of dopant ion, such that the majority carrier concentration in the channel region is lower than the majority carrier concentration in the first doping region and also lower than the majority carrier concentration in the second doping region. On the one hand, the lower majority carrier concentration in the channel region is beneficial for improving the on / off ratio of the channel region, thereby improving the sensitivity of controlling the on / off state of the channel region and ensuring that the channel region can be quickly turned on and off. On the other hand, the higher concentrations of majority carriers in both the first doping region and the second doping region are beneficial for reducing the resistance of the first doping region and the second doping region themselves, thereby reducing the threshold voltage of a transistor composed of the first doping region, the channel region, and the second doping region and increasing the saturation current of the transistor. Therefore, embodiments of the present invention are beneficial for ensuring a lower majority carrier concentration in the channel region while maintaining a higher majority carrier concentration in the first doping region and the second doping region, thereby improving the electrical performance of the semiconductor structure.

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the embodiments of the present invention to help readers better understand the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0014] An embodiment of the present invention provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Figures 1 to 6This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention is shown. Figure 2 for Figure 1 A schematic cross-sectional view of the semiconductor channel in the structure shown; Figure 3 for Figure 1 A schematic cross-sectional view of the structure shown along the first cross-sectional direction AA1, Figure 4 for Figure 1 Another cross-sectional schematic diagram of the structure shown along the first cross-sectional direction AA1, Figure 5 for Figure 1 The structure shown is a cross-sectional schematic diagram along the second cross-sectional direction BB1, Figure 6 A schematic diagram of another structure of a semiconductor structure provided by an embodiment of the present invention.

[0015] refer to Figures 1 to 6 The semiconductor structure includes: a substrate 11; a bit line 104 located on the substrate 11; a semiconductor channel 105 located on the surface of the bit line 104. In the direction along the substrate 11 pointing to the bit line 104, the semiconductor channel 105 includes a first doping region I, a channel region II and a second doping region III arranged in sequence. The first doping region I is in contact with the bit line 104, and the first doping region I, the channel region II and the second doping region III are doped with first type doping ions, and the channel region II is further doped with second type doping ions, so that the majority carrier concentration in the channel region II is lower than the majority carrier concentration in the first doping region I and the second doping region III. The first type doping ions are one of N-type ions or P-type ions, and the second type doping ions are the other of N-type ions or P-type ions.

[0016] The semiconductor structure also includes: an insulating layer 106, covering the sidewall surface of the channel region II; a word line 107, covering the sidewall surface of the insulating layer 106 away from the channel region II, and the adjacent sidewalls of the first doped region I, the adjacent sidewalls of the word line 107, and the adjacent sidewalls of the second doped region III form a gap; an isolation layer 103, the isolation layer 103 is located in the gap, and the top surface of the isolation layer 103 away from the substrate 11 is not lower than the top surface of the second doped region III away from the substrate 11.

[0017] Since the semiconductor structure includes vertical GAA transistors and the bit line 104 is located between the substrate 11 and the GAA transistors, a 3D stacked memory device can be formed, which is beneficial for improving the integration density of the semiconductor structure.

[0018] The following will be combined Figures 1 to 6 The semiconductor structure is described in more detail.

[0019] In this embodiment, the material type of substrate 11 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium. In some embodiments, substrate 11 can be doped with a second type of dopant ions.

[0020] Furthermore, the substrate 11, the bit line 104, and the semiconductor channel 105 have the same semiconductor element, so the semiconductor channel 105 and the bit line 104 can be formed using the same film layer structure. The film layer structure is composed of semiconductor elements, so that the semiconductor channel 105 and the bit line 104 are an integrated structure, thereby improving the interface state defects between the semiconductor channel 105 and the bit line 104 and improving the performance of the semiconductor structure.

[0021] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. In one example, both the bit line 104 and the semiconductor channel 105 include silicon. In other examples, both the bit line and the semiconductor channel may include germanium, or both the bit line and the semiconductor channel may include silicon and germanium, or both the bit line and the semiconductor channel may include silicon and carbon, or both the bit line and the semiconductor channel may include arsenic and gallium, or both the bit line and the semiconductor channel may include gallium and indium.

[0022] Specifically, the material of bit line 104 also includes a metal-semiconductor compound 114. Compared to unmetallized semiconductor materials, metal-semiconductor compound 114 has a relatively low resistivity. Therefore, compared to semiconductor channel 105, bit line 104 has a lower resistivity, thereby reducing the resistance of bit line 104 and the contact resistance between bit line 104 and first doped region I, further improving the electrical performance of the semiconductor structure. Furthermore, the resistivity of bit line 104 is also lower than that of substrate 11.

[0023] In some embodiments, the material of the region of the bit line 104 located directly below the first doped region I is a semiconductor material, and the material of the portion of the bit line 104 not covered by the first doped region I is a metal-semiconductor compound. It is understood that as device dimensions continue to shrink or manufacturing process parameters are adjusted, the material of the portion of the bit line 104 located directly below the first doped region I is a semiconductor material, and the material of the remaining region of the bit line 104 located directly below the first doped region I may also be a metal-semiconductor compound, with the "remaining region" herein being located outside the "partial region."

[0024] Specifically, in one example, referring to Figure 3 , the plurality of metal-semiconductor compounds 114 in the same bit line 104 are spaced apart from each other; in another example, referring to Figure 4, the multiple metal semiconductor compounds 114 in the same bit line 104 are interconnected. It should be noted that, Figure 4 The example only illustrates the case where the edges of adjacent metal semiconductor compounds 114 are just in contact with each other to be connected. In actual situations, the area in contact between adjacent metal semiconductor compounds 114 can be larger. This embodiment does not limit the size of the area in contact between adjacent metal semiconductor compounds 114.

[0025] In other examples, the material of the entire bit line may be a metal-semiconductor compound.

[0026] Taking silicon as the semiconductor element as an example, the metal semiconductor compound 114 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide.

[0027] In this embodiment, a plurality of spaced-apart bit lines 104 may be formed on the substrate 11, and each bit line 104 may be in contact with at least one first doping region I. Figures 1 to 5 In the figure, four mutually spaced bit lines 104 and each bit line 104 in contact with four first doping regions I are taken as an example. The number of bit lines 104 and the number of first doping regions I in contact with each bit line 104 can be reasonably set according to actual electrical requirements.

[0028] In some embodiments, when the bit line 104 is doped with the first type of dopant ions and the substrate 11 is doped with the second type of dopant ions, the bit line 104 and the substrate 11 form a PN junction. This PN junction helps prevent leakage of the bit line 104 and further improves the electrical performance of the semiconductor structure. It should be noted that in other embodiments, the substrate may not be doped with the second type of dopant ions.

[0029] In some embodiments, the first type of dopant ions are N-type ions, and the second type of dopant ions are P-type ions. Specifically, the N-type ions include at least one of arsenic ions, phosphorus ions, or antimony ions; and the P-type ions include at least one of boron ions, indium ions, or gallium ions. In other embodiments, the first type of dopant ions may be P-type ions, and the second type of dopant ions may be N-type ions.

[0030] Furthermore, in this embodiment, the first type dopant ions may all be phosphorus ions, and the second type dopant ions may all be boron ions. In other embodiments, the first type dopant ions in the first doping region and the first type dopant ions in the second doping region may also be different.

[0031] In this embodiment, the first doping region I, the channel region II, and the second doping region III in the semiconductor channel 105 are all doped with first type doping ions. Figure 2 , Figure 2 The example shows that the second type dopant ions are present in the diffusion region IV of the semiconductor channel 105, which is bounded by the dotted line and the periphery of the channel region. Specifically, the second type dopant ions are located not only in the channel region II, but also in the region of the first dopant region I near the channel region II and in the region of the second dopant region III near the channel region II. Furthermore, the doping concentration of the first type dopant ions in the diffusion region IV is greater than the doping concentration of the second type dopant ions in the diffusion region IV. This helps reduce the effective doping concentration of the first type dopant ions in the diffusion region IV. In this embodiment, the effective doping concentration of the first type dopant ions in the channel region II is lower than the effective doping concentration in the portion of the first dopant region I contacting the channel region II. The effective doping concentration of the first type dopant ions in the channel region II is also lower than the effective doping concentration in the portion of the second dopant region III contacting the channel region II.

[0032] It should be noted that the effective doping concentration of the first type of doping ions in the partial area where the first doping region I contacts the channel region II is specifically: the difference between the doping concentration of the first type of doping ions in the partial area and the doping concentration of the second type of doping ions; the effective doping concentration of the first type of doping ions in the partial area where the second doping region III contacts the channel region II is specifically: the difference between the doping concentration of the first type of doping ions in the partial area and the doping concentration of the second type of doping ions.

[0033] In a specific region of the semiconductor channel 105, when the region is doped with both the first type of dopant ions and the second type of dopant ions, the first type of dopant ions and the second type of dopant ions interact to produce an impurity compensation phenomenon, which reduces the majority carriers in the region. When the doping concentration of the first type of dopant ions in the region is greater than the doping concentration of the second type of dopant ions in the region, the effective doping concentration of the first type of dopant ions in the region decreases, and the concentration of majority carriers in the region decreases.

[0034] Therefore, when the effective doping concentration of the first type dopant ions in the portion of the first doping region I contacting the channel region II is reduced, the majority carrier concentration in this region is reduced, weakening the electric field strength at the junction between the first doping region I and the channel region II. This reduces the impact ionization on the semiconductor structure and reduces gate-induced drain leakage (GIDL). Consequently, when the effective doping concentration of the first type dopant ions in the portion of the second doping region III contacting the channel region II is reduced, this further reduces the impact ionization on the semiconductor structure and reduces GIDL.

[0035] Furthermore, the doping concentration of the first type doping ions in the channel region II is greater than the doping concentration of the second type doping ions in the channel region II, and the effective doping concentration of the first type doping ions in the channel region II is lower than the effective doping concentration in the first doping region I, and the effective doping concentration of the first type doping ions in the channel region II is lower than the effective doping concentration in the second doping region III.

[0036] It should be noted that the effective doping concentration of the first type doping ions in the channel region II is specifically: the difference between the doping concentration of the first type doping ions in the channel region II and the doping concentration of the second type doping ions; the effective doping concentration of the first type doping ions in the first doping region I is specifically: the difference between the doping concentration of the first type doping ions in the first doping region I and the doping concentration of the second type doping ions; the effective doping concentration of the first type doping ions in the second doping region III is specifically: the difference between the doping concentration of the first type doping ions in the second doping region III and the doping concentration of the second type doping ions.

[0037] The effective doping concentration of the first type of doping ions in the channel region II is not only lower than the effective doping concentration in the first doping region I, but also lower than the effective doping concentration in the second doping region III, so that the majority carrier concentration in the channel region II is lower than the majority carrier concentration in the first doping region I, and is also lower than the majority carrier concentration in the second doping region III. This is beneficial for ensuring that the majority carrier concentration in the channel region II is low while ensuring that the majority carrier concentration in the first doping region I and the second doping region III is high, so as to reduce the threshold voltage of the transistor composed of the first doping region I, the channel region II and the second doping region III and increase the saturation current of the transistor while increasing the on / off ratio of the channel region II, thereby improving the electrical performance of the semiconductor structure.

[0038] Furthermore, the effective doping concentration of the first type dopant ions in the channel region II is 8×10 18 atom / cm 3 ~2×10 19 atom / cm 3 Within this concentration range, the on / off ratio of the channel region II is relatively high, ensuring that the channel region II can be turned on and off quickly.

[0039] In some embodiments, the effective doping concentration of the first type dopant ions in the channel region II may be 1×10 19 atom / cm 3 This is beneficial for ensuring a higher on / off ratio of the channel region II while ensuring a higher conductivity of the channel region II.

[0040] The effective doping concentration of the first type dopant ions in the first doping region I is 3×10 19 atom / cm 3 ~1×10 20 atom / cm 3 The effective doping concentration of the first type dopant ions in the second doping region III is 3×10 19 atom / cm 3 ~1×10 20 atom / cm 3 Within this concentration range, the concentrations of majority carriers in the first doping region I and the second doping region III are both high, and the resistances of the first doping region I and the second doping region III themselves are both low, which is beneficial to ensuring that the transistor composed of the first doping region I, the channel region II and the second doping region III has a lower threshold voltage and a higher saturation current.

[0041] In some embodiments, the effective doping concentration of the first type dopant ions in the first doping region I may be 1×10 20 atom / cm 3 The effective doping concentration of the second type doping ions in the second doping region III can also be 1×10 20 atom / cm 3 , which is beneficial to ensure that both the first doping region I and the second doping region III have high conductivity.

[0042] In some embodiments, in the direction Z from the substrate 11 to the bit line 104 , the height of the semiconductor channel 105 is 100 nm to 150 nm, and the heights of the first doping region I, the channel region II, and the second doping region III are all 30 nm to 50 nm.

[0043] Furthermore, the orthographic projection of the channel region II on the substrate 11 is smaller than the orthographic projection of the second doped region III on the substrate 11, and smaller than the orthographic projection of the first doped region I on the substrate 11. This facilitates the formation of a channel region II with a smaller cross-sectional area in a cross section perpendicular to the direction Z, thereby improving the control capability of the word line 107 surrounding the sidewalls of the channel region II over the channel region II, thereby making it easier to control the conduction or shutdown of the GAA transistor. In other embodiments, the orthographic projections of the first doped region, the channel region, and the second doped region on the substrate can be equal; alternatively, the orthographic projections of the channel region and the second doped region on the substrate can both be smaller than the orthographic projection of the first doped region on the substrate.

[0044] In some examples, reference Figure 3 and Figure 5 In the cross section perpendicular to the direction Z, the width W of the channel region II and the length L of the channel region II are both no greater than 10 nm, which is beneficial to ensuring that the word line 107 has good control over the channel region II.

[0045] Specifically, the isolation layer 103 may include a second dielectric layer 123 , a third dielectric layer 133 , a fourth dielectric layer 143 and a fifth dielectric layer 153 .

[0046] The fourth dielectric layer 143 is located between adjacent bit lines 104 and between adjacent first doped regions I on adjacent bit lines 104. The fifth dielectric layer 153 is located on the sidewalls of adjacent first doped regions I on the same bit line 104 and on the sidewalls of the fourth dielectric layer 143. A first gap is formed between adjacent fifth dielectric layers 153. The fourth dielectric layer 143 and the fifth dielectric layer 153 together provide electrical insulation between adjacent first doped regions I and adjacent bit lines 104.

[0047] In some examples, the material of the fourth dielectric layer 143 is the same as the material of the fifth dielectric layer 153. Furthermore, the material of the fourth dielectric layer 143 and the material of the fifth dielectric layer 153 can both be silicon oxide. In other embodiments, the material of the fourth dielectric layer and the material of the fifth dielectric layer can also be different, as long as the material of the fourth dielectric layer and the material of the fifth dielectric layer are materials with good insulation performance.

[0048] There is a second gap between adjacent word lines 107, the second dielectric layer 123 covers the sidewall surface of the second doped region III, and a third gap is formed between the second dielectric layers 123 located on the sidewalls of adjacent second doped regions III; the third dielectric layer 133 is located in the first gap, the second gap and the third gap.

[0049] Specifically, the first gap, the second gap and the third gap are connected. In some embodiments, reference Figures 3 to 5 , the third dielectric layer 133 fills the first gap, the second gap, and the third gap, and the top surface of the third dielectric layer 133 away from the substrate 11 is higher than the top surface of the second doped region III away from the substrate 11. In some other embodiments, Figure 6 , a fourth gap 109 is provided in the third dielectric layer 133 located in the second gap. That is, in addition to the third dielectric layer 133, a fourth gap 109 is provided between adjacent word lines 107. This helps reduce the capacitance generated between adjacent word lines 107, thereby improving the electrical characteristics of the semiconductor structure. In other examples, the fourth gap may exist not only in the third dielectric layer located in the second gap, but also in the third dielectric layer located in the first gap, or in the third dielectric layer located in the third gap.

[0050] In this embodiment, the fourth dielectric layer 143 and the fifth dielectric layer 153 together constitute the first isolation layer 113. The orthographic projection of the outer periphery of the insulating layer 106 on the substrate 11 is smaller than the orthographic projection of the outer periphery of the first isolation layer 113 on the substrate 11. Figures 3 to 5The insulating layer 106 is further away from the outer wall of the semiconductor channel 105 than the first isolation layer 113 is from the outer wall of the semiconductor channel 105, and is closer to the semiconductor channel 105. The insulating layer 106 is made of silicon oxide. In other embodiments, the insulating layer and the second dielectric layer can be formed in the same film structure, that is, the insulating layer and the third dielectric layer can be formed in the same process step. The insulating layer and the third dielectric layer are made of at least one of silicon oxide and silicon nitride.

[0051] The semiconductor structure may further include a metal contact layer 108 located on a top surface of the second doped region III away from the substrate 11, wherein the metal semiconductor compound 114 and the metal contact layer 108 contain the same metal element. The metal element includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0052] Because the metal contact layer 108 contains metal elements, when the lower electrode of the capacitor structure is subsequently formed on the metal contact layer 108, the metal contact layer 108 forms an ohmic contact with the lower electrode, preventing the lower electrode from directly contacting the semiconductor material and forming a Schottky barrier contact. The ohmic contact helps reduce the contact resistance between the second doped region III and the lower electrode, thereby reducing the energy consumption of the semiconductor structure during operation and improving the RC delay effect, thereby improving the electrical performance of the semiconductor structure. In addition, from a manufacturing process perspective, the metal contact layer 108 and the metal-semiconductor compound 114 contain the same metal elements, which facilitates the formation of the metal contact layer 108 and the metal-semiconductor compound 114 in the bit line 104 in a single process step.

[0053] Furthermore, the orthographic projection of the metal contact layer 108 on the substrate 11 covers the orthographic projection of the second doping region III on the substrate 11, which is beneficial to increasing the contact area between the metal contact layer 108 and the lower electrode, thereby reducing the contact resistance between the metal contact layer 108 and the lower electrode, thereby improving the electrical performance of the semiconductor structure.

[0054] The semiconductor structure may further include: a transition layer 118, located between the second doping region III and the metal contact layer 108, and the transition layer 118 is located on a portion of the top surface of the second doping region III, and the metal contact layer 108 wraps the remaining surface of the transition layer 118, the transition layer 118 and the second doping region III are doped with the same type of doping ions, and the doping concentration of the doping ions in the transition layer 118 is greater than the doping concentration in the second doping region III, then the resistance of the transition layer 118 is less than the resistance of the second doping region III, which is beneficial to further reduce the transmission resistance between the second doping region III and the lower electrode.

[0055] In other embodiments, the semiconductor structure may not include a transition layer, and the top surface of the second doped region only has a metal contact layer.

[0056] The semiconductor structure may further include: a capacitor structure (not shown in the figure), which is located on the surface formed by the metal contact layer 108 and the third dielectric layer 133 .

[0057] To sum up, a vertical GAA transistor is provided on the substrate 11, and in the GAA transistor, the majority carrier concentration in the channel region II is lower than the majority carrier concentration in the first doping region I, and is also lower than the majority carrier concentration in the second doping region III. This is beneficial for ensuring that the majority carrier concentration in the channel region II is low while ensuring that the majority carrier concentration in the first doping region I and the second doping region III is high, so as to increase the on / off ratio of the channel region II while reducing the threshold voltage of the transistor composed of the first doping region I, the channel region II and the second doping region III and increasing the saturation current of the transistor, thereby improving the electrical performance of the semiconductor structure.

[0058] Correspondingly, another embodiment of the present invention further provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.

[0059] Figures 7 to 36 A schematic diagram of the cross-sectional structures corresponding to each step in the method for manufacturing a semiconductor structure provided in another embodiment of the present invention is provided. The method for manufacturing the semiconductor structure provided in this embodiment will be described in detail below in conjunction with the accompanying drawings, and the parts that are the same as or corresponding to the above-mentioned embodiments will not be described in detail below.

[0060] refer to Figures 7 to 10 , providing a substrate 11; forming an initial bit line 124 on the substrate 11, and forming a semiconductor channel 105 on a surface of the initial bit line 124 away from the substrate 11, wherein in a direction along the substrate 11 pointing to the initial bit line 124, the semiconductor channel 105 includes a first doping region I, a channel region II, and a second doping region III arranged in sequence, and the first doping region I, the channel region II, and the second doping region III are doped with first-type doping ions of the same doping concentration, and the first-type doping ions are one of N-type ions or P-type ions.

[0061] Specifically, providing a substrate 11 and forming an initial bit line 124 and a semiconductor channel 105 on the substrate 11 includes the following steps:

[0062] refer to Figure 7 A substrate 110 is provided. Specifically, the material type of the substrate 110 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.

[0063] The substrate 110 includes a base 11 doped with second-type dopant ions, where the second-type dopant ions are N-type ions or P-type ions; and an initial semiconductor layer 10 disposed on the base 11 .

[0064] The initial semiconductor layer 10 is doped and annealed, so that the initial semiconductor layer 10 is doped with first type dopant ions for subsequent etching of the initial semiconductor layer 10 to form initial bit lines 124 and semiconductor channels 105 .

[0065] The doping treatment may be performed by high-temperature diffusion or ion implantation. After the initial semiconductor layer 10 is doped by ion implantation, the annealing temperature is 800° C. to 1000° C.

[0066] In this embodiment, the doping concentration of the first type dopant ions in the initial semiconductor layer 10 is 3×10 19 atom / cm 3 ~1×10 20 atom / cm 3 , and in the direction from the initial semiconductor layer 10 to the substrate 11 , the doping depth of the first type dopant ions in the initial semiconductor layer 10 is 150 nm to 250 nm.

[0067] In this embodiment, the first type of dopant ions are N-type ions, and the second type of dopant ions are P-type ions. In other embodiments, the first type of dopant ions may be P-type ions, and the second type of dopant ions may be N-type ions.

[0068] A buffer layer 120 and a barrier layer 130 are sequentially stacked on the side of the initial semiconductor layer 10 away from the substrate 11. In some examples, the buffer layer 120 and the barrier layer 130 can be formed by a deposition process. The buffer layer 120 is made of silicon oxide, and the barrier layer 130 is made of silicon nitride.

[0069] Furthermore, a chemical vapor deposition process may be used to deposit silicon nitride to form the barrier layer 130 . The oxidation rate of the silicon nitride film layer is very slow, which is beneficial for protecting the substrate 110 located below the silicon nitride film layer and preventing the substrate 110 from being oxidized.

[0070] In some embodiments, substrate 110 is a silicon substrate. Since the lattice constant and thermal expansion coefficient of silicon nitride are significantly mismatched with those of the silicon substrate, if silicon nitride is directly formed on the silicon substrate, the defect density at the interface between silicon nitride and silicon is high, easily becoming carrier traps and recombination centers, affecting the carrier mobility of silicon, thereby affecting the performance and service life of the semiconductor structure. Furthermore, silicon nitride films are subject to high stress and are prone to cracking when deposited directly on a silicon substrate. Therefore, forming silicon oxide as a buffer layer 120 before depositing silicon nitride on the silicon substrate is beneficial for improving the performance and service life of the conductor structure.

[0071] Continue to refer Figure 7 A first mask layer 102 is formed on the barrier layer 130 . The first mask layer 102 has a plurality of mutually separated first openings b. In the extension direction X of the first openings b, the length of the first openings b is consistent with the length of the subsequently formed bit lines.

[0072] refer to Figure 8 The barrier layer 130 , the buffer layer 120 and the initial semiconductor layer 10 are etched using the first mask layer 102 as a mask to form a plurality of first trenches a, and the first mask layer 102 is removed.

[0073] In this embodiment, the depth of the first trench a is 250 nm to 300 nm along a direction Z perpendicular to the surface of the substrate 11. Since the depth of the first trench a is greater than the doping depth of the first type dopant ions in the initial semiconductor layer 10, it is beneficial to ensure that the initial semiconductor layer 10 doped with the first type dopant ions is completely etched, facilitating the subsequent formation of semiconductor channels and bit lines with a high doping concentration of the first type dopant ions.

[0074] refer to Figure 9 , a fourth dielectric layer 143 is formed in the first trench a.

[0075] In this embodiment, the fourth dielectric layer 143 can be formed using the following process steps: performing a deposition process to form a fourth dielectric film that covers the top surface of the barrier layer 130 and completely fills the first trench a; performing a chemical mechanical planarization process on the fourth dielectric film until the top surface of the barrier layer 130 is exposed, with the remaining fourth dielectric film serving as the fourth dielectric layer 143. The fourth dielectric film is made of silicon oxide.

[0076] Furthermore, a second mask layer 112 is formed on the top surface formed by the fourth dielectric layer 143 and the remaining barrier layer 130. The second mask layer 112 has a plurality of mutually discrete second openings c. In the extension direction Y along the second openings c, the length of the second openings c is consistent with the length of the subsequently formed word line.

[0077] In this embodiment, combined with reference Figure 7 and Figure 9The extension direction X of the first opening b is perpendicular to the extension direction Y of the second opening c, so that the semiconductor channel 105 formed finally presents a 4F 2 The arrangement is conducive to further improving the integration density of the semiconductor structure. In other embodiments, the extension direction of the first opening intersects with the extension direction of the second opening, and the angle between the two may not be 90°.

[0078] Furthermore, the ratio of the opening width of the first opening b along direction Y to the opening width of the second opening c along direction X is 2 to 1, ensuring that a through hole can be subsequently formed that exposes the initial first dielectric layer surrounding the sidewalls of the channel region II, thereby facilitating the subsequent self-aligned formation of word lines. In some examples, the opening width of the first opening b along direction Y is equal to the opening width of the second opening c along direction X, and the spacing between adjacent first openings b is equal to the spacing between adjacent second openings c. This, on the one hand, ensures that the multiple semiconductor channels formed subsequently are arranged in a regular pattern, further improving the integration density of the semiconductor structure; on the other hand, the same mask can be used to form the first mask layer 102 and the second mask layer 112, which helps reduce the manufacturing cost of the semiconductor structure.

[0079] In this embodiment, the methods of forming the first mask layer 102 and the second mask layer 112 both include self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP).

[0080] refer to Figure 10 , the initial semiconductor layer 10 is etched using the second mask layer 112 as a mask (refer to Figure 7 ) and the fourth dielectric layer 143, forming a plurality of second trenches d, initial bit lines 124, and semiconductor channels 105. In the direction Z perpendicular to the surface of the substrate 11, the depth of the second trenches d is less than the depth of the first trenches a. This facilitates the formation of the initial bit lines 124 while simultaneously forming a plurality of mutually separated semiconductor channels 105 on a side of the initial bit lines 124 away from the substrate 11, and the initial bit lines 124 are in contact with the first doped regions I of the semiconductor channels 105. The second mask layer 112 is removed.

[0081] In some examples, the depth of the second trench d is 100 nm to 150 nm. Since the doping depth of the first type of dopant ions in the initial semiconductor layer 10 is 150 nm to 250 nm, it is beneficial for the initial semiconductor layer 10 that is mostly or completely doped with the first type of dopant ions to be transformed into a semiconductor channel 105 after two etchings.

[0082] In addition, the material of the substrate 110 is silicon, and the material of the fourth dielectric layer 143 is silicon oxide. In the step of etching the initial semiconductor layer 10 and the fourth dielectric layer 143 using the second mask layer 112 as a mask, the etching rate of the silicon oxide is greater than the etching rate of the silicon, so that part of the sidewall of the initial bit line 124 will be exposed.

[0083] In order to achieve electrical insulation between adjacent initial bit lines 124 and adjacent semiconductor channels 105, after the initial semiconductor layer 10 and the fourth dielectric layer 143 are etched using the second mask layer 112 as a mask, the remaining fourth dielectric layer 143 is still located in the gaps between adjacent initial bit lines 124 and in the gaps between adjacent semiconductor channels 105.

[0084] In this embodiment, a GAA transistor in which the semiconductor channel 105 is formed perpendicular to the initial bit line 124 and away from the top surface of the substrate 11 can constitute a 3D stacked semiconductor structure. This is beneficial for designing GAA transistors with smaller size features without adversely affecting the electrical performance of the GAA transistor, thereby improving the integration density of the semiconductor structure.

[0085] In addition, the initial bit line 124 and the semiconductor channel 105 are simultaneously formed through two etching processes using the first mask layer 102 and the second mask layer 112. On the one hand, this is beneficial for regulating the size of the semiconductor channel 105 by regulating the sizes of the first opening b and the second opening c, thereby forming a semiconductor channel 105 with higher dimensional accuracy. On the other hand, the initial bit line 124 and the semiconductor channel 105 are both formed by etching the initial semiconductor layer 10, that is, the initial bit line 124 and the semiconductor channel 105 are formed using the same film layer structure, so that the initial bit line 124 and the semiconductor channel 105 are an integrated structure, thereby improving the interface state defects between the initial bit line 124 and the semiconductor channel 105 and improving the performance of the semiconductor structure.

[0086] refer to Figures 11 to 34 , forming a first isolation layer 113 covering the side wall surface of the first doping region I, and a first gap exists between the first isolation layers 113 on the side walls of adjacent first doping regions I on the same initial bit line 124, and the first gap exposes the initial bit line 124; forming a second isolation layer 163, the second isolation layer 163 is located in the first gap, and the top surface of the second isolation layer 163 away from the substrate 11 is not lower than the top surface of the second doping region III away from the substrate 11, and a second gap exists between the second isolation layer 163 and the channel region II; forming a third isolation layer 173 covering the side wall surface of the second doping region III, the third isolation layer 173 is in contact with the second isolation layer 163, and a third gap exists between the second isolation layers 163 on the side walls of adjacent second doping regions III on adjacent initial bit lines 124, and the second gap and the third gap are connected.

[0087] in, Figure 12 for Figure 11 The structure shown is a cross-sectional schematic diagram along the first cross-sectional direction AA1, Figure 13 for Figure 11 The structure shown is a schematic cross-sectional view along the second cross-sectional direction BB1. It should be noted that, in the following, one or both of the schematic cross-sectional views along the first cross-sectional direction AA1 and the second cross-sectional direction BB1 will be provided as needed for description. When only one figure is referenced, the figure is the schematic cross-sectional view along the first cross-sectional direction AA1; when both figures are referenced, the figure first shows the schematic cross-sectional view along the first cross-sectional direction AA1, followed by the schematic cross-sectional view along the second cross-sectional direction BB1.

[0088] In some embodiments, in conjunction with reference Figure 1 and references Figures 11 to 33 The steps of forming the first isolation layer 113, the second isolation layer 163, the third isolation layer 173, the insulating layer 106, the word line 107 and the isolation layer 103 include the following:

[0089] refer to Figure 11 , forming an initial first isolation layer 113 a , the initial first isolation layer 113 a surrounds the sidewall of the semiconductor channel 105 , and a fourth gap e is present between the initial first isolation layers 113 a on the sidewalls of adjacent semiconductor channels 105 on the same initial bit line 124 .

[0090] The steps of forming the initial first isolation layer 113a may include forming a first isolation film, the first isolation film conformally covering the second trench d (refer to Figure 10 ), and is also located on the sidewall and bottom of the barrier layer 130 and the top surface of the fourth dielectric layer 143; the first isolation film is subjected to a maskless dry etching process until the barrier layer 130 is exposed, and within the same etching time, the etching process etches the first isolation film to the same thickness in different areas to form a fifth dielectric layer 153.

[0091] Combined with reference Figures 11 to 13 The fifth dielectric layer 153 is located in the second trench d (refer to Figure 10 ), the fourth dielectric layer 143 is located in the gap between adjacent semiconductor channels 105, the fourth dielectric layer 143 and the fifth dielectric layer 153 together constitute the initial first isolation layer 113a, and there is a fourth gap e between the fifth dielectric layer 153 located on the sidewall of the second trench d.

[0092] The material of the fourth dielectric layer 143 is the same as that of the fifth dielectric layer 153. This facilitates the subsequent removal of the fourth and fifth dielectric layers 143 and 153 corresponding to the sidewalls of the channel region II through an etching process. This creates a gap between the sidewalls of the channel region II and the subsequently formed second isolation layer, facilitating the subsequent formation of a gap for forming word lines. Furthermore, the material of the fourth dielectric layer 143 and the fifth dielectric layer 153 are both silicon oxide.

[0093] In other embodiments, the material of the fourth dielectric layer and the material of the fifth dielectric layer may also be different, as long as the material of the fourth dielectric layer and the material of the fifth dielectric layer are materials with good insulation effect. Then, the fourth dielectric layer and the fifth dielectric layer corresponding to the sidewalls of the channel region can be removed step by step.

[0094] refer to Figure 14 , forming a second isolation layer 163, the second isolation layer 163 fills the fourth spacer e (reference Figure 13 ), and the material of the second isolation layer 163 is different from the material of the initial first isolation layer 113a. The material of the second isolation layer 163 includes silicon nitride.

[0095] refer to Figure 15 , partially etch the initial first isolation layer 113a until the sidewall of the second doped region III is exposed.

[0096] refer to Figures 16 to 19 ,in, Figure 17 for Figure 16 A top view of Figure 18 is a cross-sectional schematic diagram along the third cross-sectional direction CC1, Figure 19 It is a cross-sectional schematic diagram along the second cross-sectional direction BB1.

[0097] A third isolation layer 173 is formed, and the third isolation layer 173 surrounds the side wall of the second doping region III and the side wall of the second isolation layer 163. The third isolation layer 173 located on the side wall of the second doping region III and the third isolation layer 173 located on the side wall of the second isolation layer 163 together form a through hole f, and the bottom of the through hole f exposes the initial first isolation layer 113a, and the material of the third isolation layer 173 is different from the material of the initial first isolation layer 113a.

[0098] Further, refer to Figure 18 and Figure 19 The third isolation layer 173 surrounds the sidewall of the second doped region III and covers the top surface of the fifth dielectric layer 153 and a portion of the top surface of the fourth dielectric layer 143 . The through hole f exposes a portion of the top surface of the fourth dielectric layer 143 .

[0099] In this embodiment, the third isolation layer 173 can be formed using the following process steps: a deposition process is performed to form a third isolation film that conformally covers the surface formed by the semiconductor channel 105, the initial first isolation layer 113a, and the second isolation layer 163; the third isolation film is subjected to a maskless dry etching process until the top surface of the second doped region III is exposed, and the etching process is performed to the same thickness in different regions of the third isolation film within the same etching time, thereby forming the third isolation layer 173 that exposes the second isolation layer 163. The material of the third isolation layer 173 includes silicon nitride.

[0100] Furthermore, in the aforementioned first mask layer 102 and second mask layer 112, the ratio of the opening width of the first opening b along the direction Y to the opening width of the second opening c along the direction X is 2 to 1. This facilitates ensuring that, when forming the third isolation layer 173, the third isolation layer 173 completely fills the gaps between adjacent semiconductor channels 105 on the same initial bit line 124 while not completely filling the gaps between adjacent semiconductor channels 105 on adjacent initial bit lines 124, thereby ensuring the formation of a through hole f that exposes a portion of the top surface of the fourth dielectric layer 143, facilitating the subsequent removal of a portion of the initial first isolation layer 113a using the through hole f.

[0101] Combined with reference Figures 20 to 22 , remove the initial first isolation layer 113a on the sidewall of the channel region II exposed by the through hole f, and the remaining initial first isolation layer 113a (reference Figure 18 ) as the first isolation layer 113.

[0102] Since the through hole f exposes part of the top surface of the initial first isolation layer 113a, and the material of the initial first isolation layer 113a is different from the materials of the second isolation layer 163 and the third isolation layer 173, an etching solution can be injected into the through hole f, and the initial first isolation layer 113a located on the side wall of the channel region II is removed through a wet etching process, and the initial first isolation layer 113a located on the side wall of the first doping region I is retained as the first isolation layer 113.

[0103] Furthermore, the second isolation layer 163 and the third isolation layer 173 together form a support framework, which is in contact with and connected to the second doped region III, and partially embedded in the first isolation layer 113. During the wet etching process, the support framework, on the one hand, supports and secures the semiconductor channel 105. When the etching liquid flows, it generates a squeezing force on the semiconductor channel 105, which helps prevent the semiconductor channel 105 from tilting or deflecting due to the squeezing, thereby improving the stability of the semiconductor structure. On the other hand, the support framework wraps around the sidewalls of the second doped region III, which helps prevent the etching liquid from damaging the second doped region III.

[0104] After the initial first isolation layer 113 a located on the sidewall of the channel region II is removed, a second gap g is formed between the channel region II and the second isolation layer 163 . The through hole f and the second gap g together form a cave structure h.

[0105] In this embodiment, reference Figure 23 and Figure 24 , a protection layer 119 is formed on the sidewall surface of the channel region II, and the protection layer 119 covers the sidewall surface of the channel region II.

[0106] Taking semiconductor channel 105 made of silicon as an example, the exposed sidewalls of channel region II are thermally oxidized to form a protective layer 119. Protective layer 119 covers the remaining sidewall surfaces of channel region II, with a fifth spacer i between protective layer 119 and second isolation layer 163. Specifically, the thickness of protective layer 119 in a direction perpendicular to the sidewalls of channel region II is 1 nm to 2 nm. In other embodiments, the protective layer can also be formed by a deposition process.

[0107] On the one hand, when the sacrificial layer is subsequently formed, the protective layer 119 is used to isolate the sacrificial layer and the channel region II to avoid contamination of the channel region II when the sacrificial layer is formed; on the other hand, when the sacrificial layer and the protective layer 119 are subsequently removed, the protective layer 119 acts as an etching buffer to prevent the sidewalls of the channel region II from being over-etched.

[0108] During the thermal oxidation process, the top surface of the second doping region III is also exposed, and a portion of the second doping region III close to the top surface and the sidewall of the channel region II are converted into the protection layer 119 .

[0109] refer to Figure 25 and Figure 26 A sacrificial layer 129 doped with the second type of dopant ions is formed on the sidewall of the protection layer 119 away from the channel region II, and the sacrificial layer 129 at least covers the sidewall of the channel region II.

[0110] In this embodiment, a deposition process can be used to form a sacrificial layer 129 that fills the through hole f and the fifth spacer i, that is, the sacrificial layer 129 fills the space between the adjacent protective layer 119 and is located in the space between the adjacent second doping region III. The sacrificial layer 129 formed in this way has a larger volume, which is beneficial for providing more second-type doping ions during the subsequent annealing process, so that more second-type doping ions diffuse into the channel region II to reduce the majority carrier concentration in the channel region II.

[0111] The sacrificial layer 129 is made of polysilicon. Since polysilicon contains a lot of impurities, a protective layer 119 between the channel region II and the sacrificial layer 129 is provided to prevent the channel region II from being contaminated by impurities when forming the polysilicon. The second type of doping ions may be boron ions.

[0112] Specifically, the doping concentration of the second type dopant ions in the sacrificial layer 129 is 4×10 20 atom / cm 3 ~9×10 20 atom / cm 3 In some embodiments, the doping concentration of the second type dopant ions in the sacrificial layer 129 is 1×10 21 atom / cm 3 , which helps to ensure that after the subsequent annealing process, the effective doping concentration range of the first type of dopant ions in the channel region II is 8×10 18 atom / cm 3 ~2×10 19 atom / cm 3 .

[0113] In other embodiments, the protective layer may not be formed on the sidewalls of the channel region, and a sacrificial layer doped with the second type of dopant ions may be directly formed on the sidewall surface of the channel region.

[0114] An annealing process is employed to diffuse the second-type dopant ions into the channel region II, thereby reducing the majority carrier concentration in the channel region II. Since the first dopant region I, the channel region II, and the second dopant region III are all doped with the first-type dopant ions in the aforementioned process, when the second-type dopant ions diffuse into the channel region II, the effective doping concentration of the first-type dopant ions in the channel region II is lower than the effective doping concentration in the first dopant region I and lower than the effective doping concentration in the second dopant region III. Consequently, the majority carrier concentration in the channel region II is lower than the majority carrier concentration in the first dopant region I and also lower than the majority carrier concentration in the second dopant region III. This is beneficial for improving the on / off ratio of the channel region II while reducing the threshold voltage and increasing the saturation current of the transistor formed by the first dopant region I, the channel region II, and the second dopant region III.

[0115] Specifically, during the annealing process, the second-type dopant ions diffuse from the channel region II toward the first doping region I, or from the channel region II toward the second doping region III. This reduces the effective doping concentration of the first-type dopant ions in the portion of the first doping region I in contact with the channel region II, and reduces the effective doping concentration of the first-type dopant ions in the portion of the second doping region III in contact with the channel region II. This helps reduce the impact ionization effect on the semiconductor structure and reduces GIDL.

[0116] In addition, since the side walls of the second doped region III are protected by the third isolation layer 173 and the top surface of the second doped region III is protected by the protective layer 119, there is no need to etch the sacrificial layer 129. The annealing process can be directly performed to achieve the purpose of diffusing the second type of doped ions in the channel region II, which is beneficial to simplify the manufacturing steps of the semiconductor structure.

[0117] refer to Figure 27 and Figure 28 The sacrificial layer 129 and the protective layer 119 are removed to expose the sidewalls of the channel region II, re-forming the through hole f and the larger second spacer k. Furthermore, the orthographic projection of the channel region II on the substrate 11 is smaller than the orthographic projection of the second doped region III on the substrate 11, and smaller than the orthographic projection of the first doped region I on the substrate 11. In this embodiment, because the sacrificial layer 129 is made of polysilicon and the channel region II is made of silicon, the etch rates of the sacrificial layer 129 and the channel region II are relatively small when the same etching process is used. Therefore, when removing the sacrificial layer 129, the protective layer 119 can serve as an etch barrier to prevent damage to the channel region II.

[0118] refer to Figures 29 to 31 , forming an insulating layer 106 covering the sidewall surface of the channel region II; forming a word line 107 covering the sidewall surface of the insulating layer 106 away from the channel region II, and the word line 107 and the insulating layer 106 together fill the second spacer k (reference Figure 28 ).

[0119] In this embodiment, the exposed sidewalls of the channel region II are thermally oxidized to form an insulating layer 106, which further makes the orthographic projection of the channel region II on the substrate 11 smaller than the orthographic projection of the second doped region III on the substrate 11, and smaller than the orthographic projection of the first doped region I on the substrate 11. This is beneficial for forming a channel region II with a smaller cross-sectional area in a cross section perpendicular to the direction Z without using an etching process, which is beneficial for improving the control ability of the word line 107 over the channel region II, thereby making it easier to control the conduction or shutdown of the GAA transistor. The material of the insulating layer 106 is silicon oxide. In other embodiments, an insulating layer covering the surface of the sidewalls of the channel region can also be formed by a deposition process.

[0120] The step of forming word line 107 includes: forming an initial word line, the initial word line filling the second spacer k and the through hole f; removing the initial word line located in the through hole f, and the remaining initial word line serving as word line 107. The initial word line can be formed by a deposition process, and the material of the initial word line includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, or tungsten.

[0121] The initial word line self-aligns to fill the second spacer k and the through-hole f. After removing the initial word line in the through-hole f, it is beneficial to self-align to form a word line 107 with precise size. There is no need to design the size of the word line 107 through an etching process, which is beneficial to simplify the steps of forming the word line 107. By adjusting the size of the second spacer k, a small-sized word line 107 can be obtained.

[0122] refer to Figure 32 After forming the word line 107, a fourth isolation layer 183 is formed, and the fourth isolation layer 183 fills the through hole f (refer to Figure 30 ).

[0123] In this embodiment, the fourth isolation layer 183 is made of the same material as the second isolation layer 163 and the third isolation layer 173, all comprising silicon nitride. In other embodiments, the third isolation film may be chemically and mechanically planarized until the top surface of the second doped region is exposed. Specifically, the insulating layer located on the top surface of the second doped region is simultaneously removed, leaving the remaining third isolation film as the third isolation layer.

[0124] Continue to refer Figure 32 , remove the insulating layer 106 located on the top surface of the second doping region III (refer to Figure 29 ), an epitaxial growth process is used to form an initial transition layer 128 on the top surface of the second doping region III, and the orthographic projection of the initial transition layer 128 on the substrate 11 covers the orthographic projection of the second doping region III on the substrate 11.

[0125] In addition, in the epitaxial growth process step, the initial transition layer 128 is also doped with the first type of doping ions, and the doping concentration of the first type of doping ions in the initial transition layer 128 is greater than the doping concentration in the second doping region III, then the resistance of the initial transition layer 128 is less than the resistance of the second doping region III.

[0126] On the one hand, the use of the epitaxial growth process is beneficial to improving the continuity between the second doped region III and the initial transition layer 128, reducing contact defects caused by different lattice characteristics or lattice dislocations, reducing contact resistance caused by contact defects, and improving the carrier transmission capacity and movement speed, thereby improving the conductivity between the second doped region III and the initial transition layer 128, and reducing the heat generated during the operation of the semiconductor structure; on the other hand, the use of the epitaxial growth process is beneficial to increasing the positive projection of the initial transition layer 128 on the substrate 11, which is beneficial to making the positive projection area of ​​the initial transition layer 128 on the substrate 11 larger than the positive projection area of ​​the second doped region III on the substrate 11. It can be used as a mask subsequently to avoid the formation of a second dielectric layer surrounding the side wall of the second doped region III from being etched to expose the second doped region III, so as to ensure that the subsequently formed second dielectric layer has a good protective effect on the second doped region III.

[0127] Combined with reference Figure 32 and Figure 33 Using the initial transition layer 128 as a mask, the second isolation layer 163, the third isolation layer 173, and the fourth isolation layer 183 are etched to expose the sidewalls of the second doped region III. The top surface of the remaining second isolation layer 163 is no higher than the top surface of the word line 107. The orthographic projection of the initial transition layer 128 on the substrate 11 covers the orthographic projection of the second doped region III on the substrate 11, which helps prevent the semiconductor channel 105 from being etched during this step.

[0128] Furthermore, a second dielectric film is formed conformally covering the surface of the initial transition layer 128, the sidewalls of the second doped region III, the top surface of the wordline 107, and the top surface of the second isolation layer 163. A chemical mechanical planarization process is performed on the second dielectric film until the surface of the initial transition layer 128 is exposed. The remaining second dielectric film is then etched using the initial transition layer 128 as a mask. Because the orthographic projection area of ​​the initial transition layer 128 on the substrate 11 is larger than the orthographic projection area of ​​the second doped region III on the substrate 11, this facilitates the removal of the second dielectric film located on the surface of the initial transition layer 128, the top surface of the second isolation layer 163, and a portion of the top surface of the wordline 107 while avoiding etching of the second dielectric film directly opposite the orthographic projection of the initial transition layer 128 on the substrate 11. This results in the formation of the second dielectric layer 123 surrounding the sidewalls of the second doped region III, ensuring that the second dielectric layer 123 effectively protects the second doped region III. The second dielectric film can be formed using a deposition process.

[0129] Furthermore, the remaining second isolation layer 163 is removed to expose the top surface of the initial bit line 124 .

[0130] In other embodiments, the second isolation layer, the third isolation layer and the fourth isolation layer are etched using the initial transition layer as a mask to expose the initial bit line and the sidewall of the second doped region; then the exposed sidewall of the second doped region is thermally oxidized to form a second dielectric layer.

[0131] Combined with reference Figure 33 and Figures 1 to 5 The exposed initial bit line 124 and the initial transition layer 128 are metallized to form a bit line 104 . The material of the bit line 104 includes a metal semiconductor compound 114 .

[0132] Specifically, a metal layer is formed on the surface of the initial transition layer 128 and on the top surface of the initial bit line 124. The metal layer provides metal elements for forming the bit line 104. The metal layer is also located on the exposed surfaces of the second dielectric layer 123, the word line 107, and the first isolation layer 113. The material of the metal layer includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0133] An annealing process is performed to convert a partial thickness of the initial transition layer 128 into the metal contact layer 108 and a partial thickness of the initial bit line 124 into the bit line 104. After the bit line 104 is formed, the remaining metal layer is removed.

[0134] In some embodiments, during the annealing process, the metal layer reacts with the initial transition layer 128 and the initial bit line 124, and a portion of the initial transition layer 128 is converted into the metal contact layer 108, and a portion of the initial bit line 124 is converted into the bit line 104. Specifically, in one example, referring to Figure 3 , the plurality of metal-semiconductor compounds 114 in the same bit line 104 are spaced apart from each other; in another example, referring to Figure 4 ,, the multiple metal-semiconductor compounds 114 in the same bit line 104 are connected to each other.

[0135] In other embodiments, the entire thickness of the initial transition layer can be converted into a metal contact layer, and the entire thickness of the initial bit line can be converted into a bit line.

[0136] In other embodiments, when an initial transition layer is not formed on the top surface of the second doped region, the insulating layer on the top surface of the second doped region is not removed first, and only the initial bit line is subsequently metallized. After the bit line is formed, the insulating layer on the top surface of the second doped region is removed. Alternatively, when an initial transition layer is not formed on the top surface of the second doped region, after removing the insulating layer on the top surface of the second doped region and exposing the sidewalls of the second doped region, a second dielectric film is then formed conformally covering the top surface and sidewalls of the second doped region, the top surface of the word line, and the top surface of the second isolation layer. The second dielectric film is then vertically etched to remove the second dielectric film on the top surface of the second doped region, the top surface of the second isolation layer, and a portion of the top surface of the word line, while retaining the second dielectric film on the sidewalls of the second doped region as the second dielectric layer.

[0137] Continue to refer Figure 33 and Figures 1 to 5 , forming a third dielectric layer 133, the third dielectric layer 133 fills the first gaps between adjacent first isolation layers 113, the second gaps between adjacent word lines 107, and the third gaps between adjacent second dielectric layers 123, for achieving electrical insulation between adjacent semiconductor channels 105 and adjacent word lines 107. In some examples, referring to Figure 6 When forming the third dielectric layer 133 , the third dielectric layer 133 located in the second gap may further include a fourth gap 109 .

[0138] In this embodiment, the second dielectric layer 123 , the third dielectric layer 133 , the fourth dielectric layer 143 and the fifth dielectric layer 153 together constitute the isolation layer 103 .

[0139] In some other examples, reference Figure 11 to Figure 1 and Figures 34 to 36 , forming the first isolation layer 113, the insulating layer 106, the word line 107 and the third dielectric layer 133 includes the following steps:

[0140] refer to Figures 11 to 14 , forming an initial first isolation layer 113a, the initial first isolation layer 113a surrounds the sidewall of the semiconductor channel 105, and a fourth space e is present between the initial first isolation layers 113a on the sidewalls of adjacent semiconductor channels 105 on the same initial bit line 124; forming a second isolation layer 163, the second isolation layer 163 fills the fourth space e, and the material of the second isolation layer 163 is different from that of the initial first isolation layer 113a.

[0141] Specifically, the steps of forming the initial first isolation layer 113 a and the second isolation layer 163 are the same as those in the above example and are not described herein in detail.

[0142] refer to Figure 34 , etching part of the initial first isolation layer 113a (reference Figure 14 ) until the sidewalls of the second doping region III and the sidewalls of the channel region II are exposed, and the remaining initial first isolation layer 113a serves as the first isolation layer 113.

[0143] Furthermore, a protection layer 119 is formed to cover the sidewalls of the second doping region III and the sidewalls of the channel region II, and a sixth gap m is present between the protection layer 119 and the second isolation layer 163 .

[0144] Taking the semiconductor channel 105 material as an example, a thermal oxidation process is performed on the exposed sidewalls of the second doped region III and the sidewalls of the channel region II to form a protective layer 119. The protective layer 119 covers the remaining sidewall surfaces of the second doped region III and the remaining sidewall surfaces of the channel region II. Specifically, the thickness of the protective layer 119 in the direction perpendicular to the direction Z is 1 nm to 2 nm. In other embodiments, the protective layer can also be formed by a deposition process.

[0145] On the one hand, when the sacrificial layer is subsequently formed, the protective layer 119 is used to isolate the sacrificial layer and the channel region II to avoid contamination of the channel region II when the sacrificial layer is formed; on the other hand, when the sacrificial layer and the protective layer 119 are subsequently removed, the protective layer 119 acts as an etching buffer to prevent the sidewalls of the channel region II from being over-etched.

[0146] During the thermal oxidation process, the top surface of the second doping region III is also exposed, and a portion of the second doping region III near the top surface is also converted into the protection layer 119 .

[0147] refer to Figure 35A sacrificial layer 129 doped with the second type of dopant ions is formed on the sidewalls of the protective layer 119 away from the channel region II, and the sacrificial layer 129 only covers the sidewalls of the channel region II. The step of forming the sacrificial layer 129 may include: using a deposition process to form an initial sacrificial layer that fills the sixth spacer m; and etching back the initial sacrificial layer to remove a portion of the initial sacrificial layer until the initial sacrificial layer is only located on the sidewalls of the channel region II. This prevents the second type of dopant ions from diffusing into the second doped region III through the protective layer 119 surrounding the sidewalls of the second doped region III during a subsequent annealing process.

[0148] An annealing process is adopted to diffuse the second type doping ions into the channel region II, so as to reduce the majority carrier concentration in the channel region II.

[0149] Combined with reference Figure 35 and Figure 36 The protective layer 119 and the sacrificial layer 129 are removed to expose the sidewalls of the second doped region III and the sidewalls of the channel region II. An initial insulating layer 116 is formed to cover the sidewalls of the second doped region III and the sidewalls of the channel region II, with a gap between the initial insulating layer 116 and the second isolation layer 163. The initial insulating layer 116 on the sidewalls of the channel region II is the insulating layer 106, and the protective layer 116 covering the sidewalls of the second doped region III is the second dielectric layer 123. The method for forming the initial insulating layer 116 includes a thermal oxidation process or a deposition process.

[0150] In this embodiment, the initial insulating layer 116 located on the top surface of the remaining second doping region III is removed in a subsequent process step. In other embodiments, the initial insulating layer located on the top surface of the remaining second doping region can be removed after the thermal oxidation treatment, leaving only the initial insulating layer covering the remaining channel region and the sidewall surface of the remaining second doping region.

[0151] Furthermore, word lines 107 are formed, and the word lines 107 only surround the sidewalls of the insulating layer 106 located on the sidewalls of the channel region II. The steps of forming the word lines 107 are the same as those in the above example and are not described here in detail.

[0152] After forming the word line 107, the steps of forming a fourth isolation layer, forming an initial transition layer, metallizing the initial transition layer and the initial bit line to form a metal contact layer and the bit line, and forming a third dielectric layer are the same as the above example and will not be repeated here.

[0153] Furthermore, a capacitor structure (not shown) is formed on the surface formed by the metal contact layer 108 and the third dielectric layer 133. In other embodiments, the metal contact layer may not be formed, and after removing the insulating layer located on the top surface of the second doped region, the capacitor structure is directly formed on the surface formed by the second doped region and the third dielectric layer.

[0154] In summary, by forming a cavity structure of a specific shape; using a thermal oxidation process and an annealing process, the second type of dopant ions are diffused into the channel region II that has been doped with the first type of dopant ions, so that the effective doping concentration of the first type of dopant ions in the channel region II is lower than the effective doping concentration in the first doping region I, and lower than the effective doping concentration in the second doping region III, thereby making ditch While the majority carrier concentration of the channel region II is low, the majority carrier concentration of the first doping region I and the second doping region III is ensured to be high, so as to increase the on / off ratio of the channel region II while reducing the threshold voltage of the transistor composed of the first doping region I, the channel region II and the second doping region III and increasing the saturation current of the transistor, thereby improving the electrical performance of the semiconductor structure.

[0155] Those skilled in the art will appreciate that the above-described embodiments are specific examples of the present invention, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a bit line located on the substrate; A semiconductor channel is located on the surface of the bit line. In a direction along the substrate toward the bit line, the semiconductor channel includes a first doping region, a channel region, and a second doping region arranged in sequence. The first doping region contacts the bit line, and the first doping region, the channel region, and the second doping region are doped with first-type doping ions. The channel region is also doped with second-type doping ions, so that the majority carrier concentration in the channel region is lower than the majority carrier concentration in the first doping region and the second doping region. The first-type doping ions are one of N-type ions or P-type ions, and the second-type doping ions are the other of N-type ions or P-type ions.

2. The semiconductor structure according to claim 1, wherein The second type dopant ions are further located in a region of the first doping region close to the channel region and in a region of the second doping region close to the channel region.

3. The semiconductor structure according to claim 1, wherein: The effective doping concentration of the first type doping ions in the channel region is lower than the effective doping concentration in the first doping region, and the effective doping concentration of the first type doping ions in the channel region is lower than the effective doping concentration in the second doping region.

4. The semiconductor structure according to claim 3, wherein: The effective doping concentration of the first type dopant ions in the channel region is 8×10 18 atom / cm 3 ~2×10 19 atom / cm 3 .

5. The semiconductor structure according to claim 3, wherein: The effective doping concentration of the first type doping ions in the first doping region is 3×10 19 atom / cm 3 ~1×10 20 atom / cm 3 , the effective doping concentration of the first type of dopant ions in the second doping region is 3×10 19 atom / cm 3 ~1×10 20 atom / cm 3 .

6. The semiconductor structure according to claim 1, wherein An orthographic projection of the channel region on the substrate is smaller than an orthographic projection of the second doping region on the substrate, and smaller than an orthographic projection of the first doping region on the substrate.

7. The semiconductor structure according to claim 1, wherein The substrate, the bit line, and the semiconductor channel have the same semiconductor element.

8. The semiconductor structure according to claim 7, wherein: The material of the bit line further includes a metal semiconductor compound.

9. The semiconductor structure according to claim 8, wherein: Also includes: A metal contact layer is located on a top surface of the second doping region away from the substrate, and the metal semiconductor compound and the metal contact layer contain the same metal element.

10. The semiconductor structure according to claim 1, wherein: Also includes: an insulating layer covering the sidewall surface of the channel region; a word line covering a sidewall surface of the insulating layer away from the channel region, with a gap formed between adjacent sidewalls of the first doping region, adjacent sidewalls of the word line, and adjacent sidewalls of the second doping region; An isolation layer is located in the gap, and a top surface of the isolation layer away from the substrate is not lower than a top surface of the second doping region away from the substrate.

11. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; An initial bit line is formed on the substrate, and a semiconductor channel is formed on a surface of the initial bit line away from the substrate, wherein the semiconductor channel comprises a first doping region, a channel region, and a second doping region arranged in sequence along the substrate toward the initial bit line, and the first doping region, the channel region, and the second doping region are doped with first-type doping ions of the same doping concentration, and the first-type doping ions are one of N-type ions or P-type ions; forming a sacrificial layer doped with second-type dopant ions on sidewalls of the channel region, wherein the sacrificial layer at least covers the sidewalls of the channel region, wherein the second-type dopant ions are the other of N-type ions or P-type ions; Using an annealing process to diffuse the second type dopant ions into the channel region to reduce the majority carrier concentration in the channel region; The sacrificial layer is removed to expose the sidewalls of the channel region.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The doping concentration of the second type of dopant ions in the sacrificial layer is 4×10 20 atom / cm 3 ~9×10 20 atom / cm 3 .

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: Before forming a sacrificial layer doped with second type dopant ions on the sidewalls of the channel region, the method further includes: forming a protective layer on the sidewall surface of the channel region, wherein the protective layer covers the sidewall surface of the channel region; After removing the sacrificial layer, the method further includes removing the protective layer.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: The sacrificial layer fills the space between the adjacent protection layers and is located in the space between the adjacent second doping regions.

15. The method for manufacturing a semiconductor structure according to claim 11, wherein: In the annealing process, the diffusion direction of the second type doping ions is from the channel region to the first doping region or from the channel region to the second doping region.

16. The method for manufacturing a semiconductor structure according to claim 11, wherein: Before forming a sacrificial layer doped with second type dopant ions on the sidewalls of the channel region, the method further includes: forming a first isolation layer covering the sidewall surface of the first doped region, with a first gap between the first isolation layers on adjacent sidewalls of the first doped region on the same initial bit line, and the first gap exposing the initial bit line; forming a second isolation layer, wherein the second isolation layer is located in the first gap, and a top surface of the second isolation layer away from the substrate is not lower than a top surface of the second doped region away from the substrate, and a second gap is formed between the second isolation layer and the channel region; A third isolation layer is formed covering the sidewall surface of the second doping region, the third isolation layer is in contact with the second isolation layer, and a third spacer is provided between the second isolation layers on adjacent sidewalls of the second doping regions on adjacent initial bit lines, and the second spacer is connected to the third spacer.

17. The method for manufacturing a semiconductor structure according to claim 16, wherein: After removing the sacrificial layer, the method further comprises: forming an insulating layer covering the sidewall surface of the channel region; A word line is formed to cover the sidewall surface of the insulating layer away from the channel region, and the word line and the insulating layer together fill the second space.

18. The method for manufacturing a semiconductor structure according to claim 17, wherein: After forming the word line, the method further includes: removing the second isolation layer and the third isolation layer to expose the initial bit line; The exposed initial bit lines are metallized to form bit lines, wherein the material of the bit lines includes a metal semiconductor compound.

19. The method for manufacturing a semiconductor structure according to claim 18, wherein: After forming the word line and before removing the second isolation layer and the third isolation layer, the method further includes: An epitaxial growth process is used to form an initial transition layer on the top surface of the second doping region away from the substrate, wherein the initial transition layer is doped with the first type of doping ions, the doping concentration of the first type of doping ions in the initial transition layer is greater than the effective doping concentration in the second doping region, and the orthographic projection of the initial transition layer on the substrate covers the orthographic projection of the second doping region on the substrate.

20. The method for manufacturing a semiconductor structure according to claim 19, wherein: The step of performing the metallization process on the initial bit line further includes: performing the metallization process on the initial transition layer.

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