Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the method comprising: providing a substrate; forming a plurality of core structures on the substrate, the plurality of core structures being arranged at equal intervals, the core structure comprising a first core layer and a second core layer connected to each other, the first core layer being parallel to a first direction, the first direction being parallel to a surface of the substrate, an included angle between the first core layer and the second core layer being an obtuse angle, the plurality of first core layers being parallel to each other, and the plurality of second core layers being parallel to each other; forming a first word line layer on the substrate, a pattern of the first word line layer being a pattern of the first core layer formed through a self-aligned double patterning technology; and forming a second word line layer on the substrate, the first word line layer and the second word line layer corresponding to each other and being connected to each other, a pattern of the second word line layer being a pattern of the second core layer formed through the self-aligned double patterning technology. The semiconductor structure formed by the method has improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] With the development of flash memory, NOR (non-OR) flash memory and NAND (non-AND) flash memory are two types of flash memory that are widely used.

[0003] NAND flash memory, which uses a non-linear macrocell model, provides a cost-effective solution for realizing large-capacity solid-state memory. NAND flash memory has advantages such as large capacity and fast rewrite speed, making it suitable for storing large amounts of data. Therefore, it is increasingly widely used in the industry, such as in embedded products including digital cameras, MP3 player memory cards, and compact USB flash drives.

[0004] However, there are still some issues with the existing manufacturing processes for NAND flash memory devices that need to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the process of manufacturing NAND flash memory devices.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a plurality of first word line layers located on the substrate, the plurality of first word line layers being arranged in parallel to each other, the first word line layers being parallel to a first direction, the first direction being parallel to the substrate surface; and a second word line layer located on the substrate, the second word line layer corresponding to and connected to the first word line layer, the included angle between the second word line layer and the first word line layer being an obtuse angle, and the plurality of second word line layers being parallel to each other.

[0007] Optionally, it may also include: a first isolation layer located between adjacent first word line layers; and a second isolation layer located between adjacent second word line layers.

[0008] Optionally, it further includes: a device layer located on the substrate, the device layer having a plurality of parallel floating gate structures, the floating gate structures being parallel to the second direction; the first word line layer and the second word line layer being located on the device layer.

[0009] Optionally, the floating gate structure includes a floating gate oxide layer and a floating gate layer located on the floating gate oxide layer; the material of the floating gate oxide layer includes silicon oxide, and the material of the floating gate layer includes polysilicon or metal, wherein the metal includes tungsten.

[0010] Optionally, the device layer includes: a first dielectric layer, a floating gate structure located within the first dielectric layer, and a word line oxide layer located on the first dielectric layer and on the floating gate structure.

[0011] Optionally, the material of the first isolation layer includes a dielectric material, wherein the dielectric material includes silicon nitride; the material of the second isolation layer includes a dielectric material, wherein the dielectric material includes silicon nitride.

[0012] Optionally, the material of the first word line layer includes polycrystalline silicon or a metal, wherein the metal includes tungsten; the material of the second word line layer includes polycrystalline silicon or a metal, wherein the metal includes tungsten.

[0013] Optionally, it further includes: a plurality of connection layers located on the substrate, the plurality of connection layers being parallel to the second direction and arranged along the first direction, the second direction being parallel to the substrate surface and perpendicular to the first direction; the connection layers being connected to the second word line layer.

[0014] Optionally, the width of the connecting layer in the first direction is greater than the width of the second word line layer.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of core structures on the substrate, wherein the plurality of core structures are arranged at equal intervals, each core structure comprising a first core layer and a second core layer connected to each other, the first core layer being parallel to a first direction, the first direction being parallel to the substrate surface, the included angle between the first core layer and the second core layer being an obtuse angle, the plurality of first core layers being parallel to each other, and the plurality of second core layers being parallel to each other; forming a first word line layer on the substrate, wherein the pattern of the first word line layer is a pattern formed by the first core layer using a self-aligned double patterning technique; and forming a second word line layer on the substrate, wherein the first word line layer and the second word line layer correspond one-to-one and are connected to each other, wherein the pattern of the second word line layer is a pattern formed by the second core layer using a self-aligned double patterning technique.

[0016] Optionally, the method for forming the core structure includes: forming a core material layer on a substrate; forming a first mask layer on the core material layer, wherein the first mask layer exposes a portion of the surface of the core material layer; and etching the core material layer using the first mask layer as a mask until the surface of the substrate is exposed, thereby forming the core structure.

[0017] Optionally, the material of the first mask layer includes photoresist; the process for forming the first mask layer includes coating, exposure, and development processes.

[0018] Optionally, the first word line layer structure and the second word line layer are formed simultaneously.

[0019] Optionally, it further includes: forming a plurality of connection layers on the substrate, the plurality of connection layers being parallel to a second direction and arranged along a first direction, the second direction being parallel to the substrate surface and perpendicular to the first direction; the connection layers being connected to the second word line layer.

[0020] Optionally, the width of the connecting layer in the first direction is greater than the width of the second word line layer.

[0021] Optionally, the method for forming the first core layer, the second core layer, and the connecting layer includes: forming a first sidewall located on the sidewall of the first core layer and a second sidewall located on the sidewall of the second core layer; after forming the first sidewall and the second sidewall, removing the first core layer and the second core layer; after removing the first core layer and the second core layer, forming a plurality of second mask layers on the second sidewall, the plurality of second mask layers being parallel to a second direction and arranged along a first direction; etching the word line material layer using the first sidewall as a mask to form an initial first word line layer; etching the word line material layer using the second sidewall as a mask to form an initial... The second word line layer; the word line material layer is etched using the second mask layer as a mask to form mutually discrete connecting layers; a first isolation layer is formed in the initial first word line layer, the first isolation layer penetrates the initial first word line layer along a first direction, so that the initial first word line layer forms a discrete first word line layer; a second isolation layer is formed in the initial second word line layer, the second isolation layer penetrates the initial second word line layer along a second direction, so that the initial second word line layer forms a discrete second word line layer, one second word line layer is connected to one first word line layer, and one connecting layer is connected to one second word line layer.

[0022] Optionally, the material of the core structure includes amorphous silicon, silicon oxide, or silicon nitride; the process for removing the core structure includes a wet etching process.

[0023] Optionally, the material of the first word line layer includes polycrystalline silicon or a metal, wherein the metal includes tungsten; the material of the second word line layer includes polycrystalline silicon or a metal, wherein the metal includes tungsten.

[0024] Optionally, it also includes: forming a word line material layer on a substrate; the core structure is located on the word line material layer.

[0025] Optionally, before forming the word line material layer on the substrate, the method further includes: forming a device layer on the substrate, the device layer having a plurality of parallel floating gate structures, the floating gate structures being parallel to a second direction; the word line material layer being located on the device layer.

[0026] Optionally, the floating gate structure includes a floating gate oxide layer and a floating gate layer located on the floating gate oxide layer; the material of the floating gate oxide layer includes silicon oxide, and the material of the floating gate layer includes polysilicon or metal, wherein the metal includes tungsten.

[0027] Optionally, the device layer includes: a first dielectric layer, a floating gate structure located within the first dielectric layer, and a word line oxide layer located on the first dielectric layer and on the floating gate structure.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] In the semiconductor structure of this invention, the second word line layer corresponds one-to-one with and is interconnected with the first word line layer, and the included angle between the second word line layer and the first word line layer is an obtuse angle. This results in a more uniform pattern distribution density for the mask patterns forming the second and first word line layers. When forming the mask patterns using exposure technology, the exposure is more uniform and the exposure level is better, allowing the mask patterns to be accurately formed. This reduces the possibility of the pattern forming the first word line layer being disconnected from the pattern forming the second word line layer due to the optical proximity effect, thus improving the yield of forming the second and first word line layers.

[0030] The method of forming the present invention involves forming a plurality of core structures on a substrate. Each core structure includes a first core layer and a second core layer that are interconnected. The first core layer is parallel to a first direction, and the angle between the first core layer and the second core layer is an obtuse angle. This increases the pattern density of the mask pattern forming the first core layer on both sides of the second direction. The pattern of the second core layer increases the exposure of the region adjacent to the mask pattern forming the first core layer, thereby increasing the exposure of the mask pattern forming the first core layer. This allows the mask pattern of the first core layer to be accurately formed, reducing the possibility of the first core layer and the second core layer being disconnected due to the optical proximity effect, and thus improving the yield of the subsequent formation of the second word line layer and the first word line layer.

[0031] Furthermore, it also includes: forming a plurality of interconnect layers on the substrate, wherein the plurality of interconnect layers are parallel to a second direction and arranged along a first direction, the second direction being parallel to the substrate surface and perpendicular to the first direction, and the interconnect layers being connected to a second word line layer. The width of the interconnect layer in the first direction is greater than the width of the second word line layer, which facilitates the design and connection of interconnect lines in subsequent processes. Attached Figure Description

[0032] Figure 1 and Figure 2 This is a schematic cross-sectional view of the semiconductor structure formation process in one embodiment;

[0033] Figures 3 to 8 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0034] As described in the background section, existing manufacturing processes for NAND flash memory devices still have some issues that need improvement. These will be analyzed and explained in conjunction with specific embodiments.

[0035] Figure 1 and Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure formation process in one embodiment.

[0036] Please refer to Figure 1 and Figure 2 , Figure 1 for Figure 2 Top view, Figure 2 for Figure 1 A cross-sectional structural diagram along section line AA1 includes: a substrate 100; a floating gate structure on the substrate 100, the floating gate structure including a floating gate oxide layer 101 and a floating gate layer 102 on the floating gate oxide layer 101; source / drain doped regions 103 located in the substrate 100 on both sides of the floating gate structure; a first dielectric layer 104 on the substrate 104, the floating gate structure located within the first dielectric layer 104; word line oxide layers 105 on the first dielectric layer 104 and the floating gate structure; a second dielectric layer 106 on the word line oxide layer 105; and a core structure on the second dielectric layer 106, the core structure including a first core layer 107 and a second core layer 108 that are perpendicular to and connected to each other, the first core layer 107 extending along a first direction X parallel to the substrate surface, the second core layer 108 extending along a second direction Y parallel to the substrate surface, the first direction X and the second direction Y being perpendicular, a plurality of the first core layers 107 being parallel to each other, and a plurality of the second core layers 108 being parallel to each other.

[0037] The core structure is used to subsequently form a patterned layer on the second dielectric layer 106 using self-aligned double patterning (SADP) technology. This patterned layer serves as a mask layer for etching the second dielectric layer 106 and forming word line structures within it. The method for forming the core structure includes: forming a core material layer on the second dielectric layer 106; forming a patterned mask layer on the core material layer, the patterned mask layer exposing a portion of the surface of the core material layer; and etching the core material layer using the patterned mask layer as a mask until the surface of the second dielectric layer 106 is exposed, thus forming the core structure. The material of the patterned mask layer includes photoresist, and the process for forming the first mask layer includes coating, exposure, and development processes.

[0038] Due to design requirements, several first core layers 107 are arranged parallel to each other along the second direction Y, and several second core layers 108 are arranged parallel to each other along the first direction X. Therefore, the position between the end position where the first core layer 107 and the second core layer 108 are connected and the edge of the substrate (e.g. Figure 1 The area A shown lacks a pattern, resulting in uneven pattern density on both sides of the first core layer 107 along the second direction Y. Consequently, during the exposure process to form the patterned mask layer, due to the optical proximity effect, the pattern at the connection point between the first core layer 107 and the second core layer 108 is difficult to expose accurately due to insufficient exposure. Subsequent development processes cause some of the patterns in the first core layer 107 to break off from those in the second core layer 108, resulting in a lack of connection between the formed first core layer 107 and the second core layer 108 (e.g., ...). Figure 1 (As shown in region B), which in turn affects the performance of the subsequently formed word line structure.

[0039] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. By forming a plurality of core structures on a substrate, each core structure includes a first core layer and a second core layer interconnected. The first core layer is parallel to a first direction, and the angle between the first and second core layers is an obtuse angle. This increases the pattern density of the mask pattern forming the first core layer on both sides of the second direction. The pattern of the second core layer increases the exposure of the region adjacent to the mask pattern forming the first core layer, thereby increasing the exposure of the mask pattern forming the first core layer. This allows the mask pattern of the first core layer to be accurately formed, reducing the possibility of the first core layer and the second core layer being disconnected due to optical proximity effects, and thus improving the yield of the subsequent formation of the first word line layer and the second word line layer.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 3 to 8 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0042] Please refer to Figure 3 A substrate 200 is provided; a device layer is formed on the substrate 200, the device layer having a plurality of devices arranged along a first direction X ( Figure 4 The floating gate structure shown is arranged in parallel, and the floating gate structure is parallel to the second direction Y. Figure 4 (As shown).

[0043] The device layer includes: a first dielectric layer 204, a floating gate structure located within the first dielectric layer 204, and a word line oxide layer 205 located on the first dielectric layer 204 and the floating gate structure.

[0044] The floating gate structure includes a floating gate oxide layer 201 and a floating gate layer 202 located on the floating gate oxide layer 201; the material of the floating gate oxide layer 201 includes silicon oxide, and the material of the floating gate layer 202 includes polysilicon or metal, wherein the metal includes tungsten.

[0045] In this embodiment, the substrate 200 is made of silicon.

[0046] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0047] The first dielectric layer 204 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the first dielectric layer 204 is made of silicon oxide.

[0048] Please continue to refer to this. Figure 3 A word line material layer 206 is formed on the device layer.

[0049] The word line material layer 206 is used to subsequently form the first word line layer, the second word line layer, and the connecting layer.

[0050] The word line material layer 206 is made of polycrystalline silicon or a metal, including tungsten. The process for forming the word line material layer 206 includes physical vapor deposition or chemical vapor deposition.

[0051] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 Top view, Figure 5 for Figure 4 A cross-sectional view of the first core layer 207 along the section line BB1 ​​shows that several core structures are formed on the word line material layer 206. The core structures are arranged at equal intervals. Each core structure includes a first core layer 207 and a second core layer 208 that are connected to each other. The first core layer 207 is parallel to a first direction X, which is parallel to the surface of the substrate 200. The included angle α between the first core layer 207 and the second core layer 208 is an obtuse angle. The first core layers 207 are parallel to each other, and the second core layers 208 are parallel to each other.

[0052] The method for forming the core structure includes: forming a core material layer (not shown) on a word line material layer 206; forming a first mask layer (not shown) on the core material layer, wherein the first mask layer exposes a portion of the surface of the core material layer; etching the core material layer using the first mask layer as a mask until the surface of the word line material layer 206 is exposed, thereby forming the core structure.

[0053] The material of the first mask layer includes photoresist; the process for forming the first mask layer includes coating, exposure and development processes.

[0054] Because the pattern size of the core structure is small, the pattern of the first mask layer is easily affected by the optical proximity effect when the first mask layer pattern of the core structure is exposed.

[0055] The first core layer 207 is parallel to the first direction X, and the included angle α between the first core layer 207 and the second core layer 208 is an obtuse angle. This increases the pattern density of the mask pattern forming the first core layer 207 on both sides of the second direction Y. The second direction Y is parallel to the surface of the substrate 200 and perpendicular to the first direction X. The pattern of the second core layer 208 increases the exposure of the area adjacent to the mask pattern forming the first core layer 207, thereby increasing the exposure of the mask pattern forming the first core layer 207. This allows the mask pattern of the first core layer 207 to be accurately formed, reducing the possibility of the first core layer 207 and the second core layer 208 being disconnected due to the optical proximity effect, and thus improving the yield of the subsequent formation of the first word line layer and the second word line layer.

[0056] The core structure is made of materials including amorphous silicon, silicon oxide, or silicon nitride.

[0057] In this embodiment, the material of the core structure includes silicon oxide.

[0058] Next, a first word line layer is formed on the substrate. The pattern of the first word line layer is formed by self-aligned double patterning technology on the first core layer 207. A second word line layer is formed on the substrate. The second word line layer corresponds one-to-one with the first word line layer and is interconnected with it. The pattern of the second word line layer is formed by self-aligned double patterning technology on the second core layer 208. A plurality of connecting layers are formed on the substrate. The plurality of connecting layers are parallel to the second direction and arranged along the first direction. The connecting layers are connected to the second word line layer. For the formation process of the first word line layer, the second word line layer, and the connecting layers, please refer to [reference needed]. Figures 6 to 8 .

[0059] Please refer to Figure 6A first sidewall 209 is formed on the sidewall of the first core layer 207 and a second sidewall 210 is formed on the sidewall of the second core layer 208; after the first sidewall 209 and the second sidewall 210 are formed, the first core layer 207 and the second core layer 208 are removed.

[0060] The method for forming the first sidewall 209 and the second sidewall 210 includes: forming a sidewall material layer (not shown) on the sidewall surface and top surface of the first core layer 207, and the sidewall surface and top surface of the second core layer 208; etching back the sidewall material layer until the top surfaces of the first core layer 207 and the second core layer 208 are exposed; forming the first sidewall 209 on the sidewall of the first core layer 207; and forming the second sidewall 210 on the sidewall of the second core layer 208.

[0061] The first sidewall 209 and the second sidewall 210 are made of dielectric material, and the materials of the first sidewall 209 and the second sidewall 210 are different from the materials of the first core layer 207 and the second core layer 208. Therefore, when etching back the sidewall material layers, the etching back process can stop at the surfaces of the first core layer 207 and the second core layer 208.

[0062] The materials of the first sidewall 209 and the second sidewall 210 include silicon, silicon oxide, or silicon nitride.

[0063] In this embodiment, the materials of the first sidewall 209 and the second sidewall 210 include silicon nitride.

[0064] In this embodiment, the process of removing the first core layer 207 and the second core layer 208 includes a wet etching process.

[0065] Please refer to Figure 7 A plurality of second mask layers 211 are formed on the second sidewall 210, and the plurality of second mask layers 211 are parallel to the second direction Y and arranged along the first direction X.

[0066] The width of the second mask layer 211 in the first direction X is greater than the width of the second sidewall 210. The second mask layer 211 covers part of the second sidewall 210, and a larger connecting layer is subsequently formed. The connecting layer is parallel to the second direction Y, which facilitates the design and connection of the connecting lines in subsequent processes.

[0067] In this embodiment, the material of the second mask layer 211 includes photoresist; the process of forming the second mask layer 211 includes coating, exposure and development processes.

[0068] Please refer to Figure 8Using the first sidewall 209 as a mask, the character line material layer 206 is etched to form an initial first character line layer (not shown); using the second sidewall 210 as a mask, the character line material layer 206 is etched to form an initial second character line layer (not shown); using the second mask layer 211 as a mask, the character line material layer 206 is etched to form mutually discrete connecting layers 214; a first isolation layer 215 is formed within the initial first character line layer, the first isolation layer 215 penetrating the initial first character line layer along a first direction X, so that the initial first character line layer forms a discrete first character line layer 212; a second isolation layer 216 is formed within the initial second character line layer, the second isolation layer 216 penetrating the initial second character line layer along a second direction Y, so that the initial second character line layer forms a discrete second character line layer 213, one second character line layer 213 is connected to the first character line layer 212, and one connecting layer 214 is connected to one second character line layer 213.

[0069] The first character line layer 212, the second character line layer 213, and the connecting layer 214 are formed simultaneously.

[0070] The first isolation layer 215 is used for electrically isolated initial first word line layers, so that the initial first word line layers form a discrete first word line layer 212; the second isolation layer 216 is used for electrically isolated initial second word line layers, so that the initial second word line layers form mutually discrete second word line layers 213.

[0071] One of the connecting layers 214 is connected to a second word line layer 213, and the second word line layer 213 is connected to a first word line layer 212. Thus, the first word line layer 212 can be connected to the connecting layer 214 in the future. At the same time, the area of ​​the connecting layer 214 is large, which makes the process window for forming the subsequent connecting line larger.

[0072] The word line material layer 206 is made of polysilicon or metal, and the first word line layer 212 formed by the word line material layer 206 is made of polysilicon or metal, the metal of which includes tungsten; the second word line layer 213 formed by the word line material layer 206 is made of polysilicon or metal, the metal of which includes tungsten; the interconnect layer 214 formed by the word line material layer 206 is made of polysilicon or metal, the metal of which includes tungsten.

[0073] Accordingly, the embodiments of the invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 8 ,include:

[0074] Substrate 200;

[0075] A plurality of first word line layers 212 are located on the substrate 200, the plurality of first word line layers 212 are arranged in parallel to each other, the first word line layers 212 are parallel to a first direction X, and the first direction X is parallel to the surface of the substrate 200.

[0076] The second word line layer 213 is located on the substrate 200. The second word line layer 213 corresponds to and is connected to the first word line layer 212. The angle between the second word line layer 213 and the first word line layer 212 is an obtuse angle. Several second word line layers 213 are parallel to each other.

[0077] In this embodiment, it further includes: a first isolation layer 215 located between adjacent first word line layers 212; and a second isolation layer 216 located between adjacent second word line layers 213.

[0078] In this embodiment, it further includes: a device layer located on the substrate 200, the device layer having a plurality of parallel floating gate structures, the floating gate structures being parallel to the second direction Y; the first word line layer 212 and the second word line layer 213 being located on the device layer.

[0079] In this embodiment, the floating gate structure includes a floating gate oxide layer 201 and a floating gate layer 202 located on the floating gate oxide layer 201; the material of the floating gate oxide layer 201 includes silicon oxide, and the material of the floating gate layer 202 includes polysilicon or metal, wherein the metal includes tungsten.

[0080] In this embodiment, the device layer includes: a first dielectric layer 204, a floating gate structure located within the first dielectric layer 204, and a word line oxide layer 205 located on the first dielectric layer 204 and the floating gate structure.

[0081] In this embodiment, the material of the first isolation layer 215 includes a dielectric material, which includes silicon nitride; the material of the second isolation layer 216 includes a dielectric material, which includes silicon nitride.

[0082] In this embodiment, the material of the first word line layer 212 includes polycrystalline silicon or metal, and the metal includes tungsten; the material of the second word line layer 213 includes polycrystalline silicon or metal, and the metal includes tungsten.

[0083] In this embodiment, it further includes: a plurality of connection layers 214 located on the substrate, the plurality of connection layers 214 being parallel to the second direction Y and arranged along the first direction X, the second direction Y being parallel to the surface of the substrate 200 and perpendicular to the first direction X; the connection layers 214 being connected to the second word line layer 213.

[0084] In this embodiment, the width of the connection layer 214 in the first direction X is greater than the width of the second word line layer 213.

[0085] In the semiconductor structure, the second word line layer 213 corresponds one-to-one with and is interconnected with the first word line layer 212, and the angle between the second word line layer 213 and the first word line layer 212 is an obtuse angle. This results in a more uniform pattern distribution density in the mask patterns formed by the second word line layer 213 and the first word line layer 212. When forming the mask patterns using exposure technology, the exposure is more uniform and the exposure is better, allowing the mask patterns to be accurately formed. This reduces the possibility of the pattern forming the first word line layer 212 being disconnected from the pattern forming the second word line layer 213 due to the optical proximity effect, thus improving the yield of forming the second word line layer 213 and the first word line layer 212.

[0086] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A plurality of first word line layers are located on a substrate, the plurality of first word line layers are arranged in parallel to each other, the first word line layers are parallel to a first direction, and the first direction is parallel to the substrate surface; A second word line layer is located on the substrate. The second word line layer corresponds to and is connected to the first word line layer. The angle between the second word line layer and the first word line layer is an obtuse angle. Several second word line layers are parallel to each other. A first isolation layer is located between adjacent first word line layers. Two first word line layers are spaced apart between adjacent first isolation layers. The spacing between the two first word line layers adjacent to the first isolation layer is the same. The spacing between the two first word line layers located between two adjacent first isolation layers is the same.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The second isolation layer is located between adjacent second word line layers.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: A device layer located on a substrate, wherein the device layer has a plurality of parallel floating gate structures, the floating gate structures being parallel to a second direction; The first word line layer and the second word line layer are located on the device layer.

4. The semiconductor structure as described in claim 3, characterized in that, The floating gate structure includes a floating gate oxide layer and a floating gate layer located on the floating gate oxide layer; the material of the floating gate oxide layer includes silicon oxide, and the material of the floating gate layer includes polysilicon or metal, wherein the metal includes tungsten.

5. The semiconductor structure as described in claim 3, characterized in that, The device layer includes: a first dielectric layer, a floating gate structure located within the first dielectric layer, and a word line oxide layer located on the first dielectric layer and on the floating gate structure.

6. The semiconductor structure as described in claim 2, characterized in that, The first isolation layer is made of a dielectric material, which includes silicon nitride; the second isolation layer is made of a dielectric material, which includes silicon nitride.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the first word line layer includes polycrystalline silicon or metal, wherein the metal includes tungsten; the material of the second word line layer includes polycrystalline silicon or metal, wherein the metal includes tungsten.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: A plurality of interconnecting layers are located on a substrate, the plurality of interconnecting layers being parallel to a second direction and arranged along a first direction, the second direction being parallel to the substrate surface and perpendicular to the first direction; The connecting layer is connected to the second word line layer.

9. The semiconductor structure as described in claim 8, characterized in that, The width of the connecting layer in the first direction is greater than the width of the second word line layer.

10. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A plurality of core structures are formed on a substrate, and the plurality of core structures are arranged at equal intervals. Each core structure includes a first core layer and a second core layer that are connected to each other. The first core layer is parallel to a first direction, the first direction is parallel to the substrate surface, and the angle between the first core layer and the second core layer is an obtuse angle. The plurality of first core layers are parallel to each other, and the plurality of second core layers are parallel to each other. A first word line layer and a first isolation layer located between adjacent first word line layers are formed on a substrate. The pattern of the first word line layer is the pattern formed by the first core layer through self-aligned dual patterning technology. Two first word line layers are spaced between adjacent first isolation layers. The spacing between the two first word line layers adjacent to the first isolation layer is the same. The spacing between the two first word line layers located between the two adjacent first isolation layers is the same. A second word line layer is formed on the substrate. The first word line layer and the second word line layer correspond one-to-one and are connected to each other. The pattern of the second word line layer is the pattern formed by the second core layer through self-aligned dual patterning technology.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the core structure includes: forming a core material layer on a substrate; forming a first mask layer on the core material layer, wherein the first mask layer exposes a portion of the surface of the core material layer; and etching the core material layer using the first mask layer as a mask until the surface of the substrate is exposed, thereby forming the core structure.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the first mask layer includes photoresist; the process for forming the first mask layer includes coating, exposure and development processes.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first word line layer structure and the second word line layer are formed simultaneously.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, Also includes: A plurality of interconnect layers are formed on a substrate, the plurality of interconnect layers being parallel to a second direction and arranged along a first direction, the second direction being parallel to the substrate surface and perpendicular to the first direction; The connecting layer is connected to the second word line layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The width of the connecting layer in the first direction is greater than the width of the second word line layer.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for forming the first core layer, the second core layer, and the connecting layer includes: forming a first sidewall located on the sidewall of the first core layer and a second sidewall located on the sidewall of the second core layer; after forming the first sidewall and the second sidewall, removing the first core layer and the second core layer; after removing the first core layer and the second core layer, forming a plurality of second mask layers on the second sidewall, the plurality of second mask layers being parallel to a second direction and arranged along a first direction; etching the word line material layer using the first sidewall as a mask to form an initial first word line layer; and etching the word line material layer using the second sidewall as a mask to form an initial second... A word line layer; the word line material layer is etched using the second mask layer as a mask to form mutually discrete connecting layers; a first isolation layer is formed within the initial first word line layer, the first isolation layer penetrating the initial first word line layer along a first direction, so that the initial first word line layer forms a discrete first word line layer; a second isolation layer is formed within the initial second word line layer, the second isolation layer penetrating the initial second word line layer along a second direction, so that the initial second word line layer forms a discrete second word line layer, one second word line layer is connected to one first word line layer, and one connecting layer is connected to one second word line layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The core structure is made of amorphous silicon, silicon oxide, or silicon nitride; the process for removing the core structure includes wet etching.

18. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the first word line layer includes polycrystalline silicon or metal, wherein the metal includes tungsten; the material of the second word line layer includes polycrystalline silicon or metal, wherein the metal includes tungsten.

19. The method for forming a semiconductor structure as described in claim 10, characterized in that, Also includes: A word line material layer is formed on the substrate; The core structure is located on the word line material layer.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, Before forming a word line material layer on the substrate, the method further includes: forming a device layer on the substrate, wherein the device layer has a plurality of parallel floating gate structures, the floating gate structures being parallel to a second direction; the word line material layer is located on the device layer.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The floating gate structure includes a floating gate oxide layer and a floating gate layer located on the floating gate oxide layer; the material of the floating gate oxide layer includes silicon oxide, and the material of the floating gate layer includes polysilicon or metal, wherein the metal includes tungsten.

22. The method for forming a semiconductor structure as described in claim 20, characterized in that, The device layer includes: a first dielectric layer, a floating gate structure located within the first dielectric layer, and a word line oxide layer located on the first dielectric layer and on the floating gate structure.

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