Display substrate and display device

Abstract

The application provides a display substrate and a display device, relates to the technical field of display, and aims to solve the problem that the gate leakage of a driving transistor in a sub-pixel driving circuit increases when a negative power signal is reduced, thereby affecting the display quality of a display product. The sub-pixel in the display substrate comprises a first initialization signal line and a second initialization signal line, and the potentials of initialization signals transmitted by the first initialization signal line and the second initialization signal line are different. The sub-pixel driving circuit in the sub-pixel comprises a driving transistor, a first reset transistor and a second reset transistor. The first electrode of the driving transistor is coupled with a light-emitting element. The first electrode of the first reset transistor is coupled with the gate of the driving transistor, and the second electrode of the first reset transistor is coupled with the first initialization signal line. The first electrode of the second reset transistor is coupled with the light-emitting element, and the second electrode of the second reset transistor is coupled with the second initialization signal line. The display substrate provided by the application is used for display.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] Active matrix organic light-emitting diode (AMOLED) displays offer advantages such as self-illumination, wide color gamut, high contrast, and thinness. They are widely used in small and medium-to-large-sized display products such as mobile phones, wearable electronic devices, and automotive displays.

[0003] Because the brightness of medium and large-sized displays is significantly higher than that of small-sized displays, higher requirements are placed on their brightness. Increasing brightness requires a low-potential negative power supply signal. This, in turn, necessitates a low-potential initialization signal to ensure adequate black levels. However, setting a low-potential initialization signal increases leakage current at the gates of the driving transistors in the sub-pixel driving circuit, negatively impacting display quality. Summary of the Invention

[0004] The purpose of this invention is to provide a display substrate and display device to solve the problem that the gate leakage current of the driving transistor in the sub-pixel driving circuit increases when the negative power supply signal is reduced, thus affecting the display quality of the display product.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A first aspect of the present invention provides a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, the sub-pixels comprising:

[0007] A first initialization signal line and a second initialization signal line, wherein the potential of the first initialization signal transmitted on the first initialization signal line is different from the potential of the second initialization signal transmitted on the second initialization signal line; and,

[0008] A sub-pixel driving circuit and a light-emitting element are provided. The sub-pixel driving circuit includes a driving transistor, a first reset transistor, and a second reset transistor. The first terminal of the driving transistor is coupled to the light-emitting element. The first terminal of the first reset transistor is coupled to the gate of the driving transistor, and the second terminal of the first reset transistor is coupled to the first initialization signal line. The first terminal of the second reset transistor is coupled to the light-emitting element, and the second terminal of the second reset transistor is coupled to the second initialization signal line.

[0009] Optionally, at least a portion of the first initialization signal line extends along a first direction;

[0010] At least a portion of the second initialization signal line extends along the first direction;

[0011] The sub-pixel further includes: a first compensation signal line and / or a second compensation signal line; the first compensation signal line is coupled to the first initialization signal line, at least a portion of the first compensation signal line extends along a second direction, the second direction intersecting the first direction; the second compensation signal line is coupled to the second initialization signal line, at least a portion of the second compensation signal line extends along the second direction.

[0012] Optionally, the sub-pixel further includes:

[0013] A data cable, at least a portion of which extends along the second direction;

[0014] In the same sub-pixel, the orthographic projection of the gate of the driving transistor on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first compensation signal line on the substrate; and is located between the orthographic projection of the data line on the substrate and the orthographic projection of the second compensation signal line on the substrate;

[0015] Both the first compensation signal line and the second compensation signal line are made of the same layer and material as the data line.

[0016] Optionally, the sub-pixel further includes:

[0017] A data cable, at least a portion of which extends along the second direction;

[0018] In the same sub-pixel, the orthographic projection of the data line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the first compensation signal line on the substrate; and is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second compensation signal line on the substrate;

[0019] Both the first compensation signal line and the second compensation signal line are made of the same layer and material as the data line.

[0020] Optionally, the plurality of sub-pixels are arranged in an array, with the first initialization signal lines coupled to sub-pixels located in the same row along the first direction; and the first compensation signal lines coupled to sub-pixels located in the same column along the second direction; and / or,

[0021] In sub-pixels located in the same row along the first direction, the second initialization signal line is coupled; in sub-pixels located in the same column along the second direction, the second compensation signal line is coupled.

[0022] Optionally, the display substrate includes a display area and a peripheral area surrounding the display area; the display substrate further includes:

[0023] A first initialization signal bus is disposed in the peripheral area, at least a portion of the first initialization signal bus extends along the second direction, and a first initialization signal line is coupled to the first initialization signal bus; and / or,

[0024] A second initialization signal bus is disposed in the peripheral area, at least a portion of the second initialization signal bus extends along the second direction, and the second initialization signal line is coupled to the second initialization signal bus.

[0025] Optionally, the first initialization signal bus surrounds the display area; the first compensation signal line is coupled to the first initialization signal bus;

[0026] And / or, the second initialization signal bus surrounds the display area; the second compensation signal line is coupled to the second initialization signal bus.

[0027] Optionally, the sub-pixel further includes: a first reset signal line, at least a portion of which extends along the first direction;

[0028] The first reset transistor includes a first gate pattern and a first active pattern; the first gate pattern is coupled to the first reset signal line, the first gate pattern has a U-shaped structure, and the opening of the U-shaped structure faces the data line; the orthographic projection of the first active pattern on the substrate at least partially overlaps with the orthographic projection of the portion of the first gate pattern located on both sides of the opening on the substrate.

[0029] Optionally, the first active pattern includes the first and second terminals of the first reset transistor;

[0030] The sub-pixel further includes: a first conductive connection portion, the first conductive connection portion including a first part and a second part; the first part is coupled to the first initialization signal line and the first compensation signal line respectively, and the second part is coupled to the second pole of the first reset transistor.

[0031] Optionally, the sub-pixel further includes: a second reset signal line, at least a portion of which extends along the first direction;

[0032] The second reset transistor includes a second gate pattern and a second active pattern; the second gate pattern is coupled to the second reset signal line, and at least a portion of the second gate pattern extends along the first direction; the second active pattern, the second gate pattern and the second reset signal line are stacked sequentially along a direction away from the substrate.

[0033] Optionally, the second active pattern includes the first and second terminals of the second reset transistor;

[0034] The sub-pixel further includes: a second conductive connection portion, the second conductive connection portion including a third portion and a fourth portion, the third portion being coupled to the second initialization signal line and the second compensation signal line respectively, and the fourth portion being coupled to the second pole of the second reset transistor.

[0035] Optionally, the sub-pixel further includes:

[0036] A grid line, at least a portion of which extends along the first direction;

[0037] The sub-pixel driving circuit also includes:

[0038] A compensation transistor, the compensation transistor including a third gate pattern and a third active pattern; the third gate pattern is coupled to the gate line, the third gate pattern including a fifth portion and a sixth portion, the sixth portion extending along a first direction, the fifth portion extending along a second direction, the orthographic projection of the third active pattern on the substrate at least partially overlapping the orthographic projections of the sixth portion on the substrate and the fifth portion on the substrate, respectively.

[0039] A data writing transistor includes a fourth gate pattern and a fourth active pattern; the fourth gate pattern is coupled to the gate line and extends along the first direction; the fourth active pattern is coupled to the data line and the second terminal of the driving transistor, respectively.

[0040] Optionally, the third active pattern includes a first sub-pattern, a second sub-pattern, and a third sub-pattern; the orthographic projection of the first sub-pattern on the substrate at least partially overlaps with the orthographic projection of the sixth part on the substrate; the orthographic projection of the second sub-pattern on the substrate at least partially overlaps with the orthographic projection of the fifth part on the substrate; the third sub-pattern is located between the first sub-pattern and the second sub-pattern, and is coupled to the first sub-pattern and the second sub-pattern respectively.

[0041] The sub-pixel further includes: a power line, the power line including a portion extending along the first direction;

[0042] The sub-pixel driving circuit further includes a storage capacitor, which includes a first electrode plate and a second electrode plate disposed opposite to each other. The first electrode plate is located between the second electrode plate and the substrate. The first electrode plate is coupled to the gate of the driving transistor, and the second electrode plate is coupled to the power line. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the third sub-pattern on the substrate.

[0043] Optionally, the sub-pixel driving circuit further includes:

[0044] A compensation transistor, the compensation transistor comprising a third active pattern;

[0045] A storage capacitor includes a first electrode and a second electrode disposed opposite to each other. The second electrode includes an electrode body and an electrode shield. The orthographic projection of the electrode body on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate. The orthographic projection of the electrode shield on the substrate at least partially overlaps with the orthographic projection of the third active pattern on the substrate.

[0046] The orthographic projection of the electrode shield on the substrate does not overlap with the orthographic projection of the first compensation signal line on the substrate; and / or, the orthographic projection of the electrode shield on the substrate does not overlap with the orthographic projection of the second compensation signal line on the substrate.

[0047] Optionally, within the same sub-pixel, the orthographic projection of the first compensation signal line onto the substrate is located between the orthographic projection of the electrode shield onto the substrate and the orthographic projection of the second compensation signal line onto the substrate.

[0048] Optionally, the sub-pixel further includes: a power line; the power line includes a first power pattern, a second power pattern, and a third power pattern; the first power pattern and the second power pattern both extend along the first direction, and the third power pattern extends along the second direction; the second power pattern is coupled to the first power pattern and the third power pattern respectively; the second power pattern is coupled to the second electrode plate.

[0049] Optionally, the sub-pixel further includes: a light emission control signal line, the light emission control signal line including at least a portion extending along the first direction;

[0050] The third power supply pattern includes a first power supply sub-pattern and a second power supply sub-pattern. The width of the first power supply sub-pattern along the first direction is smaller than the width of the second power supply sub-pattern. The orthographic projection of the first power supply sub-pattern on the substrate at least partially overlaps with the orthographic projection of the light emission control signal line on the substrate.

[0051] Optionally, the orthographic projection of the second power pattern on the substrate is located inside the orthographic projection of the electrode body on the substrate.

[0052] Optionally, the sub-pixel further includes:

[0053] A light-emitting control signal line, at least a portion of which extends along the first direction, wherein the orthographic projection of the light-emitting control signal line on the substrate at least partially overlaps with the orthographic projection of the third power supply pattern on the substrate;

[0054] The sub-pixel driving circuit also includes:

[0055] A power control transistor, wherein the gate of the power control transistor is coupled to the light emission control signal line, the first terminal of the power control transistor is coupled to the second terminal of the driving transistor, and the second terminal of the power control transistor is coupled to the third power pattern;

[0056] A light-emitting control transistor, wherein the gate of the light-emitting control transistor is coupled to the light-emitting control signal line, the first terminal of the light-emitting control transistor is coupled to the light-emitting element, and the second terminal of the light-emitting control transistor is coupled to the first terminal of the driving transistor.

[0057] Optionally, the display substrate further includes a first source / drain metal layer;

[0058] The first reset signal line, the second reset signal line, the gate line, the power line, the first conductive connection portion, and the second conductive connection portion are all disposed in the same layer and with the same material as the first source / drain metal layer.

[0059] Based on the above-described display substrate technical solution, a second aspect of the present invention provides a display device including the above-described display substrate.

[0060] In the technical solution provided by this invention, the gate of the driving transistor is reset using a first initialization signal provided by the first initialization signal line, and the light-emitting element is reset using a second initialization signal provided by the second initialization signal line. This ensures that the first initialization signal for resetting the gate of the driving transistor and the second initialization signal for resetting the light-emitting element are independent of each other, enabling independent control and allowing for different voltage values. This achieves the goal of maintaining the black state brightness of the light-emitting element in low grayscale display while avoiding increased gate leakage current of the driving transistor, thus ensuring the white state brightness of the light-emitting element in high grayscale display. Therefore, when the display substrate provided by this invention is applied to a display device, it can improve defects such as image retention and first frame response time, and also improve mura defects that occur in low grayscale display, ensuring the brightness uniformity of the image in both high and low grayscale displays. Attached Figure Description

[0061] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0062] Figure 1 This is a schematic diagram of the sub-pixel driving circuit provided in an embodiment of the present invention;

[0063] Figure 2 This is a schematic diagram of the first layout of sub-pixels provided in an embodiment of the present invention;

[0064] Figure 3 This is a schematic diagram of the second layout of sub-pixels provided in an embodiment of the present invention;

[0065] Figure 4 This is a schematic diagram of the third layout of sub-pixels provided in an embodiment of the present invention;

[0066] Figure 5 This is a schematic diagram of the fourth layout of sub-pixels provided in an embodiment of the present invention;

[0067] Figure 6 for Figure 5 A schematic diagram showing the layout of the active layer and the first gate metal layer;

[0068] Figure 7 for Figure 5 A schematic diagram of the layout of the active layer;

[0069] Figure 8 for Figure 5 A schematic diagram of the layout of the first gate metal layer;

[0070] Figure 9 for Figure 5 Schematic diagram of the layout of the second gate metal layer;

[0071] Figure 10 for Figure 5 A schematic diagram of the layout of the first source / drain metal layer in the middle;

[0072] Figure 11 for Figure 5 A schematic diagram of the layout of the second source / drain metal layer in the middle;

[0073] Figure 12 This is a first schematic diagram of a display substrate provided in an embodiment of the present invention;

[0074] Figure 13 This is a second schematic diagram of a display substrate provided in an embodiment of the present invention;

[0075] Figure 14 This is a schematic diagram of the fifth layout of sub-pixels provided in an embodiment of the present invention;

[0076] Figure 15 for Figure 14 A schematic diagram of the layout of the second source / drain metal layer. Detailed Implementation

[0077] To further illustrate the display substrate and display device provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0078] Please see Figure 1 , Figure 2 , Figure 5 and Figure 6 This invention provides a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, wherein the sub-pixels include:

[0079] A first initialization signal line 11 and a second initialization signal line 12, wherein the potential of the first initialization signal transmitted on the first initialization signal line 11 is different from the potential of the second initialization signal transmitted on the second initialization signal line 12; and,

[0080] The sub-pixel driving circuit includes a driving transistor T3, a first reset transistor T1, and a second reset transistor T7. The first terminal T3-s1 of the driving transistor T3 is coupled to the light-emitting element EL. The first terminal T1-s1 of the first reset transistor T1 is coupled to the gate T3-g of the driving transistor T3, and the second terminal T1-s2 of the first reset transistor T1 is coupled to the first initialization signal line 11. The first terminal T7-s1 of the second reset transistor T7 is coupled to the light-emitting element EL, and the second terminal T7-s2 of the second reset transistor T7 is coupled to the second initialization signal line 12.

[0081] For example, the first initialization signal line 11 and the second initialization signal line 12 are independent of each other. The first initialization signal line 11 is used to provide a first initialization signal, and the second initialization signal line 12 is used to provide a second initialization signal. The first initialization signal and the second initialization signal can be adjusted independently.

[0082] For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element EL. The sub-pixel driving circuit includes a 7T1C (i.e., 7 transistors and one capacitor) circuit. The light-emitting element EL includes an anode layer, a light-emitting functional layer, and a cathode layer sequentially stacked along a direction away from the substrate. The anode layer is coupled to the sub-pixel driving circuit and is capable of receiving driving signals provided by the sub-pixel driving circuit.

[0083] For example, the sub-pixel driving circuit includes a driving transistor T3, the first electrode T3-s1 of which is coupled to the anode layer of the light-emitting element EL.

[0084] For example, the sub-pixel driving circuit further includes a first reset transistor T1. The gate of the first reset transistor T1 (i.e., the first gate pattern T1-g) is coupled to a first reset signal line 33. The first terminal T1-s1 of the first reset transistor T1 is coupled to the gate T3-g of the driving transistor T3. The second terminal T1-s2 of the first reset transistor T1 is coupled to the first initialization signal line 11. Under the control of the first reset signal Res1 provided by the first reset signal line 33, the first reset transistor T1 is turned on or off to determine whether to reset the gate T3-g of the driving transistor T3.

[0085] For example, the sub-pixel driving circuit further includes a second reset transistor T7. The gate of the second reset transistor T7 is coupled to a second reset signal line 35, the first terminal T7-s1 of the second reset transistor T7 is coupled to the anode layer of the light-emitting element EL, and the second terminal T7-s2 of the second reset transistor T7 is coupled to the second initialization signal line 12. Under the control of the second reset signal provided by the second reset signal line 35, the second reset transistor T7 is turned on or off to determine whether to reset the anode layer of the light-emitting element EL.

[0086] It should be noted that in order to improve the luminous brightness of a sub-pixel, the voltage difference between the positive and negative power supply signals received by the sub-pixel driving circuit needs to be increased. When reducing the voltage of the negative power supply signal, the voltage of the initialization signal resetting the luminous element EL also needs to be reduced simultaneously to ensure the black state brightness of the luminous element EL in low grayscale display. If the first reset transistor T1 and the second reset transistor T7 receive the same initialization signal, the voltage of the initialization signal resetting the gate T3-g of the driving transistor T3 will be reduced simultaneously, leading to increased leakage current at the gate T3-g of the driving transistor T3, affecting the white state brightness of the display product in high grayscale display.

[0087] As can be seen from the specific structure of the display substrate, in the display substrate provided by the embodiments of the present invention, the first initialization signal Vinit1 provided by the first initialization signal line 11 is used to reset the gate T3-g of the driving transistor T3, and the second initialization signal Vinit2 provided by the second initialization signal line 12 is used to reset the light-emitting element EL. This makes the first initialization signal Vinit1 for resetting the gate T3-g of the driving transistor T3 and the second initialization signal Vinit2 for resetting the light-emitting element EL independent of each other, enabling independent control and allowing for different voltage values. This ensures that while maintaining the black state brightness of the light-emitting element EL in low grayscale display, it avoids increasing the leakage current of the gate T3-g of the driving transistor T3, thus ensuring the white state brightness of the light-emitting element EL in high grayscale display. Therefore, when the display substrate provided by the embodiments of the present invention is applied to a display device, it can improve defects such as image retention and first frame response time, and also improve mura defects that occur in low grayscale display, ensuring the brightness uniformity of the display device in both high and low grayscale displays.

[0088] like Figure 1 , Figure 3 , Figure 4 , Figure 5 and Figure 11 As shown, in some embodiments, at least a portion of the first initialization signal line 11 extends along a first direction;

[0089] At least a portion of the second initialization signal line 12 extends along the first direction;

[0090] The sub-pixel further includes: a first compensation signal line 21 and / or a second compensation signal line 22; the first compensation signal line 21 is coupled to the first initialization signal line 11, and at least a portion of the first compensation signal line 21 extends along a second direction, which intersects with the first direction; the second compensation signal line 22 is coupled to the second initialization signal line 12, and at least a portion of the second compensation signal line 22 extends along the second direction.

[0091] For example, the first direction includes the lateral direction, and the second direction includes the longitudinal direction.

[0092] For example, the first initialization signal line 11 and the second initialization signal line 12 are arranged in the same layer and with the same material, the first compensation signal line 21 and the second compensation signal line 22 are arranged in the same layer and with the same material, and the first initialization signal line 11 and the first compensation signal line 21 are arranged in different layers.

[0093] For example, the orthographic projection of the first compensation signal line 21 on the substrate and the orthographic projection of the first initialization signal line 11 on the substrate have a first overlapping area. The first compensation signal line 21 and the first initialization signal line 11 are coupled through a first via, and the orthographic projection of the first via on the substrate is located in the first overlapping area.

[0094] For example, the orthographic projection of the second compensation signal line 22 on the substrate and the orthographic projection of the second initialization signal line 12 on the substrate have a second overlapping area. The second compensation signal line 22 and the second initialization signal line 12 are coupled through a second via. The orthographic projection of the second via on the substrate is located in the second overlapping area.

[0095] It should be noted that during the reset phase, the first initialization signal is recorded in the sub-pixels. This means that the first initialization signal charges all the storage capacitors Cst in a row of sub-pixels. The charging load is equal to the capacitance value of Cst multiplied by the number of sub-pixels in the row. For medium to large-sized displays, such as laptops and automotive displays, when there are many horizontally arranged sub-pixels in a row, the instantaneous loading of the first initialization signal recording can reach over 100pF. Furthermore, if the time for controlling the recording of the first initialization signal is too short, the initialization signal of a row of sub-pixels will not be sufficiently charged, affecting the display effect.

[0096] The above configuration, which couples the first compensation signal line 21 with the first initialization signal line 11, effectively reduces the resistance of the first initialization signal line 11 and reduces the voltage drop generated when the first initialization signal is transmitted on the first initialization signal line 11.

[0097] The above configuration, which couples the second compensation signal line 22 with the second initialization signal line 12, effectively reduces the resistance of the second initialization signal line 12 and reduces the voltage drop generated when the second initialization signal is transmitted on the second initialization signal line 12.

[0098] The above-described configuration, where the first compensation signal line 21 is coupled to the first initialization signal line 11, and / or the second compensation signal line 22 is coupled to the second initialization signal line 12, improves issues such as excessive loading during the transmission of the first and / or second initialization signals, and insufficient charging of the initialization signal for sub-pixels located in the middle of a row of sub-pixels. This effectively improves the uniformity of the first and / or second initialization signals. It also reduces color cast at low grayscale brightness, improving low grayscale image quality to a certain extent. Finally, it effectively improves the product yield of the display substrate.

[0099] like Figure 1 , Figure 3 , Figure 4 , Figure 5 and Figure 11 As shown, in some embodiments, setting the sub-pixel further includes:

[0100] Data line 23, at least a portion of which extends along the second direction;

[0101] In the same sub-pixel, the orthographic projection of the gate T3-g of the driving transistor T3 on the substrate is located between the orthographic projection of the data line 23 on the substrate and the orthographic projection of the first compensation signal line 21 on the substrate; and is located between the orthographic projection of the data line 23 on the substrate and the orthographic projection of the second compensation signal line 22 on the substrate;

[0102] The first compensation signal line 21 and the second compensation signal line 22 are both made of the same layer and material as the data line 23.

[0103] For example, in the same sub-pixel, the orthographic projection of the first compensation signal line 21 on the substrate and the orthographic projection of the second compensation signal line 22 on the substrate are both close to the first side of the orthographic projection of the gate T3-g of the driving transistor T3 on the substrate.

[0104] For example, the first compensation signal line 21 and the second compensation signal line 22 are arranged along the first direction.

[0105] For example, in the same sub-pixel, the orthographic projection of the first compensation signal line 21 on the substrate is located between the orthographic projection of the second compensation signal line 22 on the substrate and the orthographic projection of the gate T3-g of the driving transistor T3 on the substrate.

[0106] For example, in the same sub-pixel, the orthographic projection of the second compensation signal line 22 on the substrate is located between the orthographic projection of the first compensation signal line 21 on the substrate and the orthographic projection of the gate T3-g of the driving transistor T3 on the substrate.

[0107] The above arrangement ensures that, within the same sub-pixel, the data line 23 and the first compensation signal line 21 are located on opposite sides of the sub-pixel, and the data line 23 and the second compensation signal line 22 are also located on opposite sides of the sub-pixel. This reduces the impact of the signals transmitted by the first compensation signal line 21 and the second compensation signal line 22 on the signal transmitted by the data line 23, thus improving the stability of the display substrate.

[0108] In some embodiments, within the same sub-pixel, the orthogonal projection of the first compensation signal line 21 onto the substrate is close to a first side of the orthogonal projection of the gate T3-g of the driving transistor T3 onto the substrate, and the orthogonal projection of the second compensation signal line 22 onto the substrate is close to a second side of the orthogonal projection of the gate T3-g of the driving transistor T3 onto the substrate. The first side and the second side are opposite each other along the first direction.

[0109] In some embodiments, setting the sub-pixel further includes:

[0110] A data cable, at least a portion of which extends along the second direction;

[0111] In the same sub-pixel, the orthographic projection of the data line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the first compensation signal line on the substrate; and is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second compensation signal line on the substrate;

[0112] Both the first compensation signal line and the second compensation signal line are made of the same layer and material as the data line.

[0113] The above arrangement ensures that the data lines of one sub-pixel are far apart from the first compensation signal line and the second compensation signal line of another sub-pixel located in the same row. This reduces the impact of the signals transmitted by the first compensation signal line 21 and the second compensation signal line 22 on the signals transmitted by the data lines 23 in the adjacent sub-pixels, which helps to improve the stability of the display substrate.

[0114] like Figure 1 , Figure 3 , Figure 4 , Figure 5 and Figure 11 As shown, in some embodiments, the sub-pixel further includes:

[0115] Data line 23, at least a portion of which extends along the second direction, wherein the orthographic projection of the data line 23 on the substrate is close to the second side of the orthographic projection of the gate T3-g of the driving transistor T3 on the substrate, and the first side and the second side are opposite to each other along the first direction;

[0116] The first compensation signal line 21 and the second compensation signal line 22 are both made of the same layer and material as the data line 23.

[0117] For example, the multiple sub-pixels in the display substrate are arranged in an array, and the multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. Each row of sub-pixels includes multiple sub-pixels arranged along the first direction, and each column of sub-pixels includes multiple sub-pixels arranged along the second direction.

[0118] For example, in sub-pixels located in the same column, data lines 23 are sequentially coupled to form a single structure. The data lines 23 are used to write data signals.

[0119] For example, the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, an anode layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer, which are sequentially stacked in a direction away from the substrate.

[0120] For example, the second source / drain metal layer is used to form the first compensation signal line 21, the second compensation signal line 22, and the data line 23.

[0121] The above layout not only helps to reduce the difficulty of laying out the sub-pixels, but also helps to simplify the manufacturing process of the display substrate and reduce manufacturing costs.

[0122] In some embodiments, the plurality of sub-pixels are arranged in an array, with the first initialization signal line 11 coupled to sub-pixels in the same row along the first direction, and the first compensation signal line 21 coupled to sub-pixels in the same column along the second direction; and / or, the second initialization signal line 12 coupled to sub-pixels in the same row along the first direction, and the second compensation signal line 22 coupled to sub-pixels in the same column along the second direction.

[0123] For example, in sub-pixels located in the same row along the first direction, the first initialization signal line 11 is sequentially coupled to form an integral structure.

[0124] For example, in sub-pixels located in the same column along the second direction, the first compensation signal line 21 is sequentially coupled to form an integral structure.

[0125] For example, in sub-pixels located in the same row along the first direction, the second initialization signal line 12 is sequentially coupled to form an integral structure.

[0126] For example, in sub-pixels located in the same column along the second direction, the second compensation signal lines 22 are sequentially coupled to form an integral structure.

[0127] The above configuration allows the first initialization signal line 11 and the first compensation signal line 21 in the display substrate to form a grid structure, which effectively reduces the resistance of the first initialization signal line 11, reduces the voltage drop during the transmission of the first initialization signal, improves the display uniformity of the display substrate, and effectively improves the display yield of the display substrate.

[0128] The above configuration causes the second initialization signal line 12 and the second compensation signal line 22 in the display substrate to form a grid structure, which effectively reduces the resistance of the second initialization signal line 12, reduces the voltage drop during the transmission of the second initialization signal, improves the display uniformity of the display substrate, and effectively improves the display yield of the display substrate.

[0129] like Figure 1 , Figure 3 , Figure 4 , Figure 5 , Figure 11 and Figure 12 As shown, in some embodiments, the display substrate includes a display area 40 and a peripheral area 41 surrounding the display area 40; the display substrate further includes:

[0130] A first initialization signal bus 31 is disposed in the peripheral region 41, at least a portion of the first initialization signal bus 31 extends along the second direction, and the first initialization signal line 11 is coupled to the first initialization signal bus 31; and / or,

[0131] A second initialization signal bus 32 is disposed in the peripheral area, at least a portion of the second initialization signal bus 32 extends along the second direction, and the second initialization signal line 12 is coupled to the second initialization signal bus 32.

[0132] For example, the first initialization signal bus 31 is close to the first side and the second side of the display area 40, and the first side and the second side are opposite each other along the first direction.

[0133] For example, the first initialization signal bus 31 includes a portion near a first side of the display area 40 and a portion near a second side of the display area 40.

[0134] For example, in sub-pixels located in the same row along the first direction, the first initialization signal line 11 is sequentially coupled and coupled to the first initialization signal bus 31 on the first and second sides of the display area 40.

[0135] For example, the first initialization signal bus 31 is coupled to the driver chip in the display substrate.

[0136] The above configuration effectively reduces the resistance of the first initialization signal line 11, reduces the voltage drop during the transmission of the first initialization signal, improves the display uniformity of the display substrate, and effectively improves the display yield of the display substrate.

[0137] like Figure 13 As shown, in some embodiments, the first initialization signal bus 31 surrounds the display area 40; the first compensation signal line 21 is coupled to the first initialization signal bus 31; and / or, the second initialization signal bus 32 surrounds the display area 40; the second compensation signal line 22 is coupled to the second initialization signal bus 32.

[0138] It needs to be explained that, Figure 12 and Figure 13 The display area 40 includes multiple sub-pixels arranged in an array. Figure 12 and Figure 13 The diagram only illustrates the sub-pixel driving circuitry included in one sub-pixel.

[0139] For example, the first initialization signal bus 31 also includes a portion near a third side of the display area 40 and a portion near a fourth side of the display area 40, the third side and the fourth side being opposite each other along the second direction.

[0140] For example, in the sub-pixels located in the same column along the second direction, the first compensation signal line 21 is sequentially coupled and coupled to the first initialization signal bus 31 on the third and fourth sides of the display area 40.

[0141] The above configuration effectively reduces the resistance of the first initialization signal line 11, reduces the voltage drop during the transmission of the first initialization signal, improves the display uniformity of the display substrate, and effectively improves the display yield of the display substrate.

[0142] In some embodiments, the plurality of sub-pixels are arranged in an array, and the second initialization signal line 12 is coupled to the sub-pixels located in the same row along the first direction; the second compensation signal line 22 is coupled to the sub-pixels located in the same column along the second direction.

[0143] For example, in sub-pixels located in the same row along the first direction, the second initialization signal line 12 is sequentially coupled to form an integral structure.

[0144] For example, in sub-pixels located in the same column along the second direction, the second compensation signal lines 22 are sequentially coupled to form an integral structure.

[0145] The above configuration causes the second initialization signal line 12 and the second compensation signal line 22 in the display substrate to form a grid structure, which effectively reduces the resistance of the second initialization signal line 12, reduces the voltage drop during the transmission of the second initialization signal, improves the display uniformity of the display substrate, and effectively improves the display yield of the display substrate.

[0146] like Figure 1 , Figure 3 , Figure 4 , Figure 5 , Figure 11 and Figure 12 As shown, in some embodiments, the display substrate includes a display area 40 and a peripheral area 41 surrounding the display area 40; the display substrate further includes:

[0147] A second initialization signal bus 32 is disposed in the peripheral area 41. At least a portion of the second initialization signal bus 32 extends along the second direction. The second initialization signal bus 32 is close to a first side and a second side of the display area 40. The first side and the second side are opposite to each other along the first direction. The second initialization signal line 12 is coupled to the second initialization signal bus 32.

[0148] For example, the second initialization signal bus 32 includes a portion near a first side of the display area 40 and a portion near a second side of the display area 40.

[0149] For example, in sub-pixels located in the same row along the first direction, the second initialization signal line 12 is sequentially coupled and coupled to the second initialization signal bus 32 on the first and second sides of the display area 40.

[0150] For example, the second initialization signal bus 32 is coupled to the driver chip in the display substrate.

[0151] The above configuration effectively reduces the resistance of the second initialization signal line 12, reduces the voltage drop during the transmission of the second initialization signal, improves the display uniformity of the display substrate, and effectively improves the display yield of the display substrate.

[0152] like Figure 13 As shown, in some embodiments, the second initialization signal bus 32 surrounds the display area 40; the second compensation signal line 22 is coupled to the second initialization signal bus 32.

[0153] For example, the second initialization signal bus 32 also includes a portion near a third side of the display area 40 and a portion near a fourth side of the display area 40, the third side and the fourth side being opposite each other along the second direction.

[0154] For example, in the sub-pixels located in the same column along the second direction, the second compensation signal line 22 is sequentially coupled and coupled to the second initialization signal bus 32 on the third and fourth sides of the display area 40.

[0155] For example, the second initialization signal bus 32 and the first initialization signal bus 31 are nested. For example, the second initialization signal bus 32 surrounds the first initialization signal bus 31; or, the first initialization signal bus 31 surrounds the second initialization signal bus 32.

[0156] The above configuration effectively reduces the resistance of the second initialization signal line 12, reduces the voltage drop during the transmission of the second initialization signal, improves the display uniformity of the display substrate, and effectively improves the display yield of the display substrate.

[0157] like Figures 1 to 6 As shown, in some embodiments, the sub-pixel further includes: a first reset signal line 33, at least a portion of which extends along the first direction;

[0158] The first reset transistor T1 includes a first gate pattern T1-g and a first active pattern; the first gate pattern T1-g is coupled to the first reset signal line 33, the first gate pattern T1-g has a U-shaped structure, and the opening of the U-shaped structure faces the data line 23; the orthographic projection of the first active pattern on the substrate at least partially overlaps with the orthographic projection of the portion of the first gate pattern T1-g located on both sides of the opening on the substrate.

[0159] For example, the first reset signal line 33 is used to transmit a first reset signal Res1. The first reset signal line 33 and the first gate pattern T1-g are disposed on different layers. The orthographic projection of the first reset signal line 33 on the substrate and the orthographic projection of the first gate pattern T1-g on the substrate have a third overlapping region. The first reset signal line 33 and the first gate pattern T1-g are coupled through a third via, and the orthographic projection of the third via on the substrate is located in the third overlapping region.

[0160] It should be noted that the small squares with cross lines in the attached diagram represent vias.

[0161] For example, at least a portion of the first active pattern extends along the second direction. The orthographic projection of the first active pattern onto the substrate at least partially overlaps with the orthographic projection of the portions of the first gate pattern T1-g located on both sides of the opening onto the substrate, such that the first reset transistor T1 is formed as a dual-gate structure.

[0162] For example, the orthographic projection of the first gate pattern T1-g on the substrate does not overlap with the orthographic projection of the first initialization signal line 11 on the substrate. The orthographic projection of the first active pattern on the substrate partially overlaps with the orthographic projection of the first initialization signal line 11 on the substrate.

[0163] The above layout method helps to reduce the layout difficulty of the display substrate, reduce the layout space occupied by each sub-pixel, and improve the resolution of the display substrate.

[0164] like Figure 5 and Figure 6 As shown, in some embodiments, the first active pattern includes the first electrode T1-s1 and the second electrode T1-s2 of the first reset transistor T1.

[0165] like Figure 5 and Figure 10 As shown, the sub-pixel further includes: a first conductive connection portion 34, the first conductive connection portion 34 including a first part 341 and a second part 342, the first part 341 being coupled to the first initialization signal line 11 and the first compensation signal line 21 respectively, and the second part 342 being coupled to the second pole T1-s2 of the first reset transistor T1.

[0166] For example, in each transistor in the sub-pixel, one of the first and second electrodes can serve as the source and the other as the drain.

[0167] For example, the first portion 341 extends along the first direction, and the second portion 342 extends along the second direction.

[0168] For example, the first portion 341 and the second portion 342 are formed as an integral structure.

[0169] For example, the orthographic projection of the first portion 341 on the substrate overlaps with the orthographic projection of the first initialization signal line 11 on the substrate, and the orthographic projection of the first portion 341 on the substrate overlaps with the orthographic projection of the first compensation signal line 21 on the substrate. The first portion 341 is coupled to the first initialization signal line 11 and the first compensation signal line 21 respectively via vias.

[0170] For example, the orthographic projection of the second portion 342 onto the substrate at least partially overlaps with the orthographic projection of the second electrode T1-s2 of the first reset transistor T1 onto the substrate. The second portion 342 is coupled to the second electrode T1-s2 of the first reset transistor T1 via a via.

[0171] The above-mentioned configuration, in which the first conductive connection portion 34 is coupled to the first initialization signal line 11, the first compensation signal line 21, and the second pole T1-s2 of the first reset transistor T1, not only ensures electrical connection performance but also effectively reduces the layout difficulty of the display substrate, which is beneficial to improving the resolution of the display substrate.

[0172] like Figure 5 and Figure 6 As shown, in some embodiments, the sub-pixel further includes: a second reset signal line 35, at least a portion of which extends along the first direction;

[0173] The second reset transistor T7 includes a second gate pattern T7-g and a second active pattern; the second gate pattern T7-g is coupled to the second reset signal line 35, and at least a portion of the second gate pattern T7-g extends along the first direction; the second active pattern, the second gate pattern T7-g and the second reset signal line 35 are stacked sequentially along a direction away from the substrate.

[0174] For example, the second reset signal line 35 is used to transmit the second reset signal Res2. The second reset signal line 35 and the second gate pattern T7-g are disposed on different layers. The orthographic projection of the second reset signal line 35 on the substrate and the orthographic projection of the second gate pattern T7-g on the substrate have a fourth overlapping region. The second reset signal line 35 and the second gate pattern T7-g are coupled through a fourth via, the orthographic projection of which is located in the fourth overlapping region.

[0175] For example, the orthographic projection of the second gate pattern T7-g on the substrate is located inside the orthographic projection of the second reset signal line 35 on the substrate.

[0176] For example, the orthographic projection of the second gate pattern T7-g on the substrate does not overlap with the orthographic projection of the second initialization signal line 12 on the substrate.

[0177] For example, at least a portion of the second active pattern extends along the second direction. The second active pattern includes a first electrode T7-s1 and a second electrode T7-s2 of the second reset transistor T7.

[0178] like Figure 5 , Figure 6 , Figure 7 , Figure 9 and Figure 10 As shown, exemplarily, the orthographic projection of the second active pattern on the substrate does not overlap with the orthographic projection of the second initialization signal line 12 on the substrate. The orthographic projection of the second active pattern on the substrate at least partially overlaps with the orthographic projection of the second reset signal line 35 on the substrate.

[0179] The above layout method helps to reduce the layout difficulty of the display substrate, reduce the layout space occupied by each sub-pixel, and improve the resolution of the display substrate.

[0180] like Figure 6 and Figure 7 As shown, in some embodiments, the second active pattern includes the first electrode T7-s1 and the second electrode T7-s2 of the second reset transistor T7;

[0181] like Figure 5 and Figure 10 As shown, the sub-pixel further includes a second conductive connection portion 36, which includes a third portion 361 and a fourth portion 362. The third portion 361 is coupled to the second initialization signal line 12 and the second compensation signal line 22, respectively, and the fourth portion 362 is coupled to the second electrode T7-s2 of the second reset transistor T7.

[0182] For example, the third portion 361 extends along the first direction, and the fourth portion 362 extends along the second direction.

[0183] For example, the third part 361 and the fourth part 362 are formed as an integral structure.

[0184] For example, the orthographic projection of the third portion 361 on the substrate overlaps with the orthographic projection of the second initialization signal line 12 on the substrate, and the orthographic projection of the third portion 361 on the substrate overlaps with the orthographic projection of the second compensation signal line 22 on the substrate. The third portion 361 is coupled to the second initialization signal line 12 and the second compensation signal line 22 respectively through vias.

[0185] For example, the orthographic projection of the fourth portion 362 onto the substrate at least partially overlaps with the orthographic projection of the second electrode T7-s2 of the second reset transistor T7 onto the substrate. The fourth portion 362 is coupled to the second electrode T7-s2 of the second reset transistor T7 via a via.

[0186] The above-mentioned configuration of the second conductive connection portion 36 being coupled to the second initialization signal line 12, the second compensation signal line 22, and the second terminal T7-s2 of the second reset transistor T7 not only ensures electrical connection performance but also effectively reduces the layout difficulty of the display substrate, which is beneficial to improving the resolution of the display substrate.

[0187] like Figures 1 to 6 , Figure 8 As shown, in some embodiments, the sub-pixel further includes: a gate line 37, at least a portion of which extends along the first direction;

[0188] The sub-pixel driving circuit also includes:

[0189] The compensation transistor T2 includes a third gate pattern T2-g and a third active pattern; the third gate pattern T2-g is coupled to the gate line 37, and the third gate pattern T2-g includes a fifth portion T2-g1 and a sixth portion T2-g2, the sixth portion T2-g2 extends along the first direction, the fifth portion T2-g1 extends along the second direction, and the orthographic projection of the third active pattern on the substrate at least partially overlaps with the orthographic projections of the sixth portion T2-g2 and the fifth portion T2-g1 on the substrate;

[0190] The data writing transistor T4 includes a fourth gate pattern T4-g and a fourth active pattern; the fourth gate pattern T4-g is coupled to the gate line 37 and extends along the first direction; the fourth active pattern is coupled to the data line 23 and the second terminal T3-s2 of the driving transistor T3, respectively.

[0191] For example, the gate line 37 is used to transmit the gate scan signal Gate.

[0192] For example, the third gate pattern T2-g includes a sixth portion T2-g2 and a fifth portion T2-g1, which are formed as an integral structure.

[0193] For example, the orthographic projection of the third gate pattern T2-g on the substrate and the orthographic projection of the gate line 37 on the substrate have an overlapping area, and the third gate line pattern T2-g and the gate line 37 are coupled through a via, the orthographic projection of which on the substrate is located in the overlapping area.

[0194] For example, the third active pattern can form the first terminal T2-s1 and the second terminal T2-s2 of the compensation transistor T2, the first terminal T2-s1 of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3, and the second terminal T2-s2 of the compensation transistor T2 is coupled to the first terminal T3-s1 of the driving transistor T3.

[0195] For example, the orthographic projection of the fourth gate pattern T4-g on the substrate and the orthographic projection of the gate line 37 on the substrate have an overlapping area, and the fourth gate line 37 pattern and the gate line 37 are coupled through a via, the orthographic projection of which on the substrate is located in the overlapping area.

[0196] For example, the fourth active pattern can form the first terminal T4-s1 and the second terminal T4-s2 of the data writing transistor T4, the first terminal T4-s1 of the data writing transistor T4 being coupled to the second terminal T3-s2 of the driving transistor T3, and the second terminal T4-s2 of the data writing transistor T4 being coupled to the data line 23.

[0197] The sub-pixel driving circuit described above also includes the data writing transistor T4 and the compensation transistor T2. The data writing transistor T4 can write data signals to the second terminal T3-s2 of the driving transistor T3, and the compensation transistor T2 can compensate the threshold voltage of the driving transistor T3.

[0198] like Figures 6 to 8 As shown, in some embodiments, the third active pattern includes a first sub-pattern T2-s3, a second sub-pattern T2-s4, and a third sub-pattern T2-s5; the orthographic projection of the first sub-pattern T2-s3 on the substrate at least partially overlaps with the orthographic projection of the sixth portion T2-g2 on the substrate; the orthographic projection of the second sub-pattern T2-s4 on the substrate at least partially overlaps with the orthographic projection of the fifth portion T2-g1 on the substrate; the third sub-pattern T2-s5 is located between the first sub-pattern T2-s3 and the second sub-pattern T2-s4, and is coupled to both the first sub-pattern T2-s3 and the second sub-pattern T2-s4 respectively;

[0199] like Figure 5 As shown, the sub-pixel further includes: a power line 38, the power line 38 including a portion extending along the first direction;

[0200] like Figures 5 to 9As shown, the sub-pixel driving circuit further includes a storage capacitor Cst, which includes a first electrode Cst1 and a second electrode Cst2 disposed opposite to each other. The first electrode Cst1 is located between the second electrode Cst2 and the substrate. The first electrode Cst1 is coupled to the gate T3-g of the driving transistor T3. The second electrode Cst2 is coupled to the power line 38. The orthographic projection of the second electrode Cst2 on the substrate at least partially overlaps with the orthographic projection of the third sub-pattern T2-s5 on the substrate.

[0201] For example, the first sub-graphic T2-s3, the second sub-graphic T2-s4, and the third sub-graphic T2-s5 are formed as an integral structure.

[0202] For example, the portion where the first sub-pattern T2-s3 overlaps with the sixth portion T2-g2 includes a semiconductor portion, the portion where the second sub-pattern T2-s4 overlaps with the fifth portion T2-g1 includes a semiconductor portion, and the third sub-pattern T2-s5 includes a conductor portion.

[0203] For example, the power line 38 is used to transmit a positive power signal VDD.

[0204] For example, the display substrate further includes a cathode for transmitting a negative power signal VSS.

[0205] For example, the sub-pixel driving circuit further includes a storage capacitor Cst, which includes a first plate Cst1 and a second plate Cst2 disposed opposite to each other, and the gate T3-g of the driving transistor T3 is multiplexed to the first plate Cst1.

[0206] For example, the orthographic projection of the first electrode plate Cst1 on the substrate at least partially overlaps with the orthographic projection of the power line 38 on the substrate.

[0207] For example, the orthographic projection of the second electrode plate Cst2 on the substrate partially overlaps with the orthographic projection of the gate line 37 on the substrate. The orthographic projection of the second electrode plate Cst2 on the substrate does not overlap with the orthographic projection of the data line 23 on the substrate. The orthographic projection of the second electrode plate Cst2 on the substrate does not overlap with the orthographic projection of the light emission control signal line 51 on the substrate.

[0208] For example, the light emission control signal line 51 is used to provide a light emission control signal EM.

[0209] The above-mentioned configuration of coupling the second electrode plate Cst2 with the power line 38 enables the transmission of a positive power signal with a stable potential on the second electrode plate Cst2. By setting the orthographic projection of the second electrode plate Cst2 on the substrate to at least partially overlap with the orthographic projection of the third sub-pattern T2-s5 on the substrate, interference from other surrounding signals on the signal transmitted on the third sub-pattern T2-s5 is effectively shielded, thereby ensuring the stability of the operation of the compensation transistor T2.

[0210] like Figures 5 to 9 As shown, in some embodiments, the sub-pixel driving circuit further includes:

[0211] Compensation transistor T2, wherein the compensation transistor T2 includes a third active pattern;

[0212] A storage capacitor Cst includes a first electrode Cst1 and a second electrode Cst2 disposed opposite to each other. The second electrode Cst2 includes an electrode body Cst21 and an electrode shielding portion Cst22. The orthographic projection of the electrode body Cst21 on the substrate at least partially overlaps with the orthographic projection of the first electrode Cst1 on the substrate, and the orthographic projection of the electrode shielding portion Cst22 on the substrate at least partially overlaps with the orthographic projection of the third active pattern on the substrate.

[0213] The orthographic projection of the electrode shielding portion Cst22 on the substrate does not overlap with the orthographic projection of the first compensation signal line 21 on the substrate; and / or, the orthographic projection of the electrode shielding portion Cst22 on the substrate does not overlap with the orthographic projection of the second compensation signal line 22 on the substrate.

[0214] The above configuration can effectively avoid the generation of parasitic capacitance between the second electrode plate Cst2 and the first compensation signal line 21 and the second compensation signal line 22, which is beneficial to improving the working performance of the sub-pixel driving circuit.

[0215] In some embodiments, the first compensation signal line is disposed in the same sub-pixel, and its orthogonal projection on the substrate is located between the orthogonal projection of the electrode shielding portion Cst22 on the substrate and the orthogonal projection of the second compensation signal line on the substrate.

[0216] Since the potential of the signal transmitted by the first compensation signal line is close to the potential of the signal on the second electrode plate Cst2, the above arrangement helps to reduce the interference of the second electrode plate Cst2 from the surrounding signals.

[0217] like Figure 10As shown, in some embodiments, the sub-pixel further includes: a power line 38; the power line 38 includes a first power pattern 381, a second power pattern 382, ​​and a third power pattern 383; the first power pattern 381 and the second power pattern 382 both extend along the first direction, and the third power pattern 383 extends along the second direction; the second power pattern 382 is coupled to the first power pattern 381 and the third power pattern 383 respectively; the second power pattern 382 is coupled to the second electrode plate Cst2.

[0218] like Figure 14 and Figure 15 As shown, for example, the power line 38 further includes a fourth power pattern 384, which is coupled to the second power pattern 382.

[0219] For example, the first power pattern 381, the second power pattern 382, ​​and the third power pattern 383 are formed into a single structure.

[0220] For example, along the second direction, the width of the first power pattern 381 is smaller than the width of the second power pattern 382, ​​and the width of the second power pattern 382 is smaller than the width of the third power pattern 383.

[0221] For example, the orthographic projection of the first power pattern 381 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate Cst2 on the substrate.

[0222] For example, the orthographic projection of the first power supply pattern 381 on the substrate overlaps with the orthographic projection of the first electrode T3-s1 of the driving transistor T3 on the substrate. The orthographic projection of the first power supply pattern 381 on the substrate overlaps with the orthographic projection of the second electrode T3-s2 of the driving transistor T3 on the substrate. The orthographic projection of the first power supply pattern 381 on the substrate overlaps with the orthographic projection of the data line 23 on the substrate.

[0223] For example, the orthographic projection of the second power pattern 382 on the substrate overlaps with the orthographic projection of the second electrode plate Cst2 on the substrate. The second power pattern 382 is coupled to the second electrode plate Cst2 through a via, the orthographic projection of which is located in the overlapping area.

[0224] For example, the orthographic projection of the second power supply pattern 382 onto the substrate does not overlap with the orthographic projection of the first electrode T3-s1 of the driving transistor T3 onto the substrate. The orthographic projection of the second power supply pattern 382 onto the substrate at least partially overlaps with the orthographic projection of the second electrode T3-s2 of the driving transistor T3 onto the substrate.

[0225] For example, the orthographic projection of the third power pattern 383 on the substrate at least partially overlaps with the orthographic projection of the light emission control signal line 51 on the substrate.

[0226] For example, the orthographic projection of the third power supply pattern 383 on the substrate does not overlap with the orthographic projection of the second electrode plate Cst2 on the substrate, or at least partially overlaps.

[0227] For example, the orthographic projection of the third power pattern 383 on the substrate and the orthographic projection of the second electrode T5-s2 of the power control transistor T5 on the substrate have an overlapping area. The third power pattern 383 and the second electrode T5-s2 of the power control transistor T5 are coupled through a via, and the orthographic projection of the via on the substrate is located in the overlapping area.

[0228] The power line 38 described above includes the first power pattern 381, the second power pattern 382, ​​and the third power pattern 383, which helps to reduce the layout difficulty of the power line 38.

[0229] like Figure 5 and Figure 10 As shown, in some embodiments, setting the sub-pixel further includes: a light emission control signal line 51, the light emission control signal line 51 including at least a portion extending along the first direction;

[0230] The third power supply pattern 383 includes a first power supply sub-pattern 3831 and a second power supply sub-pattern 3832. The width of the first power supply sub-pattern 3831 along the first direction is smaller than the width of the second power supply sub-pattern 3832. The orthographic projection of the first power supply sub-pattern 3831 on the substrate at least partially overlaps with the orthographic projection of the light emission control signal line 51 on the substrate.

[0231] The above configuration helps to reduce the overlap area between the power line 38 and the light emission control signal line 51, and reduces the parasitic capacitance generated between the power line 38 and the light emission control signal line 51, thereby effectively improving the working stability of the sub-pixel driving circuit.

[0232] like Figure 5 , Figure 9 and Figure 10As shown, in some embodiments, the orthographic projection of the second power pattern 382 on the substrate is located inside the orthographic projection of the electrode body Cst21 on the substrate.

[0233] The above configuration helps to improve the flatness of the second power pattern 382 and can effectively improve the flatness of the anode layer in the sub-pixel.

[0234] like Figures 1 to 6 As shown, in some embodiments, the sub-pixel further includes:

[0235] A light-emitting control signal line 51, at least a portion of which extends along the first direction, wherein the orthographic projection of the light-emitting control signal line 51 on the substrate at least partially overlaps with the orthographic projection of the third power supply pattern 383 on the substrate;

[0236] The sub-pixel driving circuit also includes:

[0237] A power control transistor T5, wherein the gate T5-g of the power control transistor T5 is coupled to the light emission control signal line 51, the first terminal T5-s1 of the power control transistor T5 is coupled to the second terminal of the driving transistor T3, and the second terminal T5-s2 of the power control transistor T5 is coupled to the third power pattern 383.

[0238] The light-emitting control transistor T6 has its gate T6-g coupled to the light-emitting control signal line 51, its first terminal T6-s1 coupled to the light-emitting element EL, and its second terminal T6-s2 coupled to the first terminal T3-s1 of the driving transistor T3.

[0239] For example, the light emission control signal line 51 is used to transmit the light emission control signal EM.

[0240] For example, the gate T5-g of the power control transistor T5 is formed as an integral structure with the light emission control signal line 51.

[0241] For example, the gate T6-g of the light-emitting control transistor T6 is formed as an integral structure with the light-emitting control signal line 51.

[0242] For example, the first electrode T6-s1 of the light-emitting control transistor T6 and the first electrode T7-s1 of the second reset transistor T7 are formed as an integral structure.

[0243] In some embodiments, the display substrate further includes a first source / drain metal layer;

[0244] The first reset signal line 33, the second reset signal line 35, the gate line 37, the power line 38, the first conductive connection portion 34, and the second conductive connection portion 36 are all disposed in the same layer and with the same material as the first source and drain metal layer.

[0245] For example, the first source / drain metal layer is used to form the first initialization signal bus 31 and the second initialization signal bus 32.

[0246] For example, the orthographic projections of the first initialization signal line 11, the first reset signal line 33, the gate line 37, the light emission control signal line 51, the second reset signal line 35, and the second initialization signal line 12 on the substrate are arranged sequentially along the second direction.

[0247] For example, the gate of each of the above transistors and the light-emitting control signal line 51 are both made of the first gate metal layer.

[0248] For example, the second electrode Cst2, the first initialization signal line 11 and the second initialization signal line 12 are made of a second gate metal layer.

[0249] It needs to be explained that, Figure 1 The diagram also illustrates node N1.

[0250] The above-described configuration simplifies the manufacturing process of the display substrate and reduces its manufacturing cost. It also helps reduce the resistance of the first reset signal line 33, the second reset signal line 35, the gate line 37, the power line 38, the first conductive connection portion 34, and the second conductive connection portion 36, thereby improving the stability of the sub-pixel driving circuit.

[0251] In some embodiments, the first reset signal line 33 is disposed in the same layer and with the same material as the first gate metal layer.

[0252] In some embodiments, the first compensation signal line 21 and the second compensation signal line 22 are both disposed in the same layer and with the same material as the first source / drain metal layer. The conductive portions of the sub-pixel that overlap with the first compensation signal line 21 and the second compensation signal line 22 in a direction perpendicular to the substrate are fabricated using other film layers to avoid short circuits with the first compensation signal line 21 and the second compensation signal line 22.

[0253] This invention also provides a display device, including the display substrate provided in the above embodiments.

[0254] In the display substrate provided in the above embodiment, the gate T3-g of the driving transistor T3 is reset using the first initialization signal provided by the first initialization signal line 11, and the light-emitting element EL is reset using the second initialization signal provided by the second initialization signal line 12. This makes the first initialization signal for resetting the gate T3-g of the driving transistor T3 and the second initialization signal for resetting the light-emitting element EL independent of each other, enabling independent control and allowing them to have different voltage values. This achieves the goal of ensuring the black state brightness of the light-emitting element EL in low grayscale display while avoiding increasing the leakage current of the gate T3-g of the driving transistor T3, thus ensuring the white state brightness of the light-emitting element EL in high grayscale display.

[0255] Therefore, when the display device provided in the embodiments of the present invention includes the above-mentioned display substrate, it can improve defects such as image retention and first frame response time of the display device, and can also improve the mura defects that occur when displaying low grayscale, thus ensuring the brightness uniformity of the display device when displaying high grayscale and low grayscale.

[0256] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0257] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0258] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0259] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0260] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0261] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0262] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0263] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, include: A substrate and a plurality of sub-pixels disposed on the substrate, the sub-pixels including: A first initialization signal line and a second initialization signal line, wherein the potential of the first initialization signal transmitted on the first initialization signal line is different from the potential of the second initialization signal transmitted on the second initialization signal line; and, A sub-pixel driving circuit and a light-emitting element are provided. The sub-pixel driving circuit includes a driving transistor, a first reset transistor, and a second reset transistor. The first terminal of the driving transistor is coupled to the light-emitting element. The first terminal of the first reset transistor is coupled to the gate of the driving transistor, and the second terminal of the first reset transistor is coupled to the first initialization signal line. The first terminal of the second reset transistor is coupled to the light-emitting element, and the second terminal of the second reset transistor is coupled to the second initialization signal line. The sub-pixel further includes: a first compensation signal line and / or a second compensation signal line; at least a portion of the first compensation signal line extends along a second direction, and the first compensation signal line is coupled to the first initialization signal line; at least a portion of the second compensation signal line extends along the second direction, and the second compensation signal line is coupled to the second initialization signal line. The sub-pixel also includes a data line, at least a portion of which extends along the second direction; At least some sub-pixels include a minimum distance between the data line and the first compensation signal line adjacent to it along the first direction, which is less than the minimum distance between it and the second compensation signal line adjacent to it along the first direction.

2. The display substrate according to claim 1, characterized in that, At least a portion of the first initialization signal line extends along a first direction; At least a portion of the second initialization signal line extends along the first direction; The second direction intersects with the first direction.

3. The display substrate according to claim 2, characterized in that, In the same sub-pixel, the orthographic projection of the gate of the driving transistor on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first compensation signal line on the substrate; And it is located between the orthographic projection of the data line on the substrate and the orthographic projection of the second compensation signal line on the substrate; Both the first compensation signal line and the second compensation signal line are made of the same layer and material as the data line.

4. The display substrate according to claim 2, characterized in that, In the same sub-pixel, the orthographic projection of the data line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the first compensation signal line on the substrate; And it is located between the orthogonal projection of the gate of the driving transistor on the substrate and the orthogonal projection of the second compensation signal line on the substrate; Both the first compensation signal line and the second compensation signal line are made of the same layer and material as the data line.

5. The display substrate according to claim 2, characterized in that, The plurality of sub-pixels are arranged in an array. In sub-pixels located in the same row along the first direction, the first initialization signal line is coupled to each other; in sub-pixels located in the same column along the second direction, the first compensation signal line is coupled to each other. And / or, In sub-pixels located in the same row along the first direction, the second initialization signal line is coupled; in sub-pixels located in the same column along the second direction, the second compensation signal line is coupled.

6. The display substrate according to claim 5, characterized in that, The display substrate includes a display area and a peripheral area surrounding the display area; the display substrate further includes: A first initialization signal bus is disposed in the peripheral area, at least a portion of the first initialization signal bus extends along the second direction, and a first initialization signal line is coupled to the first initialization signal bus; and / or, A second initialization signal bus is disposed in the peripheral area, at least a portion of the second initialization signal bus extends along the second direction, and the second initialization signal line is coupled to the second initialization signal bus.

7. The display substrate according to claim 6, characterized in that, The first initialization signal bus surrounds the display area; the first compensation signal line is coupled to the first initialization signal bus; And / or, the second initialization signal bus surrounds the display area; The second compensation signal line is coupled to the second initialization signal bus.

8. The display substrate according to claim 3 or 4, characterized in that, The sub-pixel further includes: a first reset signal line, at least a portion of which extends along the first direction; The first reset transistor includes a first gate pattern and a first active pattern; the first gate pattern is coupled to the first reset signal line, the first gate pattern has a U-shaped structure, and the opening of the U-shaped structure faces the data line; the orthographic projection of the first active pattern on the substrate at least partially overlaps with the orthographic projection of the portion of the first gate pattern located on both sides of the opening on the substrate.

9. The display substrate according to claim 8, characterized in that, The first active pattern includes the first terminal and the second terminal of the first reset transistor; The sub-pixel further includes: a first conductive connection portion, the first conductive connection portion including a first part and a second part; the first part is coupled to the first initialization signal line and the first compensation signal line respectively, and the second part is coupled to the second pole of the first reset transistor.

10. The display substrate according to claim 9, characterized in that, The sub-pixel further includes: a second reset signal line, at least a portion of which extends along the first direction; The second reset transistor includes a second gate pattern and a second active pattern; the second gate pattern is coupled to the second reset signal line, and at least a portion of the second gate pattern extends along the first direction; the second active pattern, the second gate pattern and the second reset signal line are stacked sequentially along a direction away from the substrate.

11. The display substrate according to claim 10, characterized in that, The second active pattern includes the first and second terminals of the second reset transistor; The sub-pixel further includes: a second conductive connection portion, the second conductive connection portion including a third part and a fourth part, the third part being coupled to the second initialization signal line and the second compensation signal line respectively, and the fourth part being coupled to the second pole of the second reset transistor.

12. The display substrate according to claim 11, characterized in that, The sub-pixel also includes: A grid line, at least a portion of which extends along the first direction; The sub-pixel driving circuit also includes: A compensation transistor, the compensation transistor including a third gate pattern and a third active pattern; the third gate pattern is coupled to the gate line, the third gate pattern including a fifth portion and a sixth portion, the sixth portion extending along a first direction, the fifth portion extending along a second direction, the orthographic projection of the third active pattern on the substrate at least partially overlapping the orthographic projections of the sixth portion on the substrate and the fifth portion on the substrate, respectively. A data writing transistor includes a fourth gate pattern and a fourth active pattern; the fourth gate pattern is coupled to the gate line and extends along the first direction; the fourth active pattern is coupled to the data line and the second terminal of the driving transistor, respectively.

13. The display substrate according to claim 12, characterized in that, The third active pattern includes a first sub-pattern, a second sub-pattern, and a third sub-pattern; the orthographic projection of the first sub-pattern on the substrate at least partially overlaps with the orthographic projection of the sixth part on the substrate; the orthographic projection of the second sub-pattern on the substrate at least partially overlaps with the orthographic projection of the fifth part on the substrate; The third sub-graphic is located between the first sub-graphic and the second sub-graphic, and is coupled to both the first sub-graphic and the second sub-graphic respectively; The sub-pixel further includes: a power line, the power line including a portion extending along the first direction; The sub-pixel driving circuit further includes a storage capacitor, which includes a first electrode plate and a second electrode plate disposed opposite to each other. The first electrode plate is located between the second electrode plate and the substrate. The first electrode plate is coupled to the gate of the driving transistor, and the second electrode plate is coupled to the power line. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the third sub-pattern on the substrate.

14. The display substrate according to claim 2, characterized in that, The sub-pixel driving circuit also includes: A compensation transistor, the compensation transistor comprising a third active pattern; A storage capacitor includes a first electrode and a second electrode disposed opposite to each other. The second electrode includes an electrode body and an electrode shield. The orthographic projection of the electrode body on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate. The orthographic projection of the electrode shield on the substrate at least partially overlaps with the orthographic projection of the third active pattern on the substrate. The orthographic projection of the electrode shield on the substrate does not overlap with the orthographic projection of the first compensation signal line on the substrate; and / or, the orthographic projection of the electrode shield on the substrate does not overlap with the orthographic projection of the second compensation signal line on the substrate.

15. The display substrate according to claim 14, characterized in that, In the same sub-pixel, the orthographic projection of the first compensation signal line on the substrate is located between the orthographic projection of the electrode shield on the substrate and the orthographic projection of the second compensation signal line on the substrate.

16. The display substrate according to claim 14, characterized in that, The sub-pixel further includes: a power line; the power line includes a first power pattern, a second power pattern, and a third power pattern; the first power pattern and the second power pattern both extend along the first direction, and the third power pattern extends along the second direction; the second power pattern is coupled to the first power pattern and the third power pattern respectively; the second power pattern is coupled to the second electrode plate.

17. The display substrate according to claim 16, characterized in that, The sub-pixel further includes: a light emission control signal line, the light emission control signal line including at least a portion extending along the first direction; The third power supply pattern includes a first power supply sub-pattern and a second power supply sub-pattern. The width of the first power supply sub-pattern along the first direction is smaller than the width of the second power supply sub-pattern. The orthographic projection of the first power supply sub-pattern on the substrate at least partially overlaps with the orthographic projection of the light emission control signal line on the substrate.

18. The display substrate according to claim 16, characterized in that, The orthographic projection of the second power source pattern on the substrate is located inside the orthographic projection of the electrode body on the substrate.

19. The display substrate according to claim 16, characterized in that, The sub-pixel also includes: A light-emitting control signal line, at least a portion of which extends along the first direction, wherein the orthographic projection of the light-emitting control signal line on the substrate at least partially overlaps with the orthographic projection of the third power supply pattern on the substrate; The sub-pixel driving circuit also includes: A power control transistor, wherein the gate of the power control transistor is coupled to the light emission control signal line, the first terminal of the power control transistor is coupled to the second terminal of the driving transistor, and the second terminal of the power control transistor is coupled to the third power pattern; A light-emitting control transistor, wherein the gate of the light-emitting control transistor is coupled to the light-emitting control signal line, the first electrode of the light-emitting control transistor is coupled to the light-emitting element, and the second electrode of the light-emitting control transistor is coupled to the first electrode of the driving transistor.

20. The display substrate according to claim 19, characterized in that, The display substrate further includes a first source / drain metal layer; The first reset signal line, second reset signal line, gate line, power line, first conductive connection portion, and second conductive connection portion in the display substrate are all disposed in the same layer and with the same material as the first source / drain metal layer.

21. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 20.

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