A BUCK circuit with precisely adjustable current and its adjustment method

Abstract

This invention discloses a BUCK circuit with precisely adjustable current and its adjustment method. The circuit includes a time loop control circuit and a BUCK constant current circuit. The input terminal of the time loop control circuit is connected to the output terminal of the BUCK constant current circuit to obtain the output current Iout of the BUCK constant current circuit. The output terminal of the time loop control circuit is connected to the input terminal of the BUCK constant current circuit to adjust the output current Iout of the BUCK constant current circuit. The time loop control circuit includes a sampling circuit I0, a comparator I1, a control calculation module I2, and an AND gate I3. The BUCK constant current circuit includes a driver circuit I4, an NMOS transistor Q0, a freewheeling diode D0, an energy storage inductor L0, a current sensing resistor R0, a filter capacitor C0, a light-emitting diode D1, and a power supply. The adjustment method includes: obtaining the sampling voltage Vsns and calculating the output current Iout; if the output current Iout is adjusted to a high current adjustment, it enters the analog adjustment mode; otherwise, it enters the mixed analog-digital adjustment mode. The output current of the BUCK circuit can be precisely adjusted.

Description

Technical Field

[0001] This invention relates to the field of BUCK circuit technology, and in particular to a BUCK circuit with precisely adjustable current and its adjustment method. Background Technology

[0002] A buck circuit, also known as a step-down circuit, is a basic DC-DC converter circuit. Its output voltage is lower than its input voltage; the input current is pulsating, while the output current is continuous. A typical buck circuit is as follows: Figure 1 As shown, the circuit includes an NMOS transistor, an energy storage inductor L0, a freewheeling diode D0, a filter capacitor C0, and a load D1. When the NMOS transistor is driven at a high level, it conducts, magnetizing the energy storage inductor L0. The current flowing through the energy storage inductor L0 increases linearly, simultaneously charging the filter capacitor C0 and providing current to the load D1. When the NMOS transistor is driven at a low level, it is turned off, discharging the energy storage inductor L0 through the freewheeling diode D0. The current in the energy storage inductor L0 decreases linearly, and the output voltage is maintained by the discharge of the output filter capacitor C0 and the reduced current in the energy storage inductor L0, thus achieving a decrease in both output voltage and output current. This conventional BUCK circuit regulates current solely through the direct and continuous drive of the NMOS transistor, resulting in insufficient accuracy in current regulation. Furthermore, due to the influence of manufacturing processes and external environmental noise, it presents significant difficulties, especially in detecting and regulating small currents, thus limiting the practical application of BUCK circuits. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a BUCK circuit and its adjustment method that can precisely adjust the current, thereby solving the above-mentioned problems.

[0004] One aspect of the present invention provides a BUCK circuit with precisely adjustable current, comprising: a time loop control circuit and a BUCK constant current circuit; the input terminal of the time loop control circuit is connected to the output terminal of the BUCK constant current circuit for acquiring the output current Iout of the BUCK constant current circuit; the output terminal of the time loop control circuit is connected to the input terminal of the BUCK constant current circuit for adjusting the output current Iout of the BUCK constant current circuit; the time loop control circuit includes: a sampling circuit I0, a comparator I1, a control calculation module I2, and an AND gate I3; the BUCK constant current circuit includes: a driving circuit I4, an NMOS transistor Q0, a freewheeling diode D0, an energy storage inductor L0, a current sensing resistor R0, a filter capacitor C0, a light-emitting diode D1, and a power supply.

[0005] The comparator I1 has its positive terminal connected to the output of the sampling circuit I0 to acquire the sampled voltage Vsns and compare it with the reference voltage Vref. When the reference voltage Vref is less than the sampled voltage Vsns, the comparator I1 outputs a comparison signal Tcomp at a high level. The control calculation module I2 has its input connected to the output of the sampling circuit I0 to acquire the sampled voltage Vsns and calculate the output current Iout. The AND gate I3 has its input connected to the outputs of the comparator I1 and the control calculation module I2, respectively, to perform logical operations on the comparison signal Tcomp output by the comparator I1 and the compensation signal PASS output by the control calculation module I2. The output of the AND gate I3 has its input connected to the input of the drive circuit I4 to control the drive circuit I4.

[0006] The output of the driving circuit I4 is connected to the gate (G) terminal of the NMOS transistor Q0 to drive the NMOS transistor Q0 to switch on and off. The energy storage inductor L0 and the freewheeling diode D0 are connected in series and then in parallel across the light-emitting diode D1. The energy storage inductor L0 discharges through the freewheeling diode D0 to maintain the voltage of the light-emitting diode D1. The filter capacitor C0 is connected in parallel across the light-emitting diode D1 to stabilize the voltage of the light-emitting diode D1. The current sensing resistor R0 is also connected in series between the energy storage inductor L0 and the light-emitting diode D1. The input of the sampling circuit I0 is connected to both ends of the current sensing resistor R0 to collect the sampling voltage Vsns.

[0007] The sampling circuit I0 includes: resistors R1, R2, and R3; PMOS transistors Q1, Q2, and Q3; wherein the two ends of the current sensing resistor R0 are connected to one end of resistor R1 and one end of resistor R2, respectively; and the positive terminal of the comparator I1 is connected to the source terminal of PMOS transistor Q3 and one end of resistor R3, respectively.

[0008] The driving circuit I4 includes a PMOS transistor Q4 and an NMOS transistor Q5. The gate (G) terminals of the PMOS transistor Q4 and the NMOS transistor Q5 are connected to the output terminal of the AND gate I3 to acquire a control signal. The source (S) terminal of the PMOS transistor Q4 and the drain (D) terminal of the NMOS transistor Q5 are connected to the gate (G) terminal of the NMOS transistor Q0 to drive the NMOS transistor Q0.

[0009] Another aspect of the present invention provides a method for adjusting a BUCK circuit with precisely adjustable current, comprising:

[0010] Obtain the sampled voltage Vsns and calculate the output current Iout;

[0011] If the output current Iout is adjusted to high current adjustment, it enters analog adjustment mode; otherwise, it enters mixed analog-digital adjustment mode.

[0012] The NMOS transistor Q0 is turned off, causing the energy storage inductor L0 to discharge through the freewheeling diode D0;

[0013] The discharge of the filter capacitor C0 and the energy storage inductor L0 maintains the voltage of the light-emitting diode D1, and the output current Iout decreases.

[0014] The high current regulation is to adjust the output current Iout to 5%-100% of the maximum output current Imax.

[0015] The specific steps of the analog adjustment mode include:

[0016] Reduce the reference voltage Vref so that it is less than the sampling voltage Vsns;

[0017] The comparator I1 outputs a low-level comparison signal Tcomp.

[0018] The comparison signal Tcomp controls the driving circuit I4 to drive the NMOS transistor Q0 to turn off.

[0019] The specific steps of the digital-analog hybrid adjustment mode include:

[0020] The control calculation module I2 generates a compensation signal PASS.

[0021] The compensation signal PASS, combined with the comparison signal Tcomp, controls the driving circuit I4 to drive the NMOS transistor Q0 to turn off.

[0022] The delay TD causes the output current Iout to be discontinuous.

[0023] The steps for obtaining the sampling voltage Vsns include:

[0024] The control and calculation module I2 controls the sampling circuit I0 to sample the voltage across the current sensing resistor R0 to obtain the sampling voltage Vsns.

[0025] The beneficial effects of this invention are:

[0026] First, a comparator was added to the original circuit. By adjusting the reference voltage value Vref, large current regulation was achieved through analog regulation, while ensuring the continuity of the output current.

[0027] Secondly, a control calculation module has been added, so the adjustment of the output current no longer depends entirely on changing the reference voltage Vref. Therefore, the accuracy requirements of the analog circuit can be significantly reduced. When controlling a large current, the continuity of the output current can be ensured by analog adjustment. When controlling a small current, the use of digital-analog hybrid adjustment ensures high control accuracy and detection accuracy for small currents.

[0028] Thirdly, compared to traditional external PWM control, a delay TD can be precisely inserted when the inductor current crosses zero to ensure control accuracy. PWM control shuts down the entire BUCK circuit loop, which can lead to inaccurate determination of the inductor current at the loop shutdown point, resulting in insufficient current control accuracy and reduced efficiency. Please refer to [link to relevant documentation]. Figure 2 Due to the phase uncertainty between the PWM control signal and the inductor current, there will be different time errors (t1, t2) for each control. Furthermore, in solutions such as constant current BUCK circuit driving LEDs, the low frequency of PWM will lead to insufficient refresh rate and unstable output current. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a conventional BUCK circuit diagram from the technical background section of the specification of this invention.

[0031] Figure 2 This is a waveform diagram illustrating the problems with adjusting current using the traditional PWM method, as described in the beneficial effects of this invention.

[0032] Figure 3 This is a BUCK circuit diagram with precisely adjustable current provided in an embodiment of the present invention.

[0033] Figure 4 This is a sampling circuit diagram provided in an embodiment of the present invention.

[0034] Figure 5 This is a driving circuit diagram provided in an embodiment of the present invention.

[0035] Figure 6 This is a waveform diagram illustrating the adjustment principle under the mixed analog-digital adjustment mode in an embodiment of the present invention.

[0036] Figure 7 This is an equivalent circuit diagram in the analog adjustment mode of an embodiment of the present invention.

[0037] Figure 8 This is a diagram showing the main signal waveforms of the equivalent circuit in the analog adjustment mode of an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention.

[0039] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0040] like Figure 3 As shown, this embodiment of the invention provides a BUCK circuit with precisely adjustable current, including: a time loop control circuit and a BUCK constant current circuit;

[0041] The input terminal of the time loop control circuit is connected to the output terminal of the BUCK constant current circuit to obtain the output current Iout of the BUCK constant current circuit.

[0042] The output terminal of the time loop control circuit is connected to the input terminal of the BUCK constant current circuit, and is used to adjust the output current Iout of the BUCK constant current circuit.

[0043] The time loop control circuit includes: a sampling circuit I0, a comparator I1, a control calculation module I2, and an AND gate I3;

[0044] The BUCK constant current circuit includes: a driver circuit I4, an NMOS transistor Q0, a freewheeling diode D0, an energy storage inductor L0, a current sensing resistor R0, a filter capacitor C0, a light-emitting diode D1, and a power supply.

[0045] In a preferred embodiment, the positive terminal of comparator I1 is connected to the output terminal of the sampling circuit I0 to acquire the sampled voltage Vsns and compare it with the reference voltage Vref. When the reference voltage Vref is less than the sampled voltage Vsns, the comparator I1 outputs a comparison signal Tcomp at a high level. The input terminal of the control calculation module I2 is connected to the output terminal of the sampling circuit I0 to acquire the sampled voltage Vsns and calculate the output current Iout. The input terminal of AND gate I3 is connected to the output terminals of comparator I1 and control calculation module I2, respectively, to perform logical operations on the comparison signal Tcomp output by comparator I1 and the compensation signal PASS output by control calculation module I2. The output terminal of AND gate I3 is connected to the input terminal of the drive circuit I4 to control the drive circuit I4.

[0046] In this embodiment, by setting comparator I1 to ensure that the sampling voltage Vsns does not exceed the reference voltage Vref, the output current Iout is adjusted under pure analog regulation. The control calculation module I2 can be an MCU, DSP, FPGA, digital logic gate, or large-scale integrated circuit based on digital logic design, etc., and this solution does not impose any restrictions.

[0047] In a preferred embodiment, the output terminal of the driving circuit I4 is connected to the gate (G) terminal of the NMOS transistor Q0 to drive the NMOS transistor Q0 to switch on and off. The energy storage inductor L0 and the freewheeling diode D0 are connected in series and then in parallel across the light-emitting diode D1. The energy storage inductor L0 discharges through the freewheeling diode D0 to maintain the voltage of the light-emitting diode D1. The filter capacitor C0 is connected in parallel across the light-emitting diode D1 to stabilize the voltage of the light-emitting diode D1. The current sensing resistor R0 is also connected in series between the energy storage inductor L0 and the light-emitting diode D1. The input terminal of the sampling circuit I0 is connected to both ends of the current sensing resistor R0 to collect the sampling voltage Vsns.

[0048] In this embodiment, the positive terminal of the power supply is connected to the drain (D) of the NMOS transistor Q0, and the negative terminal of the power supply is connected to the positive terminal of the freewheeling diode D0. The NMOS transistor Q0, freewheeling diode D0, energy storage inductor L0, current sensing resistor R0, filter capacitor C0, power supply, and their connection method constitute a common BUCK architecture. In specific applications, the light-emitting diode D1 can replace any load.

[0049] As a preferred implementation method, such as Figure 4As shown, the sampling circuit I0 of this scheme includes: resistors R1, R2, and R3, PMOS transistors Q1, Q2, and Q3. The two ends of the current sensing resistor R0 are respectively connected to one end of resistor R1 and one end of resistor R2. The positive terminal of the comparator I1 is respectively connected to the source terminal of PMOS transistor Q3 and one end of resistor R3.

[0050] In this embodiment, since the constant current BUCK circuit needs to be sampled and judged, a current sensing resistor R0 and a corresponding sampling circuit I0 need to be set so that the loop timing control circuit can obtain the sampling voltage Vsns to realize the sampling detection of the output current Iout, and perform further calculations and adjustments. PMOS transistors Q1, Q2, and Q3 are detection MOS transistors. The specific formula for calculating the sampling voltage Vsns is: Vsns = K * VR0 / R3, where Vsns is the voltage across the current sensing resistor R0.

[0051] As a preferred implementation method, such as Figure 5 As shown, the driving circuit I4 in this scheme includes: a PMOS transistor Q4 and an NMOS transistor Q5; wherein, the gate (G) terminal of the PMOS transistor Q4 and the gate (G) terminal of the NMOS transistor Q5 are connected to the output terminal of the AND gate I3 to obtain a control signal; the source (S) terminal of the PMOS transistor Q4 and the drain (D) terminal of the NMOS transistor Q5 are connected to the gate (G) terminal of the NMOS transistor Q0 to drive the NMOS transistor Q0.

[0052] In this embodiment, since the NMOS transistor Q0 requires a large drive signal and cannot be controlled by a small signal, the most common push-pull output structure composed of PMOS transistor Q4 and NMOS transistor Q5 is used as the drive circuit to drive the NMOS transistor Q0 to turn on or off.

[0053] This invention provides a method for adjusting a BUCK circuit with precisely adjustable current, specifically including the following steps:

[0054] Obtain the sampled voltage Vsns and calculate the output current Iout;

[0055] If the output current Iout is adjusted to high current adjustment, it enters analog adjustment mode; otherwise, it enters mixed analog-digital adjustment mode.

[0056] The NMOS transistor Q0 is turned off, causing the energy storage inductor L0 to discharge through the freewheeling diode D0;

[0057] The discharge of the filter capacitor C0 and the energy storage inductor L0 maintains the voltage of the light-emitting diode D1, and the output current Iout decreases.

[0058] In this step, both analog regulation mode and mixed-signal mode can turn off NMOS transistor Q0. The energy storage inductor L0 discharges through the freewheeling diode D0, and the current of the energy storage inductor L0, i.e. the output current Iout, decreases linearly. The output voltage is maintained by the discharge of the output filter capacitor C0 and the reduced current of the energy storage inductor L0, thereby achieving a reduction in output voltage and output current Iout.

[0059] The high current regulation is to adjust the output current Iout to 5%-100% of the maximum output current Imax.

[0060] In this step, given the maximum output current Imax of the LED driver is set, the ratio of the current output current Iout to the maximum output current Imax determines whether the current adjustment is high-current or low-current. For example, if the maximum current Imax is set to 1A, adjusting the output current Iout between 50mA and 1A is generally considered high-current adjustment (5%-100%), while adjusting it below 50mA is considered low-current adjustment (<5%). The specific value is not fixed and depends on the actual application scenario. This solution requires selecting an appropriate adjustment mode based on the magnitude of the output current Iout for more precise control of the output current.

[0061] This solution can also add a communication module outside the control calculation module I2. The communication module can be wirelessly or wiredly connected to the host computer to realize remote control and adjustment of the current.

[0062] The communication module can use wireless transmission methods such as Wi-Fi, Bluetooth, and Zigbee, or wired connections such as serial port, IIC, SPI, RS485, CAN, and LIN for data transmission. After receiving the data from the communication module, the control and calculation module I2 adjusts the time loop control based on the received data, thereby regulating the current.

[0063] In addition, external control can be achieved by providing voltage to the control calculation module I2 (e.g., 1V indicates an output current of 1A; 0.1V indicates an output current of 100mA), PWM duty cycle (e.g., 90% duty cycle indicates an output current of 900mA; 5% duty cycle indicates an output current of 50mA), and PWM frequency conversion (e.g., 10kHz, 50% PWM indicates 100mA; 1kHz, 50% PWM indicates 10mA).

[0064] The specific steps of the analog adjustment mode include:

[0065] Reduce the reference voltage Vref so that it is less than the sampling voltage Vsns;

[0066] The comparator I1 outputs a low-level comparison signal Tcomp.

[0067] The comparison signal Tcomp controls the driving circuit I4 to drive the NMOS transistor Q0 to turn off.

[0068] In this step, the analog adjustment mode sets the output current Iout by adjusting the reference voltage Vref. The output current is Iout = (Vref × K) / R0, where K is a fixed coefficient, and in this scheme, K is 1. Therefore, if the reference voltage Vref is 100mV and the sampling resistor R0 is 100mΩ, the output current Iout is 1A. If the reference voltage Vref is 10mV and the sampling resistor R0 remains unchanged, the output current Iout is 100mA. Simultaneously, the NMOS transistor Q0 is turned off, allowing the energy storage inductor L0 to discharge through the freewheeling diode D0. The current in the energy storage inductor L0, i.e., the output current Iout, decreases linearly. The output voltage is maintained by the discharge of the output filter capacitor C0 and the reduced current in the energy storage inductor L0, thereby achieving a decrease in both the output voltage and output current.

[0069] The specific steps of the digital-analog hybrid adjustment mode include:

[0070] The control calculation module I2 generates a compensation signal PASS.

[0071] The compensation signal PASS, combined with the comparison signal Tcomp, controls the driving circuit I4 to drive the NMOS transistor Q0 to turn off.

[0072] The delay TD causes the output current Iout to be discontinuous.

[0073] In this step, such as Figure 6As shown, the compensation signal PASS is used to generate the delay TD, and the comparison signal Tcomp is the output of the comparator I1. In the mixed-signal adjustment mode, if the compensation signal PASS is high, the comparison signal Tcomp can directly control the drive circuit I4 and thus control the constant current BUCK circuit; if the compensation signal PASS is low, the NMOS transistor Q0 is forcibly turned off, thereby generating the delay TD, and the comparison signal Tcomp is ignored. The peak-to-peak voltage of the voltage Vsns across the current sensing resistor R0 is Vpk, the waveform time width is T, the time with current at the energy storage inductor L0 is T1, and the time without current at the energy storage inductor L0 is T2. When the current of the energy storage inductor L0 is continuous, T1 = T, T2 = 0. Therefore, it can be considered that the output current Iout flowing through the energy storage inductor L0 to the light-emitting diode D1 within this time T is Iout = (Vpk*T1) / (2*R0*(T1+T2)) = (Vpk*T) / (2*R0*(T+0)). As can be easily seen from the above formula, if we want to reduce the output current Iout flowing to the light-emitting diode D1, we can do so by reducing the value of Vpk (adjusting Vref) or increasing the time of T2 (making the output current Iout discontinuous).

[0074] The steps for obtaining the sampling voltage Vsns include:

[0075] The control and calculation module I2 controls the sampling circuit I0 to sample the voltage across the resistor R0 to obtain the sampling voltage Vsns.

[0076] In this embodiment, the specific output current Iout adjustment process will be further explained.

[0077] In pure analog adjustment mode, such as Figure 7 and Figure 8 As shown, comparator I1 outputs a comparison signal Tcomp. When Tcomp is high, NMOS transistor Q0 is turned on, the current in energy storage inductor L0 increases, and the voltage across current sensing resistor R0, i.e., the sampling voltage Vsns, rises. This triggers the control calculation module I2 to begin sampling the sampling voltage Vsns. When the sampling voltage Vsns exceeds the reference voltage Vref, the comparison signal Tcomp outputs a low level, NMOS transistor Q0 is turned off, the current in energy storage inductor L0 decreases, and the sampling voltage Vsns decreases. At this point, the control calculation module I2 finishes sampling, and the peak-to-peak voltage Vpk and time width T of the sampling voltage Vsns can be obtained.

[0078] In the mixed-signal regulation mode, if it is necessary to reduce the output current Iout to 1% of Imax, with the reference voltage Vref fixed, TD = 9T can be calculated according to the formula Iout = (Vpk * T) / (2 * R0 * (T + TD)). The calculation module I2 is then controlled to generate a compensation signal PASS, thereby inserting a delay TD between the current waveforms of the two consecutive energy storage inductor L0, thus reducing the output current Iout by 1%. To achieve different output current Iout values, the above formula can be used for calculation.

[0079] The above description is only a part of the embodiments of the present invention and does not limit the scope of protection of the present invention. Any equivalent device or equivalent process transformation made according to the description and drawings of the present invention, or direct or indirect application in other related technical fields, are similarly included in the patent protection scope of the present invention.

Claims

1. A BUCK circuit with precisely adjustable current, characterized in that, include: Time loop control circuit and BUCK constant current circuit; The input terminal of the time loop control circuit is connected to the output terminal of the BUCK constant current circuit to obtain the output current Iout of the BUCK constant current circuit. The output terminal of the time loop control circuit is connected to the input terminal of the BUCK constant current circuit, and is used to adjust the output current Iout of the BUCK constant current circuit. The time loop control circuit includes: a sampling circuit I0, a comparator I1, a control calculation module I2, and an AND gate I3; The BUCK constant current circuit includes: a driver circuit I4, an NMOS transistor Q0, a freewheeling diode D0, an energy storage inductor L0, a current sensing resistor R0, a filter capacitor C0, a light-emitting diode D1, and a power supply. The sampling circuit I0 is connected across the current sensing resistor R0 to acquire the sampling voltage Vsns; the comparator I1 is used to acquire the sampling voltage Vsns and compare it with the reference voltage Vref, and output a comparison signal Tcomp; the control calculation module I2 is used to acquire the sampling voltage Vsns and calculate the output current Iout. The control calculation module I2 is configured such that: a maximum output current Imax is preset, where Imax is the maximum current value allowed to be output by the BUCK constant current circuit; the control calculation module I2 determines whether the current adjustment is a high current adjustment or a low current adjustment based on the calculated ratio of the output current Iout to the maximum output current Imax. When the output current Iout is adjusted to high current regulation, it enters analog regulation mode and is regulated by adjusting the reference voltage Vref, so that the output current Iout works in continuous conduction mode. When the output current Iout is adjusted to a small current adjustment, it enters the digital-analog hybrid adjustment mode. The adjustment is performed by generating a compensation signal PASS and combining it with the comparison signal Tcomp output by the comparator I1. A delay TD is inserted when the inductor current crosses zero, so that the output current Iout works in the discontinuous conduction mode. The AND gate I3 performs logical operations on the comparison signal Tcomp and the compensation signal PASS; and controls the driving circuit I4 to drive the NMOS transistor Q0.

2. The BUCK circuit with precisely adjustable current as described in claim 1, characterized in that, The positive terminal of comparator I1 is connected to the output terminal of the sampling circuit I0 to acquire the sampled voltage Vsns and compare it with the reference voltage Vref. When the reference voltage Vref is less than the sampled voltage Vsns, the comparator I1 outputs a comparison signal Tcomp at a high level. The input terminal of the control calculation module I2 is connected to the output terminal of the sampling circuit I0 to acquire the sampled voltage Vsns and calculate the output current Iout. The input terminal of AND gate I3 is connected to the output terminals of comparator I1 and control calculation module I2 respectively, and is used to perform logical operations on the comparison signal Tcomp output by comparator I1 and the compensation signal PASS output by control calculation module I2. The output terminal of AND gate I3 is connected to the input terminal of the drive circuit I4 to control the drive circuit I4.

3. The BUCK circuit with precisely adjustable current as described in claim 1, characterized in that, The output terminal of the driving circuit I4 is connected to the gate (G) terminal of the NMOS transistor Q0, and is used to drive the NMOS transistor Q0 to switch on and off. The energy storage inductor L0 and the freewheeling diode D0 are connected in series and then in parallel across the light-emitting diode D1. The energy storage inductor L0 discharges through the freewheeling diode D0 to maintain the voltage of the light-emitting diode D1. The filter capacitor C0 is connected in parallel across the light-emitting diode D1 to stabilize the voltage of the light-emitting diode D1. The current sensing resistor R0 is also connected in series between the energy storage inductor L0 and the light-emitting diode D1. The input terminal of the sampling circuit I0 is connected to both ends of the current sensing resistor R0 to collect the sampling voltage Vsns.

4. A BUCK circuit with precisely adjustable current as described in claim 1, characterized in that, The driving circuit I4 includes a PMOS transistor Q4 and an NMOS transistor Q5; wherein the gate (G) terminals of the PMOS transistor Q4 and the NMOS transistor Q5 are connected to the output terminal of the AND gate I3 to obtain a control signal; the source (S) terminal of the PMOS transistor Q4 and the drain (D) terminal of the NMOS transistor Q5 are connected to the gate (G) terminal of the NMOS transistor Q0 to drive the NMOS transistor Q0.

5. A method for adjusting a BUCK circuit with precisely adjustable current, based on the BUCK circuit with precisely adjustable current as described in any one of claims 1-4, characterized in that, Specifically, the following steps are included: Obtain the sampled voltage Vsns and calculate the output current Iout; Based on the ratio of the output current Iout to the maximum output current Imax, determine whether the current adjustment operation of the output current Iout is a high current adjustment or a low current adjustment. In the regulation mode, the NMOS transistor Q0 is turned off, causing the energy storage inductor L0 to discharge through the freewheeling diode D0; The discharge of the filter capacitor C0 and the energy storage inductor L0 maintains the voltage of the light-emitting diode D1, and the output current Iout decreases.

6. The adjustment method of a BUCK circuit with precisely adjustable current as described in claim 5, characterized in that, The high current adjustment is to adjust the output current Iout to 5%-100% of the maximum output current Imax.

Images