A quantum chip and its preparation method, and a quantum computer

Abstract

The present application discloses a quantum chip and its preparation method, as well as a quantum computer, belonging to the field of quantum information. The quantum chip shown includes: a plurality of quantum bits, wherein the plurality of the quantum bits are arranged in an array on a substrate, and the quantum bits include: a first capacitor plate, a second capacitor plate, and a superconducting quantum interference device, wherein one end of the superconducting quantum interference device is connected to the first capacitor plate and the other end is connected to the second capacitor plate; wherein the first capacitor plate includes a first arm and a second arm that intersect; the second capacitor plate includes a third arm and a fourth arm that intersect; and one of the first arm and the second arm of one of the quantum bits in the array is coupled to one of the third arm and the fourth arm of the adjacent quantum bit. The quantum bits formed by this scheme are convenient for two-dimensional arrangement, and any quantum bit is coupled with the four adjacent quantum bits to achieve connectivity, thereby expanding the number of quantum bits.

Description

Technical Field

[0001] The present application relates to the field of quantum information, in particular to the field of quantum computing technology. In particular, the present application relates to a quantum chip and a method for preparing the same, and a quantum computer. Background Art

[0002] Quantum computers are physical devices that follow the laws of quantum mechanics to perform high-speed mathematical and logical operations, store, and process quantum information. Their key characteristics include rapid operation, robust information processing capabilities, and a wide range of applications. Compared to conventional computers, the greater the amount of information they can process, the more advantageous it is for a quantum computer to perform calculations, ensuring greater accuracy.

[0003] Superconducting quantum computing can utilize micro-nanofabrication technology to fabricate qubits onto substrates, offering superior performance in integration and scalability. In recent years, superconducting quantum computing has experienced rapid development. Current qubit structures often utilize a single grounded capacitor and a superconducting quantum interference device (SQUID) with one end grounded and the other connected to the capacitor. This capacitor is often cross-shaped, facilitating the arrangement of qubits in a one-dimensional chain. However, on a quantum chip, each qubit in a one-dimensional chain is coupled only to its two adjacent qubits, resulting in poor connectivity between qubits and a certain limitation. Invention content

[0004] In order to address the deficiencies in the prior art, the purpose of this application is to provide a quantum chip and a method for preparing the same, and a quantum computer. This application uses a first capacitor plate having an intersecting first arm and a second arm, and a second capacitor plate having an intersecting third arm and a fourth arm, and arranges a structure in which one end of a first superconducting quantum interference device is connected to the first capacitor plate and the other end is connected to the second capacitor plate in an array on a substrate. The array arrangement of this structure can avoid the limitations that exist when using the existing structure of quantum bits to perform a one-dimensional chain arrangement to expand the number of quantum bits.

[0005] One embodiment of the present application provides a quantum chip, comprising:

[0006] A plurality of quantum bits, wherein the plurality of quantum bits are arranged in an array on a substrate, the quantum bits comprising: a first capacitor plate, a second capacitor plate, and a first superconducting quantum interference device, wherein one end of the first superconducting quantum interference device is connected to the first capacitor plate, and the other end of the first superconducting quantum interference device is connected to the second capacitor plate;

[0007] The first capacitor plate includes an intersecting first arm and a second arm; the second capacitor plate includes an intersecting third arm and a fourth arm; and one of the first arm and the second arm of one of the quantum bits arranged in the array is coupled with one of the third arm and the fourth arm of an adjacent quantum bit.

[0008] In one embodiment of the quantum chip as described above, one end of the first superconducting quantum interference device is connected to the intersection of the first arm and the second arm, and the other end is connected to the intersection of the third arm and the fourth arm.

[0009] In the quantum chip as described above, in one embodiment, the first arm and the second arm are orthogonal, and the third arm and the fourth arm are orthogonal.

[0010] In the quantum chip as described above, in one embodiment, the basic unit in which the quantum bits are arranged is a square or a diamond.

[0011] In one embodiment of the quantum chip as described above, a readout resonant cavity and a control signal line coupled to the quantum bit are further formed on the substrate.

[0012] In one embodiment of the quantum chip as described above, the first superconducting quantum interference device includes Josephson junctions connected in parallel, and the Josephson junctions are tunnel junctions, point contacts, or other structures exhibiting the Josephson effect.

[0013] In the quantum chip as described above, in one embodiment, a coupling structure is further formed between the two quantum bits in adjacent positions, and the coupling structure is coupled to one of the first arm and the second arm of one quantum bit, and one of the third arm and the fourth arm of the adjacent quantum bit.

[0014] In the quantum chip as described above, in one embodiment, the frequency of the coupling structure is tunable.

[0015] Another embodiment of the present application provides a method for preparing a quantum chip, wherein the quantum chip includes a plurality of quantum bits, and the plurality of quantum bits are arranged in an array. The preparation method includes the following steps:

[0016] forming a first capacitor plate and a second capacitor plate for each of the qubits on the substrate, wherein the first capacitor plate includes a first arm and a second arm that intersect, the second capacitor plate includes a third arm and a fourth arm that intersect, and one of the first arm and the second arm of one of the qubits in the array arrangement is coupled to one of the third arm and the fourth arm of an adjacent qubit; and

[0017] A first superconducting quantum interference device is formed on the substrate, wherein one end of the first superconducting quantum interference device is connected to the first capacitor plate, and the other end of the first superconducting quantum interference device is connected to the second capacitor plate.

[0018] A third embodiment of the present application provides a quantum computer, which is provided with at least the quantum chip described above or a quantum chip prepared according to the preparation method described above, and a manipulation and reading device connected to the quantum chip.

[0019] Compared with the existing technology, the quantum chip provided by this application has the following beneficial effects:

[0020] The quantum bits on the quantum chip of the present application adopt a first capacitor plate having an intersecting first arm and a second arm, and a second capacitor plate having an intersecting third arm and a fourth arm, and one end of the first superconducting quantum interference device is connected to the first capacitor plate and the other end is connected to the second capacitor plate. The quantum bits of this structure are convenient for two-dimensional arrangement. Two quantum bits in adjacent positions in the two-dimensional array are coupled, that is, any quantum bit is coupled with the four adjacent quantum bits to achieve connectivity, thereby achieving the expansion of the number of quantum bits on the substrate.

[0021] The first superconducting quantum interference device in the present application has no direct physical contact with the ground plane (GND), so the operation of the ground plane (GND) during the production and testing of the quantum chip can avoid damage to the first superconducting quantum interference device 13. In addition, compared with the structure of a single ground capacitor, the physical size of the first capacitor plate and the second capacitor plate forming a capacitor with the ground plane (GND) is larger, and the space reserved for wiring on the substrate is larger when arranged in two dimensions, which can accommodate structures such as the reading resonant cavity and the control signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of quantum bits on a quantum chip in the prior art;

[0023] Figure 2 A schematic diagram of the structure of a quantum chip provided in this application;

[0024] Figure 3 for Figure 2 A magnified schematic diagram of area A in the middle;

[0025] Figure 4 for Figure 2 A magnified schematic diagram of area B in the middle;

[0026] Figure 5 This is a flow chart of a method for preparing a quantum chip provided in this application.

[0027] Description of reference numerals:

[0028] 1-qubit, 2-coupling structure,

[0029] 11-first capacitor plate, 12-second capacitor plate, 13-first superconducting quantum interference device, 14-pulse modulation line, 15-first magnetic flux modulation line, 16-reading resonant cavity,

[0030] 111-first arm, 112-second arm, 121-third arm, 122-fourth arm,

[0031] 21 - a third capacitor plate, 22 - a second superconducting quantum interference device, 23 - a second magnetic flux modulation line. DETAILED DESCRIPTION

[0032] The following detailed description is illustrative only and is not intended to limit the application or use of the embodiments and / or embodiments. In addition, there is no intention to be bound by any express or implied information presented in the previous "background technology" or "summary of the invention" section or "detailed description" section.

[0033] To make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it is obvious that in various cases, one or more embodiments can be practiced without these specific details, and the various embodiments can be combined and referenced with each other without contradiction.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] In addition, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate and / or intervening layers may be present. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer and / or one or more intervening layers may be present. In addition, references to being "on" and "under" various layers may be made based on the accompanying drawings.

[0036] Depending on the different physical systems used to construct quantum bits, the physical implementation methods of quantum bits include superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quantum, photons, etc.

[0037] Superconducting quantum computing is currently the fastest-growing and best approach to implementing solid-state quantum computing. Because the energy level structure of superconducting quantum circuits can be controlled by external electromagnetic signals, the circuit design and customization are highly controllable. At the same time, thanks to their use of existing mature integrated circuit technology, superconducting quantum circuits possess scalability that is unmatched by most quantum physics systems. Currently, the structure of a quantum bit often uses a single grounded capacitor and a superconducting quantum interference device with one end grounded and the other connected to the capacitor. The capacitor is often a cross-type parallel plate capacitor, see [1]. Figure 1 As shown, the cross-shaped capacitor plate C q Surrounded by the ground plane (GND), and the cross-shaped capacitor plate C q There is a gap between the ground plane (GND), and one end of the superconducting quantum interference device squid is connected to the cross-shaped capacitor plate C q , the other end is connected to the ground plane (GND), due to the cross-shaped capacitor plate C q The first end is usually used to connect to the superconducting quantum interference device squid, and the second end is used to couple with the reading resonant cavity. A certain amount of space needs to be reserved near the first and second ends for wiring. For example, space for arranging the xy signal line and the z signal line needs to be reserved near the first end. The cross-shaped capacitor plate C q The other two ends are used to couple with adjacent qubits. Qubits of this structure are convenient for one-dimensional chain arrangement. However, in qubits arranged in a one-dimensional chain on a quantum chip, each qubit is only coupled with the two qubits adjacent to it on the left and right. The connectivity between qubits is not good, and this structure has certain limitations.

[0038] To this end, the present application provides a quantum chip, a preparation method thereof, and a quantum computer to address the deficiencies in the prior art. The quantum bit structure it possesses facilitates two-dimensional arrangement, and two quantum bits in adjacent positions in the two-dimensionally arranged array form a coupling, that is, any quantum bit is coupled with the four adjacent quantum bits to achieve connectivity, thereby achieving an expansion in the number of quantum bits.

[0039] Figure 2 A schematic diagram of the structure of a quantum chip provided in this application.

[0040] Figure 3 for Figure 2 A magnified schematic diagram of area A in the middle.

[0041] Figure 4 for Figure 2 Schematic diagram of the enlarged area B.

[0042] Combine Figure 2 、 Figure 3 and Figure 4 As shown, the present application provides a quantum chip, comprising:

[0043] Multiple qubits 1, wherein the multiple qubits 1 are arranged in an array on a substrate, and the qubits 1 include: a first capacitor plate 11, a second capacitor plate 12, and a first superconducting quantum interference device 13, wherein one end of the first superconducting quantum interference device 13 is connected to the first capacitor plate 11, and the other end is connected to the second capacitor plate 12;

[0044] Among them, the first capacitor plate 11 includes an intersecting first arm 111 and a second arm 112; the second capacitor plate 12 includes an intersecting third arm 121 and a fourth arm 122, that is, in an embodiment of the present application, the first arm 111 and the second arm 112 have the same end, and the third arm 121 and the fourth arm 122 have the same end; one of the first arm 111 and the second arm 112 of one of the quantum bits 1 arranged in the array is coupled with one of the third arm 121 and the fourth arm 122 of the adjacent quantum bit 1.

[0045] In an embodiment of the present application, the quantum bit 1 on the quantum chip adopts a first capacitor plate 11 having an intersecting first arm 111 and a second arm 112, and a second capacitor plate 12 having an intersecting third arm 121 and a fourth arm 122, and one end of the first superconducting quantum interference device 13 is connected to the first capacitor plate 11, and the other end is connected to the second capacitor plate 12. The quantum bit 1 of this structure is convenient for two-dimensional arrangement, and the two quantum bits 1 in adjacent positions in the two-dimensional array are coupled, that is, any quantum bit 1 is coupled with the four adjacent quantum bits 1 to achieve coupling and connectivity, thereby achieving the expansion of the number of quantum bits on the substrate.

[0046] In addition, it should be noted that: in the embodiment of the present application, the first superconducting quantum interference device 13 has no direct physical contact with the ground plane (GND), thereby avoiding damage to the first superconducting quantum interference device 13 caused by operation of the ground plane (GND) during the production and testing of the quantum chip, and compared with the structure of a single capacitor to ground, the physical size of the first capacitor plate 11 and the second capacitor plate 12 forming a capacitor with the ground plane (GND) is larger, and the space reserved for wiring on the substrate is larger when arranged in two dimensions, which can accommodate structures such as the reading resonant cavity and the control signal line.

[0047] See also Figure 2 As shown, for the convenience of describing the embodiments of the present application, Q1, Q2, Q3, and Q4 are used to represent each qubit 1 in a basic unit arranged in an array, wherein each qubit in qubit Q1, qubit Q2, qubit Q3, and qubit Q4 includes a first capacitor plate 11 and a second capacitor plate 12. The first capacitor plate 11 and the second capacitor plate 12 are not directly connected to the ground plane (GND), but have an appropriate gap between them and the ground plane GND. The physical size of the gap is designed and determined according to the performance parameters of the quantum chip. It should be noted that a capacitor C1 is formed between the first capacitor plate 11 and the ground plane (GND), a capacitor C2 is formed between the second capacitor plate 12 and the ground plane (GND), and a capacitor C3 is formed between the first capacitor plate 11 and the second capacitor plate 12. The values of the capacitors C1, C2, and C3 can be calculated and determined based on the performance parameters of the quantum chip, and then the physical sizes of the first capacitor plate 11 and the second capacitor plate 12 can be calculated and determined. From this, the physical sizes of the first arm 111 and the second arm 112, as well as the third arm 121 and the fourth arm 122 can be determined.

[0048] Combine Figure 2 and Figure 1 As shown, in the embodiment of the present application, the anharmonicity of the quantum bit energy level system is Figure 1 When the anharmonicity of the energy level system of the qubit is the same, the capacitors C1, C2 and C3 in the embodiment of the present application are as long as they meet Relative to Figure 1 The structure of the quantum bit in the embodiment of the present application includes multiple capacitors. When designing a quantum chip, the value of each capacitor can be selected according to the actual situation (for example, considering factors such as the size of the reading resonant cavity). For example, when the capacitance C3 is relatively small, C1 = C2 = 2C q , so, relative to Figure 1 The capacitor plates in the embodiment of the present application can expand the physical size of the first capacitor plate and the second capacitor plate, thereby reserving a larger space for wiring.

[0049] In some embodiments, the first capacitor plate 11, the second capacitor plate 12, the first superconducting quantum interference device 13 and the ground plane (GND) are formed on the substrate, and the arrayed quantum bits Q1, quantum bits Q2, quantum bits Q3 and quantum bits Q4 can be surrounded by the ground plane (GND), and the first capacitor plate 11 and the second capacitor plate 12 can be separated from the ground plane (GND) by gaps that expose the substrate surface. In the embodiment of the present application, the substrate can be a dielectric substrate such as silicon or sapphire. In the embodiment of the present application, the quantum bits Q1, quantum bits Q2, quantum bits Q3, quantum bits Q4 and the ground plane (GND) are formed on the silicon substrate. The first capacitor plate 11, the second capacitor plate 12 and the ground plane (GND) can be formed of a superconducting material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature, such as aluminum, niobium or titanium nitride, etc., and are not limited to these materials in specific implementations. Materials that exhibit superconducting properties at a temperature equal to or lower than the critical temperature can be used to form the first capacitor plate 11, the second capacitor plate 12 and the ground plane (GND).

[0050] In order to manufacture the quantum chip in the embodiment of the present application, the quantum bits 1 arranged in an array on the substrate require multiple layers to form a first superconducting quantum interference device 13. In some embodiments, each first superconducting quantum interference device 13 includes two parallel Josephson junctions, each Josephson junction is a stacked structure of a superconducting layer-insulating layer-superconducting layer. A first layer of superconducting material can be deposited to form the first superconducting layer of the Josephson junction, and then oxidized in a portion of the first superconducting layer to form an insulating layer. Then, a second layer of superconducting material can be deposited to form the second superconducting layer of the Josephson junction, thereby obtaining a stacked structure of a superconducting layer-insulating layer-superconducting layer. Exemplarily, in order to facilitate the simultaneous preparation of multiple Josephson junctions on the quantum chip and reduce the difficulty of the process, the Josephson junctions on the quantum chip are all unidirectional structures, that is, the extension directions of the first superconducting layer, insulating layer, and second superconducting layer of the multiple Josephson junctions are the same, and the stacking order of the first superconducting layer, insulating layer, and second superconducting layer of the multiple Josephson junctions is also the same.

[0051] In order to maximize the space reserved on the substrate to meet the wiring requirements (structures such as reading the resonant cavity and regulating the signal line), in some embodiments of the present application, one end of the superconducting quantum interference device 13 is connected to the intersection of the first arm 111 and the second arm 112, and the other end is connected to the intersection of the third arm 121 and the fourth arm 122. Figure 3As shown, the end where the first arm 111 and the second arm 112 intersect is referred to as the first intersection end, and the end where the third arm 121 and the fourth arm 122 intersect is referred to as the second intersection end, then the superconducting quantum interference device 13 is located between the first intersection end and the second intersection end. In some other embodiments of the present application, the first arm 111 and the second arm 112 are orthogonal, and the third arm 121 and the fourth arm 122 are orthogonal. These two forms can be combined with each other as needed.

[0052] In some embodiments of the present application, the basic units in which the quantum bits 1 are arranged in an array are square or diamond-shaped, so that wiring can be performed within the square or diamond-shaped basic units. However, the specific implementation is not limited thereto.

[0053] In some embodiments of the present application, a reading resonant cavity 16 and a control signal line coupled to the quantum bit 1 are also formed on the substrate. The control signal line includes a pulse modulation line 14 and a first magnetic flux modulation line 15. In the present application, the basic unit shape of the array arrangement can be adjusted according to the size of the reading resonant cavity 16 and the control signal line, and the first arm 111 and the second arm 112, the third arm 121 and the fourth arm 122 can be orthogonal or non-orthogonal to obtain sufficient spatial wiring.

[0054] In some embodiments of the present application, the first superconducting quantum interference device 13 includes mutually parallel Josephson junctions, and the mutually parallel Josephson junctions can be composed of two mutually parallel Josephson junctions, that is, a superconducting ring formed by Josephson junctions, and the Josephson junction is a tunnel junction, a point contact, or other structure exhibiting the Josephson effect.

[0055] In some embodiments of the present application, a coupling structure 2 is further formed between two adjacent qubits 1, and the coupling structure 2 is coupled to one of the first arm 111 and the second arm 112 of one qubit 1, and one of the third arm 121 and the fourth arm 122 of the adjacent qubit. For example, Figure 2 、 Figure 3 and Figure 4As shown, the coupling structure 2 is coupled to the second arm 112 of one of the qubits 1 and the third arm 121 of the adjacent qubit. The coupling structure 2 is coupled to both of the qubits 1 to achieve indirect coupling between adjacent qubits 1. In some embodiments, the coupling structure 2 may be a capacitor, a resonant cavity, or a frequency-tunable coupling structure. Exemplarily, the frequency-tunable coupling structure includes a third capacitor plate 21 and a second superconducting quantum interference device 22. One end of the second superconducting quantum interference device 22 is connected to the third capacitor plate 21 and the other end is connected to the ground plane (GND). Thus, a ground capacitance is formed between the third capacitor plate 21 and the ground plane (GND). The ground capacitance is connected in parallel with the second superconducting quantum interference device 22. The second superconducting quantum interference device 22 is a superconducting ring structure composed of a Josephson junction. The use of this form of coupling structure 2 facilitates the regulation of the coupling strength between adjacent qubits 1 and facilitates the execution of a dual quantum logic gate on a quantum chip. In some embodiments, the superconducting ring structure includes at least three Josephson junctions, two of which are connected in parallel to form a ring structure, which is then connected in parallel to another Josephson junction. In the embodiments of the present application, the frequency of the coupling structure can be changed by changing the magnetic field generated by the current flowing through the Josephson junction. This achieves indirect coupling between qubits 1 at adjacent positions in the array arrangement. At the same time, it is also convenient to utilize the coupling structure to achieve regulation of the coupling strength between qubits. The frequency of the coupling structure 2 can be adjusted by applying an external magnetic flux. For example, the magnetic flux of the second superconducting quantum interference device 22 can be adjusted by adjusting the second magnetic flux modulation line 23 to achieve frequency regulation of the coupling structure 2.

[0056] See also Figure 2 As shown, the coupling structure 2 is coupled with the qubit Q1 and the qubit Q4 respectively, thereby generating an indirect coupling between the qubit Q1 and the qubit Q4, and the coupling strength between the qubit Q1 and the qubit Q4 can be adjusted by adjusting the frequency of the coupling structure 2. Specifically, the coupling structure 2 includes a second superconducting quantum interference device 22 and a capacitor connected in parallel with the second superconducting quantum interference device 22. Exemplarily, the coupling structure 2 includes a third capacitor plate 21 and a second superconducting quantum interference device 22, one end of the second superconducting quantum interference device 22 is connected to the third capacitor plate 21, and the other end is connected to the ground plane (GND). Thus, a ground capacitor is formed between the third capacitor plate 21 and the ground plane (GND), and the ground capacitor is connected in parallel with the second superconducting quantum interference device 22; wherein the second superconducting quantum interference device 22 includes two parallel Josephson junctions for adjusting the frequency of the coupling structure 2 by applying an external magnetic flux.

[0057] By applying an external magnetic flux to the qubit Q1 and the qubit Q4, the external magnetic flux directly affects the Josephson energy of the qubit, thereby changing the frequency of the qubit. The frequency of the qubit 1 can then be conveniently adjusted by adjusting the magnetic flux passing through the first superconducting quantum interference device 13, thereby achieving coupling between the coupled qubit Q1 and the qubit Q4.

[0058] Figure 5 This is a flow chart of a method for preparing a quantum chip provided in this application.

[0059] refer to Figure 5 As shown, combined with Figure 2 、 Figure 3 and Figure 4 As shown, an embodiment of the present application further provides a method for preparing a quantum chip, wherein the quantum chip includes a plurality of quantum bits, and the plurality of quantum bits are arranged in an array, and the preparation method includes:

[0060] S501, forming a first capacitor plate and a second capacitor plate for each of the qubits on the substrate, wherein the first capacitor plate includes a first arm and a second arm that intersect, the second capacitor plate includes a third arm and a fourth arm that intersect, and one of the first arm and the second arm of one of the qubits arranged in an array is coupled to one of the third arm and the fourth arm of an adjacent qubit; and

[0061] S502 , forming a superconducting quantum interference device on the substrate, wherein one end of the superconducting quantum interference device is connected to the first capacitor plate, and the other end of the superconducting quantum interference device is connected to the second capacitor plate.

[0062] The manufacture of a quantum chip provided in an embodiment of the present application may require the deposition of one or more materials, such as superconductors, dielectrics and / or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering) or epitaxial techniques and other deposition processes. The preparation process of a quantum chip described in an embodiment of the present application may require the removal of one or more materials from the device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching technology, dry etching technology or lift-off process. Known exposure (lithographic) techniques (e.g., photolithography or electron beam exposure) can be used to pattern the materials forming the circuit elements described herein.

[0063] An embodiment of the present application further provides a quantum computer, which is a superconducting system and is provided with at least the quantum chip described in the embodiment of the present application or the quantum chip prepared by the preparation method described in the embodiment of the present application, and a control and reading device connected to the quantum chip.

[0064] The control and reading device uses the magnetic flux control signal on the first magnetic flux modulation line 15 to adjust the frequency of the quantum bit 1 to the operating frequency. At this time, the quantum state control signal is applied through the pulse modulation line 14 to control the quantum state of the quantum bit 1 in the initial state, and the read resonant cavity 16 is used to read the quantum state of the controlled quantum bit 1. The control and reading device applies a read detection signal (for example, a microwave signal with a frequency of 4-8 GHz) to the read signal transmission line coupled to the read resonant cavity 16, and determines the quantum state of the quantum bit by analyzing the read feedback signal (a signal in response to the read detection signal) output through the read signal transmission line.

[0065] It should be noted that the quantum chip in the superconducting quantum computer described above has a similar structure and exhibits the same beneficial effects as the superconducting quantum chip embodiment described above, and therefore is not further described here. For technical details not disclosed in the superconducting quantum computer embodiment of this application, those skilled in the art are referred to the description of the superconducting structure described above for understanding; to conserve space, they are not further described here.

[0066] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the scope of protection of the present application.

Claims

1. A quantum chip, characterized in that: include: A plurality of quantum bits, wherein the plurality of quantum bits are arranged in an array on a substrate, the quantum bits comprising: a first capacitor plate, a second capacitor plate, and a first superconducting quantum interference device, wherein one end of the first superconducting quantum interference device is connected to the first capacitor plate, and the other end of the first superconducting quantum interference device is connected to the second capacitor plate; The first capacitor plate includes a first arm and a second arm that intersect; the second capacitor plate includes a third arm and a fourth arm that intersect; one of the first arm and the second arm of one of the qubits arranged in the array is coupled to one of the third arm and the fourth arm of an adjacent qubit; The quantum chip further includes a ground plane (GND), the plurality of quantum bits are surrounded by the ground plane (GND), and the first capacitor plate and the second capacitor plate are separated from the ground plane (GND).

2. The quantum chip according to claim 1, characterized in that One end of the first superconducting quantum interference device is connected to the intersection of the first arm and the second arm, and the other end is connected to the intersection of the third arm and the fourth arm.

3. The quantum chip according to claim 1 or 2, characterized in that The first arm and the second arm are orthogonal, and the third arm and the fourth arm are orthogonal.

4. The quantum chip according to claim 1 or 2, characterized in that The basic unit in which the quantum bits are arranged is a square or a diamond.

5. The quantum chip according to claim 1 or 2, characterized in that: A readout resonant cavity and a control signal line coupled to the quantum bit are also formed on the substrate.

6. The quantum chip according to any one of claims 1 or 2, characterized in that The first superconducting quantum interference device includes Josephson junctions connected in parallel, and the Josephson junctions are tunnel junctions, point contacts, or other structures exhibiting the Josephson effect.

7. The quantum chip according to claim 1 or 2, characterized in that A coupling structure is also formed between the two quantum bits at adjacent positions, and the coupling structure is coupled to one of the first arm and the second arm of one quantum bit, and one of the third arm and the fourth arm of the adjacent quantum bit.

8. The quantum chip according to any one of claim 7, characterized in that The frequency of the coupling structure is tunable.

9. A method for preparing a quantum chip, characterized in that: The quantum chip includes a plurality of quantum bits, and the plurality of quantum bits are arranged in an array. The preparation method includes: forming a first capacitor plate and a second capacitor plate for each of the qubits on a substrate, wherein the first capacitor plate includes a first arm and a second arm that intersect, the second capacitor plate includes a third arm and a fourth arm that intersect, and one of the first arm and the second arm of one of the qubits in the array arrangement is coupled to one of the third arm and the fourth arm of an adjacent qubit; and A first superconducting quantum interference device is formed on the substrate, wherein one end of the first superconducting quantum interference device is connected to the first capacitor plate, and the other end of the first superconducting quantum interference device is connected to the second capacitor plate.

10. A quantum computer, characterized in that: The quantum computer is provided with at least the quantum chip according to claims 1 to 8 or the quantum chip prepared by the preparation method according to claim 9, and a control and reading device connected to the quantum chip.

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