Interconnect structure to improve signal integrity within stacked dies

Abstract

Interconnect structures are provided that improve signal integrity within a stack of dies. A device includes a stack of dies. Each die can have a unit stepped conductive path of connection features including through-die via structures and wiring structures. A unit stepped conductive path of one die can be interconnected into another unit stepped conductive path of another die to form one of a plurality of conductive stepped structures through two or more dies. The unit stepped conductive paths can be connected to reduce signal cross-talk between the conductive stepped structures whereby at least some of the conductive stepped structures are connected to transmit electrical signals of the same polarity and are spatially separated in a dimension perpendicular to a major surface of the dies. Methods of manufacturing the device are also disclosed.

Description

Technical Field

[0001] This application generally relates to integrated circuit packaging and methods of manufacturing the same, and more specifically, to integrated circuit packaging comprising stacked dies. Background Technology

[0002] Die stacking is commonly used in off-chip memory applications, such as high-bandwidth memory (HBM), to increase memory capacity and bandwidth. Such off-chip memory applications can include graphics, networking, and supercomputing applications. Stacked dynamic random-access memory (DRAM) dies arranged to provide HBM (e.g., 3D DRAM stacks) can also help reduce or maintain a small form factor and can reduce power consumption in integrated circuit packages for such high-performance applications. Typically, signal paths through the stack use 3D interconnects, including through die via structures (TDVs) and other electrical connection features such as metal bumps and wiring, to form a laddered structure of interconnect cells. However, crosstalk between signal paths formed by TDVs and other electrical connection features can limit the maximum signaling rate through the stack. Some efforts to increase the total bandwidth through stacking include doubling the number and area of ​​TDV signal paths while maintaining the signaling rate. Summary of the Invention

[0003] One aspect of the invention provides an apparatus comprising a stack of dies. Each die may have a unit step conductive path with interconnect features including through-die vias and wiring structures. The unit step conductive path of one die may be interconnected to another unit step conductive path of another die to form one of a plurality of conductive step structures through two or more dies. The unit step conductive paths may be connected to reduce signal crosstalk between conductive step structures, whereby at least some conductive step structures are connected to transmit electrical signals of the same polarity and are spatially separated in a dimension perpendicular to the main surface of the die.

[0004] In another aspect, a method for manufacturing an apparatus is disclosed. The method includes providing dies, each die arranged to have a unit step conductive path, the unit step conductive path including through-die via structures and wiring structures. The method includes stacking dies to form a die stack, wherein a unit step conductive path of one die is interconnected with another unit step conductive path of another die to form one of a plurality of conductive step structures through two or more dies. The method includes arranging the unit step conductive paths to reduce signal crosstalk between conductive step structures, whereby at least some conductive steps carrying signals of the same polarity are spatially separated in a dimension perpendicular to the main surface of the die. Attached Figure Description

[0005] The following description is provided with reference to the accompanying drawings, in which:

[0006] Figure 1A A three-dimensional perspective view of the die stack is shown, in which there is a checkerboard TDV staircase connection array in the die stack;

[0007] Figure 1B Showing with Figure 1A The cross-sectional view of TDV in the die stack corresponding to the column view section 1B-1B shown;

[0008] Figure 1C Showing with Figure 1A The cross-sectional view of TDV in the die stack corresponding to the column view section 1C-1C shown;

[0009] Figure 1D Detailed cross-sectional views of two TDVs, which interconnect two bare dies in a stack, are given, corresponding to... Figure 1B View area D shown;

[0010] Figure 1E Showing with Figure 1B The 3D perspective view of the TDV array portion in the stack corresponding to the view area E shown;

[0011] Figure 1F-1I A 3D perspective view is displayed, highlighting the... Figure 1A-1C The selected signal path corresponding to the selected die shown in the image;

[0012] Figure 2A A 3D perspective view of a die stack with an interleaved TDV ladder connection array is shown.

[0013] Figure 2B Showing with Figure 2A The cross-sectional view of the TDV in the bare die stack corresponding to the column view section 2B-2B shown;

[0014] Figure 2C Showing with Figure 2A The cross-sectional view of TDV in the bare die stack corresponding to the column view section 2C-2C shown;

[0015] Figure 2D Showing included Figure 2B A 3D perspective view of a portion of the TDV array in the stack, including the view area D shown;

[0016] Figure 2E-2H A 3D perspective view is displayed, with its highlights and... Figure 2A-2C The selected signal path corresponding to the selected die shown in the image;

[0017] Figure 3A and3B The diagram shows a cross-sectional view of the TDV array in the die stack portion, which is similar to... Figure 1B and 1C The column view shown is shown, but the TDV stepped connection array moves and offsets between adjacent TDV columns;

[0018] Figure 4A A three-dimensional perspective view of the die stack is shown, featuring a combined checkerboard pattern and an interlaced TDV ladder connection array within the stack;

[0019] Figure 4B Showing with Figure 4A The cross-sectional view of the TDV in the bare die stack corresponding to the column view section 4B-4B shown;

[0020] Figure 4C Showing with Figure 4A The cross-sectional view of TDV in the die stack corresponding to section 4C-4C of the cylindrical view shown;

[0021] Figure 4D Showing included Figure 4B A 3D perspective view of a portion of the TDV array in the stack, including the view area D shown;

[0022] Figure 4E-4H A three-dimensional perspective view is displayed, highlighting the... Figures 4A-4C The selected signal path corresponds to the selected die shown.

[0023] Figure 5A A three-dimensional perspective view of the die stack is shown, in which there are combined serpentine and interlaced checkerboard-shaped TDV ladder connection arrays;

[0024] Figure 5B Showing with Figure 5A The column view section 5B-5B shown is a cross-sectional view of the TDV in the bare die stack corresponding to the column view section 5B-5B shown;

[0025] Figure 5C Showing with Figure 5A The column view section 5C-5C shown is a cross-sectional view of the TDV in the die stack corresponding to the bare die stack;

[0026] Figure 5D Showing included Figure 5B A 3D perspective view of a portion of the TDV array in the stack, including the view area D shown;

[0027] Figure 5E-5H A 3D perspective view is displayed, with its highlights and... Figures 5A-5C The selected signal path corresponding to the selected die shown in the image;

[0028] Figure 6AA three-dimensional perspective view of the die stack is shown, with a curved TDV ladder connection array in the stack;

[0029] Figure 6B Showing with Figure 6A The column view section 6B-6B shown is a cross-sectional view of the TDV in the bare die stack corresponding to the column view section 6B-6B shown;

[0030] Figure 6C Showing with Figure 6A The column view section 6C-6C shown is a cross-sectional view of the TDV in the die stack corresponding to the die stack;

[0031] Figure 6D Showing included Figure 6B A 3D perspective view of a portion of the TDV array in the stack, including the view area D shown.

[0032] Figure 6E-6H A 3D perspective view is displayed, with its highlights and... Figures 6A-6C The selected signal path corresponding to the selected die shown in the image;

[0033] Figure 7A A three-dimensional perspective view of a die stack with a twisted-pair TDV ladder connection array is shown.

[0034] Figure 7B The image shown is related to Figure 7A The cross-sectional view of TDV in the die stack corresponding to the column view section 7B-7B shown;

[0035] Figure 7C Showing with Figure 7A The column view section 7C-7C shown is a cross-sectional view of the TDV in the die stack corresponding to the bare die stack;

[0036] Figure 7D Showing included Figure 7B A 3D perspective view of a portion of the TDV array in the stack, including the view area D shown;

[0037] Figure 7E-7H A 3D perspective view is displayed, highlighting the... Figures 7A-7C The selected signal path corresponding to the selected die shown;

[0038] Figure 8A A three-dimensional perspective view of the die stack is shown, with a combined twisted pair and straight-through TDV ladder connection array in the stack;

[0039] Figure 8B Showing with Figure 8A The column view section 8B-8B shown is a cross-sectional view of the TDV in the bare die stack corresponding to the column view section 8B-8B shown;

[0040] Figure 8C Showing with Figure 8A The column view section 8C-8C shown is a cross-sectional view of the TDV in the die stack corresponding to the bare die stack;

[0041] Figure 8D Showing included Figure 8B A 3D perspective view of a portion of the TDV array in the stack, including the view area D shown;

[0042] Figure 8E-8H A 3D perspective view is displayed, with its highlights and Figures 8A-8C The selected signal path corresponding to the selected die shown in the image;

[0043] Figure 9 Cross-sectional views of an example IC package of this disclosure are shown, including... Figure 1A-8H Any embodiment of bare die stacking disclosed in the context of the present invention;

[0044] Figure 10 A flowchart illustrating an example embodiment of a method for manufacturing an IC package according to the principles of this disclosure is shown, including, as in... Figure 1A-8H Any stacked embodiments disclosed in the context of [the document]; and

[0045] Figure 11 Example simulation results of far-end crosstalk simulation for a curved and twisted-pair TDV ladder connection array arrangement compared to a connection array arrangement with non-interlaced and straight wiring structures. Detailed Implementation

[0046] We have developed a pattern of cell-staircase interconnects to form TDV staircase interconnect arrays, which reduce insertion loss and crosstalk within die stacks, thereby improving signal integrity and facilitating the use of high signal rates in integrated circuit packages such as HBM. Our TDV staircase interconnect array arrangement helps reduce insertion loss and crosstalk by providing shielding in three-dimensional space, particularly by enhancing the vertical shielding between TDV staircases formed by different dies in the stack. As further disclosed herein, some of these TDV staircase arrangements reduce insertion loss and crosstalk by shifting and offsetting, meandering, bending, or twisting TDV staircase pairs in the array, and / or by providing crosstalk cancellation and shielding to center the input-output connections within the TDV staircase interconnect array, as further disclosed herein.

[0047] These embodiments contrast with some previous efforts to reduce crosstalk by simply stacking adjacent columns of parallel and linear cell ladder structures to carry signals of different polarities to provide some shielding against signal crosstalk between adjacent ladder structures within a die. However, since ladders with the same signal polarity are stacked directly on top of each other, significant crosstalk occurs between signals passing through adjacent dies when these signals pass through the die stack in parallel. Furthermore, the link operations of each layer can be independent of each other. For example, consider a victim line connected in the write direction (e.g., processor to memory) and an attacker line connected in the read direction (e.g., memory to processor). The attenuated victim signal will be affected by near-end crosstalk from full-swing signals from transmitters in adjacent module layers. The crosstalk accumulated in this conventional stacking design can be significant and ultimately limit the maximum signaling rate in HBMs using such stacked memory systems.

[0048] The TDV ladder interconnect array disclosed in this paper demonstrates a remarkable advantage in improving channel signal integrity by reducing insertion loss and crosstalk through shielding in three spatial dimensions, positioning portions of the signal on the other side of the I / O circuitry, and using bent and twisted-pair structures. As further disclosed herein, these benefits were not apparent until verified by our simulation experiments. Also not apparent was the ease and inexpensiveness of constructing the TDV ladder interconnect array arrangement disclosed herein, for example, compared to conventional die stacking, where each die has the same unit ladder structure pattern, forming a set of parallel and straight unit ladder structures when stacked and interconnected, as described above. Using this identical unit ladder structure pattern in conventional die stacking allows for the use of the same die design for each layer in the stack, simplifying manufacturing and reducing manufacturing costs. For the TDV ladder arrangement disclosed herein, non-identical patterns of unit ladder structures in adjacent dies are used to achieve reduced crosstalk. However, since some dies exhibit repeating unit ladder structure patterns, it is often possible to use only one or a few die unit ladder structure patterns to form a stack. For example, dies with the same pattern can be rotated (e.g., 180 degrees every other layer in some embodiments) as part of forming a die stack, thereby reducing manufacturing costs by not having to provide a unique pattern for each die in the stack with a unit ladder structure.

[0049] One aspect of the invention is an apparatus comprising a stack of bare dies. Figure 1A-8H Various embodiments of a device 100 including stacked dies 102 (e.g., dies 105…112) according to the invention are shown, and, Figure 9 This illustrates how any such stacked embodiment can be included in a device arranged as or including an integrated circuit package 900.

[0050] Continue to refer to Figure 1A-8H For any of the embodiments of device 100, each die has a unit stepped conductive path with interconnect features, which includes via structures and wiring structures (e.g., Figure 1D Conductive paths 115a and 115b include a TDV structure 117 and a wiring structure 118. A unit step conductive path (e.g., 115a) of one die (e.g., die 105) is interconnected to another unit step conductive path (e.g., 115b) of another die (e.g., die 106) to form multiple conductive step structures (e.g., conductive step structures 120a…120d) through two or more dies. The unit step conductive paths 115a and 115b are connected to reduce signal crosstalk between conductive step structures, wherein at least some conductive step structures are connected to transmit electrical signals of the same polarity (e.g., signal 122a transmitted via conductive step structures 120a and 120b), which are spatially separated in a dimension (e.g., z) perpendicular to the main surface of the die (e.g., main surface 124).

[0051] As used herein, spatial separation means that at least some connection features (e.g., TDV structures 117a, 117b and / or wiring structures 118a, 118b) forming the unit step conductive path 115 of the conductive step structure 120, which carry signals of the same polarity (e.g., one of signal 122a or signal 122b), are separated by at least one die, and in some embodiments, are also separated by pillars.

[0052] As used herein, the term conductivity refers to the conduction of electrical signals (e.g., signals 122a, 122b) that are connected as part of the transmission of electrical signals (e.g., digital or analog signals) in a device (e.g., an integrated circuit device), such as a high-bandwidth DRAM memory device, as is familiar to those skilled in the art.

[0053] As used herein, the term interconnect or connection refers to the electrical connection features between component structures of stepped conductive paths (e.g., paths 115a, 115b...) used for transmitting electrical signals (e.g., signals 122a, 122b...).

[0054] As used herein, the term signal crosstalk refers to the reduction in signal integrity transmitted through a conductive ladder structure due to interference from other different signals simultaneously transmitted through adjacent conductive ladder structures.

[0055] Here, when adjacent conductive ladder structures transmit signals and the disturbed path is quiet / disabled, signal crosstalk can be determined by measuring the signal power at either end of the disturbed path. For example, crosstalk can be measured by measuring the change in signal power from one end of the conductive ladder structure to the other, where the target conductive ladder structure (the disturbed line) is connected in the write direction, and adjacent surrounding conductive ladder structures (the intruding lines) are connected in the write direction; or, the disturbed line is connected in the write direction and the intruding line is connected in the read direction; or, the average of both. For example, far-end crosstalk may occur when the victim and attacker are connected in the same direction (i.e., write / write or read / read), while near-end crosstalk may occur when the victim and attacker are connected in opposite directions (i.e., write / read or read / write). As disclosed herein, embodiments of the device can reduce both forms of crosstalk, and in some embodiments particularly reduce near-end crosstalk, which can be a more common form of crosstalk in some DRAM stack arrangements.

[0056] Electrical connection features may include a TDV structure 117, which may be via a through-silicon via (TSV) structure when using a DRAM silicon die, or via a germanium via (TGV) structure when using DRAM germanium or other DRAM die substrates familiar to those skilled in the art. Electrical connection features may include a wiring structure 118, which may include any combination of microbumps 125, connection pads 127, or metal wire wiring 129 located on the die (e.g., die 105 or die 106). Figure 1D On the front side 130 or rear side 132 of the die, when interconnected with a through-hole structure (e.g., structure 117a, 117b), a unit step conductive path 115 is formed.

[0057] like Figure 1A-8H As shown, spatial separation between conductive ladder structures 120a and 120b connected to transmit electrical signals 122a of the same polarity can be achieved through various embodiments of forming TDV arrays in a stack.

[0058] Figure 1A-1I Various aspects of an embodiment of a die stack 102 having a checkerboard-shaped TDV ladder connection array in a stack are illustrated. As shown, conductive ladder structures can be spatially separated by alternating conductive ladder structures (e.g., conductive ladder structures 120a, 120b) connected to transmit electrical signals as a first electrical signal (e.g., signal 122a) including a data-bearing signal (“signal”), and when conductive ladder structures (e.g., conductive ladder structures 120c, 120d) are connected to transmit electrical signals as a second electrical signal 122b, the first and second electrical signals 122a, 122b have opposite polarities.

[0059] In some such embodiments, the second electrical signal 122b is a data-bearing signal, while in other embodiments, the second electrical signal 122b includes a return path signal. As used herein, the term return path signal refers to any voltage that is part of a return path, such as a ground connection or power connection (e.g., a voltage VDD applied to the drain), which is typically represented as "GND" in the figures.

[0060] In some such embodiments, each stepped conductive path (e.g., path 115a, 115b...) is connected at one end (e.g., end 140) to an input-output circuit 142 (IO CKT) located on and near the edge of one of the dies (e.g., near or close to edge 145 of die 112), and at the other end (e.g., end 147) to a different die (e.g., metal wire wiring 129 of die 105), as an input-output (IO) wiring structure.

[0061] In some such embodiments, each stepped conductive path (e.g., path 115a, 115b…) connected to the transmission of the first electrical signal 122a can be surrounded in all three dimensions (x, y, and z) by stepped conductive paths (e.g., path 115a, 115b…) connected to the transmission of the second electrical signal 122b. For example, in some embodiments, each unit step carrying the first signal can be surrounded in all directions (above, below, left, right, front, and rear) by unit step steps carrying the second signal, such as return paths (e.g., VDD or GND). In some embodiments, this creates return paths for signals following the entire 3D path of the stack in all three dimensions to reduce return path impedance while providing shielding to avoid crosstalk due to other signals. This arrangement can produce a ground signal ground (GSG) bump array pattern maintained by horizontal metal wiring and vertical TDV / microbump transitions.

[0062] In some embodiments, this checkerboard layout can be implemented using two distinct DRAM dies (e.g., one for even-numbered layers and one for odd-numbered layers), fabricated using different masks for either the on-chip (top) or back-chip metal layers. Alternatively, the cell ladder structure for both signal and return paths can be identical. This allows stacking to be achieved using a single DRAM die, at the cost of increased return path impedance from a signal integrity and power integrity perspective, since the ground ladder can no longer be connected to the on-chip power distribution network.

[0063] Figure 2A-2HVarious aspects of an embodiment of a die stack 102 having an interleaved TDV ladder connection array in a stack are described. As shown, the conductive ladder structures (e.g., conductive ladder structures 120a, 120b) are spatially positioned on one side of the die relative to the I / O circuit 142 located at a central position (e.g., central position 210) by positioning portions of one or more ladder conductive paths (e.g., paths 115a, 115b...) for one or more different ladder structures (e.g., conductive ladder structures 120b) on the other side of the die relative to the I / O circuit 142.

[0064] In some such embodiments, the conductive stair structure (e.g., conductive stair structure 120a, 120b) provides two or more vertically stacked through-die via structures (e.g., through-die via structures 117a and 117b) such that the wiring structure of one of the stair conductive paths (e.g., the metal wire wiring 129a of stair conductive path 115a) is spatially separated from the wiring structure of another stair conductive path (e.g., the metal wire wiring 129a on die 107 from the metal wire wiring 129b on die 105) by one or more dies (e.g., die 106 separating the metal wire wiring 129a on die 107 from the metal wire wiring 129b on die 105).

[0065] This staggered arrangement reduces signal routing density in the Z direction, so that the horizontal signal routing above and below the affected lines is now spaced two DRAM die layers apart, which increases vertical spacing to reduce crosstalk. This structure also reduces the total horizontal distance signals must travel through the on-chip metal, thus reducing insertion loss. Placing the I / O circuitry at the center of the bump array also allows for symmetrical clock distribution and memory access to on-chip memory cells.

[0066] Some embodiments of this staggered arrangement can be implemented using two different DRAM die layers stacked in an alternating pattern (e.g., ABAB pattern). The different dies can be fabricated using different metal masks for the metal layers on the die or the back metal. In some embodiments, wiring on one side of the I / O circuitry can use vertical transitions (e.g., TDV only with microbumps) only on a specific die layer, while the other side of the I / O circuitry can further include horizontal metal wiring, and this pattern can be swapped every other layer. Due to this alternating pattern, stacking can also be achieved using a single DRAM die rotated 180 degrees per layer. The compatibility of this structure with die rotation allows stacking to be implemented using the same DRAM dies across all layers, thereby reducing the number of fabrication masks required.

[0067] Figures 3A-3B Various aspects of an embodiment of a die stack 102 having a shifted and offset TDV ladder connection array in a stack are shown. Figures 3A-3B The cross-sectional view shown is similar to Figure 2B and 2C The cylindrical view shown is for clarity, but only three blank pieces 105, 106, and 107 are depicted. Figure 3A As shown, conductive stair structures (e.g., conductive stair structures 120a, 120b, 120c) are spatially separated by providing unit stair conductive paths (e.g., path 115c), which form part of a first conductive stair structure (e.g., conductive stair structure 120a) such that one of the dies (e.g., die 106) moves horizontally relative to an adjacent unit stair conductive path (e.g., path 115d or 115e in die 105 or 107) in an adjacent die, forming part of a second adjacent structure in a conductive stair structure (e.g., conductive stair structures 120b or 120c, respectively), such that a through-die via structure (e.g., through-die via structure 117a) of the first conductive stair structure 120a in die 106 is vertically offset due to the horizontal movement of the conductive stair structure within die 106 relative to adjacent dies 105, 107. For example, TDVs 117a, 117b, and 117c, due to horizontal displacement in the through-hole structure position, will not directly stack on each other in adjacent dies, resulting in displacement in adjacent conductive step structures (e.g., conductive step structures 120a, 120b, and 120c in dies 105-107).

[0068] In some such embodiments, such as Figure 3B As shown, for a conductive staircase structure (e.g., staircase structure 120a), the unit staircase conductive path (e.g., path 115c) has no metal wiring 129, and the through-die via structure of the unit staircase conductive path (e.g., through-die via structure 117a of path 115c) interconnects the wiring structure of the unit staircase conductive path in the second adjacent die (e.g., metal wiring 129c of path 115f in die 107) to the wiring structure of the unit staircase conductive path in the third adjacent die (e.g., metal wiring 129d of path 115g in die 105).

[0069] Figures 4A-4HVarious aspects of an embodiment of a die stack 102 having a combined checkerboard and staggered TDV ladder connection array in a stack are illustrated. As shown, the conductive ladder structures are spatially separated in the following ways: 1) one or more portions of one or more ladder conductive paths (e.g., paths 115a, 115b…) of one or more conductive ladder structures (e.g., ladder structure 120a) are positioned on one side of the die relative to the centrally located (e.g., central location 210) circuit 142, and one or more portions of different ladder conductive paths (e.g., paths 115a, 115b…) of one or more different conductive ladder structures (e.g., ladder structure 120b) are positioned on the opposite side of the die relative to the input / output circuit 142; 2) two or more vertically stacked through-die via structures (e.g., through-die via structures 117a, 117b…) are provided, such that the wiring of one of the ladder conductive paths… The structure (e.g., metal wire wiring 129a of stepped conductive path 115a) is separated from the wiring structure of another conductive stepped structure 120 (e.g., metal wire wiring 129b of adjacent stepped conductive path 115b) by one or more dies (e.g., die 106 separating wiring structure 118a on die 107 from wiring structure 118b on die 105); and 3) the conductive stepped structure (e.g., stepped structure 120b) connected to transmit a first electrical signal 122a as a data carrier signal (“signal”) is alternated with the conductive stepped structure (e.g., stepped structure 120c) connected to transmit an electrical signal as a second electrical signal 122b (which is a ground carrier signal (“GND”), the first and second electrical signals 122a, 122b having opposite polarities.

[0070] and Figure 1A -I and Figure 2A Similar to the TDV staircase connection array shown in -H, combining checkerboard and interleaved TDV staircase connection arrays can further improve signal integrity. Similar to interleaved TDV staircase connection arrays, I / O circuitry can be located at the center of the DRAM die, with signals routed from both sides of the I / O, where vertical transitions through the stack can pass through two DRAM die layers (e.g., two TDVs plus two microbumps). In some embodiments, three-dimensional shielding can be achieved within the stack by ensuring that the second signal of the carrying staircase is positioned above, below, to the left, to the right, in front of, and behind the first signal of all carrying staircases, for example, by employing an interleaved pattern and swapping the first signal of the carrying staircase with the second signal of the adjacent carrying staircase every other one (e.g., in some embodiments, return path, VDD / GND). Embodiments of this arrangement can reduce return path impedance, increase isolation between intruder signals in all three dimensions, and produce a similar effect to... Figure 1A-1I The chessboard array of the stacked embodiments disclosed herein.

[0071] The combined checkerboard and staggered arrangements are compatible with a variety of manufacturing methods and require four unique DRAM dies (e.g., an ABCD pattern). These four dies can be fabricated using four different fab metal or back metal masks. Alternatively, if the unit step structure of the signal and return paths is the same, two metal masks can be used, but at the cost of increased return path impedance. In these embodiments, two unique DRAM dies (A, B, AR, BR) can be used in combination to utilize die rotation, reducing the number of fabrication masks and cost.

[0072] Figures 5A-5H Various aspects of an embodiment of a die stack 102 having a combined array of serpentine and staggered TDV ladder connections are illustrated. As shown, the conductive ladder structure passes through the stack 102 between at least two different cross-sections (e.g., cross-sections across dimension y) (e.g., ladder structures 120a, 120b in cross-sections 5B-5B and 5C-5C). Figure 5D A portion of at least one conductive step structure (e.g., step structure 120a connecting "Die 4 signal" to "Die 4 IO") is spatially separated, wherein a first unit step conductive path 115a in a first cross-section of an odd-numbered die (e.g., die 105) includes a wiring structure that connects to a second unit step conductive path 115b in a second cross-section of an adjacent even-numbered die (e.g., die 106), such that the unit step conductive paths sequentially and repeatedly alternate between the first and second cross-sections to form conductive step structure 120a.

[0073] In some such embodiments, stepped conductive paths 115a, 115b are connected to transmit an electrical signal as a first electrical signal 122a and are surrounded in all three dimensions (x, y, and z dimensions) by conductive stepped structures (e.g., stepped structures 120c, 120d), which are connected to transmit an electrical signal as a second electrical signal 122b, the first and second electrical signals 122a, 122b having opposite polarities.

[0074] In some such embodiments, the first electrical signal 122a may include a first data bearer signal of a first polarity, and the second electrical signal 122b may include a second data bearer signal of a second opposite polarity.

[0075] In some such embodiments, there are branch electrical connections between at least two second-unit stepped conductive paths 115b (e.g., Figure 5D The branch electrical connection 510 between the conductive staircase structures 120d and 120c enables the second unit staircase conductive path 115b to carry two different second signals, including two different second data carrying signals.

[0076] In other embodiments, the second signal may be a return path signal. In some such embodiments, where the second signal is a return path signal connected as a ground signal, there may be a series of branch connections interconnecting two or more or all of the second unit stepped conductive paths 115b (e.g., a series of branch connections electrically interconnecting two or more or all of the conductive stepped structures 120c, 120d), which are connected to carry a second data bearer signal as a common ground signal, for example, by providing an interconnected ground structure within the stack, such as a ground grid.

[0077] Similarly, for such Figure 1A-8H In any embodiment of the stack 102 shown, when the second electrical signal is a return path signal connected as a ground signal, any number of branch connections can interconnect two or more or all of the second unit conductive ladder structures 120c, 120d in the stack to provide an interconnected ground structure within the stack 102.

[0078] In this arrangement, conductive staircase structures intertwine with the first and second signals throughout the stack, providing shielding for the horizontal metal lines and the vertical TDV / microbump transitions. In some such embodiments, a combined checkerboard staggered arrangement is used ( Figures 4A-4H In contrast, due to the serpentine conductive staircase structure of long metal lines, insertion loss may be greater, which in turn may increase path inductance.

[0079] Some embodiments of combined serpentine and staggered TDV ladder interconnect arrays can be implemented using two distinct DRAM layers (using two chip metal or back metal masks) or using a single DRAM die, with die rotation on each layer in the stack.

[0080] Some embodiments of combined serpentine and staggered TDV ladder interconnect arrays can be implemented using two distinct DRAM layers (using two chip metal or back metal masks) and a single DRAM die, with the die rotated on each layer in the stack.

[0081] Figures 6A-6HVarious aspects of an embodiment of a die stack 102 having a curved TDV ladder connection array with a differential signal scheme in the stack are shown. As shown, conductive ladder structures 120 are spatially separated by portions passing through the stack between at least a first, second, and third cross-section (e.g., cross-sections through dimension y) (e.g., ladder structures 120a and 120b alternating in cross-sections 6B-6B, 6C-6C, and a third adjacent cross-section (not shown)). These portions (e.g., ladder structure 120a connecting “Die 3 signal position” to “Die 3 10”, ladder structure 120b connecting “Die 4 10” to “Die 4 signal position”, ladder structure 120c connecting “Die 3 signal negative” to “Die 3 10”, and ladder structure 120d connecting “Die 4 10” to “Die 4 signal negative”) The interconnection of the electrical signal 122a as the first electrical signal includes a wiring structure in which a unit step conductive path 115a from an odd-numbered die (e.g., die 105, 107, etc.) in the first cross section alternates with a diagonally adjacent unit step conductive path 115b in the second cross section of an adjacent even-numbered die (e.g., die 106, 108, etc.) to form the first of the conductive step structures 120a. The interconnection of the electrical signal 122b as the second electrical signal includes a wiring structure in which a unit step conductive path 115b from an even-numbered die (e.g., die 106, 108, etc.) in the third cross section alternates with one of the diagonally adjacent unit step conductive paths 115b in the second cross section of an odd-numbered die (e.g., die 105, 107, etc.) to form the second of the conductive step structures 120b.

[0082] In some such embodiments, at least some stepped conductive paths (e.g., stepped conductive path 115b) connected to transmit the first electrical signal 122a are surrounded by stepped conductive paths (e.g., stepped conductive paths 115c, 115d) in all three dimensions (x, y, and z dimensions), which are connected to transmit the second electrical signal 122b, the first and second electrical signals 122a and 122b having opposite polarities.

[0083] For differential signaling schemes, each of the first and second signals can be alternately bent left and right in the stepped structure of each die layer, as shown in Figures 6A-6H. This results in the first and second signal pairs above and below the victim signal pairs bending in opposite directions (left or right) on any given die layer. This bending reduces the coupling area between the signal pairs above and below each other, thereby reducing crosstalk.

[0084] Some embodiments of curved TDV ladder interconnect arrays can implement even and odd layers using two different dies, which can be fabricated using multiple fab metal or back metal masks. This arrangement is also compatible with single-ended signaling, but may accumulate more crosstalk, for example, compared to a checkerboard TDV ladder interconnect array arrangement. Figure 1A-1I ).

[0085] Figures 7A-7H Various aspects of an embodiment of a die stack 102 having a twisted-pair TDV ladder connection array with a differential signal scheme in the stack are shown. As shown, the conductive ladder structure 120 provides at least one portion of the conductive ladder structure (e.g., ladder structure 120a, which connects “die 3 signal position” to “die 3 10”, ladder structure 120b, which connects “die 4 10” to “die 4 signal position”, ladder structure 120c, which connects “die 3 signal negative” to “die 3 10”, ladder structure 120d, which connects “die 4 10” to “die 4 signal negative”) spatially separated (e.g., ladder structures 120a, 120b alternating in cross sections 7B-7B and 7C-7C) across the stack at least in the first and second cross sections (e.g., cross sections of dimension y). The interconnection of the electrical signal 122a as the first electrical signal includes a wiring structure that alternates from a unit stepped conductive path 115a connected to one of the odd-numbered dies (e.g., dies 105, 107) in the first cross-section to a diagonally adjacent unit stepped conductive path 115b in the second cross-section of an adjacent even-numbered die (e.g., dies 106, 108, etc.) to form the first of conductive stepped structures (e.g., conductive stepped structures 120a, 120b). The interconnection of the electrical signal 122b as the second electrical signal includes a wiring structure that, in cross-section 7B-7B, alternates from a unit stepped conductive path 115a connected to one of the odd-numbered dies (e.g., dies 105, 107, etc.) in the second group of unit stepped conductive paths to form a conductive stepped structure (e.g., conductive stepped structures 120a, 120b). The unit step conductive path 115a alternates with one diagonally adjacent to the unit step conductive path 115b in a cross section such as 7C-7C of an even-numbered die (e.g., die 106, 108, etc.) to form a second conductive step structure (e.g., conductive step structures 120c, 120d). At least some wiring structures of the first set of unit step conductive paths 115a, 115b form the first conductive step structure (e.g., conductive step structure 120a, 120b), and at least some adjacent wiring structures of the wiring structures of the second set of unit step conductive paths 115a, 115b that form the second conductive step structure (e.g., conductive step structures 120c, 120d) interweave.

[0086] In some such embodiments, at least some stepped conductive paths (e.g., stepped conductive path 120b) connected to transmit the first electrical signal 122a are surrounded by stepped conductive paths (e.g., stepped conductive paths 120c, 120d) in all three dimensions (x, y, and z dimensions), which are connected to transmit the second electrical signal 122b, the first and second electrical signals 122a and 122b having opposite polarities.

[0087] In some such embodiments, at least some wiring structures of the first set of unit step conductive paths 115a, 115b forming the first conductive staircase structure do not intersect with at least some wiring structures of the second set of unit step conductive paths 115a, 115b forming the second conductive staircase structure, where 115b forms the second conductive staircase structure. However, in some embodiments, at least some conductive staircase structures may be interwoven. Figures 8A-8H Various aspects of such an embodiment of a die stack 102 with combined twisted pairs and a straight-path TDV ladder connection array having a differential signal scheme in the stack are shown. As illustrated, in some such embodiments, for an even number of dies, the wiring structure of the first group of cell ladder conductive paths 115a, 115b does not intersect with at least some wiring structures (e.g., as shown in the figure). Figures 8A-8H (As shown in the straight wiring diagram), for the second group of odd-numbered bare dies, the wiring structure unit has stepped conductive paths 115c and 115d, and the wiring structure is crisscrossed.

[0088] Similar to a zigzag TDV ladder connection array ( Figures 6A-6H ), twisted pair ( Figures 7A-7H ) or a combination of twisted pair and straight-through TDV ladder connection array ( Figures 8A-8H This can be used for differential signaling. The use of a twisted-pair structure increases crosstalk immunity because the induced current in the two tracks becomes common-mode. This can be used with... Figures 8A-8H Various combinations of straight and twisted-pair signal pair routing, as shown, are used to achieve this, where, for example, signals to odd-numbered layers remain straight-routed throughout the stack. Furthermore, opposite types of routing (straight or twisted-pair) can be used to route adjacent signal pairs on the same layer (i.e., to the left and right sides of each signal pair shown) to further reduce crosstalk. This combination of twisted-pair and straight routing further improves crosstalk immunity due to the polarity reversal of the next nearest intruder signal. This arrangement can be implemented using multiple metal masks for the fab metal or back metal layers.

[0089] Figure 9 A cross-sectional view of an exemplary IC packaging device 100 of the present invention is shown, including... Figure 1A-8HThe context of any embodiment of the die set 102 disclosed herein. As shown, in some embodiments, the stack of dies 102 is arranged as a dynamic random access memory (DRAM) stack, wherein each die is arranged as a DRAM die having input-output circuitry connected to the die (e.g., ...). Figure 1A-8H The device comprises multiple DRAM cells (circuit 142). In some embodiments, the device is arranged as an integrated circuit package including a package substrate 910 (e.g., a printed circuit board) and a stack 102 located on the substrate 910. Some such embodiments include a processor 920 (e.g., a graphics processing unit (GPU die) located on the package substrate 910. Some such embodiments include an interposer substrate 930 having a set of wires 940 connecting the interconnecting processor 910 and the DRAM cells of the stack 102.

[0090] Figure 10 The flowchart illustrates an example embodiment of a method 1000 for manufacturing an IC package according to the principles of this disclosure, including any packaging embodiment, such as in... Figure 1A-9 It is disclosed in the context of [the context].

[0091] Continue to refer to Figure 1A-8H ,like Figure 10 As shown, method 1000 includes providing dies (e.g., dies 105…112), each die being arranged to have unit step conductive paths (paths 115a, 115b) including through-die via structures (e.g., structures 117a, 117b…) and wiring structures 118a, 129a (e.g., step 1010). Method 1000 includes arranging the unit step conductive paths (e.g., paths 115a, 115b…) to reduce signal crosstalk between conductive step structures 120 (e.g., step 1020). At least some of the conductive steps 120 carrying signals of the same polarity (e.g., signal 122a) are spatially separated in a dimension (z-axis) perpendicular to the die main surface 124. As part of arranging the unit step conductive paths in step 1030, a Figure 1A-8H Any TDV array structure described in the context of the above. Method 1000 includes stacking dies to form a die stack 102 (e.g., step 1030). As part of forming the die stack in step 1030, a cell step conductive path (e.g., path 115a) of one die (e.g., die 105) and another cell step conductive path (e.g., path 115b) of another die (e.g., die 106) form one of a plurality of conductive step structures 120 through two or more dies (e.g., dies 105, 106).

[0092] In some such embodiments, as disclosed elsewhere herein, as part of arranging the unit step conductive paths in step 1020, each die may have the same arrangement of the unit step conductive paths (e.g., paths 115a, 115b), and the stacking of dies may further include rotating the even-numbered dies 180 degrees relative to the odd-numbered dies before the unit step conductive paths (e.g., 105, 106) of the interconnected dies are arranged to form a conductive step structure (e.g., a typical conductive step structure 120).

[0093] experiment

[0094] Various embodiments of the TDV ladder-connected array arrangements disclosed herein were simulated using three-dimensional electromagnetic field simulators (e.g., HFSS and Q3D, Ansys, Fort Carnegie Hall, Pennsylvania, USA) to model and compare the signal integrity of the arrangements. Simulated embodiments included non-interlaced checkerboard (...) Figure 1A-1I ), intersecting straight ( Figure 2A-2H Combining serpentine and interlaced chessboards ( Figures 5A-5H ) as well as combination boards and interlacing ( Figures 4A-4H TDV ladder connection array and traditional (“original”) non-interlaced and straight TDV ladder connection array.

[0095] For single-ended architectures, a 24-signal model corresponding to 3 columns and 8 die layers was simulated. Each architecture was implemented using each compatible fabrication method: multiple back metal masks (BSM), multiple lower metal masks (FAB), combinations of multiple back metal and lower metal masks (FAB / BSM), and die rotation (DIE). The number of metal masks used in each architecture was two or four. However, in other embodiments, such as when die rotation is used, only one metal mask may be required. Table 1 shows the simulated signal parameter values ​​at a 4 GHz Nyquist frequency, including insertion loss (IL), power and far-end crosstalk (PSFEXT: victim and attacker in the write direction connection) and power and near-end crosstalk (PSNEXT: victim in the write direction connection, attacker in the read direction connection). The differences between IL and accumulated crosstalk (FEXT and NEXT) are also shown, as well as the improvement in IL-NEXT (ΔNEXT) compared to a conventional TDV architecture (non-interleaved, straight-wire style). These simulated arrangements are estimated to suppress worst-case crosstalk in the range of 2.4 dB to 17.3 dB.

[0096]

[0097] For differential signal schemes in stacked arrangements, three simulated columns of the signal path were further modeled for the worst-case scenario. Figure 11The simulation results show the cumulative crosstalk (PSFEXT) within stacks with different arrangements over a frequency range. The simulation shows that the cumulative crosstalk of the bent and twisted-pair TDV step-connected array arrangement is reduced compared to the original TDV step-connected array.

[0098] Those skilled in the art will understand that other and further additions, deletions, substitutions and modifications can be made to the described embodiments.

Claims

1. An apparatus comprising stacking bare dies, comprising: The dies are stacked, and each die has a unit stepped conductive path with interconnect features, including through-die via structures and wiring structures, wherein: The unit step conductive path of one die in the die is interconnected with another unit step conductive path of another die in the die, so as to form one of a plurality of conductive step structures through two or more dies, and The unit stepped conductive paths are connected to reduce signal crosstalk between the conductive stepped structures, such that at least some of the conductive stepped structures are connected to transmit electrical signals of the same polarity, and are spatially separated in a dimension perpendicular to the main surface of the die. The conductive staircase structure is spatially separated by alternating conductive staircase structures that transmit the electrical signal as a first electrical signal including a data-bearing signal and conductive staircase structures that transmit the electrical signal as a second electrical signal, the first electrical signal and the second electrical signal having opposite polarities.

2. The apparatus of claim 1, wherein each of the unit stepped conductive paths connected to transmit the first electrical signal is surrounded in all three dimensions by the unit stepped conductive path connected to transmit the second electrical signal.

3. The apparatus of claim 1, wherein one end of each of the unit stepped conductive paths is connected to an input-output circuit located on an edge therein and near one of the dies, and the other end is connected to the opposite end located on a different one of the dies, as an input-output wiring structure connection.

4. The apparatus of claim 1, wherein the conductive stair structures are spatially separated by positioning portions of one or more of the unit stair conductive paths of one or more of the conductive stair structures on one side relative to the die of the centrally located input-output circuit, and by positioning portions of different one or more of the unit stair conductive paths of one or more different conductive stair structures on opposite sides relative to the die of the input-output circuit.

5. The apparatus according to claim 4, wherein, By providing two or more vertically stacked through-die via structures, the conductive staircase structures are spatially separated, such that the wiring structure of one unit staircase conductive path is separated from the wiring structure of another unit staircase conductive path by one or more of the dies.

6. The apparatus according to claim 1, wherein, By providing the unit step conductive path forming part of a first conductive step structure in a conductive step structure, the conductive step structure is spatially separated so that one die of the die is horizontally moved relative to the adjacent unit step conductive path in the unit step conductive path of the adjacent die forming part of a second adjacent conductive step structure of the conductive step structure, such that the through-die via structure of the first conductive step structure in the one die is vertically offset from the through-die via structure of the adjacent die of the second adjacent conductive step structure.

7. The apparatus of claim 6, wherein for the conductive staircase structure, the unit staircase conductive path has no metal wiring, and the through-die via structure of the unit staircase conductive path interconnects the wiring structure of the unit staircase conductive path of the second adjacent die in the die to the wiring structure of the unit staircase conductive path of the third adjacent die in the die.

8. The apparatus of claim 1, wherein the conductive staircase structure is spatially separated in the following manner: A portion of one or more of the unit step conductive paths for one or more of the conductive step structures is positioned on one side of the die relative to the centrally located input-output circuit, and a portion of one or more of the unit step conductive paths for one or more different conductive step structures is positioned on the opposite side of the die relative to the input-output circuit. Provide two or more vertically stacked through-die via structures, such that the wiring structure of one unit step conductive path in the unit step conductive path is separated from the wiring structure of another unit step conductive path in the unit step conductive path through one or more dies, and The conductive staircase structure connected to a first electrical signal for transmitting the electrical signal as a data carrier signal alternates with the conductive staircase structure connected to a second electrical signal for transmitting the electrical signal as a ground carrier signal, wherein the first electrical signal and the second electrical signal have opposite polarities.

9. The apparatus of claim 1, wherein the conductive step structure is spatially separated by providing at least one portion of the conductive step structure between at least two different cross sections passing through the die stack, wherein a first unit step conductive path of a unit step conductive path in a first cross section of one of the odd-numbered dies includes the wiring structure connecting to a second unit step conductive path of a unit step conductive path in a second cross section of one of the adjacent even-numbered dies, such that the unit step conductive paths sequentially and repeatedly alternate between the first cross section and the second cross section to form the conductive step structure.

10. The apparatus of claim 9, wherein the unit step conductive path is connected to transmit the electrical signal as a first electrical signal, the unit step conductive path being surrounded in all three dimensions by the unit step conductive path connected to transmit the electrical signal as a second electrical signal, the first electrical signal and the second electrical signal having opposite polarities.

11. The apparatus of claim 1, wherein the conductive stair structure is spatially separated by providing a portion of at least one of the conductive stair structures between at least a first cross-section, a second cross-section, and a third cross-section of the die stack, wherein: The interconnection of the electrical signal, serving as the first electrical signal, includes a wiring structure that alternates between the unit step conductive paths of one of the odd-numbered dies in the first cross-section and diagonally adjacent unit step conductive paths in the second cross-section of an adjacent even-numbered die, to form a first conductive step structure in the conductive step structure. The interconnection of the electrical signal as the second electrical signal includes a wiring structure that alternates from the unit step conductive path of one of the even-numbered dies in the third cross section to one of the diagonally adjacent unit step conductive paths in the second cross section of one of the odd-numbered dies in the dies, to form a second conductive step structure.

12. The apparatus of claim 1, wherein the conductive stair structure is spatially separated by providing a portion of at least one conductive stair structure between at least a first cross-section and a second cross-section passing through the die stack, wherein: The interconnection of the electrical signal, serving as the first electrical signal, includes a wiring structure that alternates from a first set of unit step conductive paths. This first set of unit step conductive paths includes the unit step conductive path of one of the odd-numbered dies in the first cross-section, which is connected to the diagonally adjacent unit step conductive paths of the conductive paths in the second cross-section of an adjacent even-numbered die, to form the first conductive step structure in the conductive step structure. The interconnection of the electrical signal as the second electrical signal includes a wiring structure that alternates from a second set of unit step conductive paths from one of the odd-numbered dies in the first cross-section, which is connected to a diagonally adjacent unit step conductive path in the unit step conductive paths of one of the even-numbered dies in the second cross-section, to form a second conductive step structure in the conductive step structure. At least some of the wiring structures of the first group of unit step conductive paths forming the first conductive step structure are interleaved with at least some of the adjacent wiring structures of the second group of unit step conductive paths forming the second conductive step structure.

13. The apparatus of claim 12, wherein at least some of the wiring structures of the first set of unit step conductive paths forming the first conductive step structure do not intersect with at least some of the wiring structures of the second set of unit step conductive paths forming the second conductive step structure.

14. The apparatus of claim 1, wherein the die stack is arranged as a dynamic random access memory (DRAM) stack, wherein each die is arranged as a DRAM die, the DRAM die having a plurality of DRAM cells connected to input-output circuitry connected to the die.

15. The apparatus of claim 1, wherein the apparatus is arranged as an integrated circuit packaging apparatus, the integrated circuit packaging apparatus including a packaging substrate, the die stack being located on the substrate.

16. The apparatus of claim 15, further comprising a processor located on the package substrate.

17. The apparatus of claim 16, further comprising an interposer substrate having a set of conductive lines connected to interconnect the processor and the DRAM cells of the die stack.

18. A method of manufacturing an apparatus, comprising: A bare die is provided, each of which is arranged to have a unit stepped conductive path, the unit stepped conductive path including a through-die via structure and a wiring structure; The unit step conductive paths are arranged to reduce signal crosstalk between conductive step structures, so that at least some of the conductive step structures carrying electrical signals of the same polarity are spatially separated in a dimension perpendicular to the main surface of the die. and The dies are stacked to form a die stack, wherein the cell step conductive path of one die is interconnected with another cell step conductive path of another die to form one of a plurality of conductive step structures through two or more dies. The conductive staircase structure is spatially separated by alternating conductive staircase structures that transmit the electrical signal as a first electrical signal including a data-bearing signal and conductive staircase structures that transmit the electrical signal as a second electrical signal, the first electrical signal and the second electrical signal having opposite polarities.

19. The method of claim 18, wherein each of the dies has the same arrangement of the cell step conductive paths, and the stacking of the dies further comprises rotating the even-numbered dies 180 degrees relative to the odd-numbered dies before interconnecting the cell step conductive paths of the dies to form the conductive step structure.

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