Calibration apparatus, method and radar for pipelined analog-to-digital conversion circuitry

Abstract

A calibration apparatus, method, and radar for a pipelined analog-to-digital converter (ADC) circuit are disclosed. The pipelined ADC circuit includes a first-stage conversion module and a cascaded back-end conversion module having at least one first-stage conversion module. The first-stage conversion module includes a sub-ADC unit composed of at least one comparator. The calibration method includes: inputting a test analog signal to the first-stage conversion module; acquiring a jump output voltage output by the first-stage conversion module corresponding to a jump signal at the output of the comparator; determining, based on the jump output voltage, whether a preset reference threshold of the comparator deviates from a theoretical reference threshold; and adjusting the preset comparison threshold of the comparator when a deviation is determined. This method enables aperture error calibration of a pipelined ADC circuit without a sample-and-hold structure, improving conversion accuracy.

Description

Technical Field

[0001] This specification relates to the field of integrated circuit technology, and more particularly to a calibration device, method, and radar for pipelined analog-to-digital converter circuits. Background Technology

[0002] Many physical quantities in nature (such as velocity, pressure, temperature, sound, etc.) change continuously over time and take continuous values ​​in amplitude. Such continuously changing physical quantities are called analog quantities, and the signals that represent analog quantities are called analog signals.

[0003] Another type of physical quantity corresponding to analog quantities is called digital quantities. These are values ​​acquired at a series of discrete moments, and their magnitudes and increases / decreases are integer multiples of the quantization. In other words, they are a series of signals that are discrete in both time and value. Signals representing digital quantities are called digital signals.

[0004] With the widespread use of computers, most electronic systems use computers to process signals. However, computers cannot directly process analog signals, only digital signals. Therefore, it is necessary to convert analog signals into digital signals, which led to the development of analog-to-digital (A / D) conversion technology. The circuit that converts analog signals into digital signals can be called an analog-to-digital converter circuit.

[0005] The analog-to-digital conversion process mainly includes: 1) In the sampling stage, the analog signal is sampled to obtain a time-discrete, amplitude-continuous analog sampled signal. The amplitude continuity means that the amplitude is not quantized and is still the same as the amplitude of the analog signal; 2) In the holding stage, the amplitude of the analog signal (i.e., the sampled value) when switching from the sampling stage to the holding stage is held to obtain a time-discrete analog holding signal with the sampled value as the amplitude. A quantization unit is selected, the sampled value is divided by the quantization unit and the integer is taken to realize the signal quantization (digitization) and obtain a time-discrete and numerically discrete digital quantity; 3) The digital quantity is encoded to obtain the corresponding digital code and form a digital signal.

[0006] To facilitate computer use, binary encoding is generally used to obtain a digital code of a certain number of bits. The number of bits in the digital code is usually used to represent the number of bits in the digital signal, such as a 10-bit digital signal. The more bits a digital signal uses, the more accurately it reflects the analog signal.

[0007] In the quantization process of analog-to-digital conversion, multiple comparators are typically used to compare the analog hold signal to obtain the quantization result. Therefore, with other parameters remaining constant, the more comparators there are, the higher the quantization accuracy and the more accurate the output digital signal. However, due to limitations in space layout, cost, performance, and other factors, simply increasing the number of comparators cannot yield a digital signal with more bits.

[0008] For example, to convert an analog signal into a 10-bit digital signal, in principle, one could use 1023 comparators to output 1024 digital values, and then encode these digital values ​​to obtain a 10-bit digital signal. However, a 10-bit digital signal would require thousands of comparators, making this approach impractical in real-world scenarios.

[0009] To obtain digital signals with more bits per second using a given number of comparators, the structure of analog-to-digital (ADC) circuits has been optimized, resulting in various types such as successive approximation, integrating, voltage-to-frequency conversion, hierarchical, and pipelined ADCs. Successive approximation, integrating, and voltage-to-frequency conversion ADCs are mainly used in low-to-medium speed, low-precision ADC scenarios. Hierarchical and pipelined ADCs, on the other hand, can be used in faster, higher-precision ADC scenarios, such as high-speed transient signal processing.

[0010] The pipelined analog-to-digital converter (ADC) circuit contains a hierarchical quantization structure, using multiple low-precision conversion modules to perform sampling, quantization, and encoding conversions. Each conversion module utilizes a small number of comparators to achieve fast analog-to-digital conversion at that level, making it the mainstream choice for implementing high-speed, high-precision ADC circuits.

[0011] In some pipelined analog-to-digital converter (ADC) circuits, the sample is first obtained through a sample-and-hold amplifier (SHA), and then the sampled and held signal is input to each stage of the conversion module for analog-to-digital conversion. Except for the final stage, each stage of the conversion module includes a sub-ADC and a gain digital-to-analog converter (MDAC). However, the SHA typically consumes a lot of power. To save power, some pipelined ADC circuits omit the SHA and directly input the analog signal to the first stage of the conversion module.

[0012] However, a major problem with this type of pipelined ADC that does not include SHA is that, due to the fluctuation of analog signals over time, there is a bandwidth mismatch in the sampling paths of the Sub-ADC and the MDAC within the first-stage conversion module, resulting in aperture error. Aperture error causes a shift in the position of the transition level on the transmission curve, potentially increasing the corresponding output voltage range and affecting the accuracy of the pipelined analog-to-digital converter circuit. Summary of the Invention

[0013] In view of this, embodiments of this specification provide a calibration apparatus, method, and radar for pipelined analog-to-digital converter circuits, which can calibrate the aperture error of pipelined analog-to-digital converter circuits without sample-and-hold structures, thereby improving the accuracy of pipelined analog-to-digital converter circuits.

[0014] First, this invention provides a calibration method for a pipelined analog-to-digital converter (ADC) circuit, wherein the pipelined ADC circuit includes a first-stage conversion module and a cascaded back-end conversion module having at least one first-stage conversion module, the first-stage conversion module including a sub-ADC unit composed of at least one comparator; the calibration method includes:

[0015] Input a test simulation signal into the first-stage conversion module;

[0016] Obtain the jump output voltage output by the first-stage conversion module that corresponds to the jump signal at the output of the comparator;

[0017] Based on the jump output voltage, determine whether the comparator's preset reference threshold deviates from the theoretical reference threshold;

[0018] When it is determined that there is a deviation between the preset reference threshold of the comparator and the theoretical reference threshold, the preset comparison threshold of the comparator is adjusted.

[0019] Optionally, determining whether the preset reference threshold of the comparator deviates from the theoretical reference threshold based on the jump output voltage further includes:

[0020] The jump digital information corresponding to the first-stage conversion module is determined based on the jump output voltage;

[0021] Based on the jump digital information, it is determined whether the measurement output range of the first-level conversion module is consistent with the theoretical output range, and when they are inconsistent, it is determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold.

[0022] The step of determining the jump digital information corresponding to the first-stage conversion module based on the jump output voltage further includes:

[0023] Obtain the digital residual information corresponding to the jump output voltage, and the test digital information output by the back-end conversion module corresponding to the test analog signal;

[0024] Based on the digital residual information and the test digital information, the jump digital information corresponding to the first-level conversion module is determined.

[0025] Optionally, determining whether there is a deviation in the preset threshold of the comparator based on the jump output voltage further includes:

[0026] The jump output voltage is compared with the preset output voltage threshold. When the two are inconsistent, it is determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold.

[0027] Optionally, adjusting the preset comparison threshold of the comparator when it is determined that there is a deviation between the preset reference threshold of the comparator and the theoretical reference threshold includes:

[0028] When it is determined that the preset reference threshold of the comparator is less than the corresponding theoretical reference threshold, the preset comparison threshold of the comparator is increased.

[0029] When it is determined that the preset reference threshold of the comparator is greater than the corresponding theoretical reference threshold, the preset comparison threshold of the comparator is controlled to decrease.

[0030] This invention also provides a calibration device for a pipelined analog-to-digital converter (ADC) circuit, wherein the pipelined ADC circuit includes a first-stage conversion module and a cascaded back-end conversion module having at least one first-stage conversion module, the first-stage conversion module including a sub-ADC unit composed of at least one comparator; the calibration device includes:

[0031] A signal generation module is adapted to generate test analog signals and input them to the first-stage conversion module in the pipelined analog-to-digital conversion circuit.

[0032] The deviation determination module is adapted to acquire the jump output voltage output by the first-stage conversion module corresponding to the jump signal at the output terminal of the comparator; and to determine whether the preset reference threshold of the comparator deviates from the theoretical reference threshold based on the jump output voltage.

[0033] The deviation adjustment module is adapted to adjust the preset comparison threshold of the comparator when the deviation determination module determines that there is a deviation between the preset reference threshold of the comparator and the theoretical reference threshold.

[0034] Optionally, the deviation determination module includes:

[0035] The digital information acquisition unit is adapted to determine the jump digital information corresponding to the first-stage conversion module based on the jump output voltage;

[0036] The deviation calculation unit is adapted to determine whether the measurement output range of the first-level conversion module is consistent with the theoretical output range based on the jump digital information obtained by the digital information acquisition unit, and when the two are inconsistent, to determine that the preset reference threshold of the comparator has a deviation from the theoretical reference threshold.

[0037] Optionally, the digital information acquisition unit includes: a digital calculation subunit, adapted to acquire digital residual information corresponding to the jump output voltage, and test digital information output by the back-end conversion module corresponding to the test analog signal; and to determine the jump digital information corresponding to the first-stage conversion module based on the digital residual information and the test digital information.

[0038] Optionally, the deviation determination module includes: a comparison unit, adapted to compare the jump output voltage with a preset output voltage threshold, and output a corresponding feedback signal based on the comparison result, wherein when the two are inconsistent, it is determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold.

[0039] Optionally, the deviation adjustment module is adapted to control the increase of the preset comparison threshold of the comparator when it is determined that the preset reference threshold of the comparator is less than the corresponding theoretical reference threshold; and to control the decrease of the preset comparison reference threshold of the comparator when it is determined that the preset reference threshold of the comparator is greater than the corresponding theoretical reference threshold.

[0040] Optionally, the comparator includes:

[0041] The pre-amplification component has a first input terminal adapted to input a corresponding preset reference threshold, a second input terminal adapted to input the test simulation signal, a first output terminal adapted to output the amplified signal corresponding to the preset reference threshold, and a second output terminal adapted to output the amplified signal corresponding to the test simulation signal.

[0042] The latching component has a first input terminal coupled to the first output terminal of the pre-amplification component; its second input terminal is coupled to the second output terminal of the pre-amplification component; and its output terminal is adapted to output a comparison result based on the size relationship between the first input terminal and the second input terminal.

[0043] Optionally, the deviation adjustment module includes:

[0044] A charge storage unit group includes multiple first charge storage units and multiple second charge storage units, wherein: each first charge storage unit is coupled between a first output terminal of the pre-amplification component and ground, and each second charge storage unit is coupled between a second output terminal of the pre-amplification component and ground;

[0045] The switch unit group includes a plurality of first switches and a plurality of second switches, wherein: each first switch is coupled between a corresponding first charge storage unit and ground, and each second switch is coupled between a corresponding second charge storage unit and ground;

[0046] A switch control unit is adapted to, when determining that a preset reference threshold of the comparator is less than a theoretical reference threshold of the comparator, turn on a first switch between some or all of the first charge storage units coupled to the first output terminal of the pre-amplification component and ground; and to, when determining that a preset reference threshold of the comparator is less than a theoretical reference threshold of the corresponding comparator, turn on a second switch between some or all of the second charge storage units coupled to the first output terminal of the pre-amplification component and ground.

[0047] This invention also provides a radar, comprising: a detection device, an analog-to-digital conversion circuit, and a calibration device as described in any of the foregoing embodiments; wherein:

[0048] The detection device is adapted to acquire echo signals and output analog signals to be processed to the analog-to-digital conversion circuit.

[0049] The analog-to-digital conversion circuit is adapted to perform analog-to-digital conversion on the analog signal to be processed by the detection device or the test analog signal of the calibration device; it includes a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a first-stage conversion module, a back-end conversion module having at least one stage conversion module and a digital computing module cascaded therewith;

[0050] The calibration device is adapted to calibrate the aperture error of the pipelined analog-to-digital converter circuit by inputting a test analog signal to the pipelined analog-to-digital converter circuit.

[0051] Optionally, the radar further includes a control device, adapted to control the calibration device to calibrate the pipelined analog-to-digital conversion circuit after the radar is powered on, and to control the calibration device to end the calibration after the calibration end conditions are met, and to cause the analog-to-digital conversion circuit to perform analog-to-digital conversion processing on the analog signal to be processed.

[0052] For a pipelined analog-to-digital converter (ADC) circuit without a sample-and-hold structure, the calibration scheme of this invention involves inputting a test analog signal into its first-stage conversion module and obtaining the jump output voltage corresponding to the jump signal at the comparator output terminal of the sub-ADC unit in the first-stage conversion module. Then, based on the jump output voltage, it is determined whether the preset reference threshold of the comparator deviates from the theoretical reference threshold. When it is determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold, the preset comparison threshold of the comparator is adjusted. Through this calibration scheme, it is possible to accurately identify whether there is a deviation in the preset reference threshold of the comparator in the sub-ADC unit of the first-stage conversion module of the pipelined ADC circuit without a sample-and-hold structure, and adjust it accordingly. This avoids the shifting of the transfer curve jump level of the first-stage conversion module, thus reducing the influence of aperture error and improving the accuracy of the pipelined ADC circuit without a sample-and-hold structure. Attached Figure Description

[0053] To more clearly illustrate the technical solutions of the embodiments of this specification, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 A schematic diagram of the framework structure of a prior art pipeline-type analog-to-digital converter circuit is shown.

[0055] Figure 2 A schematic diagram of the framework structure of another prior art pipeline-type analog-to-digital converter circuit is shown.

[0056] Figure 3 A kind of Figure 1 and Figure 2 A schematic diagram of the sub-analog-to-digital converter unit used in the process.

[0057] Figure 4 A schematic diagram of the transmission characteristic curve of the conversion module in an embodiment of the present invention is shown.

[0058] Figure 5 A schematic diagram of a calibration device for a pipelined analog-to-digital converter circuit is shown in an embodiment of the present invention.

[0059] Figure 6a A schematic diagram of the circuit structure of a ramp generator used in an embodiment of the present invention is shown.

[0060] Figure 6b yes Figure 6aThe waveform of the analog signal output by the ramp generator circuit shown is shown.

[0061] Figure 7a A schematic diagram of a deviation determination module in an embodiment of the present invention is shown.

[0062] Figure 7b A schematic diagram of another deviation determination module in an embodiment of the present invention is shown.

[0063] Figure 8 This diagram illustrates a calibration scenario for a pipelined analog-to-digital converter circuit according to an embodiment of the present invention.

[0064] Figure 9 A schematic diagram of a deviation adjustment module in an embodiment of the present invention is shown.

[0065] Figure 10 A flowchart of a calibration method for a pipelined analog-to-digital converter circuit is shown in an embodiment of the present invention.

[0066] Figure 11 A flowchart illustrating a method for determining whether a preset reference threshold of a comparator has a deviation is shown in an embodiment of the present invention.

[0067] Figure 12 A schematic diagram of a seven-stage pipelined analog-to-digital converter circuit is shown.

[0068] Figure 13 A schematic diagram of the structure of a radar according to an embodiment of the present invention is shown. Detailed Implementation

[0069] To enable those skilled in the art to better understand and implement the solutions provided in this specification, the following is a schematic description of existing pipeline-type analog-to-digital converter circuits in conjunction with the accompanying drawings and specific application scenarios.

[0070] Reference Figure 1 The diagram shown illustrates the structure of a pipelined analog-to-digital converter circuit in the prior art. In practical applications, such as... Figure 1 As shown, the pipelined analog-to-digital converter circuit P0 includes: a clock generation sub-circuit 01, a bandgap reference sub-circuit 02, a sample-and-hold amplifier module 03, N cascaded conversion modules Stage1 to StageN, and a digital calculation module 04. The following is a brief description of each component.

[0071] The clock generation sub-circuit 01 serves as the clock source for the pipelined analog-to-digital converter circuit P0. It is adapted to generate multiple non-overlapping clock signals and provide multiple non-overlapping clock signals to the sample-and-hold amplifier module 03 and the stage conversion modules Stage1 to StageN respectively, thereby using different timing to control the devices in the sample-and-hold amplifier module 03 and the stage conversion modules to work alternately.

[0072] The bandgap reference sub-circuit 02 serves as the reference signal source for the pipelined analog-to-digital converter P0. It is adapted to generate reference current and reference voltage, and provides the generated reference current and reference voltage to the sample-and-hold amplifier module 03 and the conversion modules Stage1 to StageN, respectively.

[0073] Specifically, in an optional example, such as Figure 1 As shown, the bandgap reference sub-circuit 02 may include: a bandgap generation module 021, a reference current generation module 022, and a reference voltage generation module 023. Wherein:

[0074] The bandgap generation module 021, as the bandgap reference source of the pipelined analog-to-digital converter circuit P0, is suitable for providing temperature-insensitive reference electrical signals, such as reference voltage signals and reference current signals.

[0075] The reference current generation module 022 serves as the reference current source for the pipelined analog-to-digital converter circuit P0. It is adapted to generate a reference current based on the reference electrical signal and provide the generated reference current to the sample-and-hold amplifier module 03 and the conversion modules Stage1 to StageN respectively.

[0076] The reference voltage generation module 023 serves as the reference voltage source for the pipelined analog-to-digital converter circuit P0. It is adapted to generate a reference voltage based on a reference electrical signal and provide the generated reference voltage to the sample-and-hold amplifier module 03 and the conversion modules Stage1 to StageN, respectively.

[0077] Furthermore, since the reference voltage is typically used to drive the capacitor, and the capacitor has charging and discharging times, in order to enable the capacitor to perform efficient charging and discharging operations and provide accurate setup time for the reference voltage generation module 023, the bandgap reference sub-circuit 02 may also include a reference voltage buffer module 024, adapted to buffer the reference voltage output by the reference voltage generation module 023. Specifically, the reference voltage buffer module 024 may include a reference buffer.

[0078] Furthermore, since pipeline-type analog-to-digital converter circuits typically require two reference voltages of different levels, such as a positive reference voltage and a negative reference voltage, the reference voltage generation module 023 can generate two reference voltages of different levels by level shifting. Thus, the reference voltage buffer module 024 can ensure the accuracy and settling time of the reference voltage output by the reference voltage generation module 023.

[0079] The sample-and-hold amplifier module 03 is adapted to sample the analog signal input to the pipelined analog-to-digital converter circuit P0 to obtain an analog hold signal VC, and stably maintain the amplitude of the analog hold signal VC until the next sampling stage arrives for the next sampling. This ensures that no time deviation occurs when the subsequent stage-by-stage conversion modules Stage1 to StageN process the signal. The sample-and-hold amplifier module 03 may include a sample-and-hold amplifier (SHA).

[0080] It is understood that the above sampling implementation method can be set according to specific scenarios and needs, and this specification does not limit it.

[0081] The N cascaded conversion modules, Stage 1 to Stage N, can have their levels set according to the cascading order of each module, such as... Figure 1 In this diagram, Stage 1 is the first level of conversion module, Stage 2 is the second level, and so on. Among the conversion modules Stage 1 through Stage N, the first-level conversion module Stage 1 through the (N-1)th-level conversion module Stage N-1 uses the same internal structure. The description will take the first-level conversion module Stage 1 as an example, such as... Figure 1 As shown, the conversion module Stage1 may include: a sub-ADC unit 11 and a gain digital-to-analog converter (MDAC) unit 12.

[0082] The sub-analog-to-digital converter 11 can sample, quantize, and encode the received input signal to obtain the first-level thermometer code DS1, and output the first-level thermometer code DS1 to the gain digital-to-analog converter 12 and the digital calculation module 04, respectively. The number of thermometer codes that the sub-analog-to-digital converter 11 can generate is related to the precision of the sub-analog-to-digital converter 11. For example, if the precision of the sub-analog-to-digital converter 11 is x bits, then the sub-analog-to-digital converter 11 can generate 2... x -1 digit thermometer code.

[0083] The gain digital-to-analog converter unit 12 may specifically include: an arithmetic unit 121, a sub-digital-to-analog converter unit (Sub-DAC) 122, and an amplification unit 123. Typically, the precision of the gain digital-to-analog converter unit 12 is the same as that of the sub-DAC unit 11. For example, if the precision of the sub-DAC unit 11 is x bits, then the precision of the gain digital-to-analog converter unit 12 is also typically x bits.

[0084] Specifically, the sub-digital-to-analog converter 122 is adapted to receive the first-stage thermometer code DS1 output by the sub-analog-to-digital converter 11, convert the first-stage thermometer code DS1 into a corresponding first-stage analog component, and output it to the arithmetic unit 121. The arithmetic unit 121 is adapted to receive the analog hold signal VC output by the sample-and-hold amplifier module and the first-stage analog component output by the sub-analog-to-digital converter 11, subtract the first-stage analog component from the analog hold signal VC to obtain the calculation result, and output the calculation result to the amplification unit 123. The amplification unit 123 is adapted to receive the calculation result output by the arithmetic unit 121, amplify the calculation result to obtain a first-stage analog residual signal VR1 with the analog residual as the amplitude, and output it to the second-stage conversion module Stage2. The amplification unit can be an operational transconductance amplifier (OTA).

[0085] The conversion modules Stage2 to StageN-1 also include sub-analog-to-digital conversion units and gain digital-to-analog conversion units. For details on their structure, function, and working principle, please refer to the relevant description of the conversion module Stage1 above. They will not be repeated here.

[0086] Therefore, based on the received input signal (i.e., the signal output by the previous conversion module), the conversion modules Stage2 to StageN-1 can obtain the corresponding level of thermometer code and analog residual signal, and output the corresponding level of thermometer code to the digital calculation module 04, and output the corresponding level of analog residual signal to the next-level conversion module. For details, please refer to... Figure 1 The conversion module Stage2 outputs the second-level thermometer code DS2 to the digital calculation module 04, and then to the next-level conversion module ( Figure 1 (Not shown in the image) The second-level analog residual signal VR2 is output. Similarly, the conversion module StageN-1 outputs the N-1 level thermometer code DSN-1 to the digital calculation module 04, and outputs the N-1 level analog residual signal VRN-1 to the next-level conversion module StageN.

[0087] For the Nth stage conversion module, since it is the last of the N cascaded conversion modules, stage N can consist only of sub-analog-to-digital conversion units. Figure 1 (Not shown in the image), based on the analog residual signal output by the N-1th stage conversion module StageN-1, the Nth stage thermometer code DSN is output to the digital calculation module 04.

[0088] It should be noted that the number of digits of the thermometer code output by each of the conversion modules Stage1 to StageN can be set according to specific scenarios and requirements. Each conversion module can output thermometer codes with the same number of digits or thermometer codes with different numbers of digits. This manual does not impose specific restrictions on this.

[0089] The digital calculation module 04 is adapted to add the thermometer codes output by each level of the conversion module in a staggered manner according to the level, thereby aligning the thermometer codes obtained by different conversion modules at different times in time and performing binary conversion to obtain binary output codes. The number of output codes generated by the digital calculation module 04 is related to the precision of the digital calculation module 04. For example, if the precision of the digital calculation module 04 is m bits, then the digital calculation module 04 can generate 2... m -1 type of output code. Furthermore, the accuracy of the digital calculation module 04 can characterize the accuracy of the pipelined analog-to-digital converter circuit P0.

[0090] However, because sample-and-hold modules typically consume significant power, some pipelined analog-to-digital converters omit them to save power, directly inputting the analog signal to the first-stage conversion module. For example... Figure 2 The diagram shown is a schematic of a pipelined analog-to-digital converter circuit without a sample-and-hold module. It includes a pipelined analog-to-digital converter circuit P1. Except for the absence of the sample-and-hold amplifier module 03, the other structures, connections between modules, and operating principles can be referenced. Figure 1 The pipeline-type analog-to-digital converter circuit P0 shown will not be described in detail here.

[0091] After introducing the framework of existing pipelined analog-to-digital converter circuits, the following specific embodiments will be used to illustrate the specific hardware structure and connection relationship of the sub-analog-to-digital converter unit and the gain digital-to-analog converter unit.

[0092] It should be noted that the sub-analog-to-digital converter (ADC) and gain ADC units in the following examples are only used to illustrate problems existing in the prior art. In practical applications, the conversion modules Stage 1 to Stage N may include sub-analog-to-digital converters and gain ADC units of the following types, or sub-analog-to-digital converters and gain ADC units with similar or different structures may be used. This specification does not impose any limitations on these aspects in the embodiments.

[0093] In an ideal state, the input and output of each conversion module in a pipelined analog-to-digital converter circuit have a linear relationship, and the slope is the theoretical gain. Each sub-module conversion unit is responsible for the comparison operation.

[0094] In an ideal ADC, the input and output of each stage should be less than the full scale, so that the output signal range of this stage will not exceed the input range of the next stage. This is because when the input signal exceeds the range, the part exceeding the range cannot be quantized, which will cause some signal loss.

[0095] In practical applications, due to various irrational factors, the analog output signal of the current MDAC may exceed the input range of the next stage, causing the next stage MDAC to be unable to process the output signal of the previous stage correctly, resulting in the loss of numerical output of the analog-to-digital conversion circuit and a reduction in the performance of the pipelined ADC.

[0096] To ensure that the output of this stage of the MDAC does not exceed the maximum range of the next stage output, the method of reducing the interstage gain and using redundant bits for digital correction can usually be adopted.

[0097] For example, Figure 4 The diagram shows the transfer characteristic curve of the conversion module. If the conversion module uses full-scale gain (corresponding to an amplification factor of 8), the maximum output value of the theoretical input-output curve is located on the boundary of the theoretical analog domain output range. However, if the amplification factor of each stage is reduced, for example, if the amplification factor of the second-stage MDAC is changed to 4, ... Figure 4 As shown by the solid line, by adding cascades, a measurement margin is left for each stage, so that even if the reference threshold of the comparator changes, it can still be measured.

[0098] For example, a 3-bit Sub-ADC has an output range of 0–7, while a 4-bit Sub-ADC has an output range of 0–15. Therefore, when using a 4-bit Sub-ADC to output the original 3-bit range, it will only occupy half of the 4-bit range. Even if the output is slightly larger in some cases, such as fluctuating to 8–9, it can still be measured and read because it is still within the output range of the Sub-ADC.

[0099] In an optional example, such as Figure 3The diagram shows a sub-analog-to-digital converter unit, which includes a Sub-ADC 11 with a precision of K-1 bits, comprising K resistors R1, R2 to R... K-2 R K-1 and R K K-1 comparators C1, C2 to C K-2 and C K-1 .

[0100] Reference Figure 1 , Figure 2 and Figure 3 In the Sub-ADC 11, resistor R k One end of resistor R1 is connected to the first reference voltage Vref1, and one end of resistor R1 is connected to the second reference voltage Vref2. K resistors R1 to R... K The resistors are connected in series, with the first reference voltage Vref1 being greater than the second reference voltage Vref2. Thus, the K resistors divide the voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2.

[0101] The K-1 comparators C1 to C K-1 One of its input terminals is coupled between two different resistors, thereby connecting to comparison reference voltages with successively increasing voltage values. The other input terminal is connected to the input signal V. in , where the input signal V in This can be the analog hold signal output from the sample-and-hold amplifier circuit or the signal output from the previous stage conversion module. Each comparator C1 to C... K-1 The comparison reference voltage and input signal V are respectively connected to it. in The amplitudes are compared to obtain the comparison results d1~dk-1, and the comparison results d1~dk-1 are output as thermometer codes to the digital calculation module 04.

[0102] Among them, based on K-1 comparators C1 to C K-1 The order of magnitude of the input comparison reference voltages, and the comparators C1 to C2. K-1 The comparison results d1 to dk-1 are arranged from low to high, meaning that the comparison result d1 output by comparator C1 is the least significant bit of the thermometer code. k-1 The output comparison result dk-1 is the most significant bit. Furthermore, since each comparator C1 to C... K-1 The reference voltages connected to the circuit increase sequentially, therefore, according to the input signal V... in The magnitude of the amplitude is determined by the change in the thermometer code starting from the least significant bit, and the input signal V is only represented when the logic value of the least significant bit in the thermometer code (e.g., logic value "1") is equal to the input signal V. inOnly after the amplitude of the input signal V exceeds the comparison result of the corresponding reference voltage can the logic value of the next higher valid bit in the thermometer code potentially change. For example, as the input signal V... in As the amplitude increases, the thermometer code can change from "00……01" to "00……11", but it will not change to "00……10".

[0103] For example, for a 10-bit ADC, the measurement range is 0 to 1023. In the case of only grading, for example, if the first-stage conversion module (Stage 1) uses a 3-bit Sub-ADC 11 for measurement, it contains 7 comparators, meaning the digital range 0 to 1023 can be divided into eight intervals, which can be numbered, for example, 000, 001, 010, up to 111. When the current signal sample value is determined to fall into a certain interval, for example, the interval corresponding to 010 (corresponding to the 256-383 segment in 0 to 1023), to facilitate sampling by the Sub-ADC in subsequent conversion modules, the signal in that interval can be amplified 8 times using an OTA (Over-The-Air) converter. A 3-bit Sub-ADC is then used to sample the amplified interval. Assuming it falls into the second-stage encoding interval 001, a 4-bit Sub-ADC can then be used to determine its specific value. For example, the interval corresponding to 0001 can be used to determine the current signal sample value as 273.

[0104] For example Figure 2 In the example pipelined analog-to-digital converter circuit without a sample-and-hold module, due to the fluctuation of the analog signal over time, there is a bandwidth mismatch in the sampling path between the Sub-ADC and the MDAC within the first-stage conversion module, which will result in aperture error.

[0105] Aperture error causes a shift in the transition level of the conversion module's transfer characteristic curve, resulting in an increase in the corresponding output voltage range. In other words, it can be equivalent to the reference threshold of the comparator within the sub-ADC increasing or decreasing. Figure 4 As shown, the solid line represents the transfer characteristic curve of the Sub-ADC conversion module. The input voltage value corresponding to the output voltage signal Vout during the transition in the transfer characteristic curve is the preset comparison threshold of the corresponding comparator. This Sub-ADC transfer characteristic curve can be determined based on theoretical design or according to the recorded information from the previous calibration.

[0106] From a signal transmission perspective, when the value of the input voltage signal Vin is Va, it exceeds the preset reference threshold V3 of the corresponding comparator, such as... Figure 4As shown, if the output value Vout is still above the horizontal axis, it can be assumed that the comparator's actual comparison threshold has shifted to the right and the measurement range has increased. In this case, by reducing the comparator's comparison threshold V3, its measurement range can be aligned with the solid line.

[0107] Specifically, based on the transmission characteristics of the conversion module, a test analog signal is input to the first-stage conversion module. Then, based on the jump output voltage output by the first-stage conversion module, it is determined whether there is a deviation between the preset reference threshold of the corresponding comparator in the sub-analog-to-digital conversion unit of the first-stage conversion module and the theoretical reference threshold. If a deviation exists, the preset comparison threshold of the comparator is adjusted. This reduces the impact of aperture error and improves the accuracy of the pipelined analog-to-digital conversion circuit.

[0108] To enable those skilled in the art to better understand the inventive concept, technical solution, principle and beneficial effects of the embodiments of the present invention, the following detailed description is provided with reference to the accompanying drawings and through specific application scenarios.

[0109] First, the pipelined analog-to-digital converter circuit applicable to the embodiments of the present invention may include a first-stage conversion module and a back-end conversion module having at least one stage conversion module cascaded therewith, wherein the first-stage conversion module may include a sub-analog-to-digital converter unit composed of at least one comparator.

[0110] As mentioned earlier, aperture errors can cause shifts in the transfer characteristic curve of pipelined analog-to-digital converters, potentially affecting their accuracy. Therefore, embodiments of the present invention provide a calibration device for pipelined analog-to-digital converters, such as... Figure 5 As shown, the calibration device A0 can be coupled to the pipelined analog-to-digital converter (ADC0) to be calibrated. The pipelined ADC0 includes a first-stage conversion module Stage 1 and a cascaded back-end conversion module Stage B, each having at least one stage conversion module (e.g., Stages 2 through N, where N ≥ 2). The first-stage conversion module Stage 1 includes a sub-ADC composed of at least one comparator (not shown). The specific structure of the pipelined ADC used in this embodiment can be referred to... Figure 2 , Figure 8 , Figure 12 Specific application examples are shown here, but only some modules and components related to aperture error calibration are shown.

[0111] Continue to refer to Figure 5 The calibration device A0 may include: a signal generation module A1, a deviation determination module A2, and a deviation adjustment module A3, wherein:

[0112] The signal generation module A1 is adapted to generate a test analog signal and input it to the first stage conversion module Stage1 in the pipelined analog-to-digital converter circuit ADC0.

[0113] The deviation determination module A2 is adapted to acquire the jump output voltage output by the first-stage conversion module Stage1, which corresponds to the jump signal at the output of the comparator; and to determine whether the preset reference threshold of the comparator deviates from the theoretical reference threshold based on the jump output voltage.

[0114] The deviation adjustment module A3 is adapted to adjust the preset comparison threshold of the comparator when the deviation determination module A2 determines that there is a deviation between the preset reference threshold of the comparator and the theoretical reference threshold.

[0115] Using the aforementioned calibration device A0, a test simulation signal is generated by the signal generation module A1 and directly input to the first-stage conversion module Stage1. Then, the deviation determination module A2 obtains the jump output voltage corresponding to the jump signal at the output terminal of the comparator from the first-stage conversion module Stage1. Based on the jump output voltage, it is determined whether there is a deviation in the preset reference threshold of the comparator. If a deviation is determined, the deviation adjustment module A3 adjusts the preset comparison threshold of the comparator.

[0116] To enable those skilled in the art to better understand and implement this, some specific application examples of each module are shown below.

[0117] First, the signal generation module A1 can specifically be a signal generator. As mentioned earlier, the test simulation signal can be a linear analog signal changing in one direction, a nonlinear analog signal changing in one direction, a linear analog signal changing in multiple directions, or a nonlinear analog signal changing in multiple directions, etc.

[0118] In an optional example, the signal generation module A1 can specifically generate a test simulation signal via a ramp generator, such as... Figure 6a The circuit diagram shown illustrates a ramp generator. A constant current source S1 supplies current I to capacitor C1, causing capacitor C1 to integrate and generate voltage vt, which provides voltage to the gate of transistor M1, one input terminal of driver AMP1, and one input terminal of hysteresis comparator AMP2. The source of transistor M1 is connected to another constant current source S2, which outputs current 2I. The gate of transistor M1 is connected to the output terminal of hysteresis comparator AMP2. The other input terminal of hysteresis comparator AMP2 is connected to a reference voltage VCM. The output terminal of driver AMP1 outputs an analog signal VOUT. The output terminal of driver AMP1 is also grounded through capacitor C2 to achieve noise reduction.

[0119] The hysteresis comparator AMP2 controls the transistor M1 to turn on and off, causing capacitor C1 to charge and discharge, thus generating a linearly increasing and decreasing analog signal VOUT at the output of driver AMP1. (Refer to...) Figure 6b ,for Figure 6a The waveform diagram of the analog signal output by the ramp generator circuit is shown, where V0+ and V0- represent the peak values ​​of the analog signal, and the slope of the linear change of the analog signal VOUT is I / C.

[0120] Based on the linear relationship between the analog signal generated by the ramp generator and time, the output of the ramp generator can be connected to the input of a pipelined analog-to-digital converter (ADC) circuit within a specified time period. This allows the analog signal generated by the ramp generator during that time period to be used as a test analog signal input to the pipelined ADC circuit. The specified time period corresponds to the time period during which the ramp generator generates an analog signal that changes in a single direction (e.g., ...). Figure 6b The simulated signals in region ① and region ②, etc., can also correspond to the time periods during which the ramp generator generates simulated signals that change in multiple directions (e.g., ...). Figure 6b (Partial analog signals from regions ① and ②, etc.).

[0121] In some embodiments of the present invention, reference is made to... Figure 7a The deviation determination module A2 may include: a digital information acquisition unit A21 and a deviation calculation unit A22, wherein:

[0122] The digital information acquisition unit A21 is adapted to determine the jump digital information corresponding to the first stage conversion module Stage1 based on the jump output voltage;

[0123] The deviation calculation unit A22 is adapted to determine whether the measurement output range of the first-level conversion module Stage1 is consistent with the theoretical output range based on the jump digital information obtained by the digital information acquisition unit A21, and when the two are inconsistent, to determine that the preset reference threshold of the comparator has a deviation from the theoretical reference threshold.

[0124] As a specific example, the digital information acquisition unit A21 may include: a digital calculation subunit (not shown), adapted to acquire digital residual information corresponding to the jump output voltage, and test digital information output by the back-end conversion module StageB corresponding to the test analog signal; and determine the jump digital information corresponding to the first-stage conversion module Stage1 based on the digital residual information and the test digital information.

[0125] In other embodiments of the present invention, such as Figure 7bAs shown, the deviation determination module A2 may include: a comparison unit A23, adapted to compare the jump output voltage with a preset output voltage threshold, and output a corresponding feedback signal based on the comparison result, wherein when the two are inconsistent, it is determined that the preset reference threshold of the comparator has a deviation from the theoretical reference threshold.

[0126] In a specific implementation, the comparison unit A23 is a circuit or device that compares the jump output voltage (i.e., the analog voltage signal output by the first conversion module Stage1) with the preset output voltage threshold. Its two inputs are analog signals, and its output is a binary digital signal of 0 or 1 as the feedback signal. For example, if the output level is 1, it is determined that the preset reference threshold of the corresponding comparator in the sub-analog-to-digital conversion unit of the first conversion module Stage1 deviates from the theoretical reference threshold.

[0127] Reference Figure 8 The diagram illustrates a calibration scenario for a pipelined analog-to-digital converter (ADC) circuit. It includes a seven-stage pipelined ADC circuit 8A, employing a dual-input differential structure. This structure comprises a first-stage conversion module (STAGE1) and a backend-ADC module consisting of second to fifth-stage conversion modules (STAGE2-5) and a final-stage conversion module (FLASH ADC). The first-stage conversion module (STAGE1) is a sample-and-hold (SHA-LESS) conversion module. Specifically, the sub-ADC unit can be, for example, a flash ADC. The gain ADC unit (MDAC0) includes an arithmetic logic unit (ALU), a sub-ADC (DAC), and an operational amplifier (OTA). A detailed description of the gain ADC unit (MDAC0) is not provided here; please refer to the aforementioned embodiments for details.

[0128] The flash analog-to-digital converter (FLASH ADC) may include a reference voltage generation circuit (which can be composed of a series of resistors for voltage division), a comparator array, and an encoding circuit. The specific implementation of the reference voltage generation circuit and the comparator array can be found in [reference needed]. Figure 3 As shown, the encoding circuit is not shown. Taking an N-bit flash analog-to-digital converter (ADC) as an example, a resistor divider generates 2N-1 reference voltages, dividing the full-scale range of the FLASH ADC into 2N-1 equal intervals. The input signal of the FLASH ADC is compared with these reference voltages by a comparator, and the thermometer code output after comparison is processed by a binary encoder to obtain the final N-bit binary digital output.

[0129] For the seven-stage pipelined analog-to-digital converter circuit 8A, in some embodiments of the present invention, the calibration device used includes: a signal generation device RAMP GENERATOR, a comparator CMP, and a deviation adjustment module (not shown) disposed inside the flash analog-to-digital converter FLASH ADC.

[0130] Specifically, the test analog signal Analog Input is generated by the signal generation device RAMP GENERATOR and input to the first stage conversion module STAGE1. After the test analog signal Analog Input is input to the seven-stage pipelined analog-to-digital converter circuit 8A, it is processed by the first stage conversion module STAGE1 and output to the backend conversion module Backend-ADC coupled to it.

[0131] The comparator CMP is a specific example of the comparison unit A23, such as Figure 8 As shown, the analog-to-digital converter circuit 8A with a dual-input differential structure can be a 4-input, 1-output analog device. Two input signals, In1 and In2, come from the first-stage analog-to-digital converter module STAGE1, while the other two inputs are reference signals Vref1 and Vref2. Its output can be used as the control signal for the deviation adjustment module. More specifically, the signal at the first input terminal In1 can be compared with the reference signal Vref1, and based on the comparison result, the feedback signal corresponding to the first input signal is input from the output terminal out0; and the signal at the second input terminal In2 can be compared with the reference signal Vref2, and based on the comparison result, the feedback signal corresponding to the second input signal is input from the output terminal out0. It is understood that in specific implementations, the deviation determination module A2 can also simultaneously include the comparison unit A23, the digital information acquisition unit A21, and the deviation calculation unit A22. Users can configure and select to use the comparison unit A23 or the digital information acquisition unit A21 and the deviation calculation unit A22 as needed.

[0132] In a specific implementation, the deviation adjustment module A3 is adapted to control the increase of the preset comparison threshold of the comparator when it is determined that the preset reference threshold of the comparator is less than the corresponding theoretical reference threshold; and to control the decrease of the preset comparison reference threshold of the comparator when it is determined that the preset reference threshold of the comparator is greater than the corresponding theoretical reference threshold.

[0133] In practical implementation, the comparators in the sub-analog-to-digital conversion units of each level of conversion module, including the first-level conversion module, can adopt the following structure: Figure 9The diagram shows the structure of a comparator, where comparator CMP0 includes a pre-amplifier (Pre-amp0) and a latch (Latch0), wherein:

[0134] The pre-amplification component Pre-amp0 has a first input terminal adapted to input a corresponding preset reference threshold, a second input terminal adapted to input the test simulation signal, a first output terminal adapted to output the amplified signal corresponding to the preset reference threshold, and a second output terminal adapted to output the amplified signal corresponding to the test simulation signal.

[0135] The latching component Latch0 has a first input terminal coupled to the first output terminal of the pre-amplification component; its second input terminal is coupled to the second output terminal of the pre-amplification component; and its output terminal is adapted to output a comparison result based on the size relationship between the first input terminal and the second input terminal.

[0136] Based on the structure of the comparator CMP0 described above, the following illustrates a specific circuit structure of the adjustment module. The deviation adjustment module may specifically include: a charge storage unit group, a switching unit group, and a switching control unit. The following illustrates a specific circuit structure of the deviation adjustment module, see reference... Figure 9 The deviation adjustment module A3 shown, in addition to the switch control unit A3c, the charge energy storage unit group can be implemented by multiple charge energy storage units such as capacitors. The switch unit group can be implemented by multiple switches, such as transistors or other types of devices capable of switching functions.

[0137] like Figure 9 As shown, the charge storage unit group specifically includes multiple first charge storage units C1N~CkN and multiple second charge storage units C1P~CkP, wherein: each of the first charge storage units C1N~CkN is coupled between the first output terminal of the pre-amplification component Pre-amp0 and ground, and each of the second charge storage units is coupled between the second output terminal of the pre-amplification component and ground.

[0138] The switch unit group, such as Figure 9 As shown, it specifically includes multiple first switches S1N~SkN and multiple second switches S1P~SkP, wherein: each of the first switches S1N~SkN is coupled between the corresponding first charge storage unit C1N~CkN and ground GND, and each of the second switches SW1P~SWkP is coupled between the corresponding second charge storage unit C1P~CkP and ground.

[0139] The switch control unit A3c is adapted to, when determining that the preset reference threshold of the comparator CMP0 is less than the theoretical reference threshold of the comparator CMP0, turn on the first switch S1N~SkN between some or all of the first charge storage units C1N~CkN coupled to the first output terminal of the pre-amplifier Pre-amp0 and ground GND; and when determining that the preset reference threshold of the comparator CMP0 is greater than the theoretical reference threshold of the corresponding comparator CMP0, turn on the second switch S1P~SkP between some or all of the second charge storage units C1P~CkP coupled to the first output terminal of the pre-amplifier Pre-amp0 and ground.

[0140] It should be noted that, Figure 9 The first and second charge storage units shown are the same in number, as are the first and second switches. It is understood that in specific implementations, the number of the first and second charge storage units, and the number of the first and second switches, may differ.

[0141] As mentioned above, Figure 2 The pipelined analog-to-digital converter circuit shown can be used as a pipelined analog-to-digital converter circuit structure applicable to the calibration scheme of the embodiments of the present invention. It is understood that the pipelined analog-to-digital converter circuit applicable to the embodiments of the present invention is not limited to the above structure. It may have some components, and may also include circuit modules or devices that are expanded or optimized according to actual needs, as long as it does not include circuit modules or components that implement the sample-and-hold function.

[0142] Reference Figure 10 The flowchart of the calibration method shown below illustrates the method for calibrating the aperture error according to an embodiment of the present invention. The specific steps are as follows:

[0143] S11, input the test simulation signal to the first-stage conversion module.

[0144] In practical implementation, calibration can be performed using the method described in this embodiment of the invention before performing analog-to-digital conversion using the pipelined analog-to-digital conversion circuit, or calibration can be performed according to a preset period or frequency, or the calibration method of this embodiment of the invention can be manually activated as needed. After starting calibration, a test analog signal can first be input to the pipelined analog-to-digital conversion circuit, more specifically, the test analog signal can be input to the first-stage conversion module.

[0145] The test simulation signal can be a simulation signal that changes in a single direction or a simulation signal that changes in multiple directions; furthermore, the test simulation signal can be a linearly changing simulation signal or a nonlinearly changing simulation signal. For example, the test simulation signal can be a linear simulation signal that changes in a single direction, a nonlinear simulation signal that changes in a single direction, a linear simulation signal that changes in multiple directions, a nonlinear simulation signal that changes in multiple directions, etc., and this specification does not impose specific limitations on it.

[0146] The test simulation signal can be generated by a signal generator. Furthermore, linear simulation signals are easier to generate and control, and are more conducive to implementing the calibration method provided in the embodiments of this specification. As a preferred embodiment of the present invention, a linear simulation signal varying in a single direction is used as the test simulation signal for aperture error calibration.

[0147] S12, obtain the jump output voltage output by the first-stage conversion module that corresponds to the jump signal at the output of the comparator.

[0148] In practical implementation, each sub-analog-to-digital conversion unit of each conversion module, including the first-level conversion module, may include at least one comparator, as shown in the reference. Figure 3 and Figure 5 When the input voltage signal Vin reaches the comparison threshold of the corresponding comparator, the output signal of the comparator will jump, and correspondingly, the output voltage Vout of the conversion module will also jump. For ease of description, the output voltage of the conversion module corresponding to the jump signal of the corresponding comparator output is called the jump output voltage. Figure 4 As shown, the jump output voltage corresponding to the transfer characteristic curve described by the solid line is ±0.5Vref.

[0149] In a specific implementation, the change curve of the first conversion module with the test simulation signal can be monitored in real time by a sensor. When a jump is detected in the signal at the output of the first-stage conversion module, that is, when the jump output voltage at the output voltage jump is detected, the jump output voltage at the time of the jump is taken as the jump output voltage output by the first-stage conversion module corresponding to the comparator jump signal.

[0150] In the specific calibration process, in order to facilitate implementation and improve calibration efficiency, in step S11, the jump output voltage corresponding to the jump signal of each comparator output terminal in the sub-analog-to-digital conversion unit of the first-stage conversion module can be obtained one by one according to the process of the input voltage Vin gradually changing from -Vref to +Vref, and then calibrated one by one in subsequent steps.

[0151] As a preferred example, when the input voltage Vin is close to the threshold point voltage of each comparator (specifically, it may be slightly lower than or / and slightly higher than the corresponding threshold point voltage of each comparator, for example, it may be a measurement range centered on the threshold point voltage), the corresponding jump output voltage can be obtained to determine whether the current threshold point voltage needs to be adjusted.

[0152] S13, determine whether the preset reference threshold of the comparator deviates from the theoretical reference threshold based on the jump output voltage.

[0153] S14, when it is determined that there is a deviation between the preset reference threshold of the comparator and the theoretical reference threshold, the preset comparison threshold of the comparator is adjusted.

[0154] As mentioned earlier, due to aperture error, the switching output voltage output by the first-stage conversion module may deviate from the theoretical switching output voltage. For example... Figure 4 The transmission characteristic curve shown by the dashed line segment may actually be larger than the theoretical reference threshold. As can be seen from the transmission characteristic curves of the aforementioned conversion modules, under ideal conditions, the input and output of each conversion module in the pipelined analog-to-digital converter circuit have a linear relationship, and the slope represents the theoretical gain. Therefore, when the jump output voltage output through the first-stage conversion module is inconsistent with the preset reference threshold corresponding to the comparator, it can be equivalent to a deviation between the preset comparison threshold of the comparator and the theoretical comparison threshold. Therefore, the preset comparison threshold of the comparator can be adjusted accordingly, thereby reducing the shift in the jump level position of the conversion module caused by aperture error, and thus improving the accuracy of the pipelined analog-to-digital converter circuit.

[0155] Specifically, refer to Figure 4 The transmission characteristic curve shown may correspond to a theoretical reference threshold of ±0.5Vref for each comparator in the first-stage conversion module, but in reality, it may be the actual jump output voltage, such as Vr.

[0156] Specifically: For example, when the voltage value of the input test analog signal is Va, the output voltage of the first conversion module jumps, and the corresponding output voltage value is Vr, which indicates that the current actual comparison threshold Va of the corresponding comparator is greater than the current preset comparison threshold V3.

[0157] Depend on Figure 4As shown in the transfer characteristic curve of the conversion module, for the first-stage conversion module, with the slope of the transfer characteristic curve unchanged, it can be equivalent to the preset comparison threshold of the comparator corresponding to the jump output voltage of the first-stage conversion module deviating from the theoretical comparison threshold. If the jump output voltage of the first-stage conversion module is not equal to ±0.5Vref, for example, if the jump output voltage of the first-stage conversion module is obtained as Vr, the preset reference threshold of the comparator corresponding to the jump output voltage can be equivalent to Va. Figure 4 It is evident that the theoretical reference threshold of the comparator corresponding to the preset reference threshold Va is V3, and there is a clear deviation between the two. Therefore, by adjusting the corresponding comparison thresholds of each comparator, the output of the first-stage conversion module can be made to better conform to the ideal or theoretical transmission characteristic curve, reducing or even eliminating the offset caused by aperture error, thereby improving the conversion accuracy of the pipelined analog-to-digital converter circuit.

[0158] To enable those skilled in the art to better understand and implement this method, some optional examples of each step are provided below. It is understood that in specific implementations, the steps are not limited to the specific examples below.

[0159] After obtaining the jump output voltage in step S12, step S13 can be used to determine whether the preset reference threshold of the comparator deviates from the theoretical reference threshold. In specific implementations, step S13 may have multiple determination methods; two exemplary methods are given below. One can be simply referred to as the digital signal-based determination method, and the other as the analog signal-based determination method.

[0160] Specifically, regarding the digital signal-based determination method, the jump digital information corresponding to the first-stage conversion module is first determined based on the acquired jump output voltage, and then a determination is made, such as... Figure 11 The flowchart shown for determining whether there is a deviation in the preset reference threshold of the comparator may specifically include the following steps:

[0161] S131, determine the jump digital information corresponding to the first-stage conversion module based on the jump output voltage.

[0162] In specific implementation, refer to Figure 2The test analog signal is input to the pipelined analog-to-digital converter circuit P1. The sub-analog-to-digital converter units and gain digital-to-analog converter units of the first-stage conversion module perform calculations to obtain the corresponding analog residual signal, which is then passed step-by-step to the back-end conversion module, which includes at least one stage of conversion. Subsequently, the output code corresponding to the test analog signal can be obtained based on the thermometer code output by each stage of the conversion module to the sub-analog-to-digital converter unit. This output code can be used as the test digital information corresponding to the test analog signal. On the other hand, since the jump output voltage output by the first-stage conversion module corresponds to the digital signal of the back-end conversion module (excluding the first-stage conversion module), the digital signal of the back-end conversion module can be used as the digital residual information corresponding to the jump data voltage. Therefore, the jump digital information corresponding to the first-stage conversion module can be determined based on the digital residual information and the test digital information.

[0163] Reference Figure 2 Through step S13, on the one hand, the digital signals output by the back-end conversion modules, including conversion modules Stage2 to StageN, can be obtained, that is, the digital residual information corresponding to the jump output voltage. On the other hand, the digital signals output by conversion modules Stage1 to StageN can be obtained, that is, the test digital information corresponding to the jump output voltage. Therefore, based on the digital residual information and the test digital information, the jump digital information corresponding to the first-stage conversion module can be determined.

[0164] S132, based on the jump digital information, determine whether the measurement output range of the first-level conversion module is consistent with the theoretical output range, and if they are inconsistent, execute step S133.

[0165] Reference Figure 4 For example, the jump digital information can be compared with the theoretical output range of the first-level conversion module to determine whether the two are consistent. In specific implementation, the jump digital information can be directly compared with the threshold of the theoretical output range of the first-level conversion module to determine whether the two are consistent. If they are inconsistent, step S133 can be executed.

[0166] S133, It is determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold.

[0167] The following is a detailed description using a specific application scenario as an example.

[0168] Reference Figure 12The diagram shows the structure of a seven-stage pipelined analog-to-digital converter (ADC). The pipelined ADC P3 has a precision of 12 bits and includes seven conversion modules: a first-stage conversion module (Stage 11) and a back-end conversion module 102 composed of second-stage to seventh-stage conversion modules (Stage 2 through Stage 7). More specifically, the first-stage conversion module (Stage 11) and the second-stage conversion module (Stage 12) output 3 bits of first-stage thermometer code DS11 and DS12, respectively; the third-stage to sixth-stage conversion modules (Stage 13 through Stage 16) output 2 bits of third-stage to sixth-stage thermometer code DS13 through DS16, respectively; and the seventh-stage conversion module (Stage 17) outputs 4 bits of seventh-stage thermometer code DS17.

[0169] Comparison Table 1

[0170]

[0171] When the numerical calculation module 103 performs staggered addition of the thermometer codes DS11 to DS12 from the first-level conversion module Stage 12 to the seventh-level conversion module Stage 17, there is partial bit overlap between each level of the thermometer code, resulting in a 12-bit output code. See Table 1 below for details. Here, d12 to d10 represent the most significant bit to the least significant bit of the first-level thermometer code DS11, and so on. d20 to d73 represent the specific bits included in the second-level thermometer code DS12 to the seventh-level thermometer code DS17, respectively. Furthermore, Table 1 also shows the digital field weights corresponding to the first-level conversion module Stage 12 to the seventh-level conversion module Stage 17 as 512, 128, 64, 32, 16, 8, and 1, respectively.

[0172] According to the above comparison table 1, the least significant bit of the previous stage thermometer code and the most significant bit of the next stage thermometer code coincide. The numerical calculation module 103 performs staggered addition according to the coincidence relationship shown in the comparison table 1 to obtain a 12-bit output code DSC.

[0173] Furthermore, based on the current digital field weights of the first-level conversion module (Stage 12) to the seventh-level conversion module (Stage 17), the digital output information DOUT corresponding to the 12-bit output code can be calculated using the following formula:

[0174] DOUT=(d12*4+d11*2+d10*1)*512+

[0175] (d22*4+d21*2+d20*1)*128+

[0176] (d31*2+d30*1)*64+

[0177] (d41*2+d40*1)*32+

[0178] (d51*2+d50*1)*16+

[0179] (d61*2+d60*1)*8+

[0180] (d73*8+d72*4+d71*2+d70*1)*1.

[0181] The digital output information DOUT corresponding to the test analog signal is the test digital information.

[0182] By obtaining the thermometer codes (i.e., the second-level thermometer code DS12 to the seventh-level thermometer code DS17) and their corresponding digital field weights (i.e., 128~1) output by each level of the conversion module in the back-end conversion module 102, the digital residual information Residue1 can be obtained:

[0183] Residue1=(d22*4+d21*2+d20*1)*128+

[0184] (d31*2+d30*1)*64+

[0185] (d41*2+d40*1)*32+

[0186] (d51*2+d50*1)*16+

[0187] (d61*2+d60*1)*8+

[0188] (d73*8+d72*4+d71*2+d70*1)*1.

[0189] Using the above formula, the digital residual information corresponding to the jump output voltage of the first-stage conversion module Stage11 when the test analog signal is input can be obtained.

[0190] As can be seen from the above relationships, by subtracting the test digital information corresponding to the test analog signal from the digital residual information corresponding to the jump output voltage, and taking the difference between the two, the jump digital information corresponding to the first-stage conversion module can be obtained.

[0191] For schemes based on analog signal determination, refer to Figure 8 The diagram shown illustrates a calibration scenario for a pipelined analog-to-digital converter circuit. The jump output voltage of the first-stage conversion module can be directly measured using a comparator (CMP) and compared with a preset output voltage threshold. When the two are inconsistent, it can be determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold.

[0192] Combination Figure 4 The transfer characteristic curves illustrate the specific working principle of the comparator CMP: Assuming Vref1 = +0.5Vref and Vref2 = -0.5Vref, if monitoring shows that the output voltage of the first conversion module STAGE1 jumps when the input test analog signal Analog Input is Va, and assuming that the first input terminal In1 of the comparator CMP detects a jump output voltage of Vr, where Vr > +0.5Vref, according to the transfer characteristic curves, when the voltage of the test analog signal Analog Input is Va, it is no longer within the range of the corresponding comparator. This indicates that the output voltage range of the first-stage conversion module STAGE1 has increased, and it can be determined that the preset reference threshold of the corresponding comparator deviates from the theoretical reference threshold. Similarly, the jump output voltage detected by the second input terminal In2 of the comparator CMP can be compared with the reference signal Vref2, i.e., -0.5Vref, and based on the comparison result, it can be determined whether the preset reference threshold of the corresponding comparator deviates from the theoretical reference threshold.

[0193] It is understood that the determination method is not limited to the examples above. In specific implementations, further optimization or expansion can be made as needed, or other types of determination methods can be adopted, as long as it is possible to determine whether the prediction reference threshold of the comparator deviates from the theoretical threshold. The embodiments of the present invention do not limit the specific determination method.

[0194] In specific implementation, for step S14, an adjustment strategy can be adopted based on the relationship between the preset reference threshold of the comparator and the corresponding theoretical reference threshold. Specifically, when it is determined that the preset reference threshold of the comparator is less than the corresponding theoretical reference threshold, the preset comparison threshold of the comparator can be increased; conversely, when it is determined that the preset reference threshold of the comparator is greater than the corresponding theoretical reference threshold, the preset comparison threshold of the comparator can be decreased.

[0195] In a specific application example, refer to Figure 4 and combined Figure 8 Assuming Figure 8The first-stage conversion module STAGE1 contains a flash analog-to-digital converter (FLASH ADC) consisting of a comparator array of eight comparators. Assume the threshold values ​​for the first six comparators have been adjusted. For the seventh comparator, for ease of description, it is referred to as comparator A. If the preset reference threshold value for comparator A is Vr, since Vr > +0.5Vref, its corresponding comparator threshold value can be reduced in predetermined steps. For example, the preset comparator threshold value can be gradually adjusted from Va to the left until it reaches V3. More specifically, in conjunction with... Figure 9 The diagram shows the specific structure of the deviation adjustment module. For example, the structure of comparator A is as follows: Figure 9 The structure of CMP0 shown can be used when the comparator CMP detects that the signal at the first input terminal In1 is greater than the reference signal Vref1 (e.g., +0.5Vref). Figure 9 The deviation adjustment module A3 is adjusted step by step. For example, the switch control unit A3c outputs a switch control signal to first trigger the first switch S1N to close, opening the path between the first charge storage unit C1N and ground. If the comparator CMP detects that the signal at the first input terminal In1 is still greater than the reference signal Vref1, then based on the feedback signal output by CMP1, the switch control unit A3c triggers the first switch S2N to close again, opening the path between the first charge storage unit C2N and ground. This process continues until the comparator CMP detects that there is no deviation between the signal at the first input terminal In1 and the reference signal Vref1, at which point it is determined that the comparison threshold of comparator A has been adjusted. Then, the same method can be used to detect whether the preset reference threshold of the next comparator deviates from the theoretical reference threshold and adjust it using the above deviation adjustment method.

[0196] Similarly, refer to Figure 8 and Figure 9 The comparison threshold of the corresponding comparator can be calibrated based on another output signal from the first-stage conversion module to reduce or eliminate the aperture error of the pipelined analog-to-digital converter circuit and improve the accuracy of the pipelined analog-to-digital converter circuit.

[0197] The calibration device and calibration method applicable to pipelined analog-to-digital converter circuits have been described above with specific examples. It should be noted that the working principles, working mechanisms, application examples and advantages of the calibration devices and calibration methods in the above embodiments can be understood by referring to each other.

[0198] In practical implementation, analog-to-digital converter circuits are widely used. The following is an example description of a specific application in radar.

[0199] Reference Figure 13The schematic diagram of the radar shown is illustrated in an embodiment of the present invention. Figure 13 As shown, radar RD0 includes a detection device DT0, an analog-to-digital converter circuit ADC0, and a calibration device CB0; wherein:

[0200] The detection device DT0 is adapted to acquire echo signals and output the analog signal to be processed to the analog-to-digital converter circuit ADC0x;

[0201] The analog-to-digital converter circuit ADC0x is adapted to perform analog-to-digital conversion on the analog signal to be processed by the detection device DT0 or the test analog signal of the calibration device CB0; it includes a pipelined analog-to-digital converter circuit PL-ADC0, wherein the pipelined analog-to-digital converter circuit PL-ADC0 includes a first-stage conversion module Stage01, a back-end conversion module StageB with at least one stage conversion module cascaded therewith, and a digital computing module CA0;

[0202] The calibration device CB0 is adapted to perform aperture error calibration on the pipelined analog-to-digital converter circuit PL-ADC0 by inputting a test analog signal to the pipelined analog-to-digital converter circuit PL-ADC0.

[0203] The analog-to-digital converter circuit ADC0, and more specifically, the pipelined analog-to-digital converter circuit PL-ADC0, can be found in the descriptions of the foregoing embodiments. The calibration device CB0 can also be found in the detailed descriptions of the foregoing embodiments, and will not be repeated here.

[0204] In a specific implementation, the radar RD may further include a control device CT0, which is adapted to control the calibration device CB0 to calibrate the pipelined analog-to-digital converter circuit PL-ADC0 after the radar RD0 is powered on, and to control the calibration device CB0 to end the calibration after the calibration end conditions are met, and to enable the analog-to-digital converter circuit ADC0x to perform analog-to-digital conversion processing on the analog signal to be processed.

[0205] In specific implementations, the radar may be a lidar, millimeter-wave radar, etc., and the specific type is not limited in the embodiments of this specification.

[0206] It should be noted that the terms "example," "implementation," or "exemplary" used in this specification refer to a specific feature, structure, or characteristic that may be included in at least one implementation of this specification. Furthermore, in the description of this specification, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with terms such as "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or indicate importance. It is understood that such terms may be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein.

[0207] While the embodiments disclosed in this specification are as described above, they are not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments in this specification. Therefore, the scope of protection of the embodiments in this specification should be determined by the scope defined in the claims.

Claims

1. A calibration method for pipelined analog-to-digital converter circuits, wherein, The pipelined analog-to-digital converter circuit includes a first-stage conversion module and a cascaded back-end conversion module having at least one stage conversion module. The first-stage conversion module includes a sub-analog-to-digital converter unit composed of at least one comparator. The calibration method includes: Input a test simulation signal into the first-stage conversion module; Obtain the jump output voltage output by the first-stage conversion module that corresponds to the jump signal at the output of the comparator; Based on the jump output voltage, determine whether the comparator's preset reference threshold deviates from the theoretical reference threshold; When it is determined that there is a deviation between the preset reference threshold of the comparator and the theoretical reference threshold, the preset comparison threshold of the comparator is adjusted.

2. The calibration method according to claim 1, characterized in that, The step of determining whether the preset reference threshold of the comparator deviates from the theoretical reference threshold based on the jump output voltage further includes: The jump digital information corresponding to the first-stage conversion module is determined based on the jump output voltage; Based on the jump digital information, it is determined whether the measurement output range of the first-level conversion module is consistent with the theoretical output range, and when they are inconsistent, it is determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold.

3. The calibration method according to claim 2, characterized in that, The step of determining the jump digital information corresponding to the first-stage conversion module based on the jump output voltage further includes: Obtain the digital residual information corresponding to the jump output voltage, and the test digital information output by the back-end conversion module corresponding to the test analog signal; Based on the digital residual information and the test digital information, the jump digital information corresponding to the first-level conversion module is determined.

4. The calibration method according to claim 1, characterized in that, The step of determining whether there is a deviation in the preset threshold of the comparator based on the jump output voltage further includes: The jump output voltage is compared with the preset output voltage threshold. When the two are inconsistent, it is determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold.

5. The calibration method according to any one of claims 1-4, characterized in that, When it is determined that there is a deviation between the preset reference threshold of the comparator and the theoretical reference threshold, adjusting the preset comparison threshold of the comparator includes: When it is determined that the preset reference threshold of the comparator is less than the corresponding theoretical reference threshold, the preset comparison threshold of the comparator is increased. When it is determined that the preset reference threshold of the comparator is greater than the corresponding theoretical reference threshold, the preset comparison threshold of the comparator is controlled to decrease.

6. A calibration device for a pipelined analog-to-digital converter circuit, wherein, The pipelined analog-to-digital converter circuit includes a first-stage conversion module and cascaded back-end conversion modules having at least one stage conversion module, wherein the first-stage conversion module includes a sub-analog-to-digital converter unit composed of at least one comparator; characterized in that the calibration device includes: A signal generation module is adapted to generate test analog signals and input them to the first-stage conversion module in the pipelined analog-to-digital conversion circuit. The deviation determination module is adapted to acquire the jump output voltage output by the first-stage conversion module corresponding to the jump signal at the output terminal of the comparator; and to determine whether the preset reference threshold of the comparator deviates from the theoretical reference threshold based on the jump output voltage. The deviation adjustment module is adapted to adjust the preset comparison threshold of the comparator when the deviation determination module determines that there is a deviation between the preset reference threshold of the comparator and the theoretical reference threshold.

7. The calibration apparatus according to claim 6, characterized in that, The deviation determination module includes: The digital information acquisition unit is adapted to determine the jump digital information corresponding to the first-stage conversion module based on the jump output voltage; The deviation calculation unit is adapted to determine whether the measurement output range of the first-level conversion module is consistent with the theoretical output range based on the jump digital information obtained by the digital information acquisition unit, and when the two are inconsistent, to determine that the preset reference threshold of the comparator has a deviation from the theoretical reference threshold.

8. The calibration apparatus according to claim 7, characterized in that, The digital information acquisition unit includes: The digital calculation subunit is adapted to acquire digital residual information corresponding to the jump output voltage and test digital information output by the back-end conversion module corresponding to the test analog signal; and to determine the jump digital information corresponding to the first-stage conversion module based on the digital residual information and the test digital information.

9. The calibration apparatus according to claim 6, characterized in that, The deviation determination module includes: a comparison unit, adapted to compare the jump output voltage with a preset output voltage threshold, and output a corresponding feedback signal based on the comparison result, wherein when the two are inconsistent, it is determined that the preset reference threshold of the comparator deviates from the theoretical reference threshold.

10. The calibration apparatus according to any one of claims 6-9, characterized in that, The deviation adjustment module is adapted to increase the preset comparison threshold of the comparator when it is determined that the preset reference threshold of the comparator is less than the corresponding theoretical reference threshold. And when it is determined that the preset reference threshold of the comparator is greater than the corresponding theoretical reference threshold, the preset comparison reference threshold of the comparator is controlled to be reduced.

11. The calibration apparatus according to claim 10, characterized in that, The comparator includes: The pre-amplification component has a first input terminal adapted to input a corresponding preset reference threshold, a second input terminal adapted to input the test simulation signal, a first output terminal adapted to output the amplified signal corresponding to the preset reference threshold, and a second output terminal adapted to output the amplified signal corresponding to the test simulation signal. The latching component has a first input terminal coupled to the first output terminal of the pre-amplification component; its second input terminal is coupled to the second output terminal of the pre-amplification component; and its output terminal is adapted to output a comparison result based on the size relationship between the first input terminal and the second input terminal.

12. The calibration apparatus according to claim 11, characterized in that, The deviation adjustment module includes: A charge storage unit group includes multiple first charge storage units and multiple second charge storage units, wherein: each first charge storage unit is coupled between a first output terminal of the pre-amplification component and ground, and each second charge storage unit is coupled between a second output terminal of the pre-amplification component and ground; The switch unit group includes a plurality of first switches and a plurality of second switches, wherein: each first switch is coupled between a corresponding first charge storage unit and ground, and each second switch is coupled between a corresponding second charge storage unit and ground; A switch control unit is adapted to, when determining that a preset reference threshold of the comparator is less than a theoretical reference threshold of the comparator, turn on a first switch between some or all of the first charge storage units coupled to the first output terminal of the pre-amplification component and ground; and to, when determining that a preset reference threshold of the comparator is less than a theoretical reference threshold of the corresponding comparator, turn on a second switch between some or all of the second charge storage units coupled to the first output terminal of the pre-amplification component and ground.

13. A radar, characterized in that, include: The detection device, the analog-to-digital conversion circuit, and the calibration device according to any one of claims 6-12; wherein: The detection device is adapted to acquire echo signals and output analog signals to be processed to the analog-to-digital conversion circuit. The analog-to-digital conversion circuit is adapted to perform analog-to-digital conversion on the analog signal to be processed by the detection device or the test analog signal of the calibration device; it includes a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a first-stage conversion module, a back-end conversion module having at least one stage conversion module and a digital computing module cascaded therewith; The calibration device is adapted to calibrate the aperture error of the pipelined analog-to-digital converter circuit by inputting a test analog signal to the pipelined analog-to-digital converter circuit.

14. The radar according to claim 13, characterized in that, Also includes: The control device is adapted to control the calibration device to calibrate the pipelined analog-to-digital conversion circuit after the radar is powered on, and to control the calibration device to end the calibration after the calibration end conditions are met, and to cause the analog-to-digital conversion circuit to perform analog-to-digital conversion processing on the analog signal to be processed.

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