Image sensing device

Abstract

The present application relates to an image sensing device. An image sensing device may include at least one pixel group connected between alternately arranged rows and columns. The pixel group may include at least one floating diffusion and n photoelectric conversion units (n is an odd number greater than 1). The photoelectric conversion unit may be connected to the floating diffusion to generate charge for incident light.

Description

Technical Field

[0001] Various embodiments relate generally to image sensing devices, and more particularly, to imaging sensing devices for combining various sub-pixels. Background Art

[0002] Imaging sensing devices can convert optical images into electrical signals. Recently, as the computer and communication industries have developed, the demand for improved imaging sensing devices in smart phones, digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, medical micro cameras, robots, UV sensing devices, etc. may increase.

[0003] The CMOS image sensing device can be driven in a simple manner. In addition, the CMOS image sensing device can be integrated in a single chip to have a small size, high integration, and low power consumption. In addition, since the CMOS image sensing device can be manufactured using CMOS manufacturing technology, the CMOS image sensing device can have a low price. Therefore, the CMOS image sensing device can be widely used.

[0004] As the demand for smartphones with large-capacity cameras may have increased, image sensing devices as camera functions of smartphones may require noise suppression technology as well as various color expressions and night shooting focus detection. Therefore, a binning technology may be proposed, which may be able to receive more charge during the same exposure time by combining more pixels. Summary of the invention

[0005] According to an exemplary embodiment, an image sensing device may be provided. The image sensing device may include at least one pixel group connected between rows and columns that intersect each other. The pixel group may include at least one floating diffusion and n photoelectric conversion units (n is an odd number greater than 1). The photoelectric conversion unit may be connected to the floating diffusion in common to generate charge for incident light.

[0006] In example embodiments, the floating diffusions may be an even number per pixel group, and the even number of floating diffusions may be electrically connected to each other.

[0007] In an example embodiment, a row may be divided into at least three sub-rows. A column may be divided into at least one sub-column. Thus, a pixel group may be defined by a plurality of sub-pixels connected to intersections between sub-rows and sub-columns.

[0008] In example embodiments, the photoelectric conversion units may be formed at the sub-pixels, respectively. The floating diffusion may be disposed between at least three sub-pixels. The gate of the transfer transistor may be disposed between the photoelectric conversion unit and an adjacent floating diffusion.

[0009] In an example embodiment, the image sensing device may further include a pixel signal generating circuit configured to generate a pixel output signal of at least one pixel group. The pixel output signal may be determined based on an added value of the amount of charge generated by the photoelectric conversion units in the at least one pixel group.

[0010] According to example embodiments, an image sensing device may be provided. The image sensing device may include a substrate, an extended pixel group, a first floating diffusion, a second floating diffusion, a third floating diffusion, and a fourth floating diffusion. The substrate may have a first surface and a second surface opposite to the first surface. The extended pixel group includes first to ninth subpixels arranged between first to third subcolumns and first to third subrows intersecting each other. The first to third subpixels are arranged on the first subcolumn, the fourth to sixth subpixels are arranged on the second subcolumn, and the seventh to ninth subpixels are arranged on the third column. The first floating diffusion is arranged at a contact point between the first subpixel, the second subpixel, the fourth subpixel, and the fifth subpixel. The second floating diffusion is arranged at a contact point between the second subpixel, the third subpixel, the fifth subpixel, and the sixth subpixel. The third floating diffusion is arranged symmetrically with respect to the boundary of the second subcolumn and the third subcolumn with the first floating diffusion at a contact point between the seventh subpixel and the eighth subpixel. Each of the first to ninth subpixels includes a transfer gate and a photoelectric conversion unit. The transfer gate is configured to surround any one of the first to fourth floating diffusions. The photoelectric conversion unit is arranged in the sub-pixel on one side of the transfer gate. Each of the first to fourth floating diffusions is surrounded by three transfer gates.

[0011] In example embodiments, the transfer gates on the first to third subpixels of the first subcolumn may have substantially the same shape as the transfer gates on the seventh to ninth subpixels of the third subcolumn.

[0012] In example embodiments, the transfer gates on the fourth to sixth subpixels of the second subcolumn may have substantially the same shape as the transfer gates on the seventh to ninth subpixels of the third subcolumn.

[0013] In example embodiments, the transfer gates on the fourth to sixth subpixels of the second subcolumn may be symmetrical to the transfer gates on the seventh to ninth subpixels of the third subcolumn with respect to a boundary between the second and third subcolumns.

[0014] In example embodiments, the first to fourth floating diffusions may be electrically connected to each other.

[0015] In example embodiments, the image sensing device may further include a pixel signal generating circuit integrated outside the extended pixel group. The pixel signal generating circuit may generate a pixel output signal based on the amount of charge generated by the first to fourth floating diffusions.

[0016] In example embodiments, the image sensing device may further include an extended color filter disposed on the second surface of the substrate. The extended color filter may have a size corresponding to a size of the extended pixel group.

[0017] According to example embodiments, the area of ​​the pixel group can be controlled regardless of the number of pixel groups corresponding to one color filter. In addition, although an even number or an odd number of sub-pixels can form a group corresponding to one color filter, the light receiving area in each direction can be uniform. In addition, the charges of the respective sub-pixels can be added using a merging mode to improve the signal-to-noise ratio (SNR) and image quality during nighttime shooting. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a block diagram illustrating an image sensing device according to an example embodiment;

[0020] Figure 2A and Figure 2B is an equivalent circuit diagram illustrating a pixel group according to an example embodiment;

[0021] Figure 3A and Figure 3B is a plan view illustrating a pixel group according to an example embodiment;

[0022] Figure 4A is along Figure 3A A cross-sectional view taken along line IIIa-IIIa′ in FIG.

[0023] Figure 4B is along Figure 3A A cross-sectional view taken along line IIIb-IIIb′ in FIG.

[0024] Figure 4C is along Figure 3A A cross-sectional view taken along line IIIc-IIIc′;

[0025] Figure 4D is along Figure 3A A cross-sectional view taken along line IIId-IIId′;

[0026] Figure 5 is a plan view illustrating a pixel array according to an example embodiment;

[0027] Figure 6 is an example of Figure 5 A perspective view of an image sensing device having a pixel array in FIG.

[0028] Figure 7 is a plan view illustrating an extended pixel array according to an example embodiment;

[0029] Figure 8 is an example of Figure 7 A perspective view of an image sensing device with an extended pixel array;

[0030] Fig. 9 is a plan view illustrating an extended pixel group according to an example embodiment;

[0031] Fig.10 is a plan view illustrating an extended pixel group according to an example embodiment; and

[0032] Fig.11 is a perspective view illustrating an image sensing device having an extended pixel group and an extended color filter according to example embodiments. DETAILED DESCRIPTION

[0033] Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams of various embodiments (and intermediate structures). Therefore, variations in the illustrated configurations and shapes due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the described embodiments should not be interpreted as being limited to the specific configurations and shapes illustrated herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present invention as defined in the appended claims.

[0034] The present invention is described herein with reference to cross-sectional illustrations and / or planar illustrations of idealized embodiments of the present invention. However, embodiments of the present invention should not be construed as limiting the inventive concept. Although several embodiments of the present invention will be shown and described, it will be appreciated by those of ordinary skill in the art that variations may be made in these embodiments without departing from the principles and spirit of the present invention.

[0035] Figure 1 is a block diagram illustrating an image sensing device according to example embodiments.

[0036] Reference Figure 1 , the image sensing device 100 may include a pixel array 10 and a control circuit block 60 .

[0037] The pixel array 10 may include a plurality of row lines, a plurality of column lines, and a plurality of pixel groups PXG. In an example embodiment, the row lines R1 to Rn may extend in parallel in a first direction D1 and be arranged in a second direction D2. The column lines C1 to Cm may extend in the second direction D2. The first direction D1 may be substantially perpendicular to the second direction D2. The plurality of pixel groups PXG may be located between the row lines R1 to Rn and the column lines C1 to Cm, respectively. The pixel groups PXG connected to the same row lines R1 to Rn may be exposed to incident light at the same time. The pixel output signals of the pixel groups PXG connected to the selected column lines may be transmitted to the control circuit block 60 through the selected column lines.

[0038] Each pixel group PXG may include at least one photoelectric conversion unit (not shown). The pixel group PXG may correspond to at least one color filter. The photoelectric conversion unit may convert light provided from an object into an electrical signal. The photoelectric conversion unit may receive light from an object to generate a charge corresponding to the amount of light received. The pixel group PXG may be illustrated in detail later.

[0039] The control circuit block 60 may include a row driver 20 , a column driver 30 , an output circuit 40 , and a timing controller 50 .

[0040] The row driver 20 may control the plurality of row lines R1 to Rn. The row driver 20 may generate various control signals to sequentially select the row lines R1 to Rn.

[0041] The column driver 30 may control a plurality of column lines C1 to Cm. The column driver 30 may generate various control signals for selecting one of the column lines C1 to Cm. In addition, the column driver 30 may include a correlated double sampler (not shown) and an analog-to-digital converter (not shown). The correlated double sampler may detect a pixel output signal or a pixel output voltage of a pixel group PXG connected between a selected row line and a selected column line using correlated double sampling. The analog-to-digital converter may convert the pixel output signal of the selected pixel group PXG into a digital signal. The digital signal may then be transmitted to the output circuit 40.

[0042] The output circuit 40 may include a latch or a buffer that temporarily stores the digital signal. The output circuit 40 may include an amplifier circuit configured to amplify the buffered digital signal. In addition, the output circuit 40 may temporarily store the digital signal received from the column driver 30. The output circuit 40 may generate image data based on the buffered digital signal.

[0043] The timing controller 50 may provide the row driver 20, the column driver 30, and the output circuit 40 with a timing control signal for determining the operation timing of the row driver 20, the column driver 30, and the output circuit 40. The timing controller 50 may receive a control command provided from the outside. The timing controller 50 may generate a timing control signal based on the control command.

[0044] The control command may be provided from an image processor 70 located outside the image sensing device 100. The image processor 70 may process the image data transmitted from the output circuit 40. The image processor 70 may output the processed image data to a display device or a storage device for storing the image data.

[0045] Figure 2A and Figure 2B is an equivalent circuit diagram illustrating a pixel group according to example embodiments.

[0046] Reference Figure 1 and Figure 2A , the pixel group PXG may include a pixel signal generating circuit 110, a light receiving circuit 120, and at least one floating diffusion. In example embodiments, one pixel group PXG may include an even number of floating diffusions. Here, the pixel group PXG may include a first floating diffusion FD1 and a second floating diffusion FD2, but is not limited thereto.

[0047] The pixel signal generating circuit 110 may generate a pixel output signal Vout based on the amount of photocharge obtained by the light receiving circuit 120. The light receiving circuit 120 may generate the charge according to the exposure time of light.

[0048] In example embodiments, the pixel signal generating circuit 110 may include at least one pixel transistor. For example, the pixel transistor may include a reset transistor RX, a dual conversion transistor DCX, a drive transistor DX, and a selection transistor SX.

[0049] The reset transistor RX, the dual conversion transistor DCX, the drive transistor DX, and the selection transistor SX may operate in response to row-related signals (eg, the reset signal RS, the dual conversion signal DCS, and the selection signal SEL) provided from the row driver 20 .

[0050] The reset transistor RX may be electrically connected between a pixel power supply terminal V1_T for providing a pixel power supply voltage and the dual conversion transistor DCX. The reset transistor RX may reset the first floating diffusion FD1 and the second floating diffusion FD2 in response to a reset signal RS. The reset transistor RX may receive the reset signal RS as a gate signal. The reset transistor RX may provide a pixel power supply voltage for the first floating diffusion FD1 and the second floating diffusion FD2 to reset the first floating diffusion FD1 and the second floating diffusion FD2. The pixel power supply voltage may include a power supply voltage VDD or a pumping voltage VPP.

[0051] The dual conversion transistor DCX may be connected to the second floating diffusion FD2 electrically connected to the first floating diffusion FD1. The dual conversion transistor DCX may be driven in response to a dual conversion signal DCS provided from the row driver 20. For example, the gate of the dual conversion transistor DCX may receive the dual conversion signal DCS. The drain of the dual conversion transistor DCX may be connected to the second floating diffusion FD2. The source of the dual conversion transistor DCX may be floating. In some cases, the dual conversion transistor DCX may be omitted in the pixel group PXG.

[0052] Alternatively, refer to Figure 2B , the dual conversion transistor DCX may be connected between the first floating diffusion FD1 and the second floating diffusion FD2. The dual conversion transistor DCX may receive the dual conversion signal DCS as a gate signal. The drain of the dual conversion transistor DCX may be connected to the first floating diffusion FD1. The source of the dual conversion transistor DCX may be connected to the second floating diffusion FD2. Therefore, the first floating diffusion FD1 and the second floating diffusion FD2 may be selectively connected by activating the dual conversion transistor DCX.

[0053] The dual conversion transistor DCX can be turned on together with the reset transistor RX to discharge the residual charge in the first floating diffusion FD1 and the second floating diffusion FD2. The dual conversion transistor DCX can change the charge amount of the first floating diffusion FD1 and the second floating diffusion FD2 according to the object shooting environment such as low brightness or high brightness. Therefore, the pixel group PXG can be converted to a high conversion gain (HCG) or a low conversion gain (LCG) by driving the dual conversion transistor DCX.

[0054] The driving transistor DX can be driven based on the amount of charge of the first floating diffusion FD1 and / or the second floating diffusion FD2. For example, the driving transistor DX can be driven as a source follower to amplify the effective voltage according to the amount of charge accumulated in the first floating diffusion FD1 and / or the second floating diffusion FD2 to generate the pixel output signal Vout.

[0055] The selection transistor SX may be connected between the drive transistor DX and the column line CL. The selection signal SEL may be enabled sequentially in columns in the pixel array 10. The selection signal SEL may be input to the gate of the selection transistor SX. When the selection signal SEL may be enabled, the selection transistor SX may be turned on to transmit the pixel output signal Vout generated in the drive transistor DX to the selected column line CL.

[0056] The pixel transistors RX, DCX, DX, and SX in the pixel signal generating circuit 110 may include NMOS transistors. The connection structure of the pixel transistors may be changed to various other shapes.

[0057] The light receiving circuit 120 may include at least one light receiver. The light receiver may include a plurality of photoelectric conversion units configured to generate charges from exposed light. The light receiver may be connected to a floating diffusion. In example embodiments, the light receiver may include an odd number of photoelectric conversion units of more than one.

[0058] In example embodiments, when the pixel group PXG may include the first and second floating diffusions FD1 and FD2 , the light receiving circuit 120 of the pixel group PXG may include the first and second light receivers 120 a and 120 b .

[0059] The first light receiver 120a may be connected to the first floating diffusion FD1. The first light receiver 120a may include an odd number of photoelectric conversion units, for example, a first photoelectric conversion unit PD1, a second photoelectric conversion unit PD2, and a fourth photoelectric conversion unit PD4. The first light receiver 120a may also include a first transfer transistor TX1, a second transfer transistor TX2, and a fourth transfer transistor TX4 connected to the first photoelectric conversion unit PD1, the second photoelectric conversion unit PD2, and the fourth photoelectric conversion unit PD4, respectively. The first transfer transistor TX1, the second transfer transistor TX2, and the fourth transfer transistor TX4 may transfer charges generated by the first photoelectric conversion unit PD1, the second photoelectric conversion unit PD2, and the fourth photoelectric conversion unit PD4 to the first floating diffusion FD1. Therefore, the drains of the first transfer transistor TX1, the second transfer transistor TX2, and the fourth transfer transistor TX4 may correspond to the first floating diffusion FD1. The sources of the first transfer transistor TX1, the second transfer transistor TX2, and the fourth transfer transistor TX4 may correspond to the first photoelectric conversion unit PD1, the second photoelectric conversion unit PD2, and the fourth photoelectric conversion unit PD4. First, the first transmission signal TS1, the second transmission signal TS2, and the fourth transmission signal TS4 may be provided from the row driver 20. The first transmission signal TS1, the second transmission signal TS2, and the fourth transmission signal TS4 may be enabled at the same timing or at different timings.

[0060] The second light receiver 120b may have a structure substantially the same as that of the first light receiver 120a. For example, the second light receiver 120b may include a third photoelectric conversion unit PD3, a fifth photoelectric conversion unit PD5, and a sixth photoelectric conversion unit PD6, and a third transfer transistor TX3, a fifth transfer transistor TX5, and a sixth transfer transistor TX6. Similar to the operation of the first light receiver 120a, the second light receiver 120b may transmit charges generated by the third photoelectric conversion unit PD3, the fifth photoelectric conversion unit PD5, and the sixth photoelectric conversion unit PD6 to the second floating diffusion FD2 in response to the third transfer signal TS3, the fifth transfer signal TS5, and the sixth transfer signal TS6.

[0061] like Figure 2A As shown, the first floating diffusion portion FD1 and the second floating diffusion portion FD2 may be electrically connected to each other to transfer the total charge generated by the first floating diffusion portion FD1 and the second floating diffusion portion FD2 to the gate of the driving transistor DX. Figure 2B As shown, the charges of the first floating diffusion FD1 and the second floating diffusion FD2 can be selectively added in response to the conduction of the drive of the dual conversion signal DCS. The amount of charge of the first floating diffusion FD1 and the second floating diffusion FD2 can be controlled by selectively driving the transfer transistors TX1 to TX6. For example, the pixel group PXG can be configured with (3×1) sub-pixels by driving the transfer transistors TX1 to TX3 in the first light receiver 120a or by driving the transfer transistors TX4 to TX6 in the second light receiver 120b. The total charge of the first floating diffusion FD1 and the second floating diffusion FD2 can be converted into a pixel output signal Vout by the pixel signal generating circuit 110. The column driver 30, the output circuit 40 and the image processor 70 can convert the pixel output signal Vout into an image signal.

[0062] Operations of the pixel signal generating circuit 110 and the light receiving circuit 120 may be disclosed in Korean Patent Application No. 2021-00194335, which is incorporated herein by reference in its entirety.

[0063] In an example embodiment, the pixel signal generating circuit 110 may be included in one pixel group PXG, but is not limited thereto. For example, the pixel signal generating circuit 110 may be included in a plurality of pixel groups PXG. In addition, the pixel signal generating circuit 110 may have various configurations and arrangements. In addition, the transfer transistors TX1 to TX6 may be the light receiving circuit 120, but are not limited thereto. For example, the transfer transistors TX1 to TX6 may be interpreted as pixel transistors.

[0064] Figure 3A and Figure 3B is a plan view illustrating a pixel group according to an example embodiment, Figure 4A is along Figure 3A A cross-sectional view taken along line IIIa-IIIa′ in FIG. Figure 4B is along Figure 3A A cross-sectional view taken along line IIIb-IIIb′ in FIG. Figure 4C is along Figure 3A The cross-sectional view taken along line IIIc-IIIc′ in FIG. Figure 4D is along Figure 3AFor reference, a pixel group PXG including (3×2) sub-pixels may be exemplarily described in an example embodiment. Figure 3A The pixel groups in are based on Figure 2A Plan view of the equivalent circuit diagram in . Figure 3B The pixel groups in are based on Figure 2B Plan view of the equivalent circuit diagram in .

[0065] Reference Figure 3A and FIG. 4A to FIG. 4D , the pixel group PXG may include a first active region ACT1, a second active region ACT2, and a light receiving region SA. The light receiving region SA may include a plurality of sub-pixels sp1 to sp6.

[0066] The first active region ACT1, the second active region ACT2, and the light receiving region SA may be formed in the substrate 200. The first active region ACT1, the second active region ACT2, and the light receiving region SA may be defined by an isolation structure ISO in the substrate 200.

[0067] The substrate 200 may have a first surface 200a and a second surface 200b opposite to the first surface 200a. Figure 2A and Figure 2B The transistors DCX, RX, DX, and SX and the transfer transistors TX1 to TX6 in the pixel signal generating circuit 110 may be formed in the first surface 200 a of the substrate 200 , that is, in the front surface of the substrate 200 .

[0068] A plurality of color filters (not shown) and a plurality of micro lenses may be disposed on the second surface 200b of the substrate 200, that is, on the rear surface of the substrate 200. For example, light transmitted from an object may be incident through the second surface 200b of the substrate 200.

[0069] In example embodiments, the substrate 200 may include a semiconductor substrate including an element of Group IV on the periodic table. For example, the substrate 200 may include a single crystal silicon substrate. A thinning process may be performed on the substrate 200 to reduce the thickness of the substrate 200. In addition, the substrate 200 may include a single crystal silicon layer having an epitaxial layer. Alternatively, the substrate 200 may include conductive impurities or a conductive well.

[0070] The isolation structure ISO may be configured to contact at least one of the first surface 200a and the second surface 200b of the substrate 200. The isolation structure ISO may include a trench formed through the substrate 200 and a deep trench isolation (DTI) structure formed in the trench. The DTI may include an insulating material. For example, the DTI type isolation structure ISO may be formed by a back deep trench isolation (BDTI) process or a front deep trench isolation (FDTI) process. In addition, the isolation structure ISO may have a structure including a DTI structure and a junction isolation structure.

[0071] The isolation structures ISO having the same shape may be configured to be electrically isolated from each other between the first active area ACT1 and the light receiving area SA, between the second active area ACT2 and the light receiving area SA, and between the sub-pixels of the light receiving area SA. Alternatively, the isolation structures ISO having different shapes may be configured to be electrically isolated from each other between the first active area ACT1 and the light receiving area SA, between the second active area ACT2 and the light receiving area SA, and between the sub-pixels of the light receiving area SA.

[0072] In example embodiments, the first and second active regions ACT1 and ACT2 located between the light receiving regions SA may be positioned to extend in parallel in a first direction D1 (eg, a row direction).

[0073] like Figure 3A and Figure 4A As shown, the dual conversion transistor DCX and the reset transistor RX may be formed in the first active region ACT1.

[0074] To integrate the dual conversion transistor DCX and the reset transistor RX as NMOS transistors in the first active area ACT1, a first conductivity type well 205a, for example, a p-well, may be formed in the substrate 200 in the first active area ACT1. The first active area ACT1 may correspond to an optical black area configured to distinguish a color filter.

[0075] The dual conversion gate 220a and the reset gate 220b may be formed in the first active region ACT1. The dual conversion gate 220a and the reset gate 220b may be spaced apart from each other. The gate insulating layer 210 may be interposed between the dual conversion gate 220a and the surface of the first active region ACT1 (i.e., the first surface 200a), and between the reset gate 220b and the surface of the first active region ACT1. The junction regions 240a, 240b, and 240c may be formed in the first active region ACT1 on both sides of the dual conversion gate 220a and the reset gate 220b to form the dual conversion transistor DCX and the reset transistor RX. The junction regions 240a, 240b, and 240c may include a second type impurity, such as an N-type, opposite to the first conductivity type. The junction region 240a may correspond to the source of the dual conversion transistor DCX. The junction region 240b may correspond to the drain of the dual conversion transistor DCX and the source of the reset transistor RX. The junction region 240c may correspond to the drain of the reset transistor RX. based on Figure 2A , the source 240a of the dual conversion transistor DCX may be electrically floated. The gate of the dual conversion transistor DCX (hereinafter, referred to as the dual conversion gate 220a) may have a width wider than the width of the gate of the reset transistor RX (hereinafter referred to as the reset gate 220b), but is not limited thereto. Reference numeral 230 may be a gate sidewall spacer. For example, the first active region ACT1 may have a pattern shape corresponding to each pixel group PXG, but is not limited thereto.

[0076] Reference Figure 3A and Figure 4B , the driving transistor DX and the selection transistor SX may be formed in the second active region ACT2. Figure 2A and Figure 2B As shown, since the driving transistor DX and the selection transistor SX may include NMOS transistors, the second active region ACT2 may include a well 205a of the first conductivity type, ie, a p-well. Similar to the first active region ACT1, the second active region ACT2 may be formed at a position corresponding to an optical black region (not shown).

[0077] The gate of the drive transistor DX (hereinafter referred to as the drive gate 220c) and the gate of the select transistor SX (hereinafter referred to as the select gate 220d) may be located above the second active region ACT2, and the gate insulating layer 210 may be formed between the two gates and the second active region. As described above, because the drive transistor DX may be driven as a source follower configured to amplify the charge generated in the floating diffusions FD1 and FD2, the drive transistor DX may have a relatively high driving force compared to the other pixel transistors RX, DCX, SX, and TX1 to TX6. Therefore, the drive gate 220c may have a wider width than the widths of the select gate 220d, the dual conversion gate 220a, and the reset gate 220b.

[0078] The junction regions 240d, 240e and 240f may be formed in the second active region ACT2 on both sides of the drive gate 220c and the select gate 220d to form the drive transistor DX and the select transistor SX. The junction regions 240d, 240e and 240f may include a second type impurity, such as an N-type, opposite to the first conductivity type. The junction region 240d may correspond to the drain of the drive transistor DX. The junction region 240e may correspond to the source of the drive transistor DX and the drain of the select transistor SX. The junction region 240f may correspond to the source of the select transistor SX. In addition, the second active region ACT2 may have a pattern shape separated from the pixel group PXG, but is not limited thereto.

[0079] Reference Figure 3A , Figure 4C and Figure 4D , Figure 2A and Figure 2B The light receiving circuit 120 and the first and second floating diffusion portions FD1 and FD2 may be integrated in the light receiving area SA.

[0080] In example embodiments, the light receiving area SA may include first to sixth sub-pixels sp1 to sp6 arranged in a (3×2) matrix.

[0081] For example, one row R may include a first sub-row SR1, a second sub-row SR2, and a third sub-row SR3. The first sub-pixel sp1 and the fourth sub-pixel sp4 may be arranged side by side in the first sub-row SR1. The second sub-pixel sp2 and the fifth sub-pixel sp5 may be arranged side by side in the second sub-row SR2. The third sub-pixel sp3 and the sixth sub-pixel sp6 may be arranged side by side in the third sub-row SR3.

[0082] One column C substantially perpendicular to the row R may include first and second sub-columns SC1 and SC2 arranged in parallel. First to third sub-pixels sp1 to sp3 may be arranged side by side in the first sub-column SC1. Fourth to sixth sub-pixels sp4 to sp6 may be arranged side by side in the second sub-column SC2.

[0083] The first sub-pixel sp1 to the sixth sub-pixel sp6 may be electrically isolated from each other by an isolation structure ISO. The photoelectric conversion units PD1 to PD6 and the gates of the transfer transistors (hereinafter referred to as transfer gates: 220-1 to 220-6) may be formed in a space defined by the sub-pixels sp1 to sp6. Hereinafter, the sub-pixel sp may be a region in which a photoelectric conversion unit and a transfer gate may be integrated.

[0084] In an exemplary embodiment, Figure 2A and Figure 2BThe first light receiver 120a in the embodiment may include a first sub-pixel sp1, a second sub-pixel sp2, and a fourth sub-pixel sp4. The second light receiver 120b may include a third sub-pixel sp3, a fifth sub-pixel sp5, and a sixth sub-pixel sp6.

[0085] As described above, each of the photoelectric conversion units PD1 to PD6 may generate charges corresponding to the exposure amount of light incident through the second surface 200b of the substrate 200. The photoelectric conversion units PD1 to PD6 may include photodiodes, phototransistors, photogates, pinned photodiodes, combinations thereof, and the like.

[0086] In example embodiments, the photoelectric conversion units PD1 to PD6 may be formed in the substrate 200 divided into sub-pixels sp1 to sp6. For example, the photoelectric conversion units PD1 to PD6 may include a second conductive type impurity region n and a first heavily doped impurity region p + For example, the first heavily doped impurity region p + The first heavily doped impurity region p + May be configured to be in contact with the second conductivity type impurity region n.

[0087] The first floating diffusion FD1 may be formed at a contact point between the first sub-pixel sp1, the second sub-pixel sp2, the fourth sub-pixel sp4, and the fifth sub-pixel sp5. The second floating diffusion FD2 may be formed at a contact point between the second sub-pixel sp2, the third sub-pixel sp3, the fifth sub-pixel sp5, and the sixth sub-pixel sp6. The first floating diffusion FD1 and the second floating diffusion FD2 may include an impurity region of a second conductive type, for example, an n-type impurity region.

[0088] The first floating diffusion FD1 may be surrounded by the first transfer gate 220-1, the second transfer gate 220-2, and the fourth transfer gate 220-4. For example, the first transfer gate 220-1 and the second transfer gate 220-2 may be arranged symmetrically to each other with respect to the boundary BR1 between the first sub-row SR1 and the second sub-row SR2. That is, the second transfer gate 220-2 may have a shape formed by rotating the first transfer gate 220-1 by about 90° in the counterclockwise direction. The first transfer gate 220-1 and the fourth transfer gate 220-4 may be arranged folded symmetrically to each other with respect to the boundary BC1 between the first sub-column SC1 and the second sub-column SC2. That is, the fourth transfer gate 220-4 may have a shape formed by rotating the first transfer gate 220-1 by about 90° in the clockwise direction.

[0089] The second floating diffusion FD2 may be surrounded by the third transfer gate 220-3, the fifth transfer gate 220-5, and the sixth transfer gate 220-6. For example, the third transfer gate 220-3 and the sixth transfer gate 220-6 may be arranged folded symmetrically with respect to the boundary BC1 between the first sub-column SC1 and the second sub-column SC2. The sixth transfer gate 220-6 may have a shape formed by rotating the third transfer gate 220-3 by about 90° in the counterclockwise direction. The fifth transfer gate 220-5 and the sixth transfer gate 220-6 may be arranged folded symmetrically with respect to the boundary BR2 between the second sub-row SR2 and the third sub-row SR3. The sixth transfer gate 220-6 may have a shape formed by rotating the fifth transfer gate 220-5 by about 90° in the clockwise direction.

[0090] The transfer gates 220-1 and 220-4 located on the first sub-row SR1 and the transfer gates 220-3 and 220-6 located on the third sub-row SR3 may be symmetrical to each other about the second direction D2. The second transfer gate 220-2 and the fifth transfer gate 220-5 located on the second sub-row SR2 may be symmetrical to each other about the diagonal direction D3. For example, the second transfer gate 220-2 and the fifth transfer gate 220-5 may be symmetrical to each other twice about the first direction D1 and the second direction D2.

[0091] Therefore, the second transfer gate 220-2 and the third transfer gate 220-3 on the first sub-column SC1 may have substantially the same shape. The fourth transfer gate 220-4 and the fifth transfer gate 220-5 on the second sub-column SC2 may have substantially the same shape.

[0092] As above, the sub-pixels sp1 to sp6 may include transmission gates 220-1 to 220-6 and photoelectric conversion units PD1 to PD6, respectively. The photoelectric conversion units PD1 to PD6 may be sources of transmission transistors TX1 to TX6. The photoelectric conversion units PD1 to PD6 may be formed in the light receiving area SA on one side of each transmission gate 220-1 to 220-6. The floating diffusion FD1 or FD2 may be a drain of each transmission transistor TX1 to TX6.

[0093] In example embodiments, although an odd number of photoelectric conversion units PD may be connected to one floating diffusion FD1 or FD2 through transfer transistors TX1 to TX6, an even number of floating diffusions FD1 and FD2 may be provided to a light receiving area SA of the pixel group PXG such that the even number of photoelectric conversion units PD1 to PD6 may be arranged symmetrically with each other in all directions.

[0094] As described above, the sub-pixels sp1 to sp6 having the photoelectric conversion units PD1 to PD6 can be electrically isolated from each other by the full isolation type isolation structure ISO. Figure 4CAs shown, the isolation structure ISO at the region where the first and second floating diffusions FD1 and FD2 may be formed may extend from a portion that may be spaced apart from the bottom surface of the first and second floating diffusions FD1 and FD2 to the second surface 200 b of the substrate 200 .

[0095] Reference numeral DFD may be a dummy floating diffusion. In order to provide photoelectric conversion units PD1 to PD6 of uniform area, a dummy floating diffusion DFD may be arranged between sub-pixels sp1, sp3, sp4, and sp6 on the first sub-row SR1 and the third sub-row SR3. The dummy floating diffusion DFD may be formed by a process substantially the same as that of forming the first floating diffusion FD1 and the second floating diffusion FD2. However, the dummy floating diffusion DFD may be electrically floated without connecting the first floating diffusion FD1 and the second floating diffusion FD2.

[0096] In addition, the first floating diffusion portion FD1 and the second floating diffusion portion FD2 may be arranged side by side in the second direction D2. Figure 2A When the equivalent circuit diagram of FIG. 1 is shown, the first floating diffusion portion FD1 may be electrically connected to the second floating diffusion portion FD2 through the first conductive line L1. The first conductive line L1 may be located on a boundary between the second sub-pixel sp2 and the fifth sub-pixel sp5.

[0097] The first floating diffusion FD1 may be electrically connected to the drain 240b of the double conversion transistor DCX through a second conductive line L2. The second conductive line L2 may be located on a boundary between the first sub-pixel sp1 and the fourth sub-pixel sp4.

[0098] The second floating diffusion FD2 may be electrically connected to the driving gate 220c through a third conductive line L3. The third conductive line L3 may be located on a boundary between the third sub-pixel sp3 and the sixth sub-pixel sp6.

[0099] Although the first to third wires L1 to L3 may include an opaque material, since the first to third wires L1 to L3 may be located above an isolation structure ISO configured to isolate sub-pixels from each other, the fill factor of the light receiving area, i.e., the photoelectric conversion units PD1 to PD6 may not be affected.

[0100] The first to third wires L1 to L3 may be located on the same plane. Alternatively, any one of the first to third wires L1 to L3 may be located at a height different from the height at which the remaining wires may be located. In example embodiments, the height of the first to third wires L1 to L3 may be the distance between the first to third wires L1 to L3 and the first surface 200a of the substrate 200.

[0101] When the pixel group PXG can be based on Figure 2BWhen the equivalent circuit diagram is formed, Figure 3B As shown, the first floating diffusion portion FD1 can be electrically isolated from the second floating diffusion portion FD2. That is, the first floating diffusion portion FD1 can be electrically isolated from the second floating diffusion portion FD2. Figure 3A In contrast, the source 240a of the dual conversion transistor DCX may be connected to the second floating diffusion FD2 via a fourth wire L4. By driving the dual conversion transistor DCX, the first floating diffusion FD1 may be selectively connected to the second floating diffusion FD2. The fourth wire L4 may be arranged above the isolation structure ISO or in an area corresponding to an optical black area (not shown) to reduce the impact on the fill factor of the pixel group PXG.

[0102] Figure 5 is a plan view illustrating a pixel array according to an example embodiment, and Figure 6 is an example with Figure 5 A three-dimensional diagram of an image sensing device with a pixel array in FIG.

[0103] Reference Figure 5 and Figure 6 , the image sensing device 100a may include a pixel array 10a and a color filter layer 300a.

[0104] The pixel array 10a may include a plurality of pixel groups PXG1 to PXG6 arranged in a matrix type between a plurality of rows R1 and R2 and a plurality of columns C1, C2, and C3. The plurality of pixel groups PXG1 to PXG6 may be integrated on a first surface 200a of a substrate 200. Each of the pixel groups PXG1 to PXG6 may include Figure 3A or Figure 3B Sub-pixels sp1 to SP6 are arranged in a matrix type.

[0105] In example embodiments, the first to third pixel groups PXG1 to PXG3 may be arranged side by side along the first row R1. Figure 1 By the signal for selecting the first row R1 provided from the row driver 20 in the embodiment, all of the first pixel groups PXG1 to the third pixel groups PXG3 on the first row R1 may be selected. The fourth pixel groups PXG4 to the sixth pixel groups PXG6 may be arranged side by side along the second row R2 substantially parallel to the first row R1. By the signal for selecting the second row R2 provided from the row driver 20, all of the fourth pixel groups PXG4 to the sixth pixel groups PXG6 on the second row R2 may be selected.

[0106] The first pixel group PXG1 and the fourth pixel group PXG4 may be arranged side by side on the first column C1. Figure 1 The pixel output signals of the first pixel group PXG1 or the fourth pixel group PXG4 are read out using the signal for selecting the first column C1 provided by the column driver 30 in FIG.

[0107] The second pixel group PXG2 and the fifth pixel group PXG5 may be arranged side by side on the second column C2. A pixel output signal of the second pixel group PXG2 or the fifth pixel group PXG5 may be read out by a signal for selecting the second column C2 provided from the column driver 30.

[0108] The third pixel group PXG3 and the sixth pixel group PXG6 may be arranged side by side on the third column C3. A pixel output signal of the third pixel group PXG3 or the sixth pixel group PXG6 may be read out by a signal for selecting the third column C3 provided from the column driver 30.

[0109] For example, it can be formed Figure 2A or Figure 2B The active areas ACT1 and ACT2 of the pixel signal generating circuit 110 in the pixel signal generating circuit 110 may extend in the first direction D1 outside the light receiving area SA of the pixel group PXG. The first active area ACT1 in which the reset transistor RX and the dual conversion transistor DCX for controlling the first pixel group PXG1 to the third pixel group PXG3 may be formed may be arranged outside the first row R1 opposite to the first pixel group PXG1 to the third pixel group PXG3. The first active area ACT1 in which the reset transistor RX and the dual conversion transistor DCX for controlling the fourth pixel group PXG4 to the sixth pixel group PXG6 may be formed may be arranged outside the second row R2 opposite to the fourth pixel group PXG4 to the sixth pixel group PXG6.

[0110] The second active region ACT2 in which the drive transistor DX and the select transistor SX may be formed may be arranged to correspond to the pixels between the first row R1 and the second row R2 .

[0111] In example embodiments, the first pixel group PXG1 and the fourth pixel group PXG4 may share the driving transistor DX and the selecting transistor SX integrated in the second active region ACT2. Figure 5 In the embodiment, the pixel groups arranged adjacently along the second direction D2 may share the drive transistor DX and the selection transistor SX, but are not limited thereto. For example, the adjacent pixel groups may share the dual conversion transistor DCX and the reset transistor RX through various design variations. The arrangement of the pixel signal generating circuit 110 may be changed in various ways without affecting the light receiving area. The pixel output signal of the pixel group selected by various control signals (e.g., the selection signal SEL) that may be provided from the row driver 20 and the column driver 30 may be generated.

[0112] The color filter layer 300a may be arranged on the second surface 200b of the substrate 200. The color filter layer 300a may include a plurality of color filters 320 and an optical black area 330a. Each of the plurality of color filters 320 may be divided by the optical black area 330a. The plurality of color filters 320 may include primary color filters. The plurality of color filters 320 may include first color filters 320a to third color filters 320c having different colors. For example, the first color filter 320a to the third color filter 320c may include a green color filter (G), a red color filter (R), and a blue color filter (B), respectively. The first color filter 320a to the third color filter 320c may be arranged in a Bayer pattern, but is not limited thereto. Alternatively, the first color filter 320a to the third color filter 320c may include a cyan color filter, a magenta color filter, a yellow color filter, etc.

[0113] Each of the plurality of pixel groups PXG1 to PXG6 may correspond to each of the color filters 320a to 320c. The size of each color filter 320a to 320c may correspond to the size of the light receiving area SA of each pixel group PXG1 to PXG6. For example, when the first pixel group PXG1 may correspond to the first color filter 320a, the pixel output signal Vout of the first pixel group PXG1 may output first color information about incident light on an object (not shown). For example, a pixel output signal Vout corresponding to one of the color filters 320a, 320b, or 320c may be generated based on charges collected from the photoelectric conversion units PD1 to PD6. Figure 6 , the direction D4 may be a depth direction of the substrate 200 .

[0114] Figure 7 is a plan view illustrating an extended pixel array according to an example embodiment, and Figure 8 is an example with Figure 7 A three-dimensional diagram of an image sensing device with an extended pixel array.

[0115] Reference Figure 7 and Figure 8 , the image sensing device 100b may include a pixel array 100b and a color filter layer 300b.

[0116] The pixel array 10b may include a plurality of extended pixel groups EPX1 to EPX3 arranged in a matrix type. Each of the extended pixel groups EPX1 to EPX3 may include sub-pixels sp1 to sp12 arranged in a (6×2) matrix type. Hereinafter, the structure of the first extended pixel group EPX1 may be exemplarily explained.

[0117] In example embodiments, the first extended pixel group EPX1 may include a first pixel group PXG1 and a fourth pixel group PXG4 arranged side by side in the second direction D2. The first pixel group PXG1 may have Figure 5 The fourth pixel group PXG4 may have a configuration substantially similar to the structure of the first pixel group PXG1 in FIG. Figure 5 The structure of the fourth pixel group PXG4 is basically the same configuration.

[0118] It can form Figure 2A or Figure 2B The reset transistor RX and the first active area ACT1 of the dual conversion transistor DCX of the pixel signal generating circuit 110 can be connected to Figure 5 Similarly disposed at an upper edge portion of the first pixel group PXG1 . A second active region ACT2 in which the driving transistor DX and the selection transistor SX of the pixel signal generating circuit 110 may be formed may be disposed between the first pixel group PXG1 and the fourth pixel group PXG4 .

[0119] The first extended pixel group EPX1 may include first and second floating diffusions FD1 and FD2 of the first pixel group PXG1 (or the second pixel group PXG2 or the third pixel group PXG3) and third and fourth floating diffusions FD3 and FD4 of the fourth pixel group PXG4 (or the fifth pixel group PXG5 or the sixth pixel group PXG6) electrically connected to each other.

[0120] Specifically, the first pixel group PXG1 in the first extended pixel group EPX1 may include a conductive line La connected between the drain 240b of the dual conversion transistor DCX and the first floating diffusion FD1, between the first floating diffusion FD1 and the second floating diffusion FD2, and between the second floating diffusion FD2 and the driving gate 220c.

[0121] The fourth pixel group PXG4 in the first extended pixel group EPX1 may include a conductive line Lb connected between the driving gate 220 c and the third floating diffusion FD3 , and between the third floating diffusion FD3 and the fourth floating diffusion FD4 .

[0122] The charges collected in the (6×2) sub-pixels can be transferred to the driving gate 220c through the wires La and Lb, and the driving transistor DX can output the pixel output signal when the selection signal SEL is enabled. As described above, the amount of charge of the first floating diffusion FD1 to the fourth floating diffusion FD4 can be controlled by activating the transfer transistors TX1 to TX12 in each of the sub-pixels sp1 to sp12.

[0123] Alternatively, when the transmission gates 220-1 to 220-3 and 220-7 to 220-9 located in the first sub-column SC1 receive an enable signal and the transmission gates 220-4 to 220-6 and 220-10 to 220-12 located in the second sub-column SC2 receive a disable signal, the extended pixel group EPX can be configured with (6×1) sub-pixels (sp1 to sp3 and sp7 to sp9).

[0124] and Figure 6 Similarly, the color filter layer 300b may be disposed on the second surface 200b of the substrate 200. The color filter layer 300b may include a plurality of color filters 325 and an optical black region 330b. Figure 6 Similarly, each color filter 325 may include a first color filter 325a, a second color filter 325b, and a third color filter 325c. The size of each color filter 325a to 325c may correspond to the size of each extended pixel group EPX1 to EPX3.

[0125] Therefore, the pixel output signal output from the charges collected by the (6×1) or (6×2) sub-pixels may represent the information of the corresponding color filter 325 a , 325 b , or 325 c .

[0126] Fig. 9 is a plan view illustrating an extended pixel group according to an example embodiment, Fig.10 is a plan view illustrating an extended pixel group according to an example embodiment, and Fig.11 is a perspective view illustrating an image sensing device having an extended pixel group and an extended color filter according to example embodiments.

[0127] Reference Fig. 9 and Fig.11 , the image sensing device 100c may include a pixel array 10c and a color filter layer 300c.

[0128] The pixel array 10 c may include a plurality of extended pixel groups TPX1 to TPX4 arranged in a matrix type.

[0129] Each of the extended pixel groups TPX1 to TPX4 may include Figure 5 The sub-pixels sp1 to sp6 of each pixel group PXG are larger than the sub-pixels sp1 to sp9. For example, the extended pixel group TPX may include an odd number of sub-pixels.

[0130] For example, the extended pixel group TPX may include (3×3) sub-pixels sp1 to sp9 arranged between three sub-rows SR1 to SR3 and three sub-columns SC1 to SC3 that cross each other.

[0131] The first subpixel sp1, the fourth subpixel sp4 and the seventh subpixel sp7 may form a first subrow SR1, the second subpixel sp2, the fifth subpixel sp5 and the eighth subpixel sp8 may form a second subrow SR2, and the third subpixel sp3, the sixth subpixel sp6 and the ninth subpixel sp9 may form a third subrow SR3.

[0132] The first to third subpixels sp1, sp2, and sp3 may form a first subcolumn SC1. The fourth to sixth subpixels sp4, sp5, and sp6 may form a second subcolumn SC2. The seventh to ninth subpixels sp7, sp8, and sp9 may form a third subcolumn SC3.

[0133] The extended pixel group TPX may include first to fourth floating diffusions FD1 to FD4. The first floating diffusion FD1 may be formed at a contact point between at least three sub-pixels (e.g., a first sub-pixel sp1, a second sub-pixel sp2, a fourth sub-pixel sp4, and a fifth sub-pixel sp5). The second floating diffusion FD2 may be formed at a contact point between at least three sub-pixels (e.g., a second sub-pixel sp2, a third sub-pixel sp3, a fifth sub-pixel sp5, and a sixth sub-pixel sp6). The third floating diffusion FD3 may be formed symmetrically with respect to a boundary between the second sub-column SC2 and the third sub-column SC3 and the first floating diffusion FD1 at a contact point between the seventh sub-pixel sp7 and the eighth sub-pixel sp8. The fourth floating diffusion FD4 may be formed symmetrically with respect to a boundary between the second sub-column SC2 and the third sub-column SC3 and the second floating diffusion FD2 at a contact point between the eighth sub-pixel sp8 and the ninth sub-pixel sp9.

[0134] The first transfer gate 220-1 and the second transfer gate 220-2 of the first sub-column SC1 may be configured to surround the first floating diffusion portion FD1. The third transfer gate 220-3 may be configured to surround the second floating diffusion portion FD2. The first to third transfer gates 220-1 to 220-3 may have the same Figure 5 The arrangement of the first to third transfer gates 220 - 1 to 220 - 3 in FIG. 1 is substantially the same as that in FIG.

[0135] The fourth transfer gate 220-4 of the second sub-column SC2 may be configured to surround the first floating diffusion portion FD1 together with the first transfer gate 220-1 and the second transfer gate 220-2. The fifth transfer gate 220-5 and the sixth transfer gate 220-6 may be configured to surround the second floating diffusion portion FD2 together with the third transfer gate 210-3. The fourth transfer gate 220-4 to the sixth transfer gate 210-6 may have the same Figure 5 The arrangement of the fourth transfer gate 220 - 4 to the sixth transfer gate 210 - 6 in FIG. 1 is substantially the same arrangement.

[0136] The seventh to ninth photoelectric conversion units PD7 to PD9 and the seventh to ninth transfer gates 220-7 to 220-9 corresponding to the third sub-column SC3 may have substantially the same arrangement as the first to third photoelectric conversion units PD1 to PD3 and the first to third transfer gates 220-1 to 220-3 of the first sub-column SC1. For example, the seventh transfer gate 220-7 and the eighth transfer gate 220-8 may surround the third floating diffusion FD3. The ninth transfer gate 220-9 may surround the fourth floating diffusion FD4. In addition Figure 5 In addition to the pixel group PXG in the extended pixel group TPX, the extended pixel group TPX may also include at least one sub-column SC.

[0137] exist Figure 5 In the embodiment, the tenth to twelfth sub-pixels sp10, sp11, and sp12 corresponding to the fourth sub-column SC4 may be included in the second pixel group PXG2 together with the sub-pixels of the third sub-column SC3. Fig. 9 and Fig.10 , the tenth to twelfth subpixels sp10, sp11, and sp12 corresponding to the fourth subcolumn SC4 may be included in another adjacent extended pixel group TPX. In addition, different extended pixel groups TPX may share the third and fourth floating diffusions FD3 and FD4 in common.

[0138] In an example embodiment, the pixel signal generating circuits 110-1 and 110-2 may correspond to Figure 5 Each pixel group PXG in. Alternatively, two adjacent pixel signal generating circuits 110-1 and 110-2 may cooperate with each other to control one extended pixel group TPX. In addition, the pixel signal generating circuit may be reconfigured to match one extended pixel group TPX.

[0139] The light receiving areas of the (3×3) sub-pixels sp1 to sp9 may be symmetrical about the diagonal direction D3 and the first and second directions D1 and D2 to provide uniform light to all regions of the extended pixel group TPX.

[0140] Alternatively, if Fig.10 As shown, the pixel array 10d may include Fig. 9The first sub-column SC1 and the second sub-column of the pixel array 10c are the same as the first sub-column SC1 and the second sub-column. The pixel array 10d may further include a third sub-column SC3, and the third sub-column SC3 includes photoelectric conversion units PD7 to PD9 and transmission gates 220-7 to 220-9. The photoelectric conversion units PD7 to PD9 and the transmission gates 220-7 to 220-9 may be folded symmetrically with the photoelectric conversion units PD4 to PD6 and the transmission gates 220-4 to 220-6 of the fourth sub-pixel sp4 to the sixth sub-pixel sp6 of the second sub-column SC2 about the boundary between the second sub-column SC2 and the third sub-column SC3. That is, the photoelectric conversion units PD7 to PD9 and the transmission gates 220-7 to 220-9 of the seventh sub-pixel sp7 to the ninth sub-pixel sp9 may be symmetrical with the photoelectric conversion units PD4 to PD6 and the transmission gates 220-4 to 220-6 of the fourth sub-pixel sp4 to the sixth sub-pixel sp6 at about 180°. Therefore, the seventh transfer gate 220-7 may surround the third floating diffusion portion FD3. The eighth transfer gate 220-8 and the ninth transfer gate 220-9 may surround the fourth floating diffusion portion FD4.

[0141] Although the arrangement of the transmission gates 220 - 7 to 220 - 9 of the third sub-column SC3 may be changed, the light receiving regions may be uniformly disposed in the diagonal direction D3 and the first and second directions D1 and D2 .

[0142] In addition, the charges generated in the first sub-column SC1 and the second sub-column SC2 can be converted into pixel output signals by the pixel signal generating circuit 110-1 of the first pixel group PXG1 and the charges generated in the third sub-column SC3 can be converted into pixel output signals by the pixel signal generating circuit 110-2 of the second pixel group PXG2.

[0143] However, in the extended pixel group TPX of the example embodiment, the charges generated in the first sub-column SC1 and the second sub-column SC2 may not be read intermediately through the output node of the first pixel signal generating circuit 110-1 according to the known merging technology. Instead, the charges may be transferred to the register. The charges in the register may be added to the charges generated in the third sub-column SC3. The added charges may be converted into the output signal of the extended pixel group TPX by the pixel signal generating circuit 110-2 of the second pixel group PXG2. In order to add the charges of the photoelectric conversion units PD1 to PD9 in the extended pixel group TPX, the first floating diffusion FD1 to the fourth floating diffusion FD4 may be electrically connected to each other by direct connection or indirect connection. The direct connection method may use at least one wire. The indirect connection method may use serial or parallel register shift charges. When the pixel output signal of the extended pixel group TPX may be generated, all signals applied to the tenth transmission gate 220-10 to the twelfth transmission gate 220-12 may be disabled to prevent the charges generated in the fourth sub-column SC4 corresponding to other color filters from being mixed. The above operations may be examples of merging techniques, but are not limited thereto.

[0144] The color filter layer 300c may be disposed on the second surface 200b of the substrate 200. The color filter layer 300c may include first to third color filters 327a, 327b, and 327c and an optical black area 330c. The extended first to third color filters 327a, 327b, and 327c may have a size corresponding to the size of the extended pixel group TPX.

[0145] Specifically, each of the extended first color filter to the third color filter 327a, 327b and 327c may correspond to (3×3) sub-pixels. Therefore, the pixel output signal generated from an extended pixel group TPX may be a value converted from the charge transmitted by nine photoelectric conversion units. According to example embodiments, the area of ​​the pixel group may be controlled regardless of the number of pixel groups corresponding to one color filter. In addition, although an even or odd number of sub-pixels may form a group corresponding to one color filter, the light receiving area may be uniform in all directions.

[0146] In addition, binning techniques can be used to add the charges of multiple sub-pixels to improve the characteristics of high SNR and provide improved image quality when shooting at night.

[0147] The above embodiments of the present invention are intended to illustrate rather than limit the present disclosure. Various alternatives and equivalents are possible. The present invention is not limited to the embodiments described herein. The present invention is also not limited to any particular type of semiconductor device. In view of the present disclosure, other additions, reductions or modifications are obvious and are intended to fall within the scope of the appended claims.

[0148] CROSS-REFERENCE TO RELATED APPLICATIONS

[0149] This application claims the benefit of Korean Application No. 10-2021-0101554 filed on August 2, 2021, and Korean Application No. 10-2022-0064862 filed on May 26, 2022, in the Korean Intellectual Property Office, which are incorporated herein by reference.

Claims

1. An image sensing device, comprising: A plurality of pixel groups arranged in a matrix, each pixel group including 3x2 sub-pixels; as well as a first floating diffusion and a second floating diffusion, each of the first floating diffusion and the second floating diffusion being arranged between four adjacent sub-pixels among the 3×2 sub-pixels, wherein three sub-pixels among the four adjacent sub-pixels share one of the first floating diffusion and the second floating diffusion, Each of the 3×2 sub-pixels includes: a photoelectric conversion unit configured to convert incident light to generate electric charges; and a transfer gate disposed between the photoelectric conversion unit and a selected one of the first floating diffusion portion and the second floating diffusion portion, the transfer gate being adjacent to the selected one of the first floating diffusion portion and the second floating diffusion portion, and The 3x2 transfer gates of the 3x2 sub-pixels in the pixel group are arranged symmetrically with respect to a diagonal direction of the pixel group.

2. The image sensing device according to claim 1, wherein: The first floating diffusion is adjacent to three transmission gates among the 3×2 transmission gates, and the second floating diffusion is adjacent to the remaining three transmission gates among the 3×2 transmission gates. 3 . The image sensing device according to claim 1 , further comprising a color filter having a size corresponding to a size of the pixel group.

4. An image sensing device, comprising: a substrate having a first surface and a second surface opposite to the first surface; An extended pixel group, the extended pixel group comprising first to ninth subpixels arranged between first to third subcolumns and first to third subrows intersecting each other, wherein the first to third subpixels are arranged on the first subcolumn, the fourth to sixth subpixels are arranged on the second subcolumn, and the seventh to ninth subpixels are arranged on the third subcolumn; a first floating diffusion disposed at a contact point between the first sub-pixel, the second sub-pixel, the fourth sub-pixel, and the fifth sub-pixel; a second floating diffusion disposed at a contact point between the second sub-pixel, the third sub-pixel, the fifth sub-pixel, and the sixth sub-pixel; a third floating diffusion portion, the third floating diffusion portion being arranged symmetrically with the first floating diffusion portion with respect to a boundary between the second sub-column and the third sub-column at a contact point between the seventh sub-pixel and the eighth sub-pixel; as well as a fourth floating diffusion portion, the fourth floating diffusion portion being arranged symmetrically with respect to a boundary between the second sub-column and the third sub-column and at a contact point between the eighth sub-pixel and the ninth sub-pixel, and the second floating diffusion portion; Wherein, each of the first to ninth sub-pixels includes: a transmission gate surrounding any one of the first to fourth floating diffusions; and a photoelectric conversion unit arranged in the sub-pixel on one side of the transfer gate, Wherein, each of the first to fourth floating diffusion portions is surrounded by three transfer gates.

5. The image sensing device according to claim 4, wherein: The first floating diffusion is surrounded by a first transfer gate in the first sub-pixel, a second transfer gate in the second sub-pixel, and a fourth transfer gate in the fourth sub-pixel.

6. The image sensing device according to claim 4, wherein: The second floating diffusion is surrounded by a third transfer gate in the third sub-pixel, a fifth transfer gate in the fifth sub-pixel, and a sixth transfer gate in the sixth sub-pixel.

7. The image sensing device according to claim 4, wherein: The third floating diffusion is surrounded by a seventh transfer gate in the seventh sub-pixel and an eighth transfer gate in the eighth sub-pixel, and the fourth floating diffusion is surrounded by a ninth transfer gate in the ninth sub-pixel.

8. The image sensing device according to claim 4, wherein: The third floating diffusion is surrounded by a seventh transfer gate in the seventh sub-pixel, and the fourth floating diffusion is surrounded by an eighth transfer gate in the eighth sub-pixel and a ninth transfer gate in the ninth sub-pixel.

9. The image sensing device according to claim 4, wherein: The transfer gates on the first to third sub-pixels of the first sub-column have the same shape as that of the transfer gates on the seventh to ninth sub-pixels of the third sub-column.

10. The image sensing device according to claim 4, wherein: The transfer gates on the fourth to sixth subpixels of the second subcolumn have shapes symmetrical to those of the transfer gates on the seventh to ninth subpixels of the third subcolumn with respect to a boundary between the second and third subcolumns.

11. The image sensing device according to claim 4, wherein: The first to fourth floating diffusions are electrically connected to each other.

12. The image sensing device according to claim 4, wherein: A pixel signal generation circuit is integrated outside the extended pixel group, and the pixel signal generation circuit generates a pixel output signal based on an amount of charge generated by the first to fourth floating diffusions.

13. The image sensing device according to claim 12, wherein: The pixel signal generating circuit comprises: a first active region, the first active region being located in a region outside any sub-row of a first sub-row including the first sub-pixel, the fourth sub-pixel and the seventh sub-pixel and a third sub-row including the third sub-pixel, the sixth sub-pixel and the ninth sub-pixel; a second active region, the second active region being located in a region outside the remaining one of the first sub-row and the third sub-row; a reset transistor and a dual conversion transistor, the reset transistor and the dual conversion transistor being arranged in the first active region to commonly share a junction region with each other; and a driving transistor and a selecting transistor, the driving transistor and the selecting transistor being arranged in the second active region to commonly share a junction region with each other, The driving transistor is turned on based on the amount of charge.

14. The image sensing device according to claim 13, wherein: The first active area, the first to ninth subpixels of the extended pixel group, and the second active area are electrically isolated from each other by at least one isolation structure in the substrate, and any one of the isolation structures extends to the second surface of the substrate.

15. The image sensing device according to claim 4, further comprising: An extended color filter is disposed on the second surface of the substrate and has a size corresponding to a size of the extended pixel structure.

Images