Semiconductor structure preparation method, semiconductor structure and semiconductor memory

Abstract

Embodiments of the present application disclose a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method for preparing the semiconductor structure includes: providing a substrate; forming an isolation structure having a first depth in the substrate; forming a word line structure having a second depth in the substrate, wherein the word line structure is partially formed in the isolation structure, and the second depth is less than the first depth; etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure; and forming a first insulating layer covering the word line structure and the first trench on the substrate to form an air gap structure in the isolation structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor memory technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor memory. Background Art

[0002] When forming semiconductor devices such as Dynamic Random Access Memory (DRAM), it is necessary to ensure electrical isolation between components within the semiconductor device. Shallow Trench Isolation (STI) is a commonly used electrical isolation technology, particularly suitable for ultra-large-scale integrated devices. The STI structure facilitates higher levels of circuit integration. However, as semiconductor feature sizes continue to shrink, the capacitive coupling effect between word lines is becoming increasingly pronounced. Summary of the Invention

[0003] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor memory, which can not only reduce the capacitive coupling effect between word lines, but also reduce the influence of tip leakage.

[0004] The technical solution of this application is achieved as follows:

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising:

[0006] Providing a substrate; forming an isolation structure having a first depth in the substrate;

[0007] forming a word line structure having a second depth in the substrate, wherein the word line structure is partially formed in the isolation structure, and the second depth is less than the first depth;

[0008] Etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure;

[0009] A first insulating layer covering the word line structure and the first trench is formed on the substrate to form an air gap structure in the isolation structure.

[0010] In some embodiments, the cross-section of the isolation structure includes an upper portion and a lower portion, the upper portion is square, and the lower portion is in an inverted trapezoidal shape; the method further includes:

[0011] Based on the first trench having the third depth, the substrate is continuously etched in a direction perpendicular to the substrate to form a first trench having a fourth depth; and the fourth depth is greater than the first depth.

[0012] In some embodiments, before forming a first insulating layer covering the word line structure and the first trench on the substrate, the method further includes:

[0013] A second insulating layer is formed on the surface of the substrate exposed by the first trench.

[0014] In some embodiments, forming a second insulating layer on the surface of the substrate exposed by the first trench includes:

[0015] The surface of the substrate exposed by the first trench is oxidized to form the second insulating layer.

[0016] In some embodiments, forming a word line structure having a second depth in the substrate includes:

[0017] forming a word line trench having a second depth in the substrate, wherein the word line trench is partially formed in the isolation structure;

[0018] forming a gate dielectric layer on the sidewalls and bottom of the word line trench;

[0019] forming an adhesion layer on a surface of the gate dielectric layer;

[0020] Filling word line metal in the word line trench.

[0021] In some embodiments, forming a word line trench having a second depth in the substrate includes:

[0022] forming a mask layer and a patterned photoresist layer on the substrate in sequence;

[0023] transferring the pattern of the photoresist layer to the mask layer;

[0024] The substrate is etched using the mask layer as a mask to form the word line trench having the second depth.

[0025] In some embodiments, the method further comprises:

[0026] The adhesion layer and the word line metal are etched so that the upper surfaces of the adhesion layer and the word line metal after etching are lower than the upper surface of the substrate, thereby forming a word line top trench.

[0027] In some embodiments, forming a first insulating layer on the substrate covering the word line structure and the first trench includes:

[0028] Silicon nitride is deposited over the word line top trench, the substrate, and the first trench to form the first insulating layer.

[0029] In some embodiments, before etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure, the method further includes:

[0030] A protection layer is formed above the substrate to protect the substrate when the isolation structure is etched.

[0031] In some embodiments, etching the isolation structure along a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure includes:

[0032] Based on an etching selectivity ratio between different materials, the isolation structure is etched in a direction perpendicular to the substrate to form the first trench having a third depth.

[0033] In some embodiments, after forming a second insulating layer on the surface of the substrate exposed by the first trench, the method further includes:

[0034] The protective layer is removed.

[0035] In some embodiments, the word line structure is a buried word line structure.

[0036] In a second aspect, an embodiment of the present application provides a semiconductor structure, the semiconductor structure comprising:

[0037] substrate;

[0038] an isolation structure formed in the substrate and having a first depth;

[0039] a word line structure formed in the substrate and having a second depth, wherein the word line structure is partially formed in the isolation structure, and the second depth is less than the first depth;

[0040] a first trench formed in the isolation structure along a direction perpendicular to the substrate and having a third depth;

[0041] A first insulating layer is formed on the substrate and covers the word line structure and the first trench to form an air gap structure in the isolation structure.

[0042] In some embodiments, a cross-section of the isolation structure includes an upper portion and a lower portion; wherein the upper portion is square and the lower portion is in an inverted trapezoidal shape.

[0043] In some embodiments, the first trench is formed in the isolation structure and the substrate along a direction perpendicular to the substrate and has a fourth depth; wherein the fourth depth is greater than the first depth.

[0044] In some embodiments, the semiconductor structure further comprises:

[0045] A second insulating layer is formed on the surface of the substrate exposed by the first trench.

[0046] In some embodiments, the word line structure includes:

[0047] a word line trench formed in the substrate and having a second depth, wherein the word line trench is partially formed in the isolation structure;

[0048] a gate dielectric layer formed on the sidewalls and bottom of the word line trench;

[0049] an adhesion layer formed on a surface of the gate dielectric layer;

[0050] A word line metal is filled in the word line trench.

[0051] In some embodiments, upper surfaces of the adhesion layer and the word line metal are lower than an upper surface of the substrate.

[0052] In some embodiments, the word line structure is a buried word line structure.

[0053] In a third aspect, an embodiment of the present application provides a semiconductor memory, which includes a semiconductor structure as described in any one of the second aspects.

[0054] The present invention provides a method for fabricating a semiconductor structure, a semiconductor structure, and a semiconductor memory device. The method comprises providing a substrate; forming an isolation structure having a first depth in the substrate; forming a wordline structure having a second depth in the substrate, wherein the wordline structure is partially formed in the isolation structure, and the second depth is less than the first depth; etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure; and forming a first insulating layer on the substrate covering the wordline structure and the first trench to form an air gap structure in the isolation structure. Thus, by forming the air gap structure in the isolation structure, insulation is increased, thereby reducing not only the capacitive coupling effect but also the influence of tip leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic cross-sectional view of a conventional semiconductor structure provided in an embodiment of the present application;

[0056] Figure 2 A schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0057] Figure 3a A schematic cross-sectional view of a substrate with an isolation structure provided in an embodiment of the present application;

[0058] Figure 3bA schematic top view of a substrate with an isolation structure provided in an embodiment of the present application;

[0059] Figure 3c A schematic cross-sectional view of an isolation structure provided in an embodiment of the present application;

[0060] Figure 4a A schematic cross-sectional view of a structure obtained after forming a word line trench in a substrate according to an embodiment of the present application;

[0061] Figure 4b A schematic top view of a structure obtained after forming a word line trench in a substrate according to an embodiment of the present application;

[0062] Figure 5 A schematic cross-sectional view of a structure obtained after forming a word line structure in a substrate according to an embodiment of the present application;

[0063] Figure 6 A schematic cross-sectional view of a structure obtained after forming a word line top trench in a word line structure according to an embodiment of the present application;

[0064] Figure 7 A schematic cross-sectional view of a structure obtained after forming a protective layer on a substrate provided in an embodiment of the present application;

[0065] Figure 8 A schematic cross-sectional view of a structure obtained after forming a first trench having a third depth according to an embodiment of the present application;

[0066] Figure 9 A schematic cross-sectional view of a structure obtained after forming a first trench having a fourth depth according to an embodiment of the present application;

[0067] Figure 10 A schematic cross-sectional view of a structure obtained after forming a second insulating layer provided in an embodiment of the present application;

[0068] Figure 11 A schematic cross-sectional view of a structure obtained after removing a protective layer provided in an embodiment of the present application;

[0069] Figure 12 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application;

[0070] Figure 13 A schematic cross-sectional comparison diagram of a semiconductor structure with an air gap structure and a semiconductor structure without an air gap structure provided in an embodiment of the present application;

[0071] Figure 14 A schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the applications. It should also be noted that for ease of description, only the portions relevant to the related applications are shown in the drawings.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0074] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0075] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0076] See also Figure 1 , which shows a cross-sectional schematic diagram of a conventional semiconductor structure provided by an embodiment of the present application. Figure 1 As shown, the conventional semiconductor structure may include a substrate, an isolation structure, and a wordline structure. The isolation structure may be a shallow trench isolation structure. Moore's Law exists in the semiconductor field, the core of which states that the number of transistors that can be accommodated on an integrated circuit doubles approximately every 18 months. As Moore's Law progresses, the feature size of semiconductors continues to shrink. However, as the feature size of semiconductors continues to shrink, the capacitive coupling effect between wordlines becomes increasingly pronounced.

[0077] Based on this, an embodiment of the present application provides a method for fabricating a semiconductor structure. The basic concept of the method is as follows: providing a substrate; forming an isolation structure having a first depth in the substrate; forming a wordline structure having a second depth in the substrate, wherein the wordline structure is partially formed in the isolation structure, and the second depth is less than the first depth; etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure; and forming a first insulating layer on the substrate covering the wordline structure and the first trench to form an air gap structure in the isolation structure. In this way, by forming the air gap structure in the isolation structure, the insulation of the semiconductor structure is effectively increased, thereby reducing not only the capacitive coupling effect between wordlines but also the impact of tip leakage.

[0078] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0079] In one embodiment of the present application, see Figure 2 , which shows a schematic flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present application. Figure 2 As shown, the method may include:

[0080] S101 , providing a substrate; and forming an isolation structure having a first depth in the substrate.

[0081] The substrate may include a doped or undoped single crystal silicon substrate, a polycrystalline silicon substrate, or the like. For example, an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. In the embodiments of the present application, a polycrystalline silicon substrate is used as an example for illustration, but is not specifically limited thereto.

[0082] In the examples of this application, see 3a and Figure 3b , Figure 3a It shows a cross-sectional schematic diagram of a substrate with an isolation structure provided by an embodiment of the present application. Figure 3b A schematic top view of a substrate with an isolation structure provided by an embodiment of the present application is shown; wherein, Figure 3a For Figure 3b Schematic diagram of the cross section in the AA' direction.

[0083] Among them, Figure 3a As shown, a substrate 10 is provided and etched to form a trench. A deposited filler material is deposited in the trench to form an isolation structure 11. The deposited filler material may include an insulating material such as silicon nitride. The isolation structure 11 has a first depth H1 and defines multiple active regions in the substrate 10.

[0084] It should also be noted that if Figure 3cAs shown, it shows a cross-sectional schematic diagram of an isolation structure provided by an embodiment of the present application. In one embodiment of the present application, the cross section of the isolation structure 11 may include an upper portion and a lower portion, and the upper portion is square and the lower portion is inverted trapezoidal. The specific implementation of the embodiment of the present application is described by taking the isolation structure 11 with such structural features as an example. Figure 3c As shown, the white square frame depicts the square outline of the upper cross-section of the isolation structure 11, and the black trapezoidal frame depicts the inverted trapezoidal outline of the lower cross-section of the isolation structure 11. It is understandable that the isolation structure 11 may also have other forms known to those skilled in the art. For example, the cross-sectional shape of the isolation structure 11 may also be "U-shaped at the top and V-shaped at the bottom", or the cross-sectional shape of the isolation structure 11 may also be "U-shaped or V-shaped as a whole", or the cross-sectional shape of the isolation structure 11 may also be "inverted trapezoidal or square as a whole", etc., and the embodiments of the present application do not specifically limit this.

[0085] S102 , forming a word line structure having a second depth in the substrate, wherein a portion of the word line structure is formed in the isolation structure, and the second depth is smaller than the first depth.

[0086] It should be noted that when the word line structure is formed in the substrate, the word line structure is also partially formed in the isolation structure. The word line structure has a second depth, and the second depth is smaller than the first depth.

[0087] It should also be noted that, in the embodiment of the present application, the wordline structure is a buried wordline (BW) structure.

[0088] In some embodiments, for S102, forming a word line structure having a second depth in the substrate may include:

[0089] forming a word line trench having a second depth in the substrate, wherein the word line trench is partially formed in the isolation structure;

[0090] forming a gate dielectric layer on the sidewalls and bottom of the word line trench;

[0091] forming an adhesion layer on a surface of the gate dielectric layer;

[0092] Filling word line metal in the word line trench.

[0093] It should be noted that, see Figure 4a and Figure 4b , Figure 4a FIG2 shows a cross-sectional schematic diagram of a structure obtained after forming a word line trench in a substrate according to an embodiment of the present application. Figure 4b FIG. 1 shows a schematic top view of a structure obtained after forming word line trenches in a substrate according to an embodiment of the present application; wherein, Figure 4a For Figure 4bSchematic diagram of the cross section in the AA' direction.

[0094] like Figure 4a As shown, a word line trench having a second depth H2 is formed in the substrate 10 , and the word line trench is partially formed in the isolation structure 11 .

[0095] Specifically, a plurality of wordline trenches can be formed by etching the substrate 10 and the isolation structure 11. Since the wordline structures are formed in the wordline trenches, the depth of the wordline trenches is also the second depth H2, and the second depth H2 is less than the second depth H1 of the isolation structure 11.

[0096] Furthermore, in some embodiments, forming a word line trench having a second depth in the substrate may include:

[0097] forming a mask layer and a patterned photoresist layer on the substrate in sequence;

[0098] transferring the pattern of the photoresist layer to the mask layer;

[0099] The substrate is etched using the mask layer as a mask to form a word line trench with a second depth.

[0100] It should be noted that when forming the wordline trenches, the following method can be used: first, a mask layer and a patterned photoresist layer are sequentially formed on the substrate 10, and then the pattern of the photoresist layer is transferred to the mask layer through an etching process. The mask layer can be a single layer or a multi-layer mask layer. For example, the mask layer can include a stack of one or more of a silicon dioxide layer, a polysilicon layer, and a carbon layer. The mask layer can also include a stack of one or more of an anti-reflective layer and a silicon oxynitride layer.

[0101] After the pattern of the photoresist layer is transferred to the mask layer, the substrate 10 is etched using the mask layer as a mask to form a number of word line trenches. The etching gas may include chlorine, hydrogen bromide, and difluoromethane. Periodic radio frequency output can also be used to improve the time difference between ions and neutral particles staying on the substrate 10, thereby improving the uniformity of the word line trench depth.

[0102] according to Figure 4a and Figure 4b It can be seen that the word line trench is formed in the substrate 10 and is also partially formed in the isolation structure 11 .

[0103] After forming the word line trench, see Figure 5 , which shows a cross-sectional schematic diagram of a structure obtained after a word line structure is formed in a substrate according to an embodiment of the present application. Figure 5 As shown, a gate dielectric layer 12, an adhesion layer 13 and a word line metal 14 are sequentially formed in the word line trench, thereby obtaining a word line structure.

[0104] Specifically, a gate dielectric layer 12 is first formed on the sidewalls and bottom of the word line trench. The gate dielectric layer 12 is a high-k material such as silicon dioxide. The material of the gate dielectric layer 12 can also be silicon monoxide, silicon nitride, etc., and can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD) or rapid thermal oxidation (RTO).

[0105] After forming the gate dielectric layer 12 , an adhesion layer 13 may be formed on the surface of the gate dielectric layer 12 . The material of the adhesion layer 13 may include titanium nitride. The adhesion layer 13 may improve the adhesion between the subsequently formed word line metal 14 and the gate dielectric layer 12 .

[0106] After forming the adhesion layer 13, word line metal 14 is filled in the word line trench. The material of the word line metal 14 may include tungsten, etc. In some embodiments, the adhesion layer 13 may not be formed, and the word line metal 14 may be directly filled in the word line trench after forming the gate dielectric layer 12.

[0107] That is to say, in the embodiment of the present application, the word line structure is formed in the word line groove and includes three parts: the gate dielectric layer 12, the adhesion layer 13 and the word line metal 14; alternatively, the word line structure may also include only two parts: the gate dielectric layer 12 and the word line metal 14. In the embodiment of the present application, the word line structure including the gate dielectric layer 12, the adhesion layer 13 and the word line metal 14 is mainly taken as an example.

[0108] Furthermore, after forming the word line structure, in some embodiments, the method may further include:

[0109] The adhesion layer and the word line metal are etched so that the upper surfaces of the etched adhesion layer and the word line metal are lower than the upper surface of the substrate, thereby forming a word line top trench.

[0110] It should be noted that, see Figure 6 , which shows a cross-sectional schematic diagram of a structure obtained after forming a word line top trench in a word line structure provided by an embodiment of the present application. Figure 6 As shown, the adhesion layer 13 and the word line metal 14 are etched to form an opening above the word line structure, so that the upper surface of the adhesion layer 13 and the word line metal 14 after etching is lower than the upper surface of the substrate 10; the opening is the word line top groove, the lower surface of the word line top groove is the surface where the adhesion layer 13 and the word line metal 14 are located after etching, and the upper surface is in the same plane as the upper surface of the substrate 10.

[0111] S103 , etching the isolation structure along a direction perpendicular to the substrate to form a first trench with a third depth in the isolation structure.

[0112] It should be noted that after the word line structure is formed, the isolation structure may be etched in a direction perpendicular to the substrate, thereby forming a first trench with a third depth in the isolation structure.

[0113] For step S103, in some embodiments, before etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure, the method may further include: forming a protective layer above the substrate to protect the substrate when etching the isolation structure.

[0114] It should be noted that, before etching the isolation structure, in one embodiment of the present application, a protection layer may be formed on the substrate to protect the substrate when etching the isolation structure. Figure 7 , which shows a cross-sectional schematic diagram of a structure obtained after forming a protective layer on a substrate provided by an embodiment of the present application. Figure 7 As shown, a protective layer 15 is formed on the substrate 10. The process of forming the protective layer 15 may include in-situ growth, etc. The material of the protective layer 15 may include silicon dioxide. The function of the protective layer 15 is to protect the substrate 10 during the subsequent etching of the isolation structure 11 to prevent the substrate 10 from being etched.

[0115] After forming the protection layer 15, the isolation structure 11 is etched in a direction perpendicular to the substrate 10 to form a first trench having a third depth H3 in the isolation structure 11. Figure 8 , which shows a cross-sectional schematic diagram of a structure obtained after forming a first trench having a third depth provided in an embodiment of the present application.

[0116] When etching the isolation structure to form the first trench having the third depth, in some embodiments, etching the isolation structure along a direction perpendicular to the substrate to form the first trench having the third depth in the isolation structure may include:

[0117] Based on the etching selectivity ratio between different materials, the isolation structure is etched in a direction perpendicular to the substrate to form a first trench with a third depth.

[0118] It should be noted that, since the word line structure is partially formed in the isolation structure 11, that is, the gate dielectric layer 12 of the word line structure is in close contact with the isolation structure 11, in order to avoid damage to the gate dielectric layer 12 when etching the isolation structure 11, and also to avoid damage to the substrate 10, the isolation structure 11 can be etched based on the etching selectivity between different materials. Figure 8The isolation structure 11 in the vertical direction is removed in a direction perpendicular to the substrate 10 as shown in FIG. Since the material of the gate dielectric layer 12 may include silicon dioxide and the material of the isolation structure 11 may include silicon nitride, the silicon nitride in the vertical direction can be removed based on the etching selectivity of silicon dioxide and silicon nitride, thereby forming a first trench.

[0119] In addition, in the embodiment of the present application, the cross-section of the isolation structure 11 includes an upper portion and a lower portion, the upper portion is square, and the lower portion is in an inverted trapezoidal shape. Based on the isolation structure 11 having such structural features, the method may further include:

[0120] Based on the first trench of the third depth, the substrate is continuously etched in a direction perpendicular to the substrate to form a first trench of a fourth depth; and the fourth depth is greater than the first depth.

[0121] It should be noted that, based on the "upper square and lower inverted trapezoidal" shape of the cross section of the isolation structure 11, the substrate 10 is further etched in a direction perpendicular to the substrate 10, so that the depth of the first trench is further deepened to a fourth depth H4, and the fourth depth is greater than the first depth of the isolation structure 11. Figure 9 , which shows a cross-sectional schematic diagram of a structure obtained after forming a first trench having a fourth depth provided in an embodiment of the present application.

[0122] like Figure 9 As shown, when the cross-section of the isolation structure 11 has a "square top and inverted trapezoidal bottom" shape, the first trench includes not only the portion formed by etching the isolation structure 11, but also the portion formed by continuing to etch downward into the substrate 10. In other words, in this case, the first trench can be divided into a first portion and a second portion; the first portion is formed by etching the isolation structure 11 in a direction perpendicular to the substrate 10, and the second portion is formed by continuing to etch the substrate 10 in a direction perpendicular to the substrate 10 based on the first portion. These two portions together constitute the first trench in this case.

[0123] It should also be noted that when etching the substrate 10 downward based on the first portion, an anisotropic etching method can be used so that the etching direction is downward, mainly etching the substrate 10 below the first portion, thereby reducing damage to the side surface of the substrate 10.

[0124] S104 , forming a first insulating layer on the substrate to cover the word line structure and the first trench, so as to form an air gap structure in the isolation structure.

[0125] It should be noted that after the first trench is formed, a first insulating layer covering the word line structure and the first trench is formed on the substrate, thereby sealing the first trench and forming an air gap structure.

[0126] Regarding step S104 , in some embodiments, before forming a first insulating layer covering the word line structure and the first trench on the substrate, the method may further include: forming a second insulating layer on the surface of the substrate exposed by the first trench.

[0127] It should be noted that, in the embodiment of the present application, after the first trench is formed, the first trench is formed between the substrate 10 and the isolation structure 11, and the first trench exposes a portion of the substrate 10. In order to further improve the insulation, a second insulating layer 16 is formed on the surface of the portion of the substrate 10 exposed by the first trench. Figure 10 , which shows a cross-sectional schematic diagram of a structure obtained after forming a second insulating layer provided in an embodiment of the present application.

[0128] Furthermore, in some embodiments, for the second insulating layer, forming the second insulating layer on the surface of the substrate exposed by the first trench may include: performing an oxidation treatment on the surface of the substrate exposed by the first trench to form the second insulating layer.

[0129] It should be noted that the second insulating layer 16 can be formed by directly oxidizing the exposed portion of the substrate 10. Specifically, the substrate 10 can be oxidized by in-situ steam generation to form the second insulating layer 16.

[0130] After forming the second insulating layer 16 to further enhance insulation, a first insulating layer can be formed covering the wordline structure and the first trench. Prior to this, the protective layer 15 needs to be removed. Therefore, in some embodiments, after forming the second insulating layer on the substrate surface exposed by the first trench, the method may further include removing the protective layer.

[0131] It should be noted that after forming the second insulating layer 16, the protective layer 15 is removed. Figure 11 , which shows a cross-sectional schematic diagram of a structure obtained after removing the protective layer provided in an embodiment of the present application.

[0132] Regarding forming the first insulating layer, in some embodiments, forming the first insulating layer covering the word line structure and the first trench on the substrate may include:

[0133] Silicon nitride is deposited on the word line top trench, the substrate and the first trench to form a first insulating layer.

[0134] It should be noted that an insulating material such as silicon nitride is deposited on the top trench of the word line, the substrate 10 and the first trench to form a first insulating layer 17, thereby obtaining a semiconductor structure. Figure 12 , which shows a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present application.

[0135] Furthermore, to prevent the deposited material from entering and filling the first trench during the deposition process, a rapid sealing method can be employed in this step, so that the deposited material only enters a relatively small depth above the first trench. Thus, after the top of the first trench is covered, an air gap structure 18 is formed. This air gap structure 18 effectively increases the insulation properties of the semiconductor structure, and the presence of the second insulating layer 16 further enhances the insulation properties.

[0136] In short, the present invention provides a method for preparing a semiconductor structure related to semiconductor memory technology, particularly to the structure and process of a memory device, using transistors to control digital signal storage for application in dynamic random access memory. The process of the method is briefly described as follows: first, a wordline trench of a buried wordline structure is formed in a substrate having STI, and silicon dioxide (gate dielectric layer), titanium nitride (adhesion layer) and tungsten (wordline metal) are sequentially formed in the wordline trench; then, excess titanium nitride and tungsten are etched away to form a wordline top trench; then, a layer of silicon dioxide (protective layer) is formed on the substrate surface by in-situ growth; then, the silicon nitride (STI) in the vertical direction is removed by etching the selectivity of silicon dioxide and silicon nitride; then, the polysilicon (substrate) is further etched downward to form a first trench, and the height of the first trench is greater than the height of the STI; then, the polysilicon in the first trench is oxidized by the ISSG method to form a second insulating layer to further increase the insulation; finally, the silicon dioxide at the top is removed and the top is covered with silicon nitride (first insulating layer).

[0137] See also Figure 13 , which shows a schematic cross-sectional comparison diagram of a semiconductor structure with an air gap structure and a semiconductor structure without an air gap structure provided by an embodiment of the present application, wherein: Figure 13 (a) is a schematic diagram of a semiconductor structure without an air gap structure. Figure 13 (b) is a schematic diagram of a semiconductor structure with an air gap structure. By forming an air gap structure in the STI, the insulation can be significantly improved, the capacitive coupling effect between word lines can be reduced, and the impact of tip leakage can be reduced.

[0138] This embodiment provides a method for fabricating a semiconductor structure, comprising providing a substrate; forming an isolation structure having a first depth in the substrate; forming a wordline structure having a second depth in the substrate, wherein the wordline structure is partially formed in the isolation structure, and the second depth is less than the first depth; etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure; and forming a first insulating layer on the substrate covering the wordline structure and the first trench to form an air gap structure in the isolation structure. Forming the air gap structure in the isolation structure thus increases insulation, thereby reducing not only capacitive coupling effects but also the influence of tip leakage.

[0139] In another embodiment of the present application, see the aforementioned Figure 12 , which shows a cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present application. Figure 12 As shown, the semiconductor structure may include:

[0140] substrate 10;

[0141] An isolation structure 11 is formed in the substrate 10 and has a first depth;

[0142] A word line structure is formed in the substrate 10 and has a second depth, wherein the word line structure is partially formed in the isolation structure 11, and the second depth is less than the first depth;

[0143] a first trench formed in the isolation structure 11 along a direction perpendicular to the substrate 10 and having a third depth;

[0144] A first insulating layer 17 is formed on the substrate 10 and covers the word line structure and the first trench to form an air gap structure 18 in the isolation structure 11 .

[0145] In some embodiments, the cross-section of the isolation structure 11 may include an upper portion and a lower portion; wherein the upper portion is square and the lower portion is in an inverted trapezoid.

[0146] In some embodiments, the first trench is formed in the isolation structure 11 and the substrate 10 along a direction perpendicular to the substrate 10 and has a fourth depth; wherein the fourth depth is greater than the first depth.

[0147] In some embodiments, the semiconductor structure may further include:

[0148] The second insulating layer 16 is formed on the surface of the substrate 10 exposed by the first trench.

[0149] In some embodiments, the word line structure may include:

[0150] a word line trench formed in the substrate 10 and having a second depth, wherein the word line trench is partially formed in the isolation structure 11;

[0151] A gate dielectric layer 12 is formed on the sidewalls and bottom of the word line trench;

[0152] an adhesion layer 13 formed on a surface of the gate dielectric layer 12;

[0153] The word line metal 14 is filled in the word line trench.

[0154] In some embodiments, upper surfaces of the adhesion layer 13 and the word line metal 14 are lower than an upper surface of the substrate 10 .

[0155] In some embodiments, the word line structure is a buried word line structure.

[0156] An embodiment of the present application provides a semiconductor structure comprising: a substrate; an isolation structure formed in the substrate and having a first depth; a wordline structure formed in the substrate and having a second depth, with the wordline structure partially formed in the isolation structure, and the second depth being less than the first depth; a first trench formed in the isolation structure in a direction perpendicular to the substrate and having a third depth; and a first insulating layer formed on the substrate and covering the wordline structure and the first trench, thereby forming an air gap structure in the isolation structure. Thus, by forming the air gap structure in the isolation structure of the semiconductor structure, insulation is enhanced, thereby reducing not only capacitive coupling effects but also the influence of tip leakage. Furthermore, because a second insulating layer is formed on the substrate surface within the air gap structure, insulation is further enhanced.

[0157] In another embodiment of the present application, see Figure 14 , which shows a schematic diagram of the composition structure of a semiconductor memory provided by an embodiment of the present application, such as Figure 14 As shown, the semiconductor memory 20 may include the semiconductor structure described in any one of the aforementioned embodiments.

[0158] In some embodiments, the semiconductor memory 20 may be a dynamic random access memory (DRAM).

[0159] As for the semiconductor memory 20, since it includes the semiconductor structure in the aforementioned embodiment, the semiconductor structure can reduce the capacitive coupling effect and the influence of tip leakage when the characteristic size of the semiconductor is reduced, thereby improving the storage capacity of the semiconductor memory.

[0160] The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.

[0161] It should be noted that, in this application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0162] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0163] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0164] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0165] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0166] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: Providing a substrate; forming an isolation structure having a first depth in the substrate; forming a word line structure having a second depth in the substrate, wherein the word line structure is partially formed in the isolation structure, and the second depth is less than the first depth; Etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure; forming a first insulating layer covering the word line structure and the first trench on the substrate to form an air gap structure in the isolation structure; wherein, The cross-section of the isolation structure includes an upper portion and a lower portion, the upper portion is square and the lower portion is in an inverted trapezoidal shape; the method further includes: Based on the first trench having the third depth, the substrate is continuously etched in a direction perpendicular to the substrate to form a first trench having a fourth depth; and the fourth depth is greater than the first depth.

2. The method according to claim 1, characterized in that Before forming a first insulating layer covering the word line structure and the first trench on the substrate, the method further includes: A second insulating layer is formed on the surface of the substrate exposed by the first trench.

3. The method according to claim 2, characterized in that The forming of a second insulating layer on the surface of the substrate exposed by the first trench comprises: The surface of the substrate exposed by the first trench is oxidized to form the second insulating layer.

4. The method according to claim 1, wherein The step of forming a word line structure having a second depth in the substrate includes: forming a word line trench having a second depth in the substrate, wherein the word line trench is partially formed in the isolation structure; forming a gate dielectric layer on the sidewalls and bottom of the word line trench; forming an adhesion layer on a surface of the gate dielectric layer; Filling word line metal in the word line trench.

5. The method according to claim 4, characterized in that The step of forming a word line trench having a second depth in the substrate comprises: forming a mask layer and a patterned photoresist layer on the substrate in sequence; transferring the pattern of the photoresist layer to the mask layer; The substrate is etched using the mask layer as a mask to form the word line trench having the second depth.

6. The method according to claim 4, characterized in that The method further comprises: The adhesion layer and the word line metal are etched so that the upper surfaces of the adhesion layer and the word line metal after etching are lower than the upper surface of the substrate, thereby forming a word line top trench.

7. The method according to claim 6, characterized in that The step of forming a first insulating layer on the substrate covering the word line structure and the first trench comprises: Silicon nitride is deposited over the word line top trench, the substrate, and the first trench to form the first insulating layer.

8. The method according to claim 2, characterized in that Before etching the isolation structure in a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure, the method further includes: A protection layer is formed above the substrate to protect the substrate when the isolation structure is etched.

9. The method according to claim 8, characterized in that The etching the isolation structure along a direction perpendicular to the substrate to form a first trench having a third depth in the isolation structure includes: Based on an etching selectivity ratio between different materials, the isolation structure is etched in a direction perpendicular to the substrate to form the first trench having a third depth.

10. The method according to claim 9, characterized in that After forming a second insulating layer on the surface of the substrate exposed by the first trench, the method further includes: The protective layer is removed.

11. The method according to claim 1, wherein The word line structure is a buried word line structure.

12. A semiconductor structure, characterized in that The semiconductor structure comprises: substrate; an isolation structure formed in the substrate and having a first depth; a word line structure formed in the substrate and having a second depth, wherein the word line structure is partially formed in the isolation structure, and the second depth is less than the first depth; a first trench formed in the isolation structure along a direction perpendicular to the substrate and having a third depth; a first insulating layer formed on the substrate and covering the word line structure and the first trench to form an air gap structure in the isolation structure; The cross section of the isolation structure includes an upper portion and a lower portion; wherein the upper portion is square and the lower portion is in an inverted trapezoidal shape; The first trench is formed in the isolation structure and the substrate along a direction perpendicular to the substrate and has a fourth depth; wherein the fourth depth is greater than the first depth.

13. The semiconductor structure according to claim 12, wherein: The semiconductor structure further comprises: A second insulating layer is formed on the surface of the substrate exposed by the first trench.

14. The semiconductor structure according to claim 12, wherein: The word line structure includes: a word line trench formed in the substrate and having a second depth, wherein the word line trench is partially formed in the isolation structure; a gate dielectric layer formed on the sidewalls and bottom of the word line trench; an adhesion layer formed on a surface of the gate dielectric layer; A word line metal is filled in the word line trench.

15. The semiconductor structure according to claim 14, wherein: Upper surfaces of the adhesion layer and the word line metal are lower than an upper surface of the substrate.

16. The semiconductor structure according to claim 12, wherein: The word line structure is a buried word line structure.

17. A semiconductor memory, characterized in that: Comprising the semiconductor structure according to any one of claims 12 to 16.

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