Measuring instrument and measuring method

Abstract

This invention provides a measuring device and a measuring method. In a structure including multiple modules with different maximum sampling rates, the waveforms of the output signals of each module can be compared in real time. The measuring device (10) includes: a first processing unit (12a) that performs first pipelined processing on a first input signal according to a first sampling timing; a second processing unit (12b) that performs second pipelined processing on a second input signal according to a second sampling timing with a sampling period longer than the first sampling timing; an adjustment unit that adjusts the output timing of the first input signal that has undergone first pipelined processing in conjunction with the output timing of the second input signal that has undergone second pipelined processing; and a production unit (17) that sequentially produces the waveform of the first input signal that has undergone first pipelined processing and whose output timing has been adjusted by the adjustment unit, and the waveform of the second input signal that has undergone second pipelined processing.

Description

[0001] Cross-referencing of related applications

[0002] This application claims priority to Japanese patent application 2021-132435, filed on August 16, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to a measuring instrument and a measuring method. Background Technology

[0004] A measuring device is known that takes various physical quantities as electrical signal inputs and measures their waveforms in real time. This type of measuring device generally takes electrical signals as analog signals as inputs and performs various signal processing operations on the input signals, including A / D (Analog-to-Digital) conversion. Among such measuring devices, a measuring device is known that includes multiple modules that perform signal processing on each input signal, thereby enabling real-time measurement and comparison of the waveforms of multiple input signals (Non-Patent Document 1).

[0005] Existing technical documents

[0006] Non-Patent Literature 1: Etsuro Nakayama and Chiaki Yamamoto, "Real-time Calculation Function of DL850 Encoder for Observation Instrument", Yokogawa Technical Report, Yokogawa Electric Corporation, 2012, Vol. 55, No. 1, pp. 9-14

[0007] Consider a measuring device comprising multiple modules. A common sampling signal with a predetermined sampling timing is input from an external source, and various signal processing operations, such as A / D conversion, are performed synchronously with the sampling timing represented by the sampling signal. Here, it is assumed that each module can handle a different maximum sampling rate (frequency). In this measuring device, if the sampling rate of the input sampling signal exceeds the maximum sampling rate of a subset of modules, the signal processing of those modules is delayed compared to the modules outside that subset. Therefore, the timing of signal processing completion will deviate between the modules whose sampling rate exceeds the maximum sampling rate and the other modules. If multiple signal processing operations in each module are executed via a pipeline, the cumulative deviation in the time required for each process within the pipeline results in a larger time deviation in the output signals of each module as a whole.

[0008] Therefore, in the existing structure, when the sampling rate of the sampled signal exceeds the maximum sampling rate of some modules (i.e., when the sampling period of the sampled signal is shorter than the maximum sampling period of some modules), it is not possible to compare the waveforms of the output signals of each module in real time and accurately. Especially when the sampling rate of the sampled signal varies over time, the deviation in the time required for signal processing in each module also varies, making it even more difficult to ensure that the output signals of each module are time-consistent and to compare them in real time within the existing structure. Summary of the Invention

[0009] The purpose of this invention is to provide a measuring instrument and a measuring method that can compare the waveforms of the output signals of each module in real time in a structure comprising multiple modules with different maximum sampling rates.

[0010] One embodiment of the measuring device is a waveform measuring device for an input signal. The measuring device includes: a first processing unit that performs first pipelined processing on a first input signal according to a first sampling timing; a second processing unit that performs second pipelined processing on a second input signal according to a second sampling timing with a sampling period longer than the first sampling timing; an adjustment unit that adjusts the output timing of the first input signal processed by the first processing unit in conjunction with the output timing of the second input signal processed by the second processing unit; and a generation unit that sequentially generates the waveform of the first input signal processed by the first pipelined processing unit and the waveform of the second input signal processed by the second pipelined processing unit. Thus, the measuring device adjusts the output timing of the first input signal processed by the first processing unit in conjunction with the output timing of the second input signal processed by the second processing unit. Therefore, even if the highest sampling rate (highest sampling period) differs between the first and second processing units, the waveforms of the output signals of each module can be compared in real time.

[0011] In one embodiment, the system further includes a memory capable of storing the first input signal that has undergone the first pipelined processing and the second input signal that has undergone the second pipelined processing. The adjustment unit includes: a holding unit that sequentially holds the first input signal that has undergone the first pipelined processing by the first processing unit according to the first sampling timing; a counting unit that counts the number of first sampling times generated during the period of the second sampling timing; and a control unit that, according to the second sampling timing, sequentially reads the first input signal that has undergone the first pipelined processing, counted by the counting unit, from the holding unit and holds it in the memory, and holds the second input signal that has undergone the second pipelined processing, counted by the counting unit, in the memory. The fabrication unit sequentially fabricates the waveforms of the first input signal and the second input signal held in the memory. Thus, by sequentially holding the first input signal that has undergone the first pipelined processing according to the first sampling timing in the holding unit, the adjustment unit coordinates the timing of writing the first input signal that has undergone the first pipelined processing to the memory with the second pipelined processing. Furthermore, the adjustment unit counts the number of first sampling timings generated during the period of the second sampling timing, and repeatedly stores the second input signal, which has undergone the second pipeline processing, in memory according to the number counted by the counting unit. Therefore, since the time deviation and the difference in the number of samples between the first and second input signals are eliminated, the waveforms of the output signals of each module can be compared in real time.

[0012] In one embodiment, the holding unit has a FIFO function. Therefore, it is possible to maintain the first input signal that has undergone the first pipeline processing in a state that maintains the temporal order.

[0013] In one embodiment, a memory is further included, capable of storing the first input signal that has undergone the first pipelined processing and the second input signal that has undergone the second pipelined processing. The first input signal that has undergone the first pipelined processing by the first processing unit according to the first sampling timing is sequentially stored in the memory. The adjustment unit includes: a counting unit that counts the number of first sampling timings generated during the period of the second sampling timing; and a control unit that, according to the second sampling timing, stores the second input signal that has undergone the second pipelined processing, counted by the counting unit, in the memory. The fabrication unit reads the first input signal that has undergone the first pipelined processing from the memory after delaying the number of first sampling timings. The fabrication unit stores the second input signal that has undergone the second pipelined processing in the memory, reads the second input signal that has undergone the second pipelined processing from the memory, and sequentially fabricates the waveforms of the first input signal read from the memory and the waveforms of the second input signal read from the memory. Thus, the adjustment unit counts the number of first sampling timings generated during the period of the second sampling timing and repeatedly stores the second input signal that has undergone the second pipelined processing in the memory according to the count counted by the counting unit. Furthermore, the manufacturing department delays the process of reading the first input signal from memory, which has undergone the first pipeline processing, in conjunction with the second pipeline processing. Therefore, by eliminating the time deviation and the difference in the number of samples between the first and second input signals, it is possible to compare the waveforms of the output signals of each module in real time.

[0014] In one embodiment, a timing generation unit is further included. This unit generates a first timing signal representing the first sampling timing and a second timing signal representing the second sampling timing based on a sampling signal representing a sampling timing input from an external source. The first timing signal is output to the first processing unit, and the second timing signal is output to the second processing unit. The first processing unit performs the first pipelined processing based on the first sampling timing represented by the first timing signal input from the timing generation unit, and the second processing unit performs the second pipelined processing based on the second sampling timing represented by the second timing signal input from the timing generation unit. Thus, by generating the first and second timing signals based on the sampling signal representing the sampling timing input from an external source, processing can be synchronized with the external sampling signal and advanced in real time.

[0015] In one embodiment, when the sampling period of the externally input sampling timing is shorter than the highest sampling period that the second processing unit can handle, the timing generation unit generates a second timing signal that represents the sampling timing of the highest sampling period as the second sampling timing, serving as the second timing signal. Therefore, when the sampling period of the externally input sampling timing is shorter than the highest sampling period of the second processing unit, the highest sampling period is used as the second sampling timing, thus enabling processing to be advanced in conjunction with the performance of the second processing unit.

[0016] In one embodiment, the first pipeline processing and the second pipeline processing include A / D conversion processing. Therefore, even if the processing speeds of the A / D conversion processes in the measuring instruments differ, the waveforms of the output signals of each module can be compared in real time.

[0017] One embodiment of the measurement method is a measurement method for a measuring device that measures the waveform of an input signal. The measurement method includes: a first processing unit performing a first pipelined processing on a first input signal according to a first sampling timing; a second processing unit performing a second pipelined processing on a second input signal according to a second sampling timing with a sampling period longer than the first sampling timing; an adjustment unit adjusting the output timing of the first input signal that has undergone the first pipelined processing by the first processing unit in conjunction with the output timing of the second input signal that has undergone the second pipelined processing by the second processing unit; and a manufacturing unit sequentially manufacturing the waveform of the first input signal that has undergone the first pipelined processing and whose output timing has been adjusted by the adjustment unit, and the waveform of the second input signal that has undergone the second pipelined processing. Thus, the measurement method of the measuring device adjusts the output timing of the first input signal that has undergone the first pipelined processing by the first processing unit in conjunction with the output timing of the second input signal that has undergone the second pipelined processing by the second processing unit. Therefore, even if the highest sampling rate (highest sampling period) differs between the first processing unit and the second processing unit, the waveforms of the output signals of each module can be compared in real time.

[0018] According to one embodiment of the present invention, in a structure comprising multiple modules with different maximum sampling rates, the waveforms of the output signals of each module can be compared in real time. Attached Figure Description

[0019] Figure 1 This is a block diagram schematically showing the configuration of the measuring device for the comparative example.

[0020] Figure 2 It is a timing diagram that schematically represents the interval rejection process of the sampling rate of the sampled signal.

[0021] Figure 3It is a schematic representation Figure 1 Timing diagrams for the processing of A / D converters 92a and 92b.

[0022] Figure 4A It is a schematic representation Figure 1 Timing diagram of the A / D converter 92a.

[0023] Figure 4B It is a schematic representation Figure 1 Timing diagram of the A / D converter 92b.

[0024] Figure 5 This is a block diagram schematically showing the configuration of the measuring device according to the first embodiment.

[0025] Figure 6 It is a schematic representation Figure 5 Timing diagrams for the processing of A / D converters 12a and 12b.

[0026] Figure 7 This is a timing diagram schematically representing the processing results of a measuring device according to one embodiment.

[0027] Figure 8 This is a flowchart illustrating the processing steps of a measuring device according to one embodiment.

[0028] Figure 9 This is a block diagram schematically showing the configuration of the measuring device according to the second embodiment.

[0029] Figure 10 This is a flowchart illustrating the processing steps of the measuring device of the present invention.

[0030] Explanation of reference numerals in the attached figures

[0031] 10. Measuring device, 11. Input amplifier, 12. A / D converter, 13. Interface circuit, 14. Timing generation circuit, 15. Storage controller, 16. Waveform memory, 17. Waveform creation circuit, 18. Display, 21. FIFO, 22. Counting circuit, 23. Number memory, 24. Timing controller, 90. Measuring device, 91. Input amplifier, 92. A / D converter, 93. Interface circuit, 94. Timing generation circuit, 95. Storage controller, 96. Waveform memory, 97. Waveform creation circuit, 98. Display, 101. Low-speed timing cycle, 102. High-speed timing cycle, 103. Shielding. Detailed Implementation

[0032] <Comparative Example>

[0033] The comparative measuring device 90 includes multiple modules that process the input signals respectively, and measures the waveforms of the multiple input signals in real time. Each module includes an input terminal for receiving a common sampling signal with a specified sampling timing from an external source, and acquires data synchronously with the sampling timing represented by the sampling signal. The maximum sampling rate (maximum sampling period) that each module of the measuring device 90 can correspond to is different.

[0034] An example of sampling based on externally sourced signals is as follows: an encoder that outputs a signal based on a certain rotation angle is mounted on a rotating component. Data is acquired based on the signal from the encoder, in conjunction with the rotation of the component. By sampling corresponding to the rotation angle of this rotating component, the movement of the object being measured can be accurately recorded at a specific rotation angle, and effective analytical data about the rotating component can be obtained.

[0035] Users can freely combine and mount multiple input modules with different maximum sampling rates (frequency) onto the measuring instrument 90. Generally, when using A / D converters in input modules, with the same circuit size, there is a trade-off between the A / D conversion resolution (digital signal resolution) and the A / D conversion sampling rate (time resolution). A / D converters with a higher bit count have a lower maximum conversion sampling rate compared to those with a lower bit count. Users determine the input modules by prioritizing either the A / D conversion resolution or the sampling rate based on the characteristics and intended use of the observed signal.

[0036] Figure 1 This is a block diagram schematically illustrating the configuration of the measuring device 90 for a comparative example. The measuring device 90 includes: input amplifiers 91 (91a, 91b), A / D converters 92 (92a, 92b), interface circuits 93 (93a, 93b), timing generation circuit 94, storage controller 95, waveform memory 96, waveform creation circuit 97, and display 98. The measuring device 90 receives analog input signals from CH (channel) 1 and CH2 respectively, which are converted into digital signals in the input circuits for each channel and displayed on the display 98. Input amplifiers 91a, A / D converters 92a, and interface circuits 93a function as input circuits (input modules) for A / D conversion of the signal from CH1. Input amplifiers 91b, A / D converters 92b, and interface circuits 93b function as input circuits for A / D conversion of the signal from CH2. Although the A / D converter 92a for CH1 has low resolution, it can perform A / D conversion at high speed. Compared to A / D converter 92a, CH2's A / D converter 92b has a higher resolution, but its A / D conversion speed is lower.

[0037] Input amplifiers 91 (91a, 91b) take the analog electrical signal corresponding to the physical quantity as input signal, and amplify the input signal in conjunction with the specifications of A / D converters 92 (92a, 92b). The analog signal of observed CH1 is normalized by input amplifier 91a and output to A / D converter 92a. The analog signal of observed CH2 is normalized by input amplifier 91b and output to A / D converter 92b.

[0038] The timing of data acquisition is input externally as the sampling timing to the timing generation circuit 94. The timing generation circuit 94 performs appropriate interval filtering on the sampling timing in a manner that does not exceed the highest sampling rate of the A / D converters 92 (92a, 92b) of each channel, and then outputs it as a timing signal indicating the conversion timing to the A / D converters 92 (92a, 92b).

[0039] Figure 2 This is a timing diagram schematically illustrating the interval rejection process performed by the timing generation circuit 94 on the sampled signal's sampling rate. Figure 2 In the diagram, external sampling timing schematically represents the waveform of the sampling timing from an external input to the timing generation circuit 94. High-speed timing schematically represents the waveform of the timing signal output from the timing generation circuit 94 to the A / D converter 92a. Low-speed timing schematically represents the waveform of the timing signal output from the timing generation circuit 94 to the A / D converter 92b. Memory write timing schematically represents the waveform of the timing signal output from the timing generation circuit 94 to the memory controller 95. Figure 2 In this circuit, the external sampling timing period 102 is shorter than the low-speed timing period 101. Therefore, the timing generation circuit 94, in order to prevent sampling timings faster than the highest sampling rate of the A / D converter 92b from being input to the A / D converter 92b, performs interval filtering on the sampling timings when a timing faster than the highest sampling rate is input. Specifically, as shown... Figure 2 As shown, the timing generation circuit 94 shields the signals that the A / D converter 92b cannot follow in the externally sampled timing signals, as indicated by reference numeral 103 in the attached figure.

[0040] The A / D converters 92 (92a, 92b) work in conjunction with the sampling timing represented by the input timing signal to perform A / D conversion, and output the converted digital input signal to the interface circuits 93 (93a, 93b). The bit length of the digital signal output by A / D converter 92a is shorter than the bit length of the digital signal output by A / D converter 92b.

[0041] Interface circuits 93 (93a, 93b) convert the data formats of digital signals with different bit lengths input from A / D converters 92 (92a, 92b) into a unified data format. Interface circuits 93 (93a, 93b), in conjunction with the timing signal input from timing generation circuit 94, output the unified data format of the input signal to storage controller 95.

[0042] The storage controller 95, in coordination with the timing signal input from the timing generation circuit 94, stores the input signal data from the interface circuits 93 (93a, 93b) into the waveform memory 96. The timing generation circuit 94 outputs a timing signal to the storage controller 95 at the same time as the sampling signal input to the A / D converter 92a, which performs higher-speed A / D conversion. Therefore, the storage controller 95 stores the input signal data of CH1 and CH2 into the waveform memory 96 at the sampling rate of the A / D converter 92a, which performs high-speed A / D conversion. If the data transmission from the low-speed A / D converter 92b fails to keep up, the storage controller 95 stores the same data as previously stored data into the waveform memory 96. This repeated storage of data identical to previously stored data is called filling.

[0043] As needed, the data stored in the waveform memory 96 is controlled by a processor such as a CPU (Central Processing Unit) to generate a display waveform, which is then displayed on a monitor 98.

[0044] Next, refer to Figure 3 , Figure 4A and Figure 4B This indicates the operation of the measuring device 90. Figure 3 This is a timing diagram schematically illustrating the processing of A / D converters 92a and 92b when the sampling rate of the external sampling timing does not exceed the maximum sampling rate of A / D converter 92b, which is the low-speed side CH2. Figure 3 In the diagram, t1, t2, t3, ... represent the sampling times indicated by the external sampling timing. A, B, C, ... represent the variations in the analog data values ​​through their vertical positions in the attached diagram. "External sampling timing" schematically represents the waveform from the external input to the sampling timing of the timing generation circuit 94. "High-speed A / D" refers to the processing in the A / D converter 92a of CH1. "Low-speed A / D" refers to the processing in the A / D converter 92b of CH2.

[0045] Typically, within an A / D converter, data processing is performed via pipelined processing to optimize efficiency. Therefore, several clock cycles are required from the timing signal input to the converted data output. Figure 3 In the example, at time t1, the A / D conversion of analog data A begins; at time t2, internal pipeline processing is implemented; and at time t3, internal pipeline processing for the second clock cycle is implemented. At t4, data is output from A / D converters 92a and 92b and input to interface circuits 93a and 93b, and then transmitted to the memory controller 95. At t5, the digital data corresponding to analog data A is stored in waveform memory 96. Thus, at... Figure 3 In this example, it takes four clock cycles from the start of the A / D conversion to the storage of the waveform in the waveform memory 96. Figure 3 In this process, the external sampling timing does not exceed the maximum sampling rate of the A / D converter 92b on the low-speed side CH2. Therefore, the same timing is input to the A / D converter 92a on the high-speed side and the A / D converter 92b on the low-speed side. Since the timing input to each channel is the same, the data stored in the waveform memory 96 also becomes data with the same timing, so the stored data does not deviate in time.

[0046] However, when the external sampling timing is higher than the maximum sampling rate of the A / D converter 92b on the low-speed side (CH2), the data output from the A / D converter 92a on the high-speed side (CH1) and the A / D converter 92b on the low-speed side deviate in time. (Refer to...) Figure 4A and Figure 4B This needs to be explained. Figure 4A This is a timing diagram schematically illustrating the processing of A / D converter 92a when the sampling rate of the external sampling timing exceeds the maximum sampling rate of A / D converter 92b. Figure 4B It is a schematic representation of the input being related to... Figure 4A The timing diagram shows the processing of the A / D converter 92b with the same external sampling timing. Generally, if a timing signal with a frequency higher than the A / D converter's inherent maximum sampling rate is input, malfunctions will occur. Therefore, to avoid exceeding the maximum sampling rate, the timing signal needs to be periodically filtered before input. Therefore, refer to... Figure 2 As described above, the timing generation circuit 94 outputs a timing signal to the A / D converter 92b of CH2 on the low-speed side, which has been interval-removed for sampling timing.

[0047] exist Figure 4A In the middle, the high-speed A / D converter side (CH1) and Figure 3 Similarly, at time t5, four clock cycles after the start of the A / D conversion process at time t1, the A / D conversion result of analog data A is stored in waveform memory 96. On the other hand, the timing of the A / D converter 92b on the low-speed side CH2 is achieved by eliminating sampling timing intervals through timing generation circuit 94 to prevent malfunctions in the A / D converter 92b. Figure 4BAs shown, the timing of the low-speed side (CH2), such as times t1, t4, t7, t10, and t13, is periodically discarded and applied in a manner that does not exceed the highest sampling rate of the A / D converter 92b.

[0048] In A / D converter 92b, the conversion of analog data A begins at time t1, but four clock cycles of pipelined processing are required until the data is output in the same manner as on the high-speed side (CH1). Therefore, pipelined processing occurs at times t4 and t7, data transfer to the memory controller 95 occurs at time t10, and the data corresponding to analog data A is stored in the waveform memory 96 starting at time t13. To ensure that the number of data stored after A / D conversion on the high-speed side (CH1) matches the number of data stored after A / D conversion on the low-speed side (CH2), the memory controller 95 stores data according to the timing of A / D converter 92a on the high-speed side. In the absence of data transfer from A / D converter 92b on the low-speed side, the memory controller 95 performs data filling by repeatedly storing the most recently transferred data. Furthermore, the external sampling timing, as observed by the measuring instrument 90, is an external factor and is irregular and unpredictable. Therefore, in general, the interval of the interval rejection in the timing generation circuit 94 is irregular, and the number of data on the high-speed side (CH1) and the low-speed side (CH2) is not correlated. Therefore, if the data on the low-speed side (CH2) is not filled to make the number of data consistent, it is impossible to obtain the correspondence between the high-speed side data and the low-speed side data after the data is received.

[0049] from Figure 4A and Figure 4B It can be seen that on the high-speed side (CH1), the data A, B, C, ... after A / D conversion are stored sequentially in the waveform memory 96. Figure 4A In the high-speed side (CH1), the completed A / D conversion data A, B, C, ... are stored in the waveform memory 96 in the area corresponding to addresses 0, 1, 2, ... used by the high-speed side (CH1). On the low-speed side (CH2), at the start time t5 of data storage in the high-speed side (CH1), the pipeline processing of the A / D converter 92b has not yet been completed; therefore, data remaining in the pipeline from previous A / D conversions is stored as indeterminate values ​​in the waveform memory 96. Figure 4BIn the example, variable values ​​are stored in the regions of waveform memory 96 corresponding to addresses 0, 1, 2, ..., 7 used by the low-speed side (CH2). Furthermore, the data corresponding to analog data A is stored starting from address 8 of waveform memory 96, a storage location that deviates from the data on the high-speed side. The amount of this data deviation varies depending on the sampling rate of the externally provided sampling timing (sampling signal). Moreover, since the sampling rate of the sampling signal changes in real time, the data deviation between the high-speed side (CH1) and the low-speed side (CH2) is not a fixed value but varies depending on the external sampling conditions. Therefore, if the waveforms of the high-speed and low-speed side data are simultaneously displayed on display 98, these waveforms include the temporal deviation as a measurement error. Therefore, in the comparative example's measuring device 90, when the sampling rate of the sampling signal exceeds the maximum sampling rate of some modules, it is impossible to compare the waveforms of the output signals of each module in real time and accurately.

[0050] <Implementation Method>

[0051] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. In the drawings, parts having the same structure or function are labeled with the same reference numerals. In the description of this embodiment, sometimes identical parts are appropriately omitted or repeated descriptions are simplified.

[0052] (First Implementation)

[0053] Even when external sampling is performed using A / D converters with different maximum sampling rates (maximum sampling periods), the measuring device 10a of this embodiment ensures that the data delay from each A / D converter is consistent, thereby storing the data in the waveform memory 16 in a manner that maintains the sampling simultaneity of each A / D converter. Therefore, according to the measuring device 10a, sampling errors between modules can be eliminated, and the waveforms of the output signals of each module can be compared in real time and accurately.

[0054] Figure 5This is a block diagram schematically illustrating the configuration of the measuring device 10a according to the first embodiment. The measuring device 10a includes: input amplifiers 11 (11a, 11b), A / D converters 12 (12a, 12b), interface circuits 13 (13a, 13b), timing generation circuit 14, storage controller 15, waveform memory 16, waveform creation circuit 17, display 18, FIFO (First In First Out) 21, counting circuit 22, count memory 23, and timing controller 24. The measuring device 10a receives analog input signals from CH1 and CH2 respectively, converts them into digital signals in the input circuits of each channel, and displays them on the display 18. Input amplifiers 11a, A / D converters 12a (serving as a first processing unit), and interface circuits 13a function as input circuits (input modules) for A / D conversion of the signal from CH1. Input amplifiers 11b, A / D converters 12b (serving as a second processing unit), and interface circuits 13b function as input circuits for A / D conversion of the signal from CH2. The A / D converter 12a of CH1 has low resolution but can perform A / D conversion at high speed. The A / D converter 12b of CH2 has higher resolution than the A / D converter 12a, but its A / D conversion is slower. The following describes an example where the sampling rate of the external sampling timing does not exceed the maximum sampling rate of the A / D converter 12a but exceeds the maximum sampling rate of the A / D converter 12b. The measuring device 10a temporarily holds the completed A / D conversion data of CH1 on the high-speed side in the FIFO 21, which serves as a holding unit, and writes it to the waveform memory 16 in conjunction with the timing of the output of the completed A / D conversion data of CH2 on the low-speed side, thereby eliminating the time deviation between the high-speed and low-speed data. That is, the FIFO 21, the counting circuit 22 (as a counting unit), the count memory 23, and the timing controller 24 (as a control unit or timing generation unit) function as an adjustment unit, which adjusts the time deviation between the output signal of the interface circuit 13a and the output signal of the interface circuit 13b.

[0055] Input amplifiers 11 (11a, 11b) take the analog electrical signals corresponding to the physical quantities as input signals, and amplify the input signals in conjunction with the specifications of A / D converters 12 (12a, 12b). The analog signal of observed CH1 is normalized by input amplifier 11a and output to A / D converter 12a. Simultaneously, the analog signal of observed CH2 is normalized by input amplifier 11b and output to A / D converter 12b.

[0056] The timing generation circuit 14 receives an external sampling timing signal as an external input to define the sampling timing. After appropriately omitting the sampling timing at intervals that do not exceed the highest sampling rate of each channel's A / D converter 12 (12a, 12b), the timing generation circuit 14 outputs it to the A / D converter 12 (12a, 12b) as a timing signal indicating the conversion opportunity. The interval omitting process performed by the timing generation circuit 14 on the sampling timing of the sampled signal is related to the reference... Figure 2 The timing generation circuit 94 of the comparative example measuring device 90 described herein processes the same process. The timing generation circuit 14 outputs a high-speed timing signal, which represents the same timing as the external sampling timing, to the A / D converter 12a, interface circuit 13a, FIFO 21, counting circuit 22, and timing controller 24. The timing generation circuit 14 also outputs a low-speed timing signal, representing the timing after interval filtering of the external sampling timing in conjunction with the highest sampling rate of the A / D converter 12b, to the A / D converter 12b, interface circuit 13b, FIFO 21, counting circuit 22, and timing controller 24.

[0057] A / D converters 12 (12a, 12b) perform A / D conversion in conjunction with the sampling timing indicated by the input timing signal, and output the converted digital input signal to interface circuits 13 (13a, 13b). The bit length of the digital signal output by A / D converter 12a is shorter than the bit length of the digital signal output by A / D converter 12b.

[0058] Interface circuits 13 (13a, 13b) convert the data formats of digital signals with different bit lengths input from A / D converters 12 (12a, 12b) into a unified data format. Interface circuit 13a, in conjunction with the high-speed timing signal represented by the timing signal input from timing generation circuit 14, outputs the unified data format input signal to FIFO 21. Thus, the A / D conversion data from A / D converter 12a is accumulated in FIFO 21. Interface circuit 13b, in conjunction with the low-speed timing signal represented by the timing signal input from timing generation circuit 14, outputs the unified data format input signal to storage controller 15.

[0059] The A / D conversion completed data accumulated in FIFO 21 from A / D converter 12a is read out by the read signal of timing controller 24 and input to storage controller 15. Storage controller 15 writes timing signals according to the data from timing controller 24, and stores the A / D conversion completed data from A / D converter 12a in waveform memory 16.

[0060] The A / D conversion data from the A / D converter 12b input to the storage controller 15 is written into a timing signal based on the data from the timing controller 24 and stored in the waveform memory 16. If the frequency of the data written into the timing signal from the timing controller 24 is faster than the data frequency from the low-speed A / D converter 12b, the storage controller 15 fills the waveform memory 16 with the most recently transmitted data from the interface circuit 13b.

[0061] The counting circuit 22 counts the number of high-speed timers each time it receives a low-speed timer signal from the timing generation circuit 14. That is, if a low-speed timer signal is generated, the counting circuit 22 resets the high-speed timer count and begins counting. The counting circuit 22 increments the count by 1 each time a high-speed timer is generated. Thus, the counting circuit 22 counts the number of high-speed timers generated during the period from the generation of one low-speed timer to the generation of the next. The counting circuit 22 stores the counting result as a count data in the count memory 23 each time a low-speed timer is generated. The count memory 23 may also maintain the count data, for example, in a FIFO manner.

[0062] The timing controller 24 reads the count data from the count memory 23 based on the high-speed and low-speed timing from the timing generation circuit 14. The timing controller 24 outputs a write signal to the storage controller 15, which is used to read the count data represented by the read count data from the FIFO 21.

[0063] The storage controller 15 receives a write signal and stores the data from the FIFO 21 in the waveform memory 16. Simultaneously, the storage controller 15 receives data from the low-speed side from the interface circuit 13b and stores it in the waveform memory 16. If the data transmission from the low-speed side A / D converter 12b fails to keep up, the storage controller 15 will store the same data as previously stored data in the waveform memory 16 to fill it.

[0064] As needed, the data stored in the waveform memory 16 is controlled by a processor such as a CPU, and a display waveform is generated by the waveform generation circuit 17, which serves as the generation unit, and displayed on the display 18. The display 18 is implemented, for example, by a liquid crystal display (LCD) or an organic EL display (OELD).

[0065] Next, refer to Figure 6 This explains the operation of the measuring device 10a. Figure 6 It is a schematic representation Figure 5 Timing diagrams for the processing of A / D converters 12a and 12b. Figure 6 This example illustrates the processing of A / D converters 12a and 12b when the sampling rate of the external sampling timing exceeds the maximum sampling rate of A / D converter 12b but does not exceed the maximum sampling rate of A / D converter 12a. Figure 6 In the diagram, T1, T2, T3, ... represent the times when sampling should be performed, as indicated by the external sampling timing. Figure 6 This illustrates an example where the time interval of the external sampling timing increases over time, but the variation of the external sampling timing is arbitrary. "High-speed data" refers to the data of the analog signal input from CH1. "Low-speed data" refers to the data of the analog signal input from CH2. "External sampling operation start" indicates the timing of the start of sampling by the measuring device 10a by switching a binary signal from OFF to ON. "High-speed sampling timing" refers to the waveform of the high-speed timing processed by the A / D converter 12a, etc., specifying CH1. "FIFO" refers to the data written to FIFO 21. "High-speed write data" refers to the data written from FIFO 21 to the high-speed side (CH1) of the waveform memory 16 via the storage controller 15. "Low-speed sampling timing" refers to the waveform of the low-speed timing processed by the A / D converter 12b, etc., specifying CH2. "Number memory" refers to the number of high-speed samples stored in the number memory 23. "Low-speed write data" refers to the data written from the interface circuit 13b to the low-speed side (CH2) of the waveform memory 16 via the storage controller 15. "Count memory read" indicates the number of data read from the count memory 23. "Write start" indicates the timing of writing data from the low-speed side (CH2) to the waveform memory 16 by switching the binary signal from OFF to ON.

[0066] exist Figure 6 In the example, external sampling begins at time T0. If an external sampling timing signal is input at time T1, the timing generation circuit 14 outputs a high-speed sampling timing signal to the A / D converter 12a, interface circuit 13a, FIFO 21, counting circuit 22, and timing controller 24. This signal initiates the operation of the high-speed A / D converter 12a. The A / D converter 12a performs A / D conversion through pipelined processing. Figure 6 In the example, high-speed data A from T1 is output from interface circuit 13a at time T4 and stored in FIFO 21. Subsequently, if timing is sampled from external inputs sequentially at times T2, T3, ..., the timing generation circuit 14 outputs high-speed sampling timing accordingly. In conjunction with this, the input data B, C, ... from the high-speed side CH1 are sequentially digitally converted. Figure 6In the example, the digital data of data B at time T2 is stored in FIFO21 at time T5, and the digital data of data C at time T3 is stored in FIFO21 at time T6. Subsequently, data converted by A / D converter 12a according to the high-speed sampling timing is stored in FIFO21 at the high-speed sampling timing.

[0067] On the other hand, the timing generation circuit 14 periodically discards the sampling timing input from the outside, in a manner that does not exceed the highest sampling rate of the low-speed side A / D converter 12b, and outputs the low-speed sampling timing as low-speed sampling, such as times T1, T6, T11, and T15. During this low-speed sampling timing, the A / D converter 12b converts the low-speed data a at time T1, the low-speed data f at time T6, the low-speed data k at time T11, the low-speed data o at time T15, and so on, into digital data. The low-speed side A / D converter 12b also performs pipelined processing, so the low-speed side data a at T1 is output from the interface circuit 13b at time T15.

[0068] The counting circuit 22 counts how many high-speed samples occurred between the occurrence of one low-speed sample and the occurrence of the next low-speed sample. For example, in Figure 6 In this process, the initial low-speed sample is generated at time T1, and the next low-speed sample is generated at T6. The counting circuit 22 counts the number of high-speed samples generated during this period. In this example, high-speed samples are generated at times T1, T2, T3, T4, and T5, so the count result is 5. The counting circuit 22 stores this count result sequentially in the count memory 23 at the times when the low-speed samples are generated. Figure 6 In the next low-speed sampling timing T11, high-speed sampling generates five times at times T6, T7, T8, T9, and T10. Therefore, the counting circuit 22 stores these times in the count memory 23 at time T11. Subsequently, the counting circuit 22 stores 4 times at time T15 and 4 times at time T18.

[0069] The timing controller 24 has the following functions: it remains in standby mode from the moment T1 when it switches from OFF to ON starting from the external sampling operation until the A / D converter 12b on the low-speed side (CH2) outputs valid data. Figure 6In the process, the initial data output from the low-speed side (CH2) via interface circuit 13b occurs at time T15, therefore the timing controller 24 remains in standby mode until time T15. After remaining in standby mode until time T15, the timing controller 24 reads the initial value from the counting memory 23. The timing controller 24 controls the storage controller 15 to read the same number of data items from FIFO 21 as those read from the counting memory 23, and writes the data read from FIFO 21 to waveform memory 16. Simultaneously, the timing controller 24 controls the storage controller 15 to continuously write the same number of data items as those read from the counting memory 23, output from the low-speed side A / D converter 12b. Figure 6 In the example, at time T15, the high-speed side data A, B, C, D, and E are written to the waveform memory 16, and the low-speed side data a is written repeatedly five times.

[0070] Next, during low-speed sampling timing, the timing controller 24 reads the count data from the count memory 23, and based on this count data, reads the digital data of the high-speed side (CH1) from the FIFO 21 and stores it in the waveform memory 16. Simultaneously, the same digital data of the low-speed side (CH2) is continuously stored in the waveform memory 16 according to the count data read from the count memory 23. Figure 6 In the example, at time T19, the count 5 is read from the count memory 23, and data F, G, H, I, and J are read from FIFO 21 and stored in the waveform memory 16. Simultaneously, the low-speed data f is stored in the waveform memory 16 five times consecutively. Similarly, at time T22, the count 4 is read from the count memory 23, and data K, L, M, and N are read from FIFO 21 and stored in the waveform memory 16. In parallel, the low-speed data k is stored in the waveform memory 16 four times consecutively.

[0071] Figure 7 This is a timing diagram schematically representing the processing results of the measuring device 10a as described above. Figure 7This refers to the data stored in waveform memory 96 by measuring device 90 (comparative example) and the data stored in waveform memory 16 by measuring device 10a. In measuring device 90, when sampling is performed at an external sampling timing exceeding the highest sampling rate of the A / D converter 92b on the low-speed side, a sampling deviation occurs between the high-speed side sampling data and the low-speed side sampling data. For example, the high-speed side data A of measuring device 90 is stored in waveform memory 96 at time T4, and the low-speed side data a is stored in waveform memory 96 at time T15. In contrast, in measuring device 10a, for the data to be retrieved, the high-speed sampling data and the low-speed sampling data are sampled synchronously, and no deviation occurs during sampling. For example, both the high-speed side data A and the low-speed side data a of measuring device 10a are stored in waveform memory 16 at time T15. Furthermore, in measuring device 10a, the low-speed side sampling data is filled in during high-speed sampling until the next low-speed side sampling data is output. For example, the low-speed side data 'a' output at time T15 is filled with the same number of four data 'B' to 'E' as the high-speed side data, until the next low-speed side data 'f' is output at time T19.

[0072] Therefore, even when sampling is performed at an external sampling timing that exceeds the highest sampling rate of the A / D converter 12b on the low-speed side, the measuring device 10a can accurately acquire the data from the low-speed side and perform fill interpolation. Thus, according to the measuring device 10a, waveforms can be measured and compared in a manner that does not produce a deviation in sampling time between high-speed and low-speed sampling.

[0073] Figure 8 This is a flowchart illustrating the processing steps of the measuring device 10a according to one embodiment. (Refer to...) Figure 8 The operation of the measuring device 10a described is equivalent to one of the measuring methods of the measuring device 10a in this embodiment. Figure 8 The actions of each step are performed based on the control of the measuring device 10a.

[0074] exist Figure 8 In step S1, the timing generation circuit 14 of the measuring device 10a receives sampling timing from an external source.

[0075] In step S2, the counting circuit 22 of the measuring device 10a increments the count data by 1.

[0076] In step S3, the measuring device 10a determines whether the sampling timing from the outside is in sync with the sampling timing of the low-speed A / D converter 12b. If the sampling timing is in sync with the A / D converter 12b (yes in step S3), the measuring device 10a proceeds to step S4; otherwise (no in step S3), it returns to step S1.

[0077] In step S4, the counting circuit 22 of the measuring device 10a writes the count data in the counting circuit 22 into the count memory 23, and then clears the count data and resets it to 0.

[0078] In step S5, the measuring device 10a determines whether the initial data from the low-speed side A / D converter 12b is output from the pipeline. If the data is output ("Yes" in step S5), the measuring device 10a proceeds to step S6; otherwise ("No" in step S5), it returns to step S1.

[0079] In step S6, the timing controller 24 of the measuring device 10a reads the count data from the count memory 23.

[0080] In step S7, the timing controller 24 of the measuring device 10a is controlled to read the number of data read in step S6 from the FIFO 21 and write it to the waveform memory 16 via the storage controller 15.

[0081] In step S8, the timing controller 24 of the measuring device 10a controls the data output from the low-speed side of the interface circuit 13b to repeat the number of data read in step S6, and writes it to the waveform memory 16 via the storage controller 15.

[0082] In step S9, the measuring device 10a determines whether the acquisition of sampling data from the outside has ended. If the measuring device 10a determines that the acquisition has ended (yes in step S9), it ends the processing of the flowchart; otherwise (no in step S9), it proceeds to step S10.

[0083] In step S10, in the measuring device 10a, the timing generation circuit 14 of the measuring device 10a receives the sampling timing from an external source.

[0084] In step S11, the counting circuit 22 of the measuring device 10a increments the count data by 1.

[0085] In step S12, the measuring device 10a determines whether the sampling timing from the external source is synchronized with the sampling timing of the low-speed A / D converter 12b. If the sampling timing of the A / D converter 12b is synchronized ("Yes" in step S12), the measuring device 10a proceeds to step S13. If the sampling timing of the A / D converter 12b is not synchronized ("No" in step S12), the measuring device 10a returns to step S10.

[0086] In step S13, the counting circuit 22 of the measuring device 10a writes the count data in the counting circuit 22 to the count memory 23, then clears the count data and resets it to 0. The measuring device 10a then returns to step S6.

[0087] In addition, Figure 6 and Figure 7 The example described is a case where the pipeline stages of the high-speed A / D converter 12a and the low-speed A / D converter 12b are the same, but the pipeline stages do not need to be the same. Furthermore, this embodiment describes an example of A / D conversion processing performed as pipeline processing by the measuring device 10a, but processing other than A / D conversion processing can also be performed.

[0088] (Second Implementation)

[0089] In the first embodiment, a configuration example is described where the high-speed side A / D conversion completion data is temporarily held in FIFO 21 and written to waveform memory 16 in conjunction with the output of low-speed side A / D conversion completion data, thereby eliminating the time deviation between the high-speed and low-speed data. In this embodiment, the measuring device 10b immediately stores the high-speed side A / D conversion completion data in waveform memory 16 after outputting it from interface circuit 13a, but the timing of reading the high-speed side data from waveform memory 16 to waveform creation circuit 17 is coordinated with the output of low-speed side data. Therefore, according to the measuring device 10b, the time deviation between the high-speed and low-speed data can be eliminated.

[0090] Figure 9 This is a block diagram schematically illustrating the configuration of the measuring device 10b according to the second embodiment. Figure 9 In this drawing, structures that perform the same functions as in the first embodiment are labeled with the same reference numerals, and detailed descriptions are omitted.

[0091] In the measuring device 10b, high-speed side (CH1) data is written directly from the interface circuit 13a to the waveform memory 16 via the storage controller 15 without passing through a FIFO, based on the generation of high-speed timing. On the other hand, similar to the first embodiment, the counting circuit 22 counts the number of high-speed timings generated during the period from the generation of one low-speed timing to the generation of the next. The counting circuit 22 stores the counting result as a count data in the count memory 23 each time a low-speed timing is generated. Starting from the start of low-speed side data writing, low-speed side (CH2) data is read from the interface circuit 13b at each low-speed sampling timing, and the low-speed side (CH2) data is repeatedly written to the waveform memory 16 via the storage controller 15 according to the number of data read from the count memory 23. The waveform creation circuit 17 reads data from the high-speed side and low-speed side according to the number of times each data is written, creates a waveform, and displays it on the display 18. The waveform creation circuit 17 reads the same amount of high-speed data as the data stored in the waveform memory 16 on the low-speed side and creates a waveform, thus delaying the display of data on the high-speed sampling side. This allows the reading of high-speed data to be synchronized with the reading of low-speed data.

[0092] Figure 10 This is a flowchart illustrating the processing steps of the measuring device of the present invention. As described above, in the measuring device 10 (10a, 10b) for measuring the waveform of the input signal, the A / D converter 12a performs first pipelined processing on the first input signal according to a first sampling timing (high-speed timing) (step S21). The A / D converter 12b performs second pipelined processing on the second input signal according to a second sampling timing (low-speed timing) with a sampling period longer than the first sampling timing (step S22). The FIFO 21, the counting circuit 22, the count memory 23, and the timing controller 24 adjust the output timing of the first input signal that has undergone first pipelined processing by the A / D converter 12a in conjunction with the output timing of the second input signal that has undergone second pipelined processing by the A / D converter 12b (step S23). The waveform creation circuit 17 sequentially creates the waveform of the first input signal that has undergone first pipelined processing and whose output timing has been adjusted, and the waveform of the second input signal that has undergone second pipelined processing (step S24). The measuring devices 10 (10a, 10b) display the waveforms of the generated first and second input signals on the display 18 (step S25). Thus, the measuring devices 10 (10a, 10b) adjust the output timing of the first input signal, which has undergone the first pipelined processing by the A / D converter 12a, to match the output timing of the second input signal, which has undergone the second pipelined processing by the A / D converter 12b. Therefore, even if the highest sampling rates (highest sampling periods) in the A / D converters 12a and 12b are different, the waveforms of the output signals of each module can be compared in real time.

[0093] Furthermore, the measuring device 10a also includes a waveform memory 16, which can store a first input signal that has undergone a first pipelined process and a second input signal that has undergone a second pipelined process. The FIFO 21 of the measuring device 10a sequentially stores the first input signal that has undergone the first pipelined process by the A / D converter 12a according to a first sampling timing. The counting circuit 22 counts the number of first sampling timings generated during the period of the second sampling timing. The timing controller 24, according to the second sampling timing, sequentially reads the first input signal that has undergone the first pipelined process from the FIFO 21 according to the count count by the counting circuit 22 and stores it in the waveform memory 16. Furthermore, the timing controller 24, according to the second sampling timing, repeatedly stores the second input signal that has undergone the second pipelined process in the waveform memory 16 according to the count count by the counting circuit 22. The waveform creation circuit 17 sequentially creates the waveforms of the first input signal and the second input signal stored in the waveform memory 16. Therefore, the measuring device 10a sequentially holds the first input signal, which has undergone the first pipelined processing according to the first sampling timing, in FIFO 21, so that the timing of writing the first input signal, which has undergone the first pipelined processing, into the memory is coordinated with the second pipelined processing. Furthermore, the measuring device 10a counts the number of first sampling timings generated during the period of the second sampling timing, and repeatedly holds the second input signal, which has undergone the second pipelined processing, in waveform memory 16 according to the counted number. Therefore, since the time deviation and the difference in the number of samples between the first and second input signals are eliminated, the waveforms of the output signals of each module can be compared in real time.

[0094] Furthermore, by using FIFO21, the measuring device 10a is able to maintain the first input signal that has undergone the first pipeline processing in a state that maintains the time sequence.

[0095] Furthermore, the measuring device 10b includes a waveform memory 16, which can store a first input signal that has undergone a first pipelined process and a second input signal that has undergone a second pipelined process. The first input signal, which has undergone the first pipelined process by the first processing unit according to a first sampling timing, is sequentially stored in the waveform memory 16. The counting circuit 22 counts the number of first sampling timings generated during the period of the second sampling timing. The timing controller 24, according to the second sampling timing, repeatedly stores the second input signal that has undergone the second pipelined process in the waveform memory 16 according to the number counted by the counting circuit 22. The waveform creation circuit 17 reads the first input signal that has undergone the first pipelined process from the waveform memory 16 after a first sampling timing delay of the count. Furthermore, the waveform creation circuit 17 stores the second input signal that has undergone the second pipelined process in the waveform memory 16 and reads the second input signal that has undergone the second pipelined process from the waveform memory 16. The waveform creation circuit 17 sequentially creates the waveform of the first input signal read from the waveform memory 16 and the waveform of the second input signal read from the waveform memory 16. Therefore, the measuring device 10b counts the number of first sampling times generated during the period of the second sampling timing, and repeatedly stores the second input signal, which has undergone the second pipelined processing, in the waveform memory 16 according to the counted number. Furthermore, the waveform creation circuit 17 delays the processing of the first input signal, which has undergone the first pipelined processing, from the waveform memory 16 in conjunction with the second pipelined processing. Therefore, since the time deviation and the difference in the number of samples between the first and second input signals are eliminated, the waveforms of the output signals of each module can be compared in real time.

[0096] Furthermore, the timing generation circuit 14 generates a first timing signal representing a first sampling timing and a second timing signal representing a second sampling timing based on a sampling signal representing a sampling timing input from an external source. The timing generation circuit 14 outputs the first timing signal to the A / D converter 12a and the second timing signal to the A / D converter 12b. The A / D converter 12a performs a first pipelined process based on the first sampling timing represented by the first timing signal input from the timing generation circuit 14. The A / D converter 12b performs a second pipelined process based on the second sampling timing represented by the second timing signal input from the timing generation circuit 14. Thus, the measuring devices 10 (10a, 10b) generate the first and second timing signals based on the sampling signals representing the sampling timing input from an external source, thereby enabling them to synchronize with the sampling signals from the external source and advance the processing in real time.

[0097] Furthermore, when the sampling period of the externally input sampling timing is shorter than the highest sampling period that the A / D converter 12b can handle, the timing generation circuit 14 generates a second timing signal that represents the sampling timing of the highest sampling period as the second sampling timing. Thus, when the sampling period of the externally input sampling timing is shorter than the highest sampling period of the A / D converter 12b, the highest sampling period is used as the second sampling timing, thereby enabling processing to be advanced in conjunction with the performance of the A / D converter 12b.

[0098] Furthermore, the first and second pipeline processes include A / D conversion processing. Therefore, even if the processing speeds of the A / D converters (12a, 12b) in the measuring devices 10 (10a, 10b) are different, the waveforms of the output signals of each module can be compared in real time.

[0099] This invention is not limited to the embodiments described above. For example, the multiple blocks shown in the block diagram can be merged, or a single block can be divided. The multiple steps shown in the flowchart can also be executed in parallel or in a different order, depending on the processing capability of the device performing each step or as needed, instead of being executed in the described chronological order. Furthermore, modifications can be made without departing from the spirit of this invention.

Claims

1. A measurer which measures a waveform of an input signal, characterized by include: The first processing unit performs first pipeline processing on the first input signal according to a first sampling timing, wherein the first sampling timing is synchronized with an external sampling timing having a sampling rate slower than the first highest sampling rate; The second processing unit performs second pipeline processing on the second input signal according to the second sampling timing. The second sampling timing is generated by intermittently eliminating the external sampling timing according to the second highest sampling rate when the second highest sampling rate is slower than the sampling rate of the external sampling timing. The adjustment unit adjusts the output timing of the first input signal that has undergone the first pipeline processing by the first processing unit to synchronize with the output timing of the second input signal that has undergone the second pipeline processing by the second processing unit; as well as The production department sequentially produces the waveform of the first input signal that has undergone the first pipeline processing and whose output timing has been adjusted by the adjustment department, and the waveform of the second input signal that has undergone the second pipeline processing.

2. The measuring device according to claim 1, characterized in that, It also includes a memory capable of storing the first input signal that has undergone the first pipelined processing and the second input signal that has undergone the second pipelined processing. The adjustment unit includes: The holding unit sequentially holds the first input signal, which has undergone the first pipeline processing by the first processing unit according to the first sampling timing, in the holding unit; The counting unit counts the number of first sampling times generated during the period of the second sampling timing; and The control unit, according to the second sampling timing, sequentially reads the first input signal, which has undergone the first pipeline processing and is counted by the counting unit, from the holding unit and stores it in the memory, and also stores the second input signal, which has undergone the second pipeline processing and is counted by the counting unit, in the memory. The manufacturing unit sequentially manufactures the waveforms of the first input signal and the second input signal stored in the memory.

3. The measuring device according to claim 2, characterized in that, The holding part has a FIFO function.

4. The measuring device according to claim 1, characterized in that, It also includes a memory capable of storing the first input signal that has undergone the first pipelined processing and the second input signal that has undergone the second pipelined processing. The first input signal, which has undergone the first pipeline processing by the first processing unit according to the first sampling timing, is sequentially stored in the memory. The adjustment unit includes: The counting unit counts the number of first sampling times generated during the period of the second sampling timing; and The control unit, based on the second sampling timing, stores the second input signal, which represents the number of counts by the counting unit and has undergone the second pipeline processing, in the memory. The manufacturing unit reads the first input signal, which has undergone the first pipeline processing, from the memory after delaying the first sampling time by the specified number of times. The manufacturing unit stores the second input signal that has undergone the second pipeline processing in the memory, and reads the second input signal that has undergone the second pipeline processing from the memory. The production unit sequentially produces the waveforms of the first input signal read from the memory and the waveforms of the second input signal read from the memory.

5. The measuring device according to any one of claims 1 to 4, characterized in that, It also includes a timing generation unit, which generates a first timing signal representing the first sampling timing and a second timing signal representing the second sampling timing based on a sampling signal representing the external sampling timing input from the outside, and outputs the first timing signal to the first processing unit and the second timing signal to the second processing unit. The first processing unit performs the first pipeline processing based on the first sampling timing represented by the first timing signal input from the timing generation unit. The second processing unit performs the second pipeline processing based on the second sampling timing indicated by the second timing signal input from the timing generation unit.

6. The measuring device according to claim 5, characterized in that, When the sampling rate of the external sampling timing is faster than the second highest sampling rate, the timing generation unit generates a second timing signal that represents the sampling timing of the second highest sampling rate as the second sampling timing, serving as the second timing signal.

7. The measuring device according to any one of claims 1 to 4, characterized in that, The first pipeline processing and the second pipeline processing include A / D conversion processing.

8. A method for measuring an input signal, characterized in that... include: The first processing unit performs a first pipelined processing step on the first input signal according to the first sampling timing, wherein the first sampling timing is synchronized with an external sampling timing having a sampling rate that is slower than the first highest sampling rate; The second processing unit performs a second pipeline processing on the second input signal according to the second sampling timing. The second sampling timing is generated by intermittently eliminating the external sampling timing according to the second highest sampling rate when the second highest sampling rate is slower than the sampling rate of the external sampling timing. The adjustment unit adjusts the output timing of the first input signal that has undergone the first pipeline processing by the first processing unit to synchronize with the output timing of the second input signal that has undergone the second pipeline processing by the second processing unit; as well as The manufacturing department sequentially produces the waveform of the first input signal that has undergone the first assembly line processing and whose output timing has been adjusted by the adjustment department, and the waveform of the second input signal that has undergone the second assembly line processing.

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