Devices, Systems, and Methods for Input / Output Mapping

Abstract

The present disclosure is directed to devices, systems, and methods for input / output mapping. A memory device may support multiple DQ mappings. Two or more of the DQ mappings may support memory operations using the same input-output width. In some instances, one or more components for supporting DQ mappings for different input-output widths may be used to also support one or more of the DQ mappings for the same input-output width.

Description

Technical Field

[0001] The present disclosure is directed to devices, systems, and methods for input / output mapping. Background Art

[0002] Semiconductor memories are used in many electronic systems to store data that can be retrieved later. Information can be stored as physical signals on individual memory cells of the memory (e.g., charge on a capacitive element). The memory cells can be arranged in a memory array of rows (e.g., word lines) and columns (e.g., bit lines). The memory array can be further organized into bank groups, banks, planes, etc.

[0003] An external device, such as a memory controller, can provide data together with a write command to the semiconductor memory to store the data in the memory array. The data can be provided serially to one or more external data terminals (DQ terminals). The data is deserialized (e.g., parallelized) by the semiconductor memory and provided to the memory array for storage in the memory cells. To retrieve data, the external device can provide a read command to the semiconductor memory. In response, the semiconductor device can retrieve data from the memory array in parallel. The semiconductor memory can serialize the data and provide the data to the external device via the DQ terminals.

[0004] The location of data in the memory array can be indicated by a memory address, which can indicate the bank and row in which the data is stored in the memory cell. Depending on the organization of the memory array, the address can further indicate a sub - part of a bank or other part of the memory array. The memory address can be provided to the semiconductor memory together with read and write commands by an external device.

[0005] When the memory address can indicate the location where data will be stored in the memory array, the data can be provided to or from the location in the memory array in a predetermined format via the DQ terminals, which is referred to as DQ mapping. DQ mapping can provide the relationship between the memory cells of the memory array and the DQ terminals. For example, DQ mapping can indicate which data from which memory cells is provided to which DQ terminals in what order. DQ mapping can also indicate which data received from which DQ terminals at different times is provided to which memory cells of the memory array. DQ mapping can be based on one or more factors, such as the DQ terminals, burst length, and the organization of the memory array. Summary of the Invention

[0006] In one aspect, the present disclosure is directed to an apparatus that includes: a plurality of data terminals; a memory bank that includes a plurality of memory cells; and a plurality of circuits that include a first plurality of circuits and a second plurality of circuits, wherein the first plurality of circuits are configured to implement a first mapping between the memory bank and the plurality of data terminals, and the second plurality of circuits are configured to implement a second mapping between the memory bank and the plurality of data terminals, wherein the first mapping indicates a first relationship between the plurality of memory cells of the memory bank and the plurality of data terminals, and the second mapping indicates a second relationship different from the first relationship between the plurality of memory cells of the memory bank and the plurality of data terminals.

[0007] In another aspect, the present disclosure is directed to a system that includes: a memory controller that includes a first plurality of data terminals; and a memory device that includes: a second plurality of data terminals, wherein at least a portion of the second plurality of data terminals is coupled to the first plurality of data terminals; a memory bank that includes a plurality of memory cells; and a plurality of circuits that are configured to implement one of a first mapping or a second mapping, wherein the first mapping indicates a first relationship between the plurality of memory cells of the memory bank and the portion of the second plurality of data terminals that is coupled to the first plurality of data terminals, and the second mapping indicates a second relationship different from the first relationship between the plurality of memory cells of the memory bank and the portion of the second plurality of data terminals that is coupled to the first plurality of data terminals.

[0008] In another aspect, the present disclosure is directed to a method that includes: receiving a command at a command address terminal; in response to the command, activating or deactivating at least one circuit to implement one of a plurality of mappings, wherein an individual mapping of the plurality of mappings indicates a relationship between a plurality of memory cells and at least a portion of a plurality of data terminals, wherein at least two of the plurality of mappings indicate relationships for the same portion of the plurality of data terminals; and providing data from the memory cells to at least the portion of the plurality of data terminals according to the implemented mapping of the plurality of mappings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a system in accordance with at least one embodiment of the present disclosure.

[0010] Figure 2 is a block diagram of an apparatus in accordance with at least one embodiment of the present disclosure.

[0011] Figure 3 is an example of a DQ mapping for an input-output width for four DQ terminals.

[0012] Figure 4An example of DQ mapping for the input-output width of eight DQ terminals.

[0013] Figure 5 An example of DQ mapping for the input-output width of eight DQ terminals.

[0014] Figure 6 A block diagram of a part of a semiconductor device.

[0015] Figure 7 A block diagram of a part of a semiconductor device according to at least one embodiment of the present disclosure.

[0016] Figure 8 A flowchart of a method according to at least one embodiment of the present disclosure. Detailed Description

[0017] Disclosed are devices and methods for supporting multiple DQ mappings in a memory device, including circuitry, DQ mappings, and memory array layouts. Different DQ mappings may be provided for different data input-output (I / O) widths (e.g., the number of DQ terminals utilized). In some embodiments, multiple DQ mappings may be supported for the same data I / O width (e.g., the same number of active DQ terminals). In some embodiments, different DQ mappings for the same I / O width may provide at least some different characteristics from each other. In some embodiments, circuitry that supports DQ mappings for different I / O widths may be used to at least partially support one or more of the multiple DQ mappings for the same I / O width.

[0018] Figure 1is a block diagram of an example system in accordance with at least one embodiment of the present disclosure. System 100 includes memory controllers (e.g., memory controllers 101(A), 101(B), or 101(C)) and a memory device 110. In some examples, the memory device 110 may be a dynamic random access memory (DRAM) device. In some examples, the memory device 110 may be a double data rate (DDR) DRAM device. In some examples, the memory device 110 may include one or more individual memory devices, embedded memories, etc. In some examples, the memory device 110 may be included in a memory module. In some examples, one or more of the memory controllers may be included in the same package and represent a system-on-chip. Other examples may implement system 100 in different arrangements but still remain within the scope of the present disclosure. Memory controllers 101(A)-101(C) may generate a variety of I / O widths. For example, memory controller 101(A) has an I / O width of four (x4). That is, it has four DQ terminals DQ0-3 for providing and receiving data. In contrast, memory controllers 101(B) and 101(C) have eight DQ terminals DQ0-7 (x8) for providing and receiving data. One of memory controllers 101(A)-101(C) may provide data to and receive data from memory device 110 via the DQ terminals on memory controllers 101(A)-101(C) and the corresponding DQ terminals of memory device 110. The DQ terminals of memory controllers 101(A)-101(C) and memory device 110 may be coupled by conductive paths, which may be collectively referred to as a data bus as indicated by arrow 112.

[0019] Although in some applications, the memory device 110 may be specifically designed to work with a particular memory controller, the memory device 110 may be designed to support operations with different memory controllers as Figure 1 indicated. In the Figure 1 example shown, the memory device 110 includes eight DQ terminals DQ0-7. The memory device 110 may support operations with a memory controller that includes only four DQ terminals (e.g., memory controller 101(A)), as well as with memory controllers 101(B) and 101(C) that include eight DQ terminals. In some applications, the memory device 110 may include two DQ mappings, one DQ mapping that utilizes a subset of the DQ terminals, such as four DQ terminals (e.g., I / O width x4), and one DQ mapping that utilizes all of the DQ terminals, such as eight DQ terminals (e.g., I / O width x8). The number of DQ terminals of the memory controller is provided only as an example, and in other examples, the memory controller may have more or fewer DQ terminals (e.g., two, sixteen, thirty-two).

[0020] As systems and their applications become more diverse, memory controllers can have different other characteristics, or systems that include a memory controller and a memory device can have different requirements. For example, memory controller 101(C) can be included in a system or perform operations that are more sensitive to errors compared to memory controller 101(B). In another example, memory controller 101(B) can be included in a system or perform operations that require faster data transfer. According to embodiments of the present disclosure, a memory device such as memory device 110 can support multiple DQ mappings for the same I / O width (e.g., the same / equal number of DQ terminals). In some instances, the multiple DQ mappings can accommodate different memory controller characteristics and / or system requirements. This can allow a single memory device to support a wider range of products.

[0021] As disclosed herein, in some embodiments, a memory device can support one or more DQ mappings for different I / O widths. Returning to Figure 1 the example in, memory device 110 can include a DQ mapping for I / O width x4 and two or more DQ mappings for I / O width x8 in order to support operations with all memory controllers 101(A)-101(C). In some embodiments, the circuitry for I / O width x4 can be used to support one or more of the DQ mappings for I / O width x8. In some applications, this can reduce the number of components added to support additional DQ mappings.

[0022] Figure 2 is a block diagram of a device according to at least one embodiment of the present disclosure. The device can be semiconductor device 200 and will be referred to as such. Semiconductor device 200 can include, but is not limited to, DRAM devices. In some embodiments of the present disclosure, semiconductor device 200 can be integrated into a single semiconductor chip. In some embodiments, semiconductor device 200 can be included in Figure 1 memory device 110 of.

[0023] Semiconductor device 200 includes memory array 250. Memory array 250 is shown as including multiple memory banks. In Figure 2In an embodiment, the memory array 250 is shown to include sixteen memory banks, Bank 0 - Bank 15. However, in other instances, the memory array 250 may have more or fewer memory banks (e.g., 4, 8, 32). In some instances, the memory banks may be organized into bank groups BG. For example, memory banks Bank 0 - 15 may be organized into four bank groups BG0 - 3, where each bank group contains four banks. In another instance, memory banks Bank 0 - 15 may be organized into eight bank groups, where each bank group contains two banks. In yet another instance, memory banks Bank 0 - 15 may be organized into two bank groups, where each bank group contains eight banks. Other groupings may also be used. In some embodiments, Figure 2 not shown, each memory bank Bank 0 - 15 may be organized into one or more planes (sometimes referred to as memory tiles). For example, each memory bank Bank 0 - 15 may include sixteen planes.

[0024] Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC disposed at intersections of the plurality of word lines WL and the plurality of bit lines BL and / BL. Selection of the word lines WL is performed by the row decoder 240 and selection of the bit lines BL and / BL is performed by the column decoder 245. In Figure 2 an embodiment, the row decoder 240 includes a respective row decoder for each memory bank, and the column decoder 245 includes a respective column decoder for each memory bank. The bit lines BL and / BL are coupled to respective sense amplifiers (SAMP). Read data from the bit lines BL or / BL is amplified by the sense amplifier SAMP and transferred to the error correction and data bus inversion control (ECC / DBI) circuit 255 on complementary local data lines (LIOT / B), transfer gates (TG), and complementary main data lines (MIOT / B). Conversely, write data output from the ECC / DBI circuit 255 is transferred to the sense amplifier SAMP on the complementary main data line MIOT / B, transfer gate TG, and complementary local data line LIOT / B, and written into the memory cells MC coupled to the bit lines BL or / BL.

[0025] Although the row decoder 240, column decoder 245, and other components are shown in Figure 2 to be external to the memory array 250, the semiconductor device 200 may have a different arrangement. For example, all or a portion of the row decoder 240 may be disposed between plane groups of the memory banks Bank 0 - 15.

[0026] The ECC / DBI circuit 255 can perform error correction encoding and decoding. For example, the ECC / DBI circuit 255 can receive ECC data (e.g., one or more parity bits) associated with read data and perform error correction operations to correct the read data as needed, and provide the ECC data together with the read data to an external device, such as a memory controller (e.g., memory controllers 101(A)-101(C)). Similarly, the ECC / DBI circuit 255 can receive ECC data associated with write data and perform error correction operations to correct the write data as needed, and provide the ECC data to be stored together with the write data to the memory array 250. The ECC / DBI circuit 255 can also perform DBI operations to generate DBI information. The DBI information can be used to encode and / or decode read and / or write information to reduce voltage transitions at the DQ terminals. This can reduce power consumption during data transfer in some applications. In some applications, the ECC and / or DBI operations performed by the ECC / DBI circuit 255 can be optional. Although shown as a single component in Figure 2 , in some embodiments, the ECC / DBI circuit 255 can include multiple circuits. In some embodiments, the circuit for providing ECC data can be separate from the circuit for providing DBI information.

[0027] The semiconductor device 200 can employ multiple external terminals, including command and address and chip select (CA / CS) terminals, which are coupled to the command and address bus to receive commands and addresses as well as CS signals. The external terminals can additionally include clock terminals, which receive clocks CK_t and CK_c, as well as data clocks WCK_t and WCK_c, and provide access data clocks RDQS_t and RDQS_c; data terminals DQ; data mask terminals DM and data bus inversion terminals DBI; and power supply terminals, which receive power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0028] An external clock CK_t and CK_c are supplied to the clock terminals to be provided to the input buffer 220. The external clocks can be complementary. The input buffer 220 generates an internal clock ICLK based on the CK_t and CK_c clocks. The ICLK clock is provided to the command decoder 215 and to the internal clock generator 222. The internal clock generator 222 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks can be used for the timing operations of various internal circuits. Data clocks WCK_t and WCK_c are also provided to the external clock terminals. The WCK_t and WCK_c clocks are provided to the data clock circuit 275, and the data clock circuit generates an internal data clock based on the WCK_t and WCK_c clocks. The internal data clock is provided to the input / output circuit 260 to time the operations of the circuits included in the input / output circuit 260, and thus to time the reception of write data.

[0029] The CA / CS terminals can be supplied with memory addresses. The memory addresses supplied to the CA / CS terminals are transferred to the address decoder 212 via the command / address input circuit 205. The address decoder 212 receives the addresses and supplies the decoded row address XADD to the row decoder 240 and the decoded column address YADD to the column decoder 245. Commands can be supplied to the CA / CS terminals. Examples of commands include access commands for accessing the memory (such as a read command for performing a read operation and a write command for performing a write operation), mode register write and read commands for performing mode register write and read operations, and other commands and operations.

[0030] Commands can be provided to the command decoder 215 as internal command signals via the command / address input circuit 205. The command decoder 215 includes circuits for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 215 can provide a row command signal ACT to select a word line and a column command signal R / W to select a bit line.

[0031] A power supply potential VDD and VSS are supplied to the power supply terminals. The power supply potential VDD and VSS are supplied to the internal voltage generator circuit 270. The internal voltage generator circuit 270 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potential VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 240, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array 250, and the internal potential VPERI is used in a plurality of other peripheral circuit blocks.

[0032] A supply potential VDDQ and VSSQ are also supplied to the supply terminals. The supply potential VDDQ and VSSQ are supplied to the input / output circuit 260. In some embodiments of the present disclosure, the supply potential VDDQ and VSSQ supplied to the supply terminals may be the same potential as the supply potential VDD and VSS supplied to the supply terminals. In another embodiment of the present disclosure, the supply potential VDDQ and VSSQ supplied to the supply terminals may be a different potential from the supply potential VDD and VSS supplied to the supply terminals. The supply potential VDDQ and VSSQ supplied to the supply terminals are used for the input / output circuit 260 so that the power supply noise generated by the input / output circuit 260 does not propagate to other circuit blocks.

[0033] When an activation command and a row address are received, and subsequently a read command and a column address are received, read data and corresponding ECC data are read from a memory cell corresponding to the row address and the column address in the memory array 250. The read command is received by the command decoder 215, and the command decoder 215 provides an internal command to cause the read data and the corresponding ECC data to be provided from the memory array 250 to the ECC / DBI circuit 255. The ECC / DBI circuit 255 performs ECC decoding to generate corrected read data and corrected corresponding ECC data. For example, if the read data contains an error, such as an error determined by the ECC control circuit 255 based on the corresponding ECC data, then the read data is corrected. The ECC / DBI circuit 255 may further perform a DBI operation to provide DBI information associated with the read data and the corresponding ECC data. The read data, the associated ECC data, and the DBI information are provided to the input / output circuit 260 and output to the data terminal DQ according to a DQ mapping ( Figure 2 not shown). In some instances, the DQ mapping may be selectable.

[0034] When an activation command and a row address are received, and subsequently a write command and a column address are received, write data and corresponding ECC data supplied to the data terminal DQ are written to a memory cell corresponding to the row address and the column address in the memory array 250. The write data and the corresponding ECC data may also be provided to the DBI information via the DBI terminal. A data mask may be provided to the data masking terminal DM to mask a portion of the data when writing to the memory. The write command is received by the command decoder 215, and the command decoder 215 provides an internal command to cause the write data to be received by an input receiver in the input / output circuit 260. The write data, the corresponding ECC data, and the DBI information are supplied from the data terminal DQ to the ECC / DBI circuit 255 via the input / output circuit 260 according to a DQ mapping, and are supplied to the memory array 250 by the ECC / DBI circuit 255 to be written to the memory cell MC. In some instances, the DQ mapping may be selectable.

[0035] Reading and writing may combine data with one or more clock signals (and in some embodiments, provide ECC data and / or DBI information via the DQ terminals and / or the DBI terminals), for example, data clocks WCK_t and WCK_c are provided to the DQ terminals, and access data clocks RDQS_t and RDQS_c are provided. Generally, each DQ terminal provides or receives a bit sequence for each read or write operation. The number of bits in the sequence may be referred to as the burst length. Each bit in the sequence is provided within at least a portion of a clock cycle of an appropriate clock signal at the corresponding DQ terminal, and then the next bit in the sequence is provided to the DQ terminal. When the bit transitions occur relative to the clock signal (e.g., rising edge and / or falling edge) and how long each bit is provided on the corresponding DQ terminal may be at least partially based on the structure of the semiconductor device 200, industry standards (e.g., JEDEC), and / or the operating mode of the semiconductor device 200. Regardless of the clock frequency or other operating settings, the length of time each bit exists on the DQ terminal is referred to as the unit interval (UI). Thus, an 8-bit burst length may take 8 UIs to provide all bits to the DQ terminal for a read or write operation.

[0036] When a bit sequence is provided to the DQ terminals during a write operation, the IO circuit 260 may deserialize the sequence for further processing (e.g., error correction and DBI operations) by the ECC / DBI circuit 255 and write it to the memory array 250. The bit sequence may be deserialized and provided in the memory array 250 according to a DQ mapping that defines the relationship between the memory cells of the memory array 250 and the DQ terminals. The DQ mapping may indicate where each bit in the bit sequence for each DQ terminal will be stored in the memory array 250 (e.g., which memory cell of the memory array 250 will store which bit received from the DQ terminal). Where the bit is stored is at least partially based on at which DQ terminal the bit is received and when the bit is received in the bit sequence.

[0037] Similarly, when bits are provided to the DQ terminals during a read operation, the bits may be provided in parallel from the memory array 250 to the ECC / DBI 255 for processing, and then provided to the IO circuit 260. The IO circuit 260 may serialize the bits according to the DQ mapping. The DQ mapping may indicate to which DQ terminal each bit will be provided and when each bit in the bit sequence will be provided to the DQ terminal (e.g., which memory cell will provide which bit to the DQ terminal).

[0038] As referenced Figure 1As mentioned, the semiconductor device 200 may include multiple DQ mappings. As disclosed herein, the DQ mappings may be selected for different IO widths (e.g., different numbers of DQ terminals for receiving and providing data) and / or for different operating characteristics. The semiconductor device 200 may include one or more components (e.g., signal lines, read / write drivers, logic circuits) that implement the multiple DQ mappings. In some embodiments, at least some of the components may be included in the IO circuit 260. In some embodiments, depending on the characteristics of the DQ mapping, additional components may be included in other circuits (e.g., ECC / DBI circuit 255). Collectively, the components for implementing one or more DQ mappings may be referred to as a circuit and / or circuitry. The DQ mapping may be selected in a variety of ways. For example, one or more fuses, antifuses, and / or switches may be used to activate or deactivate one or more components to implement the desired DQ mapping. In some embodiments, the manufacturer of the semiconductor device 200 may set the status of the fuses, antifuses, and / or switches. In some embodiments, an external device (e.g., a memory controller) may issue a command to set the status of the fuses, antifuses, and / or switches. In another example, the DQ mapping may be selected at least in part based on the value written to the mode register 230. The value may be written by a memory controller that issues a mode register write command.

[0039] Figure 3 is an example of a DQ mapping for an input-output width of four DQ terminals. The DQ mapping 300 represents the DQ mapping for one memory bank (e.g., Figure 2 banks 0-15 in). Each memory bank may have the same DQ mapping. Each row is a plane 302 of the memory bank, planes 0-15. In some embodiments, each plane may include one or more word lines of the memory bank. In Figure 3In the illustrated example, the memory bank is divided into two sides, a P side 304 and a Q side 306, where the P side 304 includes planes 0-7 and the Q side 306 includes planes 8-15. The two sides, the P side 304 and the Q side 306, can be separated by a peripheral region 312. The peripheral region 312 can include one or more components of the memory device (e.g., semiconductor device 200), such as a central global row decoder (e.g., row decoder 240), word line (phase / FX) drivers, and a sense amplifier controller disposed between the two sides. Each side, P and Q, is further subdivided into an upper half J and a lower half K. The planes 302 of the K half are indicated by boxes 308 (planes 4-7) and 310 (planes 12-15). A row address (RA) that includes multiple bits can indicate which part of the bank is to be activated during an access operation (e.g., read or write). In the illustrated example, when bit 16 of the row address (RA16) is 0 and bit 17 of the row address (RA17) is 1, the K half of the P side of the bank is accessed. However, in other examples, other memory banks can have different architectures and / or different address configurations, and the present disclosure is not limited to the specific bank architecture and address configuration shown in the DQ mapping disclosed herein.

[0040] In the illustrated example, each plane 302 can provide or receive eight bits during an access operation. The DQ mapping 300 indicates how bits from each plane 302 are provided to the DQ terminals during a read data burst and how bits from the DQ terminals are stored in the memory plane 302 during a write data burst. CA indicates the unit interval (UI) of the data burst at the DQ terminals. In the illustrated example, the data burst is eight UIs (CA0-C7). For example, when accessing the K half of the P side of the bank for a write operation, the bits received from terminals DQ0-3 during CA0 and CA1 can be stored in plane 7. Similarly, continuing this example, during a read operation, bits can be provided from plane 7 during CA0 and CA1 of the burst as the bits provided on DQ0-3.

[0041] Note that the number of UIs associated with providing or receiving data from the memory plane 302 within a data burst does not necessarily correspond to the number of UIs associated with the burst length of the data burst on the DQ terminals. Data is provided to and from the memory plane 302 in parallel, while the data provided to and received on the DQ terminals is serial. Thus, for example, while one or two UIs (e.g., in parallel) may be used to write or read bits from the memory plane 302, eight UIs for the memory controller may be used to receive or provide data on the DQ terminals (e.g., serially). In addition, the bits provided from the memory plane 302 may undergo buffering and serialization before being provided to the DQ terminals. Similarly, the bits provided from the DQ terminals may undergo buffering and deserialization before being provided to the memory plane 302.

[0042] Figure 4 is an example of a DQ mapping for the input-output width of eight DQ terminals. The DQ mapping 400 represents the DQ mapping for one memory bank (e.g., Figure 2 bank 0-7 in ). Each bank of the memory may have the same DQ mapping. The architecture and address configuration of the bank corresponding to the DQ mapping 400 may be the same as that of the bank corresponding to the DQ mapping 300.

[0043] Similar to the DQ mapping 300, the DQ mapping 400 indicates at what UI (CA) of the data burst which bits received at which DQ pins are stored in which memory plane 402 of the memory bank. However, compared to the DQ mapping 300, since each memory plane 402 stores eight bits and uses eight DQ terminals, each memory plane 402 stores bits associated with only a single CA rather than two CAs of the data burst according to the DQ mapping 400. In addition, bits may be provided for the entire side P side 404 or Q side 406 during the CA, rather than only for the half J, K 410.

[0044] Both the DQ mapping 300 and the DQ mapping 400 may be supported by the same memory device (e.g., semiconductor device 200). The DQ mappings 300, 400 may allow the semiconductor device to operate with external devices having I / O widths four and I / O width eight.

[0045] Some memory controllers and / or systems having the same I / O width (e.g., x8) may have different characteristics that require different DQ mappings for the same I / O width. For example, some systems may be "critical" and have increased requirements for error correction. In some cases, the DQ mapping 400 may not be sufficient to meet these error requirements and a different DQ mapping may be used.

[0046] Occasional defective bits or isolated memory cell defects attributable to interference during read, write, and / or emission can typically be corrected through ECC operations because these errors typically affect only one bit or only a few bits among the bits associated with the same ECC information (e.g., parity bits, codewords). However, defective bits can also be caused by physical damage to a portion of the memory array, which can affect an entire word line or a group of word lines that are physically adjacent to each other. If a group of bits is stored in the same adjacent physical location in the memory (e.g., the same word line, adjacent word lines, the same plane), and that physical location is damaged, then it is possible that most or all of the bits have errors. If all of those bits are associated with the same ECC data, then there may be too many errors to correct in the ECC data, and the data will be lost.

[0047] Returning to DQ mapping 400, all of the bits provided on the DQ terminals during UI are stored in the same memory plane 402. All of the bits for UI may have been processed by the ECC / DBI circuit (e.g., ECC / DBI circuit 255) and may be associated with the same ECC data. If the memory plane 402 in which all of the bits for UI are stored is damaged, then there may be more error bits than the ECC data can correct. Therefore, for error-sensitive systems, a DQ mapping different from DQ mapping 400 may be required.

[0048] Figure 5 is another example of a DQ mapping for the input-output width of eight DQ terminals. DQ mapping 500 represents the DQ mapping for one memory bank (e.g., Figure 2 banks 0 - 7 in

[0049] Although DQ mapping 500 is similar to DQ mapping 400 in that it utilizes all eight DQ terminals DQ0 - 7 and can provide bits for the entire side P 504 or Q 506 of the memory bank during CA, rather than just for the halves J, K 510, it is similar to DQ mapping 300 in that the memory plane 502 stores data for multiple UIs (e.g., CA0 and CA1, CA2 and CA3, etc.). Thus, in Figure 5 the example shown, half of the bits stored in the memory plane 502 are from one UI and the other half of the bits are from another UI.

[0050] All bits provided on the DQ terminals during the same UI of a data burst (e.g., DQ0-7 during CA0) can be associated with the same ECC data (e.g., the ECC data provided by ECC / DBI circuit 255). However, unlike the DQ mapping 400, when the memory device (e.g., semiconductor device 200) utilizes the DQ mapping 500, the bits can be stored in two different physical locations in the memory, i.e., in two different memory planes 502. In some applications, this can reduce the risk that the number of error bits exceeds the number of error bits that the ECC data can correct.

[0051] However, although the DQ mapping 500 has the advantage of error resistance, in some applications, the DQ mapping 400 may be more desirable. For example, the DQ mapping 400 can support data masking while the DQ mapping 500 may not support data masking. Thus, some users of the memory device (e.g., semiconductor device 200) may find the DQ mapping 500 more preferable, while other users may prefer the DQ mapping 400. Providing different memory devices for different users may be too costly or impractical. Thus, just as it may be desirable to provide devices that support multiple I / O widths, it may be desirable to provide devices that provide different DQ mappings for different applications. Although as an example, a DQ mapping with increased error resistance is provided, other DQ mappings providing other features may be used in other embodiments.

[0052] Although the DQ mappings 300-500 are shown as tables, the mappings indicated by the DQ mappings can be implemented by various components such as conductive paths (e.g., between the memory array and the DQ terminals), drivers (e.g., read and write drivers), repeaters (e.g., amplifiers), logic circuits (e.g., multiplexers, AND gates), etc., some or all of which can be included in or coupled to an IO circuit such as IO circuit 260. Supporting multiple DQ mappings may require additional components, even if the DQ mappings are for the same I / O width. According to embodiments of the present disclosure, one or more components used to implement one DQ mapping can be used to implement another DQ mapping. In some embodiments, the two DQ mappings can have different I / O widths. In the examples disclosed herein, a memory device such as semiconductor device 200 can support implementations of all three DQ mappings 300-500.

[0053] Figure 6 is a block diagram of a portion of a semiconductor device. In some embodiments, semiconductor device 600 can be included in semiconductor device 200. Semiconductor device 600 can support multiple DQ mappings, such as DQ mapping 300 and DQ mapping 400, to allow operation with different I / O widths.

[0054] The semiconductor device 600 may include a memory array 602 organized into bank groups BG0-4, each bank group including four memory banks Bank0-15. Although four bank groups with four memory banks are shown in this example, other numbers of memory banks and / or organization into bank groups may be used in other instances. The semiconductor device 600 may additionally include a lower DQ block 620, which may include a plurality of output terminals, such as DQ terminals, DM terminals, and / or DBI terminals. The memory array 602 may be coupled to the lower DQ block 620 via various circuits.

[0055] Each memory bank Bank0-15 may have the same structure as the memory banks shown in the DQ mappings 300 and 400. Each memory bank Bank0-15 may be coupled to the DpTier region 604 of the semiconductor device 600 via a plurality of data lines. In the illustrated example, eight data lines 608 are provided to each J side of the P and Q portions of the memory bank, and four data lines 610 are provided to each K side of the P and Q portions. The difference in the number of data lines between the K side and the J side is due to the change in the order of the DQ terminals for the J side between the DQ mapping 300 and the DQ 400, while the order of the first two DQ terminals of the K side is the same for the DQ mapping 300 and the DQ 400.

[0056] The DpTier region 604 includes drive circuits 612 for each bank group, which includes two read drivers for each J side and one read driver for each K side. An additional read driver is provided for the J side to drive the additional data lines 608. The DpTier region 604 additionally includes a Write DBI (WDBI) circuit 614 and a Read DBI (RDBI) circuit 616 to generate DBI information for the data provided from the memory array 602 for write and read operations, respectively. In some embodiments, the DBI information may be a single-bit (1-b) signal as shown in Figure 6 as shown.

[0057] The data and DBI information may be provided from the DpTier region 604 to one of the data buses GDRW_BG0, GDRW_BG1, GDRW_BG2, GDRW_BG3, each corresponding to a bank group BG0-3. Optionally, as shown in Figure 6As shown, data from BG0 and DBI information can be provided to relay circuit 618, data from BG2 and DBI information can be provided to relay circuit 622, and data from BG3 and DBI information can be provided to relay circuit 624 and / or relay circuit 622 before being provided to DQ block 620. Relay circuits 618, 622, and 624 can amplify signals from the bank groups, which may attenuate within the distance of the data bus. However, if a bank group such as BG1 is close enough to DQ block 620, or the signal is strong enough, then one or more of relay circuits 618, 622, and 624 can be omitted.

[0058] However, the circuitry of semiconductor device 600 may not support multiple DQ mappings for the same I / O width. For example, semiconductor device 600 may support DQ mapping 300 but only one of DQ mapping 400 or DQ mapping 500.

[0059] Figure 7 is a block diagram of a portion of a semiconductor device in accordance with at least one embodiment of the present disclosure. In some embodiments, semiconductor device 700 may be included in semiconductor device 200. Semiconductor device 700 may support multiple DQ mappings, including DQ mappings for the same I / O width. For example, in some embodiments, semiconductor device 700 may support DQ mapping 300, DQ mapping 400, and DQ mapping 500.

[0060] As Figure 7 shown, semiconductor device 700 may include some components that are substantially the same as those of semiconductor device 600. Thus, for the sake of brevity, functions of components in semiconductor device 700 that are substantially the same as those of the components of semiconductor device 600 will not be described in detail with reference to semiconductor device 700. When appropriate, circuit and component differences between semiconductor device 600 and semiconductor device 700 will be pointed out.

[0061] Similar to semiconductor device 600, data is provided from the bank groups BG0-3 of memory array 702 to DpTier region 704 via data lines. Comparing DQ mapping 300 and DQ mapping 500, the DQ mappings for the memory planes on the J side are the same, so data lines 708 can be substantially the same as data lines 608. However, the data for the memory planes on the K side is swapped between DQ mapping 300 and DQ mapping 500. Thus, eight data lines 710 are provided for each K side, four more than data lines 610. Although Figure 7Although not shown in the figure, in some embodiments, a multiplexer may be used to swap the data on the K side to implement the DQ mapping according to the DQ mapping 500. To support the additional data lines 710, the driver circuit 712 for each bank group may include two read drivers for each J side and two read drivers for each K side. Thus, two read drivers are provided for both the J side and the K side, rather than only one read driver for the K side as in the driver circuit 612.

[0062] When implementing the DQ mapping 500, data from two UIs may be provided. Thus, the DBI information must be a two-bit signal that generates data for two UIs, rather than a single-bit signal. Additional logic may be provided in the WDBI circuit 714 to provide 2-bWDBI information. In some embodiments, the RDBI circuit 716 may also include additional logic for generating 2-bRDBI information. However, in some embodiments, the DpTier region 704 may be crowded, and adding additional logic may require an increase in the die size of the semiconductor device 700. This may be undesirable in some applications.

[0063] In some embodiments, the region surrounding the DQ block 720 and the repeaters 718, 722, 724 may be less crowded than the DpTier region 704. Thus, in some embodiments, such as Figure 7 the embodiment shown in the figure, additional RDBI circuits 728, 730, 732, 734, and 736 for providing the second bit of the RDBI information may be located along the data buses GDRW_BG0, GDRW_BG1, GDRW_BG2, GDRW_BG3. Placing the additional RDBI circuits 728, 730, 732, 734, and 736 outside the DpTier region 704 may reduce or eliminate the increase in die size required to support all three DQ mappings 300, 400, and 500.

[0064] In some embodiments, semiconductor device 700 may include a selection circuit 740. The selection circuit 740 may include one or more fuses, antifuses, and / or switches. The selection circuit 740 may selectively activate or deactivate (e.g., enable or disable) one or more of the components of the semiconductor device 700 depending on which of multiple DQ mappings is implemented. For example, if DQ mapping 300 or 400 is implemented, the selection circuit 740 may deactivate the additional read drivers on the K side in the drive circuit 712, the additional logic for the 2-b WDBI signal in the WDBI circuit 714, and / or the additional RDBI circuits 728, 730, 732, 734, and 736. In some embodiments, the selection circuit 740 may provide signals that implement data swapping or other signal routing to one or more multiplexers (not shown). In some embodiments, the selection circuit 740 may be initially programmed by the manufacturer of the semiconductor device 700. In other embodiments, the selection circuit 740 may be programmed by the user of the semiconductor device 700. For example, the user may provide a command to set the state of one or more fuses, antifuses, and / or switches of the selection circuit 740 via a command address terminal (e.g., as Figure 2 shown). In some embodiments, the selection circuit 740 may be programmed to select a desired DQ mapping by writing a value to a mode register (e.g., mode register 230). The value in the mode register may determine the state of one or more fuses, antifuses, and / or switches of the selection circuit 740. In some embodiments, the selection circuit 740 may be programmed only once. That is, once selected, the DQ mapping used for the semiconductor device 700 cannot be changed. In other embodiments, the DQ mapping may be changed by providing an additional command to select a different DQ mapping.

[0065] Although Figure 7 the examples shown in

[0066] Figure 6 and 7 show that specific circuits may be used to at least partially support multiple DQ mappings, in other examples, the circuitry for supporting different DQ mappings may be mutually exclusive. Figures 3 to 5 The circuitry for supporting multiple DQ mappings shown in

[0067] Figure 8 is provided only as an example and is based on the specific DQ mapping examples provided in

[0068] At block 802, "receiving a command at a command address terminal" may be performed. The command may be received at a semiconductor device (e.g., semiconductor devices 200, 600, and / or 700). The command may be received from a memory controller such as memory controllers 101(A)-101(C).

[0069] In response to the command, at block 804, "activating or deactivating at least one circuit to implement one of a plurality of mappings" may be performed. The mapping may be a DQ mapping, where an individual mapping of the plurality of mappings indicates a relationship between a plurality of memory cells and at least a portion of a plurality of data terminals. At least two of the plurality of mappings may indicate a relationship for the same portion of the plurality of data terminals. That is, at least two in the DQ mapping may be for the same I / O width (e.g., x8, x4). In some embodiments, activating or deactivating the at least one circuit may include setting a state of at least one of a fuse, an antifuse, or a switch.

[0070] At block 806, "providing data from memory cells to at least a portion of a plurality of data terminals according to the implemented mapping of the plurality of mappings" may be performed. Additionally or alternatively, at block 808, "storing data received at the at least a portion of the data terminals in memory cells according to the implemented mapping of the plurality of mappings" may be performed.

[0071] The devices, systems, and methods disclosed herein may support multiple DQ mappings in a memory device. Different DQ mappings may be provided for different I / O widths as well as for the same I / O width. Different DQ mappings for the same I / O width may provide at least some different characteristics from each other. This may allow a wider range of customers to utilize the memory device and / or to utilize the memory device in a wider range of applications. In some embodiments, the circuitry for supporting DQ mappings for different I / O widths may be used to at least partially support one or more of the multiple DQ mappings for the same I / O width. This may reduce the number of additional circuits or other components required to support multiple DQ mappings.

[0072] Certain details are set forth herein to provide a sufficient understanding of examples of the present disclosure. However, one of ordinary skill in the art will understand that examples of the present disclosure may be practiced without these specific details. Additionally, the specific examples of the present disclosure described herein should not be construed as limiting the scope of the present disclosure to these specific examples. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail so as not to unnecessarily obscure the present disclosure. Additionally, terms such as "couples" and "coupled" mean that two components may be directly or indirectly electrically coupled. Indirect coupling may imply that two components are coupled through one or more intermediate components.

Claims

1. An apparatus, comprising: Comprising: A plurality of data terminals; A memory bank including a plurality of memory cells; And A plurality of circuits including a first plurality of circuits and a second plurality of circuits, wherein the first plurality of circuits are configured to implement a first mapping between the memory bank and the plurality of data terminals, and the second plurality of circuits are configured to implement a second mapping between the memory bank and the plurality of data terminals, Wherein the first mapping indicates a first relationship between the plurality of memory cells of the memory bank and the plurality of data terminals, and the second mapping indicates a second relationship different from the first relationship between the plurality of memory cells of the memory bank and the plurality of data terminals.

2. The apparatus according to claim 1, wherein the plurality of circuits further includes a third plurality of circuits configured to implement a third mapping between the memory bank and a subset of the plurality of data terminals, wherein the subset includes less than all of the plurality of data terminals.

3. The apparatus according to claim 2, wherein at least one of the first plurality of circuits and the second plurality of circuits includes at least a portion of the third plurality of circuits.

4. The apparatus according to claim 1, wherein the circuits in the first plurality of circuits and the circuits in the second plurality of circuits are mutually exclusive.

5. The apparatus according to claim 1, wherein at least one of the plurality of circuits includes a circuit configured to provide data bus transposition information for a plurality of bits provided on one of the plurality of data terminals.

6. The apparatus according to claim 1, wherein at least one of the plurality of circuits includes a circuit configured to provide error correction code (ECC) data for a plurality of bits provided on one of the plurality of data terminals.

7. The apparatus according to claim 1, further comprising at least one of a fuse, an anti-fuse, or a switch, wherein the plurality of circuits are configured to implement the first mapping or the second mapping at least in part based on the state of the fuse, the anti-fuse, or the switch.

8. The apparatus according to claim 7, wherein at least a portion of the plurality of circuits is enabled or disabled at least in part based on the state of the fuse, the anti-fuse, or the switch.

9. The apparatus according to claim 1, wherein the first relationship indicates a memory cell in the plurality of memory cells that stores a bit received from one of the plurality of data terminals.

10. A system, comprising: Comprising: A memory controller including a first plurality of data terminals; And A memory device, comprising: A second plurality of data terminals, wherein at least a portion of the second plurality of data terminals is coupled to the first plurality of data terminals; A memory bank including a plurality of memory cells; and Multiple circuits configured to implement one of a first mapping or a second mapping, where the first mapping indicates a first relationship between the multiple memory cells of the memory bank and the portion of the second multiple data terminals coupled to the first multiple data terminals, and the second mapping indicates a second relationship different from the first relationship between the multiple memory cells of the memory bank and the portion of the second multiple data terminals coupled to the first multiple data terminals.

11. The system of claim 10, wherein the number of the first multiple data terminals is equal to the number of the second multiple data terminals.

12. The system of claim 10, wherein the memory controller is configured to provide a command to the memory device that causes the multiple circuits to implement the first mapping or the second mapping.

13. The system of claim 12, wherein the memory device includes a mode register and the command includes a mode register write command.

14. The system of claim 12, wherein the memory device includes at least one of a fuse, an antifuse, or a switch, and the command sets the state of at least one of the fuse, the antifuse, or the switch.

15. The system of claim 12, wherein the multiple circuits include a first multiple circuits configured to implement the first mapping and a second multiple circuits configured to implement the second mapping.

16. The system of claim 15, wherein the multiple circuits further include a third multiple circuits configured to implement a third mapping between the memory bank and several of the second multiple data terminals, the number of the several of the second multiple data terminals being different from the number of the portion of the second multiple data terminals coupled to the first multiple data terminals.

17. The system of claim 16, wherein at least one of the first multiple circuits and the second multiple circuits includes at least a portion of the third multiple circuits.

18. A method, which includes: receiving a command at a command address terminal; in response to the command, activating or deactivating at least one circuit to implement one of multiple mappings, where individual mappings of the multiple mappings indicate relationships between multiple memory cells and at least a portion of multiple data terminals, and where at least two of the multiple mappings indicate relationships for the same portion of the multiple data terminals; and providing data from the memory cells to at least the portion of the multiple data terminals according to the implemented mapping of the multiple mappings.

19. The method of claim 18, which further includes storing data received at at least the portion of the data terminals in the memory cells according to the implemented mapping of the multiple mappings.

20. The method of claim 18, wherein activating or deactivating the at least one circuit includes setting the state of at least one of a fuse, an antifuse, or a switch.

21. The method according to claim 18, wherein activating or deactivating the at least one circuit includes writing a value to a mode register.

22. The method according to claim 18, wherein the portion of the plurality of data terminals includes all of the plurality of data terminals.

Images