Display device

Abstract

Embodiments of the present disclosure relate to display devices. Specifically, a display device is provided, which includes: a display panel, which includes a plurality of data lines, a plurality of gate lines, a plurality of sub-pixels, and a plurality of reference voltage lines electrically connected to the plurality of sub-pixels, each of the plurality of sub-pixels including a driving transistor and a light-emitting element; and a gate driving circuit, which is configured to supply a gate signal to the plurality of gate lines, wherein there are three or more time periods, during which, when the gate driving circuit applies a gate signal of a turn-on level voltage to any one of the plurality of sub-pixels, the voltage change slope of the reference voltage line electrically connected to any one of the sub-pixels decreases and then recovers. Therefore, a display device that reduces the voltage level of a high-potential driving voltage applied to the display panel to a minimum can be provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0105623, filed on August 10, 2021, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device. Background Art

[0004] As the information society develops, various demands for display devices for displaying images are increasing, and various types of display devices such as liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays are used.

[0005] Such a display device includes a display panel including a plurality of sub-pixels, and a high potential driving voltage EVDD is applied to the display panel to drive the plurality of sub-pixels.

[0006] Meanwhile, such a high potential driving voltage EVDD is applied to the display panel at a high voltage level. A scheme for appropriately lowering the voltage level of the high potential driving voltage EVDD and supplying it to the display panel is required. Summary of the invention

[0007] Embodiments of the present disclosure may provide a display device that reduces a voltage level of a high-potential driving voltage and supplies it to a display panel.

[0008] An embodiment of the present disclosure may provide a display device, comprising: a display panel, comprising a plurality of gate lines, a plurality of sub-pixels, and a plurality of reference voltage lines electrically connected to the plurality of sub-pixels, each of the plurality of sub-pixels comprising a driving transistor and a light-emitting element; and a gate driving circuit, configured to supply gate signals to the plurality of gate lines, wherein there are three or more time periods, during which, when the gate driving circuit applies a gate signal of an on-level voltage to any one of the plurality of sub-pixels, a voltage change slope of the reference voltage line electrically connected to any one of the sub-pixels decreases and then recovers.

[0009] An embodiment of the present disclosure may provide a display device, which includes: a display panel, which includes a plurality of sub-pixels, each of which includes a driving transistor and a light-emitting element; and a driving circuit, which is configured to drive the display panel, wherein the driving circuit includes: an original high-potential driving voltage input terminal, to which the original high-potential driving voltage is input; a high-potential driving voltage output terminal, which outputs the high-potential driving voltage to the display panel, and outputs the high-potential driving voltage having a voltage level lower than the original high-potential driving voltage; a driving voltage via line, which electrically connects the original high-potential input terminal with the high-potential driving voltage output terminal; a reference resistor, which is located on the driving voltage via line; a resistor unit, which is electrically connected to the driving voltage via line; a switch unit, which is configured to switch the electrical connection between the resistor unit and a low-potential power supply; and a controller, which is configured to control the switch unit.

[0010] An embodiment of the present disclosure may provide a display device, comprising: a display panel; a controller for controlling a data driving circuit and a gate driving circuit of the display panel, wherein the controller is mounted on a control printed circuit board; and a setting board electrically connected to the control printed circuit board, wherein a main power management circuit for managing the total power of the display device is arranged on the setting board, wherein the control printed circuit board comprises an original high potential driving voltage input terminal and a high potential driving voltage output terminal, the original high potential driving voltage output from the setting board is input to the original high potential driving voltage input terminal, and the high potential driving voltage output terminal outputs the high potential driving voltage to the display panel, and the controller controls the main power management circuit to reduce the voltage level of the original high potential driving voltage output from the setting board.

[0011] According to various embodiments, a display device that reduces a voltage level of a high potential driving voltage and supplies it to a display panel may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a view showing a display device according to the present disclosure;

[0014] Figure 2 is a view schematically showing a display device according to the present disclosure;

[0015] Figure 3 is a view showing an example of a path from output of an original high potential driving voltage from a setting board to input of the high potential driving voltage to a display panel;

[0016] Figure 4 is a view schematically showing an equivalent circuit of a sub-pixel and a configuration for compensating a characteristic value of the sub-pixel according to the present disclosure;

[0017] Figure 5 is a view showing a threshold voltage sensing driving scheme of a driving transistor of a display device according to the present disclosure;

[0018] Figure 6 is a view showing a mobility sensing driving scheme of a driving transistor of a display device according to the present disclosure;

[0019] Figure 7 is a view showing a plurality of sampling processes MSP for generating a driving voltage EVDD of an appropriate level in a display device according to the present disclosure;

[0020] Figure 8 is a view showing according to Figure 7 an example of a drain voltage Vds and a drain current Id of a driving transistor at a sampling time;

[0021] Fig. 9 is a view showing adjustment of a voltage output from a high-potential driving voltage output terminal by a controller;

[0022] Fig.10 is a view showing adjustment of a voltage input to an original high-potential driving voltage input terminal by a controller; and

[0023] Fig.11 is a view showing a reduction of a high-potential driving voltage in a display device according to the present disclosure. DETAILED DESCRIPTION

[0024] In the following description of examples or embodiments of the present invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated by way of illustration, and the same reference numerals and symbols in the drawings can be used to designate the same or similar components, even if they are shown in different drawings from each other. Further, in the following description of examples or embodiments of the present invention, when it is determined that the description may make the subject matter in some embodiments of the present invention quite unclear, a detailed description of well-known functions and components incorporated herein will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of", and "formed of" as used herein are generally intended to allow the addition of other components, unless the term is used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0025] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present invention. Each of these terms is not used to limit the nature, order, sequence or number of elements, etc., but is only used to distinguish the corresponding element from other elements.

[0026] When it is mentioned that a first element is "connected or coupled to", "contacts or overlaps", etc. a second element, it should be understood that not only the first element may be "directly connected or coupled to" or "directly contact or overlaps" the second element, but also a third element may be "interposed" between the first and second elements, or the first and second elements may be "connected or coupled to", "contacts or overlaps", etc. each other via a fourth element. Here, the second element may be included in at least one of the two or more elements that are "connected or coupled to", "contacts or overlaps", etc. each other.

[0027] When time-related terms such as "after", "subsequently", "next", "before", etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe non-sequential or non-sequential processes or operations unless the terms "directly" or "immediately" are used together.

[0028] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully includes all meanings of the term "can".

[0029] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0030] Figure 1 is a view showing a display device 100 according to the present disclosure.

[0031] Reference Figure 1 , a display device 100 according to the present disclosure may include: a display panel 110 ; a data driving circuit 120 and a gate driving circuit 130 for driving the display panel 110 ; and a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130 .

[0032] In the display panel 110, signal lines such as a plurality of data lines DL and a plurality of gate lines GL may be disposed on a substrate. In the display panel 110, a plurality of sub-pixels SP connected to the plurality of data lines DL and the gate lines GL may be disposed.

[0033] The display panel 110 may include a display area AA in which an image is displayed and a non-display area NA in which an image is not displayed. In the display panel 110, a plurality of sub-pixels SP for displaying an image may be disposed in the display area AA, and in the non-display area NA, a data driving circuit 120 and a gate driving circuit 130 may be installed, or a pad unit connected to the data driving circuit 120 or the gate driving circuit 130 may be disposed.

[0034] The data driving circuit 120 is a circuit configured to drive a plurality of data lines DL, and may supply a data voltage to the plurality of data lines DL. The gate driving circuit 130 is a circuit configured to drive a plurality of gate lines GL, and may supply a gate signal Vgate to the plurality of gate lines GL. The controller 140 may supply a data driving timing control signal DCS to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 may supply a gate driving timing control signal GCS to the gate driving circuit 130 for controlling the operation timing of the gate driving circuit 130.

[0035] The controller 140 can start scanning according to the timing implemented in each frame, convert the input image data input from the outside into image data DATA in a data signal format suitable for use in the data driving circuit 120, supply the image data DATA to the data driving circuit 120, and control the data drive at an appropriate time suitable for scanning.

[0036] The controller 140 receives various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, and a clock signal, and input image data from the outside (eg, a host system).

[0037] In order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE and a clock signal CLK, generates various control signals DCS and GCS, and outputs the control signals to the data driving circuit 120 and the gate driving circuit 130.

[0038] In order to control the gate driving circuit 130 , the controller 140 outputs various gate driving timing control signals GCS, including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE.

[0039] In order to control the data driving circuit 120 , the controller 140 outputs various data driving timing control signals DCS including, for example, a source start pulse SSP and a source sampling clock.

[0040] The data driving circuit 120 receives image data DATA from the controller 140 and drives a plurality of data lines DL.

[0041] The data driving circuit 120 may include one or more source driver integrated circuits SDIC.

[0042] Each source driver integrated circuit SDIC can be connected to the display panel 110 through a tape automated bonding (TAB) method, or connected to a bonding pad of the display panel 110 through a chip on glass (COG) method, or can be implemented through a chip on film (COF) method and connected to the display panel 110.

[0043] The gate driving circuit 130 may output a gate signal of an on-level voltage or a gate signal of an off-level voltage according to the control of the controller 140. The gate driving circuit 130 may drive the plurality of gate lines GL by supplying the gate signal of an on-level voltage to the plurality of gate lines GL.

[0044] The gate driving circuit 130 can be connected to the display panel 110 through a tape automated bonding (TAB) method, or connected to a bonding pad of the self-luminous display panel 110 through a COG or chip on panel (COP) method, or can be connected to the display panel 110 according to a COF method.

[0045] The gate driving circuit 130 may be formed in a gate-in-panel (GIP) type in the non-display area NA of the display panel 110. The gate driving circuit 130 may be disposed on a substrate of the display panel 110 or may be connected to the substrate of the display panel 110. The gate driving circuit 130 of the GIP type may be disposed in the non-display area NA of the substrate. The gate driving circuit 130 of the chip-on-glass (COG) type or the chip-on-film (COF) type may be connected to the substrate of the display panel 110.

[0046] When a specific gate line GL is turned on by the gate driving circuit 130 , the data driving circuit 120 may convert the image data DATA received from the controller 140 into an analog data voltage and supply it to the plurality of data lines DL.

[0047] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on a driving scheme or a panel design scheme, the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the self-luminous display panel 110, or to two or more of the four sides of the self-luminous display panel 110.

[0048] The gate driving circuit 130 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on a driving scheme or a panel design scheme, the gate driving circuit 130 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or to two or more of the four sides of the display panel 110.

[0049] The controller 140 may be a timing controller used in a typical display technology, a control device that may perform other control functions as well as the functions of the timing controller, or a control device other than the timing controller, or may be a circuit in the control device. The controller 140 may be implemented as various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0050] The controller 140 may be mounted on a printed circuit board or a flexible printed circuit, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board or the flexible printed circuit.

[0051] The controller 140 may transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces. The interface may include, for example, a low voltage differential signaling (LVDS) interface, an EPI interface, and a serial peripheral interface (SPI).

[0052] The controller 140 may include a storage medium such as one or more registers.

[0053] The display device 100 according to an embodiment of the present disclosure may be a display including a backlight unit, such as a liquid crystal display, or may be a self-luminous display, such as an organic light emitting diode (OLED) display, a quantum dot display, or a micro light emitting diode (LED) display.

[0054] According to an embodiment, when the display device 100 is an OLED display, each sub-pixel SP may include a self-luminous organic light emitting diode (OLED) as a light emitting element. According to an embodiment, when the display device 100 is a quantum dot display, each sub-pixel SP may include a light emitting element formed of a quantum dot as a self-luminous semiconductor crystal. According to an embodiment, when the display device 100 is a micro LED display, each sub-pixel SP may include a self-luminous micro light emitting diode formed of an inorganic material as a light emitting element.

[0055] Figure 2 is a view schematically showing a display device 100 according to the present disclosure.

[0056] Figure 2An example is shown in which the data driving circuit 120 in the display device 100 according to the present disclosure is implemented in a chip on film (COF) scheme among various schemes such as TAB, COG, or COF.

[0057] The data driving circuit 120 may include one or more data driving circuits. The data driving circuit 120 may be implemented as a source driver integrated circuit SDIC. When the data driving circuit 120 is implemented in a chip on film (COF) scheme, the source driver integrated circuit SDIC may be mounted on a source circuit film SF.

[0058] One side of the source circuit film SF may be electrically connected to the display panel 110. A line for electrically connecting the source driver integrated circuit SDIC and the display panel 110 may be disposed on the source circuit film SF.

[0059] The display device 100 according to the present disclosure may include: at least one source printed circuit board SPCB for circuit connection between one or more source driving integrated circuits SDIC and other devices; and a control printed circuit board CPCB.

[0060] The other side of the source circuit film SF may be electrically connected to the source printed circuit board SPCB.

[0061] Figure 2 An example is shown in which the gate driving circuit 130 in the display device 100 according to the present disclosure is implemented in a chip on film (COF) scheme among various schemes such as TAB, COG, COF, or GIP.

[0062] The gate driving circuit 130 may include a gate driver integrated circuit GDIC. When the gate driving circuit 130 is implemented in a chip on film (COF) scheme, the gate driver integrated circuit GDIC may be mounted on the gate circuit film GF.

[0063] One side of the gate circuit film GF may be electrically connected to the display panel 110. A line for electrically connecting the gate driver integrated circuit GDIC and the display panel 110 may be disposed on the gate circuit film GF.

[0064] The controller 140 and the power management integrated circuit (PMIC) 240 may be mounted on the control printed circuit board CPCB. The controller 140 may control the data driving circuit 120 and the gate driving circuit 130. The power management integrated circuit 240 may supply driving voltage or current to the display panel 110, the data driving circuit 120, and the gate driving circuit 130.

[0065] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be circuit-connected by at least one connecting member. The connecting member may be, for example, a flexible printed circuit FPC or a flexible flat cable FFC.

[0066] At least one source printed circuit board SPCB and a control printed circuit board CPCB may be integrated into one printed circuit board.

[0067] The display device 100 according to the present disclosure may further include a setting board 210 electrically connected to the control printed circuit board CPCB. A main power management circuit 220 for managing the total power of the display device 100 may be on the setting board 210. The main power management circuit 220 may interwork with a power management integrated circuit 240.

[0068] The driving voltage generated by the setting board 210 is transmitted to the power management integrated circuit 240 in the control printed circuit board CPCB. The power management integrated circuit 240 transmits the driving voltage required for driving the display device 100 or sensing the characteristic value (for example, sensing the characteristic value of the sub-pixel) to the source printed circuit board SPCB through the connection member. The power management integrated circuit 240 can supply the driving voltage to the data driving circuit 120, the gate driving circuit 130 or the display panel 110.

[0069] Figure 3 1 is a view showing an example of a path from the output of the original high potential driving voltage EVDD_in from the setting board 210 to the input of the high potential driving voltage EVDD_out to the display panel 110 .

[0070] Reference Figure 3 , a main power management circuit 220 may be provided on the setting board 210. The main power management circuit 220 may be a circuit for managing power of the entire display device.

[0071] The setup board 210 outputs an original high potential driving voltage EVDD_in. The original high potential driving voltage EVDD_in may be input to the control printed circuit board CPCB.

[0072] The original high potential driving voltage EVDD_in output from the setting board 210 is input to the original high potential driving voltage input terminal 310 of the control printed circuit board CPCB.

[0073] The control printed circuit board CPCB may include a high potential driving voltage output terminal 320. The high potential driving voltage EVDD_out is output from the high potential driving voltage output terminal 320.

[0074] The setup board 210 may output an original high potential driving voltage EVDD_in having a preset voltage level to drive the display panel 110 .

[0075] In order to stably drive the display panel 110 , the setup board 210 may output the original high potential driving voltage EVDD_in having a higher voltage level than a minimum voltage level required to actually drive the display panel 110 .

[0076] The control printed circuit board CPCB may output the high potential driving voltage EVDD_out having the same voltage level as the input original high potential driving voltage EVDD_in from the high potential driving voltage output terminal 320 .

[0077] In other words, the high potential driving voltage EVDD_out ensuring a sufficient margin is continuously output from the high potential driving voltage output terminal 320 regardless of the minimum voltage required to drive the display panel 110 .

[0078] The high potential driving voltage EVDD_out output from the high potential driving voltage output terminal 320 may be input to the display panel 110 through the source printed circuit board.

[0079] Hereinafter, the high potential driving voltage EVDD_out input to the display panel 110 is referred to as a driving voltage EVDD.

[0080] Figure 4 is a view schematically illustrating an equivalent circuit of a sub-pixel SP and a configuration for compensating a characteristic value of the sub-pixel SP according to the present disclosure.

[0081] Reference Figure 4 , each of a plurality of sub-pixels SP provided on the display panel 110 of the display device 100 according to the present disclosure may include a light emitting element ED, a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0082] The light emitting element ED may include a pixel electrode PE and a common electrode CE, and may include a light emitting layer EL between the pixel electrode PE and the common electrode CE.

[0083] The pixel electrode PE of the light emitting element ED may be an electrode provided in each sub-pixel SP, and the common electrode CE may be an electrode provided in common in all sub-pixels SP. Here, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. Conversely, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode.

[0084] For example, the light emitting element ED may be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting element.

[0085] The driving transistor DRT is a transistor for driving the light-emitting element ED, and may include a first node N1, a second node N2, and a third node N3.

[0086] The first node N1 of the driving transistor DRT may be the gate node of the driving transistor DRT, and may be electrically connected to the source node or the drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT may be the source node or the drain node of the driving transistor DRT, and may be electrically connected to the source node or the drain node of the sensing transistor SENT, and may also be electrically connected to the pixel electrode PE of the light-emitting element ED. The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL that supplies the driving voltage EVDD.

[0087] The scanning transistor SCT may be controlled by a scanning pulse SCAN which is a kind of gate signal, and may be connected between the first node N1 of the driving transistor DRT and the data line DL. In other words, the scanning transistor SCT may be turned on or off according to the scanning pulse SCAN supplied from the scanning line SCL which is a kind of gate line GL, thereby controlling the connection between the data line DL and the first node N1 of the driving transistor DRT.

[0088] The scanning transistor SCT may be turned on by the scanning pulse SCAN having a turn-on level voltage, and transmit the data voltage Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT.

[0089] If the scanning transistor SCT is an n-type transistor, the turn-on level voltage of the scanning pulse SCAN may be a high level voltage. If the scanning transistor SCT is a p-type transistor, the turn-on level voltage of the scanning pulse SCAN may be a low level voltage.

[0090] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with an amount of electric charge corresponding to the voltage difference between its two ends, and is used to maintain the voltage difference between the two ends within a predetermined frame time. Therefore, during the predetermined frame time, the corresponding sub-pixel SP may emit light.

[0091] Refer to Figure 4 , each of the plurality of sub-pixels SP provided on the display panel 110 of the display device 100 may further include a sensing transistor SENT.

[0092] The sensing transistor SENT may be controlled by a sensing pulse SENSE as a gate signal and may be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. In other words, the sensing transistor SENT may be turned on or off according to the sensing pulse SENSE supplied from the sensing line SENL as another gate line GL, thereby controlling the connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0093] The second node N2 of the driving transistor DRT is also referred to as a sensing node.

[0094] The sensing transistor SENT may be turned on by a sensing pulse SENSE having an on-level voltage and transmit a reference voltage Vref supplied from a reference voltage line RVL to a second node N2 of the driving transistor DRT. The reference voltage line RVL is also referred to as a sensing line.

[0095] The initialization switch SPRE switches the electrical connection between the reference voltage line RVL and the reference voltage supply node Nref. The initialization switch SPRE may include one end electrically connected to the reference voltage line RVL and the other end electrically connected to the reference voltage supply node Nref.

[0096] A reference voltage Vref is applied to a reference voltage supply node Nref.

[0097] The sensing transistor SENT may be turned on by the sensing pulse SENSE having an on-level voltage and transmit the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0098] If the sensing transistor SENT is an n-type transistor, the on-level voltage of the sensing pulse SENSE may be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the on-level voltage of the sensing pulse SENSE may be a low-level voltage.

[0099] The function in which the sensing transistor SENT transmits the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used to sense the characteristic value of the sub-pixel SP during driving. In this case, the voltage transmitted to the reference voltage line RVL can be a voltage for calculating the characteristic value of the sub-pixel SP or a voltage reflecting the characteristic value of the sub-pixel SP.

[0100] Each of the driving transistor DRT, the scanning transistor SCT and the sensing transistor SENT may be an n-type transistor or a p-type transistor. In an embodiment of the present disclosure, for ease of description, each of the driving transistor DRT, the scanning transistor SCT and the sensing transistor SENT is an n-type transistor.

[0101] The storage capacitor Cst is not a parasitic capacitor (eg, Cgs or Cgd) as an internal capacitor existing between the gate node and the source node (or drain node) of the driving transistor DRT, but may be an external capacitor intentionally designed outside the driving transistor DRT.

[0102] The scan line SCL and the sensing line SENL may be different gate lines GL. In this case, the scan pulse SCAN and the sensing pulse SENSE may be separate gate signals, and the on-off timing of the scan transistor SCT in one sub-pixel SP and the on-off timing of the sensing transistor SENT may be independent. In other words, the on-off timing of the scan transistor SCT in one sub-pixel SP and the on-off timing of the sensing transistor SENT may be the same or different.

[0103] Alternatively, the scan line SCL and the sensing line SENL may be the same gate line GL. In other words, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP may be connected to one gate line GL. In this case, the scan pulse SCAN and the sensing pulse SENSE may be the same gate signal, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be the same.

[0104] Figure 4 The structure of the subpixel SP shown is merely an example, and various changes may be made thereto, such as including one or more transistors or one or more capacitors, for example.

[0105] Although reference is made to the assumption that the display device 100 is a self-luminous display device Figure 4 The structure of the sub-pixel SP is described, but if the display device 100 is a liquid crystal display, each sub-pixel SP may include a transistor and a pixel electrode.

[0106] Reference Figure 4 , the display device 100 according to the present disclosure may include a line capacitor Cline. The line capacitor Cline may be a capacitor element having one end electrically connected to the reference voltage line RVL, or may be a parasitic capacitor formed on the reference voltage line RVL.

[0107] Reference Figure 4 , the source driver integrated circuit SDIC may further include an analog-to-digital converter ADC and a sampling switch SAM.

[0108] The reference voltage line RVL may be electrically connected to the analog-to-digital converter ADC. The analog-to-digital converter ADC may sense the voltage of the reference voltage line RVL. The voltage sensed by the analog-to-digital converter ADC may be a voltage reflecting a characteristic value of the sub-pixel SP.

[0109] In the present disclosure, the characteristic value of the subpixel SP may be a characteristic value of the driving transistor DRT or the light emitting element ED. The characteristic value of the driving transistor DRT may include a threshold voltage and mobility of the driving transistor DRT. The characteristic value of the light emitting element ED may include a threshold voltage of the light emitting element ED.

[0110] The analog-to-digital converter ADC may receive an analog voltage, convert the analog voltage into a digital value, and output the digital value to the controller 140 .

[0111] The sampling switch SAM may be located between the analog-to-digital converter ADC and the reference voltage line RVL. The sampling switch SAM may switch the electrical connection between the reference voltage line RVL and the analog-to-digital converter ADC.

[0112] The controller 140 may include a storage unit 410 that stores characteristic value information about the sub-pixel SP and a compensation circuit 420 that performs calculation for compensating for a variation in the characteristic value of the sub-pixel SP based on the information stored in the storage unit 410 .

[0113] The storage unit 410 may store information for compensating the characteristic value of the sub-pixel SP. For example, the storage unit 410 may store information about the threshold voltage and mobility of the driving transistor DRT of each of the plurality of sub-pixels SP and information about the threshold voltage of the light emitting element ED included in the sub-pixel SP.

[0114] Information on the threshold voltage of the light emitting element ED may be stored in a lookup table LUT.

[0115] The compensation circuit 420 calculates the variation degree of the characteristic value of the corresponding subpixel SP based on the characteristic value information about the subpixel SP stored in the storage unit 410 and the digital value received from the analog-to-digital converter ADC. The compensation circuit 420 updates the characteristic value of the subpixel SP stored in the storage unit 410.

[0116] The controller 140 compensates for the image data by applying the variation of the characteristic value of the sub-pixel SP calculated by the compensation circuit 420 , thereby driving the data driving circuit 120 .

[0117] The data voltage Vdata reflecting the change of the characteristic value of the sub-pixel SP may be output to the data line DL through the digital-to-analog converter DAC.

[0118] The process of sensing the change in the characteristic value of the sub-pixel SP and compensating for it is referred to as a “sub-pixel characteristic value compensation process”.

[0119] Figure 5 is a view showing a threshold voltage Vth sensing driving scheme of a driving transistor DRT of a display device according to the present disclosure.

[0120] The threshold voltage sensing drive for the driving transistor DRT may be performed through a sensing process including an initialization step, a tracking step, and a sampling step.

[0121] The initialization step is a step of initializing the first node N1 and the second node N2 of the driving transistor DRT.

[0122] In the initialization step, the scanning transistor SCT and the sensing transistor SENT are turned on, and the initialization switch SPRE is turned on.

[0123] Therefore, the first node N1 and the second node N2 of the driving transistor DRT are initialized to the threshold voltage sensing driving data voltage Vdata and the reference voltage Vref ( V1 =Vdata, V2 =Vref), respectively.

[0124] The tracking step is a step of changing the voltage V2 of the second node N2 of the driving transistor DRT until the voltage of the second node N2 of the driving transistor DRT becomes a voltage state reflecting the threshold voltage or a change thereof.

[0125] In other words, the tracking step is a step of tracking the voltage of the second node N2 of the driving transistor DRT which may reflect the threshold voltage or a change thereof.

[0126] In the tracking step, the initialization switch SPRE is turned off or the sensing transistor SENT is turned off, so that the second node N2 of the driving transistor DRT floats.

[0127] Therefore, the voltage of the second node N2 of the driving transistor DRT rises.

[0128] The rise of the voltage V2 of the second node N2 of the driving transistor DRT gradually slows down, and then the voltage V2 is saturated.

[0129] The saturation voltage of the second node N2 of the driving transistor DRT may correspond to a difference between the data voltage Vdata and the threshold voltage Vth or a difference between the data voltage Vdata and the threshold voltage deviation ΔVth.

[0130] If the voltage V2 of the second node N2 of the driving transistor DRT is saturated, the sampling step may be performed.

[0131] The sampling step is a step of measuring a voltage reflecting a threshold voltage or a change thereof, and the analog-to-digital converter ADC senses the voltage of the reference voltage line RVL, that is, the voltage V2 of the second node N2 of the driving transistor DRT.

[0132] The voltage Vsen sensed by the analog-to-digital converter ADC may be a voltage Vdata_SEN-Vth obtained by subtracting a threshold voltage Vth from the data voltage Vdata, or a voltage Vdata-ΔVth obtained by subtracting a threshold voltage deviation ΔVth from the data voltage Vdata. Here, Vth may be a positive threshold voltage or a negative threshold voltage.

[0133] Figure 6 is a view showing a mobility sensing driving scheme of a driving transistor DRT of a display device according to the present disclosure.

[0134] The mobility sensing drive for the driving transistor DRT may be performed through a sensing process including an initialization step, a tracking step, and a sampling step.

[0135] The initialization step is a step of initializing the first node N1 and the second node N2 of the driving transistor DRT.

[0136] In the initialization step, the scanning transistor SCT and the sensing transistor SENT are turned on, and the initialization switch SPRE is turned on.

[0137] Therefore, the first node N1 and the second node N2 of the driving transistor DRT are initialized to the mobility sensing driving data voltage Vdata and the reference voltage Vref ( V1 =Vdata, V2 =Vref), respectively.

[0138] The tracking step is a step of changing the voltage V2 of the second node N2 of the driving transistor DRT until the voltage of the second node N2 of the driving transistor DRT becomes a voltage state reflecting the mobility or a change thereof.

[0139] In other words, the tracking step is a step of tracking the voltage of the second node N2 of the driving transistor DRT which may reflect the mobility or a change thereof.

[0140] In the tracking step, the initialization switch SPRE is turned off or the sensing transistor SENT is turned off, so that the second node N2 of the driving transistor DRT floats. In this case, the scanning transistor SCT can be turned off, so that the first node N1 of the driving transistor DRT can also float.

[0141] Therefore, the voltage V2 of the second node N2 of the driving transistor DRT starts to rise.

[0142] The rising rate of the voltage V2 of the second node N2 of the driving transistor DRT varies depending on the current capability (ie, mobility) of the driving transistor DRT.

[0143] As the current capability (mobility) of the driving transistor DRT increases, the voltage V2 of the second node N2 of the driving transistor DRT further rises sharply.

[0144] After the tracking period is performed during the predetermined time Δt, that is, after the voltage V2 of the second node N2 of the driving transistor DRT rises during the preset tracking time Δt, the sampling period may be performed.

[0145] During the tracking step, the rising rate of the voltage of the second node N2 of the driving transistor DRT corresponds to the voltage variation ΔV within the predetermined time Δt.

[0146] In the sampling step, the sampling switch SAM is turned on, so that the analog-to-digital converter ADC and the reference voltage line RVL are electrically connected.

[0147] Therefore, the analog-to-digital converter ADC senses the voltage of the reference voltage line RVL, that is, the voltage V2 of the second node N2 of the driving transistor DRT.

[0148] The voltage Vsen sensed by the analog-to-digital converter ADC may be a voltage obtained by adding a reference voltage Vref to a voltage variation ΔV during a preset tracking time Δt.

[0149] According to the above combination Figure 5 and Figure 6 In the described threshold voltage or mobility sensing drive, the analog-to-digital converter ADC converts the voltage Vsen sensed for threshold voltage sensing or mobility sensing into a digital value, and generates and outputs sensing data including the digital value (sensing value).

[0150] The sensing data output from the analog-to-digital converter ADC may be provided to the compensation circuit 420. In some cases, the sensing data may be provided to the compensation circuit 420 through the storage unit 410.

[0151] The compensation circuit 420 can grasp the characteristic value (e.g., threshold voltage or mobility) of the driving transistor DRT in the corresponding sub-pixel or the change in the characteristic value of the driving transistor DRT (e.g., change in threshold voltage or change in mobility) based on the sensing data provided from the analog-to-digital converter ADC, and perform a characteristic value compensation process.

[0152] The change in the characteristic value of the driving transistor DRT may mean a change in current sensing data relative to previous sensing data or a change in current sensing data relative to initial compensation data.

[0153] Therefore, the characteristic value deviation between the driving transistors DRT can be grasped by comparing the characteristic values or the changes in the characteristic values between the driving transistors DRT. When the change in the characteristic value of the driving transistor DRT means the change in the current sensed data with respect to the initial compensation data, the characteristic value deviation (i.e., the sub-pixel luminance deviation) between the driving transistors DRT can be grasped based on the change in the characteristic value of the driving transistor DRT.

[0154] The initial compensation data can be the initial setting data set and stored during the manufacture of the display device.

[0155] The characteristic value compensation process may include a threshold voltage compensation process for compensating the threshold voltage of the driving transistor DRT and a mobility compensation process for compensating the mobility of the driving transistor DRT.

[0156] The threshold voltage compensation process may include the following processes: calculating compensation data for compensating the threshold voltage or the threshold voltage deviation (change in the threshold voltage), storing the calculated compensation data in the storage unit 410, or changing the image data DATA to the calculated compensation data.

[0157] The mobility compensation process may include the following processes: calculating compensation data for compensating the mobility or the mobility deviation (change in the mobility), storing the calculated compensation data in the storage unit 410, or changing the image data DATA to the calculated compensation data.

[0158] The compensation circuit 420 may change the image data DATA through the threshold voltage compensation process or the mobility compensation process, and supply the changed data to the corresponding source driver integrated circuit SDIC in the data driver circuit 120.

[0159] Therefore, the source driver integrated circuit SDIC converts the data changed by the compensation unit 420 into a data voltage through an analog-to-digital converter (DAC), and supplies it to the corresponding sub-pixel. By doing so, the compensation of the sub-pixel characteristic value (threshold voltage compensation or mobility compensation) can actually be achieved.

[0160] The driving voltage EVDD is input to the third node N3 of the driving transistor DRT, and the data voltage Vdata is input to the second node N2. The driving transistor DRT can control the amount of current flowing to the light-emitting element ED electrically connected to the driving transistor DRT according to the voltage difference between the second node N2 and the first node N1 (also referred to as the "source-gate voltage difference").

[0161] The driving voltage EVDD has a voltage level capable of operating the driving transistor DRT and driving the light-emitting element ED, and is supplied to the third node N3 of the driving transistor DRT.

[0162] As driving time elapses, the light emitting element ED deteriorates, and a voltage level required to drive the light emitting element ED increases.

[0163] Therefore, the driving voltage EVDD has a sufficiently larger voltage margin than a voltage level required to drive the light emitting element ED and the driving transistor DRT in the initial state, and is applied to the driving transistor DRT.

[0164] However, if the degradation of the light emitting element ED does not occur, such a large voltage margin is not required to drive the display device 100. Therefore, it is necessary to reduce the driving voltage EVDD to an appropriate level.

[0165] Figure 7 is a view showing a plurality of sampling processes MSP for generating a driving voltage EVDD of an appropriate level in the display device 100 according to the present disclosure.

[0166] Reference Figure 7 , the display device 100 can perform multiple sampling processes MSP on one sub-pixel SP.

[0167] The multi-sampling process MSP may be a shutdown sensing process performed before a shutdown sequence such as power-off is performed.

[0168] When the above-described threshold voltage sensing drive is performed as a turn-off sensing process performed before a turn-off sequence such as power-off is performed, a plurality of sampling processes MSP may be performed on the sub-pixels SP where the threshold voltage sensing drive is not performed.

[0169] The plurality of sampling processes MSP may include a first period T1 to a fourth period T4. The first period T1 to the fourth period T4 may be divided according to operation timings of circuit elements included in the sub-pixel SP.

[0170] During the first to fourth periods T1 to T4 , the driving voltage EVDDold before the change is applied to the third node N3 of the driving transistor DRT.

[0171] In the following description, it is assumed that the first node N1 of the driving transistor DRT is a gate node of the driving transistor DRT, the second node N2 of the driving transistor DRT is a source node of the driving transistor DRT, and the third node N3 is a drain node of the driving transistor DRT.

[0172] During the first period T1, a sensing pulse SENSE of an on-level voltage is applied to the sensing transistor SENT and the initialization switch SPRE is turned on. A reference voltage Vref is applied to the reference voltage line RVL and the second node N2 of the driving transistor DRT is initialized to the reference voltage Vref.

[0173] When the sensing pulse SENSE of an on-level voltage is applied to the sensing transistor SENT, the reference voltage line RVL may reflect a change in the voltage of the second node N2 of the driving transistor DRT.

[0174] During the first period T1 , a scan pulse SCAN of an off-level voltage may be applied to the scan transistor SCT.

[0175] During the second period T2, the data voltage Vdata is applied to the data line DL, and the scan pulse SCAN of the on-level voltage is applied to the scan transistor SCT. The data voltage Vdata may be a voltage level of a plurality of sampling processes. The voltage of the first node N1 of the driving transistor DRT may be initialized to the data voltage Vdata of the plurality of sampling processes.

[0176] During the second period T2 , the voltage level of the data voltage Vdata applied to the data line DL may be the same as the voltage level of the mobility sensing driving data voltage of the driving transistor DRT.

[0177] During the second period T2 , the voltage level of the data voltage Vdata applied to the data line DL may be higher than the threshold voltage sensing voltage level of the driving transistor DRT to drive the data voltage.

[0178] During the second period T2, a direct current (DC) voltage is applied to the data line DL. The data voltage Vdata applied to the data line DL during the second period T2 may have a waveform different from an alternating current (AC) data voltage Vdata applied to the data line DL for image display during the image display period.

[0179] During the second period T2 , the voltage of the first node N1 of the transistor DRT is initialized to the data voltage Vdata of a plurality of sampling processes, and the voltage of the second node N2 of the driving transistor DRT is initialized to the reference voltage Vref.

[0180] During the third period T3 , a scan pulse SCAN of an off level voltage may be applied to the scan transistor SCT. A voltage supplied from the storage capacitor Cst is applied to the first node N1 of the driving transistor DRT.

[0181] During the fourth period T4, the initialization switch SPRE is turned off. During the fourth period T4, the sensing pulse SENSE of an on-level voltage is applied to the sensing transistor SENT.

[0182] During the fourth period T4 , the driving transistor DRT is turned on, the second node N2 of the driving transistor DRT floats, and the voltage of the second node N2 of the driving transistor DRT gradually increases from the reference voltage Vref.

[0183] The voltage of the second node N2 of the driving transistor DRT may continuously change according to time t until a specific time t=T. In other words, the change of the voltage of the second node N2 of the driving transistor DRT with time t may be constant until a specific time t=T. Until the specific time t=T, the change of the voltage of the second node N2 of the driving transistor DRT per unit time may be constant.

[0184] After the specific time t=T, a change in the voltage of the second node N2 of the driving transistor DRT per unit time may be reduced compared to before the specific time t=T.

[0185] In other words, starting from a certain point t=T, a slope of a voltage change (eg, a voltage rise or a voltage drop) of the second node N2 of the driving transistor DRT per unit time may decrease.

[0186] Before a certain time t=T, the driving transistor DRT may be driven in a saturation region.

[0187] After a certain time t=T, the driving transistor DRT may be driven in the triode region.

[0188] The analog-to-digital converter ADC may sample the voltage of the second node N2 of the driving transistor DRT three or more times during the fourth period T4 .

[0189] The sampling switch SAM switches the electrical connection between the reference voltage line RVL and the analog-to-digital converter ADC. The sampling switch SAM may be switched three or more times during the fourth period T4.

[0190] Therefore, during the fourth period T4 , a time point at which the voltage rise of the reference voltage line RVL electrically connected to the second node N2 of the driving transistor DRT stops may exist three or more times.

[0191] During the fourth period T4, the voltage rise of the reference voltage line RVL electrically connected to the second node N2 of the driving transistor DRT may be restored after being stopped three or more times. Figure 7 , the sampling switch SAM can be switched four times during the fourth time period T4.

[0192] The sampling switch SAM is turned on at the first sampling time SAM 1st, and the analog-to-digital converter ADC receives the analog voltage of the second node N2 of the driving transistor DRT.

[0193] The analog-to-digital converter ADC converts the analog voltage input at the first sampling time SAM 1st into a digital value and outputs it to the controller 140 .

[0194] Reference Figure 7, the voltage of the reference voltage line RVL may rise at a constant slope until immediately before the first sampling time SAM 1st.

[0195] According to the operation of the sampling switch SAM, the voltage change slope of the reference voltage line RVL may be reduced and then restored. In an embodiment of the present disclosure, the voltage change may include a voltage rise or a voltage drop (voltage drop). However, for the convenience of description, the voltage change is described in terms of a voltage rise. In this regard, in an embodiment of the present disclosure, the voltage change slope may include a voltage rise slope or a voltage drop slope. However, for the convenience of description, the voltage change slope is described in terms of a voltage rise slope.

[0196] When the sampling switch SAM is turned on, the voltage change slope of the reference voltage line RVL may decrease.

[0197] When the sampling switch SAM is turned off, the voltage change slope of the reference voltage line RVL may be restored to the same value as the voltage change slope of the reference voltage line RVL before the sampling switch SAM is turned on.

[0198] During a period in which the sensing pulse SENSE as an on-level voltage of the gate signal Vgate is input to the sub-pixel SP, a voltage change slope of the second node N2 of the driving transistor DRT may be applied to the reference voltage line RVL.

[0199] In the following description, it is assumed that the voltage change slope of the reference voltage line RVL electrically connected to the sub-pixel SP during the period when the gate signal Vgate of the on-level voltage is input to the sub-pixel SP means the voltage change slope of the second node N2 of the driving transistor DRT of the sub-pixel SP during the period when the sensing pulse SENSE of the on-level voltage is input.

[0200] Specifically, it is assumed that the voltage change slope of the second node N2 of the driving transistor DRT in the subpixel SP during the fourth period T4 means the voltage change slope of the reference voltage line RVL electrically connected to the subpixel SP during the fourth period T4.

[0201] According to the on and off of the sampling switch SAM, the voltage change slope of the reference voltage line RVL decreases and then recovers. This can be distinguished from the following characteristics: as the driving region of the driving transistor DRT changes from the saturation region to the triode region, the voltage change slope of the reference voltage line RVL decreases and does not recover.

[0202] Next, a driving region of the driving transistor DRT is described.

[0203] The voltage waveform of the reference voltage line RVL immediately after the first sampling time SAM 1st may be different from the waveform of the reference voltage line RVL immediately before the first sampling time SAM 1st.

[0204] When the sampling switch SAM is turned on, the reference voltage line RVL electrically connected to one end of the sampling switch SAM can be electrically connected to the other end of the sampling switch SAM. Charge stored in the line capacitor Cline electrically connected to the reference voltage line RVL can flow to the other end of the sampling switch SAM.

[0205] Therefore, if the sampling switch SAM is turned on, the voltage rise of the reference voltage line RVL is temporarily stopped at the time when the sampling switch SAM is turned on.

[0206] The voltage of the reference voltage line RVL may rise again according to the time when the sampling switch SAM is turned off, or may rise again even when the sampling switch SAM is turned off.

[0207] When the voltage rise of the reference voltage line RVL stops and then resumes, a voltage level rise width per unit time of the reference voltage line RVL may be equal to a voltage level rise width before the voltage rise stops.

[0208] In other words, the rising width of the voltage level per unit time of the reference voltage line RVL during the predetermined period before the voltage rise is temporarily stopped may be equal to the rising width of the voltage level per unit time of the reference voltage line RVL during the period after the voltage rise is resumed.

[0209] In other words, the voltage change slope of the reference voltage line RVL after the voltage rise is resumed may be equal to the voltage change slope of the reference voltage line RVL before the voltage rise is temporarily stopped.

[0210] Reference Figure 7 , the voltage of the reference voltage line RVL rises during the fourth period T4, the voltage rise is temporarily stopped at the first sampling time SAM 1st, and then the voltage rise of the reference voltage line RVL is resumed.

[0211] The rising width of the voltage level of the reference voltage line RVL per unit time during the predetermined period before the first sampling time SAM 1st is equal to the rising width of the voltage level of the reference voltage line RVL per unit time during the predetermined period after the voltage rise stopped at the first sampling time SAM 1st is resumed.

[0212] In other words, the voltage rising width per unit time of the reference voltage line RVL before the voltage rising of the reference voltage line RVL stops may be equal to the voltage rising width per unit time of the reference voltage line after the voltage rising of the reference voltage line RVL resumes.

[0213] That a voltage rising width is equal to another voltage rising width may mean both that the voltage rising width is exactly the same as the other voltage rising width and that the voltage rising widths are identical to each other within an error range.

[0214] The sampling switch SAM is turned on at the second sampling time SAM 2nd, and the analog-to-digital converter ADC receives the analog voltage of the second node N2 of the driving transistor DRT.

[0215] The analog-to-digital converter ADC converts the analog voltage input at the second sampling time SAM 2nd into a digital value and outputs it to the controller 140 .

[0216] The controller 140 may calculate a first voltage change slope of the second node N2 of the driving transistor DRT based on the voltage of the second node N2 of the driving transistor DRT sensed at each sampling timing and a time interval Δt1 between the first sampling time SAM 1st and the second sampling time SAM 2nd.

[0217] The sampling switch SAM is turned on at the third sampling time SAM 3rd, and the analog-to-digital converter ADC receives the analog voltage of the second node N2 of the driving transistor DRT.

[0218] The analog-to-digital converter ADC converts the analog voltage input at the third sampling time SAM 3rd into a digital value and outputs it to the controller 140 .

[0219] The controller 140 may calculate a second voltage change slope of the second node N2 of the driving transistor DRT based on the voltage of the second node N2 of the driving transistor DRT sensed at each sampling timing and a time interval Δt2 between the second sampling time SAM 2nd and the third sampling time SAM 3rd.

[0220] The controller 140 may compare the calculated second voltage change slope of the second node N2 of the driving transistor DRT with the first voltage change slope of the second node N2 of the driving transistor DRT.

[0221] When it is determined that the second voltage change slope of the second node N2 of the driving transistor DRT is equal to the first voltage change slope of the second node N2 of the driving transistor DRT or the difference between the two calculated slopes falls within a preset error range, the controller 140 can determine that the driving region of the driving transistor DRT at the third sampling time SAM3rd is a saturation region.

[0222] When it is determined that the second voltage change slope of the second node N2 of the driving transistor DRT is different from the first voltage change slope of the second node N2 of the driving transistor DRT or the difference between the two calculated slopes falls outside the preset error range, the controller 140 can determine that the driving region of the driving transistor DRT at the third sampling time SAM 3rd is the triode region.

[0223] exist Figure 7 , the second voltage change slope of the second node N2 of the driving transistor DRT is equal to the first voltage change slope of the second node N2 of the driving transistor DRT, and based on this, the controller 140 can determine that the driving region of the driving transistor DRT at the third sampling time SAM3rd is the saturation region.

[0224] The time interval Δt2 between the second sampling time SAM 2nd and the third sampling time SAM 3rd may be equal to the time interval Δt1 between the third sampling time SAM 3rd and the second sampling time SAM 2nd. In this case, the controller 140 may determine whether the driving region of the driving transistor DRT is a saturation region or a triode region by comparing only the voltage rise of the second node N2 of the driving transistor DRT.

[0225] The sampling switch SAM is turned on at the fourth sampling time SAM 4th, and the analog-to-digital converter ADC receives the analog voltage of the second node N2 of the driving transistor DRT.

[0226] The analog-to-digital converter ADC converts the analog voltage input at the fourth sampling time SAM 4th into a digital value and outputs it to the controller 140 .

[0227] The controller 140 calculates a third voltage change slope of the second node N2 of the driving transistor DRT based on the voltage of the second node N2 of the driving transistor DRT sensed at each sampling timing and a time interval Δt3 between the third sampling time SAM 3rd and the fourth sampling time SAM 4th.

[0228] The controller 140 may compare a voltage change slope of the second node N2 of the driving transistor DRT with a first voltage change slope of the second node N2 of the driving transistor DRT.

[0229] When it is determined that the third voltage change slope of the second node N2 of the driving transistor DRT is equal to the first voltage change slope of the second node N2 of the driving transistor DRT or the difference between the two slopes falls within a preset error range, the controller 140 can determine that the driving region of the driving transistor DRT at the fourth sampling time SAM 4th is a saturation region.

[0230] When it is determined that the third voltage change slope of the second node N2 of the driving transistor DRT is different from the first voltage change slope of the second node N2 of the driving transistor DRT or the difference between the two slopes falls outside the preset error range, the controller 140 can determine that the driving region of the driving transistor DRT at the fourth sampling time SAM 4th is the triode region.

[0231] exist Figure 7 , the voltage change slope of the second node N2 of the driving transistor DRT decreases from a specific time t=T between the third sampling time SAM 3rd and the fourth sampling time SAM 4th. Therefore, the third voltage change slope of the second node N2 of the driving transistor DRT calculated based on the voltage of the second node N2 of the driving transistor DRT at the fourth sampling time SAM4th is less than the first voltage change slope of the second node N2 of the driving transistor DRT. Based on this, the controller 140 can determine that the driving region of the driving transistor DRT at the fourth sampling time SAM 4th is the triode region.

[0232] When determining that the driving region of the driving transistor DRT at the immediately previous sampling time is a saturation region, the controller 140 may compare the voltage change slope of the second node N2 of the driving transistor DRT at the corresponding sampling time with the voltage change slope of the second node N2 of the driving transistor DRT at the immediately previous sampling time. Based on the comparison result, the controller 140 may determine whether the driving region of the driving transistor DRT at the corresponding sampling time is a saturation region or a triode region.

[0233] For example, as described above, the controller 140 may determine whether the driving region of the driving transistor DRT at the third sampling time SAM 3rd is a saturation region. The controller 140 may also compare the voltage change slope of the second node N2 of the driving transistor DRT at the fourth sampling time SAM 4th with the voltage change slope of the driving transistor DRT at the third sampling time SAM 3rd, which is the immediately preceding sampling time. The controller 140 may compare the third voltage change slope of the second node N2 of the driving transistor DRT with the second voltage change slope of the second node N2 of the driving transistor DRT, and as a result of the comparison, determine that the third voltage change slope is less than the second voltage change slope. Based on such a comparison result, the controller 140 may determine that the driving region of the driving transistor DRT at the fourth sampling time SAM 4th is a triode region.

[0234] Reference Figure 7, the voltage change slope of the second node N2 of the driving transistor DRT starts to change from a specific time t=T between the third sampling time SAM 3rd and the fourth sampling time SAM 4th.

[0235] Therefore, the controller 140 may determine that the driving transistor DRT is driven in the saturation region at the first sampling time SAM 1st, the second sampling time SAM 2nd, and the third sampling time SAM 3rd, and that the driving transistor DRT is driven in the triode region at the fourth sampling time SAM 4th.

[0236] The controller 140 may know the last sampling time when the driving transistor DRT is driven in the saturation region according to the voltage value of the second node N2 of the driving transistor DRT obtained at several sampling times.

[0237] The controller 140 may store the voltage of the second node N2 of the driving transistor DRT sensed at the last sampling time when the driving transistor DRT is driven in the saturation region as a 'driving voltage calculation variable'.

[0238] Reference Figure 7 , the controller 140 may store the voltage of the second node N2 of the driving transistor DRT sensed at the third sampling time SAM 3rd of the driving transistor DRT as a “driving voltage calculation variable”.

[0239] Figure 8 It shows that according to Figure 7 FIG. 1 is a view of an example of a drain voltage Vds and a drain current Id of a driving transistor at a sampling time of FIG.

[0240] Figure 8 The relationship between the drain voltage Vds and the drain current Id of the driving transistor DRT is shown.

[0241] Reference Figure 7 and Figure 8 , the driving voltage EVDDold before the change is applied to the third node N3 of the driving transistor DRT, and the voltage of the second node N2 of the driving transistor DRT gradually rises.

[0242] Reference Figure 8 , the drain voltage Vds of the driving transistor DRT gradually decreases from the first sampling time SAM 1st to the third sampling time SAM 3rd, but the drain current Id of the driving transistor DRT remains constant.

[0243] As the drain voltage Vds of the driving transistor DRT decreases between the third sampling time SAM 3rd and the fourth sampling time SAM4th, there is a period during which the drain current Id of the driving transistor DRT increases.

[0244] Accordingly, the drain voltage Vds of the driving transistor DRT at the third sampling time SAM 3rd is the drain voltage Vds of the driving transistor DRT driven in the saturation region, and the drain voltage Vds of the driving transistor DRT at the fourth sampling time SAM 4th is the drain voltage Vds of the driving transistor DRT driven in the triode region.

[0245] Reference Figure 8 , if the driving transistor DRT is driven in the saturation region, the drain voltage Vds does not affect the drain current Id. Therefore, the drain current Id can be adjusted by simply adjusting the gate voltage, resulting in a stable image display.

[0246] Therefore, what is required is the driving voltage EVDD of a voltage level that minimizes the driving voltage EVDD, and the driving transistor DRT can be driven in a saturation region.

[0247] Based on sampling the voltage of the second node N2 of the driving transistor DRT three or more times, a target driving voltage EVDDgoal for driving the driving transistor DRT in the saturation region is as follows.

[0248] [Formula 1]

[0249] EVDDgoal = EVDDold-V (driving voltage calculation variable) + light-emitting element driving voltage

[0250] In the above Formula 1, "EVDDgoal" represents the minimum driving voltage EVDD for driving the driving transistor DRT in the saturation region and driving the light emitting element ED.

[0251] “EVDDold” represents the driving voltage EVDD previously applied to the third node N3 of the driving transistor DRT when the voltage of the second node N2 of the driving transistor DRT is sampled several times.

[0252] “V (driving voltage calculation variable)” represents an analog voltage value of the second node N2 of the driving transistor DRT at the last sampling time at which the driving transistor DRT is determined to be driven in the saturation region.

[0253] The “light emitting element driving voltage” is a voltage value required to drive the light emitting element ED. The light emitting element driving voltage may be read from a value in a lookup table stored in the controller 140.

[0254] In Formula 1, “EVDDold-V (driving voltage calculation variable)” corresponds to the minimum drain voltage Vds for driving the driving transistor DRT in the saturation region.

[0255] The controller 140 may calculate the target driving voltage EVDDgoal according to Equation 1.

[0256] Reference Figure 7 and Figure 8 , the controller 140 may sample the voltage of the second node N2 of the driving transistor DRT four times during the fourth period T4. On the contrary, the controller 140 may sample the voltage of the second node N2 of the driving transistor DRT more times at shorter time intervals.

[0257] By sampling the voltage of the second node N2 of the driving transistor DRT more times at shorter intervals, the specific time t=T when the driving region of the driving transistor DRT switches from the saturation region to the triode region can be known more accurately.

[0258] Through accurate sensing, a voltage margin of the driving voltage EVDD for driving the driving transistor DRT in the saturation region can be further reduced. Therefore, a voltage level of the driving voltage EVDD applied to the display panel 110 can be further reduced.

[0259] On the contrary, during the fourth period T4, the voltage of the driving transistor DRT may also be sampled only three times at longer time intervals during the same time period.

[0260] When the voltage of the second node N2 of the driving transistor DRT is sampled only three times at a longer time interval, the voltage margin of the driving voltage EVDD for driving the driving transistor DRT in the saturation region may be slightly higher than the voltage margin when the voltage of the second node N2 of the driving transistor DRT is sampled four times or more, but the driving voltage EVDD having a smaller voltage margin than the voltage margin of the driving voltage EVDDold before the change may be applied to the display panel 110.

[0261] The controller 140 may perform a plurality of sampling processes MSP on a plurality of sub-pixels SP, and calculate a target driving voltage EVDDgoal based on the calculated driving voltage calculation variables.

[0262] When calculating the target driving voltage EVDDgoal, the controller 140 may use a minimum value among driving voltage calculation variables of the plurality of sub-pixels SP.

[0263] The sub-pixel SP in which the driving voltage calculation variable is the smallest may be the sub-pixel SP in which the voltage of the second node N2 of the driving transistor DRT changes the least over time. Since mobility sensing is performed, such a sub-pixel SP may be the sub-pixel SP having the smallest mobility.

[0264] The controller 140 may perform the plurality of sampling processes MSP only on the sub-pixel SP having the minimum mobility and calculate the target driving voltage using the driving voltage calculation variables calculated in the plurality of sampling processes MSP on the corresponding sub-pixel SP.

[0265] Therefore, the target driving voltage EVDDgoal is conservatively calculated. The display panel 110 can be stably driven.

[0266] In particular, when the voltage of the second node N2 of the driving transistor DRT is sampled multiple times at shorter time intervals during the fourth period T4, a sensed single characteristic value of the driving transistor DRT may be reflected. In this case, conservatively calculating the target driving voltage EVDDgoal may be more effective.

[0267] Therefore, the controller 140 may calculate the target driving voltage EVDDgoal.

[0268] Fig. 9 is a view showing an example in which the controller 140 adjusts the voltage EVDD_out output from the high potential driving voltage output terminal 320 .

[0269] Reference Fig. 9 , the controller 140 may be mounted on a control printed circuit board CPCB. The switch unit 910, the resistor unit 920, the original drive voltage input terminal 310, the high potential drive voltage output terminal 320, and the drive voltage via line 940 may be located on the control printed circuit board CPCB. The above components may be referred to as a "drive circuit" for driving the display panel. The drive circuit may include all printed circuit boards PCB and various circuits located on the printed circuit board PCB. The printed circuit board PCB may be, for example, a control printed circuit board CPCB.

[0270] Reference Fig. 9 , the original high potential driving voltage EVDD_in is input to the original high potential driving voltage input terminal 310. The original high potential driving voltage EVDD_in may be output from the above-mentioned setting board.

[0271] The high potential driving voltage output terminal 320 is electrically connected to the original high potential input terminal 310 through a driving voltage via line 940. A reference resistor 950 is located on the driving voltage via line 940.

[0272] The resistor unit 920 may be electrically connected to the driving voltage via line 940. The resistor unit 920 may include at least one resistor R.

[0273] The resistor R includes one end electrically connected to the original driving voltage division node 930 and the other end electrically connected to the switching unit 910 .

[0274] The switch unit 910 includes a switch element SW for switching the connection between the resistor unit 920 and the low potential power source. A ground level voltage may be supplied from the low potential power source.

[0275] Reference Fig. 9 , the resistor unit 920 may include two or more resistors R having different resistances. The switch unit 910 may include the same number of switch elements SW as the number of resistors R included in the resistor unit 920. When the resistor unit 920 includes two or more resistors R, the two or more resistors R are connected in parallel to the driving voltage via line 940.

[0276] For example, the resistor unit 920 may include three resistors R1, R2, and R3 having different resistances. Among the three resistors R1, R2, and R3, the first resistor R1 may have the largest resistance, and the third resistor may have the smallest resistance. The resistances of the three resistors R1, R2, and R3 may satisfy R1>R2>R3.

[0277] The switch unit 910 may include three switch elements SW1 , SW2 , and SW3 for respectively switching electrical connections between the three resistors R1 , R2 , and R3 and the low potential power source.

[0278] The controller 140 may control the switching unit 910 .

[0279] The switch unit 910 may be included in a power management circuit mounted on a control printed circuit board CPCB. In this case, the controller 140 may control the switch unit 910 in an I2C communication scheme.

[0280] According to operations of the three switching elements SW1 , SW2 , and SW3 included in the switching unit 910 , the magnitudes of voltages applied to the respective original driving voltage-dividing nodes 930 a , 930 b , and 930 c of the three resistors R1 , R2 , and R3 are different.

[0281] Therefore, the voltage level of the voltage output from the high potential driving voltage output terminal EVDD_out can be lowered.

[0282] The controller 140 controls the switch unit 910 so that the voltage level of the voltage output from the high potential driving voltage output terminal 320 is reduced to a range closest to the target driving voltage EVDDgoal.

[0283] For example, the controller 140 may control the switch unit 910 including three switch elements SW1, SW2, and SW3. Therefore, the controller 140 may finely adjust the voltage output from the high potential driving voltage output terminal 320 into eight individual steps EVDD_1 to EVDD_8.

[0284] The controller 140 divides the voltage output from the high potential driving voltage output terminal 320 into eight stages EVDD_1 to EVDD_8, and can control the switching unit 910 so that a voltage closest to the target driving voltage EVDDgoal within a range equal to or greater than the target driving voltage EVDDgoal is output from the high potential driving voltage output terminal 320.

[0285] Therefore, the high potential driving voltage output terminal 320 can output a high potential driving voltage EVDD_out whose voltage level is lower than the voltage level of the original high potential driving voltage EVDD_in. The high potential driving voltage EVDD_out has a value closest to the target driving voltage EVDDgoal within a range equal to or greater than the target driving voltage EVDDgoal, and can ensure an appropriate margin of the driving voltage EVDD.

[0286] When the plurality of sampling processes MSP are performed as a shutdown sensing process performed before a shutdown sequence such as power off, the controller 140 may control the switching unit 910 when the display device is turned on for the first time since power supply to the display device is cut off.

[0287] In other words, the voltage level of the high potential driving voltage EVDD_out output from the high potential driving voltage output terminal 320 before the shutdown sequence may be different from the voltage level of the high potential driving voltage EVDD_out when the display device is first turned on after the plurality of sampling processes MSP.

[0288] Fig.10 is a view showing an example in which the controller 140 adjusts the voltage EVDD_in input to the original high potential driving voltage input terminal 310 .

[0289] Reference Fig.10 , the controller 140 may control the main power management circuit 220 included in the setting board 210 .

[0290] When the controller 140 is mounted on the control printed circuit board CPCB and the main power management circuit 220 is mounted on the setting board 210, the controller 140 can control the main power management circuit 220 to reduce the voltage level of the original high potential driving voltage EVDD_in output from the setting board 210 through the I2C communication scheme.

[0291] Under the control of the controller 140 , the setup board 210 may output the original high potential driving voltage EVDD_in having a lower voltage level than the driving voltage EVDDold before the change.

[0292] The voltage level of the original high potential driving voltage EVDD_in output from the setup board 210 may be equal to, for example, the voltage level of the target driving voltage EVDDgoal.

[0293] The original high potential driving voltage input terminal 310 receives the original high potential driving voltage EVDD_in having a stepped-down voltage level and outputs it to the high potential driving voltage output terminal 320 via the driving voltage line 940 .

[0294] The high potential driving voltage output terminal 320 outputs the high potential driving voltage EVDD_out to the display panel.

[0295] Therefore, the driving voltage EVDD whose voltage level has been lowered to an appropriate level can be applied.

[0296] Therefore, power consumption may be reduced by lowering the voltage level of the original high potential driving voltage EVDD_in output from the setup board 210 .

[0297] When the multiple sampling process MSP is performed as a shutdown sensing process performed before a shutdown sequence such as power off, the controller 140 may control the main power management circuit 220 when the display device is turned on for the first time since power supply to the display device was cut off.

[0298] In other words, the voltage level of the original high potential driving voltage EVDD_in input to the original high potential driving voltage input terminal 310 before the shutdown sequence may be different from the voltage level of the original high potential driving voltage EVDD_in when the display device is first turned on after the plurality of sampling processes MSP.

[0299] Fig.11 is a view showing a reduction in a high potential driving voltage EVDD_out in a display device according to the present disclosure.

[0300] The display device according to the present disclosure may reduce the voltage level of the high potential driving voltage EVDD_out output from the high potential driving voltage output terminal.

[0301] The display device according to the present disclosure may reduce the voltage level of the driving voltage EVDD by sampling the voltage of the second node N2 of the driving transistor DRT three or more times during a plurality of sampling process MSP periods, and calculate a target driving voltage EVDDgoal capable of driving the driving transistor DRT in a saturation region.

[0302] The display device according to the present disclosure may calculate a target driving voltage EVDDgoal for stably driving the display panel by performing a plurality of sampling processes MSP on a plurality of sub-pixels SP.

[0303] The display device according to the present disclosure can reduce the voltage level of the original high potential driving voltage EVDD_in input to the original high potential driving voltage input terminal, and input the high potential driving voltage EVDD_out whose voltage level has been reduced to be close to the target driving voltage EVDDgoal to the display panel.

[0304] The display device according to the present disclosure may reduce the voltage level of the original high potential driving voltage EVDD_in to the voltage level of the target driving voltage EVDDgoal.

[0305] Therefore, the voltage level of the driving voltage EVDD may be adaptively lowered based on the state of the display panel.

[0306] By adaptively lowering the voltage level of the driving voltage EVDD based on the state of the display panel, the driving voltage EVDD having a voltage level higher than a required voltage level can be prevented from being stably applied to the driving transistor. Therefore, the variation of the characteristic value of the driving transistor DRT can be mitigated.

[0307] The foregoing embodiments are briefly described below.

[0308] An embodiment of the present disclosure may provide a display device 100, which includes: a display panel 110, which includes a plurality of gate lines GL, a plurality of sub-pixels SP, and a plurality of reference voltage lines RVL electrically connected to the plurality of sub-pixels SP, each of the plurality of sub-pixels SP including a driving transistor DRT and a light-emitting element ED; and a gate driving circuit 130, which is configured to supply a gate signal Vgate to the plurality of gate lines GL, wherein there are three or more time periods, during which, when the gate driving circuit 130 applies a gate signal Vgate of an on-level voltage to any one of the plurality of sub-pixels SP, a voltage change slope of the reference voltage line RVL electrically connected to any one of the sub-pixels SP decreases and then recovers.

[0309] For example, the following will describe in detail a case where there are three recovery periods after the voltage change slope (e.g., voltage rising slope or voltage falling slope) of the reference voltage line RVL decreases. For example, during the first period, the voltage of the reference voltage line RVL may change according to the first voltage change slope, and then, may not change or may change at a voltage change slope less than the first voltage change slope. Thereafter, during the second period, the voltage of the reference voltage line RVL may change again at the first voltage change slope, and then, may not change or may change at a voltage change slope less than the first voltage change slope. Thereafter, during the third period, the voltage of the reference voltage line RVL may change again at the first voltage change slope, and then, may not change or may change at a voltage change slope less than the first voltage change slope.

[0310] An embodiment of the present disclosure may provide a display device 100, which further includes a data driving circuit 120, the data driving circuit 120 including: an initialization switch SPRE configured to switch an electrical connection between each of a plurality of reference voltage lines RVL and a reference voltage supply node Nref; an analog-to-digital converter ADC configured to sample the voltages of the plurality of reference voltage lines RVL; and a sampling switch SAM configured to switch an electrical connection between the analog-to-digital converter ADC and each of the plurality of reference voltage lines RVL, wherein when the sampling switch SAM is turned on and then turned off, the sampling switch SAM is connected to the sampling switch SAM. The voltage change slope of the reference voltage line RVL electrically connected to the display panel 110 decreases and then recovers, and wherein, when the data driving circuit 120 samples the voltage of the reference voltage line RVL three or more times, the voltage change slope of the reference voltage line RVL at a specific sampling time after a second sampling time among the three or more samplings is different from the voltage change slope of the reference voltage line RVL immediately before the sampling at the specific sampling time, and the voltage level of the high potential driving voltage EVDD_out applied to the display panel 110 varies depending on the voltage applied to the reference voltage line RVL at the sampling time immediately before the specific sampling time.

[0311] An embodiment of the present disclosure may provide a display device 100, which further includes a controller 140 configured to drive a gate driving circuit 130 and a data driving circuit 120, wherein, starting from a second sampling time SAM 2nd in which a second sampling among three or more samplings is performed, the controller 140 calculates a voltage change slope of a reference voltage line RVL at a corresponding sampling time based on a voltage difference between a voltage sampled at the corresponding sampling time and a voltage sampled at an immediately preceding sampling time, and compares a voltage change slope of the reference voltage line RVL after a third sampling time SAM 3rd among the three or more samplings with a voltage change slope of the reference voltage line RVL at the second sampling time SAM 2nd, and wherein a voltage level of a high potential driving voltage EVDD_out applied to the display panel 110 is reduced according to a result of the comparison.

[0312] An embodiment of the present disclosure may provide a display device 100, wherein, when a voltage change slope of a reference voltage line RVL at a specific sampling time is less than a voltage change slope of a reference voltage line RVL at a second sampling time SAM 2nd, a controller 140 is configured to calculate a target drive voltage EVDDgoal based on a voltage of the reference voltage line RVL sampled at a sampling time immediately before the specific sampling time.

[0313] An embodiment of the present disclosure may provide a display device 100, wherein each of the plurality of sub-pixels SP further includes: a scan transistor SCT configured to be controlled by a scan pulse SCAN of a gate signal Vgate and configured to transmit a data voltage supplied from one of a plurality of data lines DL included in the display panel 110 to a first node N1 of a driving transistor DRT; a sensing transistor SENT configured to be controlled by a sensing pulse SENSE of a gate signal Vgate and configured to switch an electrical connection between a second node N2 of the driving transistor DRT and a reference voltage line RVL; and a storage capacitor Cst including a first end electrically connected to the first node N1 of the driving transistor DRT and a second end electrically connected to a second node N2 of the driving transistor DRT, wherein the second node N2 of the driving transistor DRT is electrically connected to a first electrode of the light emitting element ED, wherein a third node N3 of the driving transistor DRT is electrically connected to a driving voltage line DVL, wherein a driving voltage for operating the driving transistor DRT and driving the light emitting element ED is applied to the driving voltage line DVL.

[0314] An embodiment of the present disclosure may provide a display device 100, which further includes a controller 140 configured to drive a gate driving circuit 130 and a data driving circuit 120, wherein the display device 100 has a plurality of sampling process periods, during which a plurality of sampling processes MSP are performed to sample a voltage of a reference voltage line RVL three or more times, wherein the plurality of sampling process periods include a first period T1, a second period T2, a third period T3, and a fourth period T4, wherein during the first period T1, a sensing pulse SENSE of an on-level voltage is applied to a sensing transistor SENT, the initialization switch SPRE is turned on, and the voltage of the second node N2 of the driving transistor DRT is initialized to the reference voltage Vref, wherein, during the second period T2, the scan pulse SCAN of the on-level voltage is applied to the scan transistor SCT, and the data voltage Vdata is applied to the plurality of data lines DL, wherein, during the third period T3, the scan transistor SCT is turned off, and wherein, during the fourth period T4, the initialization switch SPRE is turned off, the voltage of the second node N2 of the driving transistor DRT increases, and when the voltage of the second node N2 increases, the sampling switch SAM is switched three or more times.

[0315] An embodiment of the present disclosure may provide a display device 100, wherein a controller 140 is configured to calculate a voltage change slope of a second node N2 of a driving transistor DRT at a sampling time based on a sampled voltage value of the second node N2 of the driving transistor DRT, and to store a voltage value sampled immediately before the voltage change slope decreases as a driving voltage calculation variable.

[0316] Embodiments of the present disclosure may provide a display device 100 in which the controller 140 is configured to calculate and store a driving voltage calculation variable for each of a plurality of sub-pixels SP.

[0317] Embodiments of the present disclosure may provide a display device 100 in which the controller 140 is configured to calculate a target driving voltage EVDDgoal using a minimum value among driving voltage calculation variables calculated for corresponding sub-pixels among a plurality of sub-pixels SP.

[0318] An embodiment of the present disclosure may provide a display device 100, which further includes a controller 140 configured to drive a gate driving circuit 130, wherein the controller 140 is configured to control the gate driving circuit 130 to supply a gate signal Vgate of an on-level voltage to a sub-pixel SP having the smallest mobility among a plurality of sub-pixels SP, and wherein a voltage change slope of a reference voltage line RVL electrically connected to the sub-pixel SP having the smallest mobility decreases three or more times and then recovers.

[0319] An embodiment of the present disclosure may provide a display device 100, wherein, for each of three time periods, during each of the three time periods, a voltage change slope of a reference voltage line RVL decreases and then recovers, and a voltage rise width per unit time of the reference voltage line RVL before the voltage change slope of the reference voltage line RVL decreases is equal to a voltage rise width per unit time of the reference voltage line RVL after the voltage change slope of the reference voltage line RVL recovers.

[0320] An embodiment of the present disclosure may provide a display device 100, which further includes a driving circuit configured to drive a display panel 110, wherein the driving circuit includes: an original high potential driving voltage input terminal 310, to which an original high potential driving voltage EVDD_in is input; a high potential driving voltage output terminal 320, which outputs a high potential driving voltage EVDD_out to the display panel 110; a driving voltage via line 940, which electrically connects the original high potential driving voltage input terminal 310 with the high potential driving voltage output terminal 320; a reference resistor 950, which is located on the driving voltage via line 940; a resistor unit 920, which is electrically connected to the driving voltage via line 940; and a switch unit 910, which is configured to switch the connection between the resistor unit 920 and a low potential power supply.

[0321] Embodiments of the present disclosure may provide a display device 100 in which a voltage level of a high potential driving voltage EVDD_out is lower than a voltage level of an original high potential driving voltage EVDD_in.

[0322] An embodiment of the present disclosure may provide a display device 100, wherein a resistor unit 920 includes two or more resistors R having different resistances, wherein each of the two or more resistors R includes a first end electrically connected to a driving voltage via line 940 and a second end electrically connected to a switching unit 910, wherein each of the two or more resistors R is connected in parallel to the driving voltage via line 940, and wherein the switching unit 910 includes the same number of switching elements SW as the number of resistors R included in the resistor unit 920.

[0323] An embodiment of the present disclosure may provide a display device 100, wherein a controller 140 is configured to control a switching unit 910 to reduce a voltage level of a high-potential driving voltage EVDD_out within a range of voltage levels equal to or higher than a voltage level of a target driving voltage EVDDgoal, and to control the switching unit 910 to minimize (or reduce) a voltage level difference between the high-potential driving voltage EVDD_out and the target driving voltage EVDDgoal.

[0324] An embodiment of the present disclosure may provide a display device 100, which further includes a main power management circuit 220, which is configured to adjust the voltage level of an original high-potential driving voltage EVDD_in, wherein a controller 140 is configured to control the main power management circuit 220 so that the voltage level of the original high-potential driving voltage EVDD_in can be equal to the voltage level of a target driving voltage EVDDgoal.

[0325] An embodiment of the present disclosure may provide a display device 100, which includes: a display panel 110, which includes a plurality of sub-pixels SP, each of which includes a driver transistor DRT and a light-emitting element ED; and a driving circuit configured to drive the display panel 110, wherein the driving circuit includes: an original high-potential driving voltage input terminal 310, to which an original high-potential driving voltage EVDD_in is input; and a high-potential driving voltage output terminal 320, which outputs the high-potential driving voltage EVDD_in to the display panel 110. out, and outputs a high potential driving voltage EVDD_out having a voltage level lower than the original high potential driving voltage EVDD_in; a driving voltage via line 940, which electrically connects the original high potential driving voltage input terminal 310 with the high potential driving voltage output terminal 320; a reference resistor 950, which is located on the driving voltage via line 940; a resistor unit 920, which is electrically connected to the driving voltage via line 940; a switch unit 910, which is configured to switch the electrical connection between the resistor unit 920 and a low potential power supply; and a controller 140, which is configured to control the switch unit 910.

[0326] An embodiment of the present disclosure may provide a display device 100, wherein the driving circuit further comprises a printed circuit board PCB, wherein the controller 140 is mounted on the printed circuit board PCB, and wherein an original high potential driving voltage input terminal 310, a high potential driving voltage output terminal 320 driving voltage via line 940, a reference resistor 950, a resistor unit 920 and a switch unit 910 are located on the printed circuit board PCB.

[0327] An embodiment of the present disclosure may provide a display device 100, which further includes a gate driving circuit 130, which is configured to supply a gate signal Vgate to a plurality of gate lines GL included in a display panel 110, wherein there are three or more time periods, during which, when the gate driving circuit 130 applies a gate signal Vgate of an on-level voltage to any one of a plurality of sub-pixels SP, a voltage change slope of a reference voltage line RVL electrically connected to any one of the sub-pixels SP decreases and then recovers.

[0328] An embodiment of the present disclosure may provide a display device 100, wherein, when a voltage variation per unit time of a reference voltage line RVL calculated at a specific sampling time among three or more samplings of the voltage of the reference voltage line is less than a voltage variation per unit time of the reference voltage line RVL calculated at a second sampling time SAM 2nd among three or more samplings, the controller 140 calculates a target drive voltage EVDDgoal based on the voltage of the reference voltage line RVL sampled at a sampling time immediately before the specific sampling time, and controls the switch unit 910 to reduce the voltage level of the voltage output from the high potential drive voltage output terminal 320 within a range of voltage levels equal to or higher than the voltage level of the target drive voltage EVDDgoal.

[0329] An embodiment of the present disclosure may provide a display device, comprising: a display panel; a controller for controlling a data driving circuit and a gate driving circuit of the display panel, wherein the controller is mounted on a control printed circuit board; and a setting board electrically connected to the control printed circuit board, wherein a main power management circuit for managing the total power of the display device is arranged on the setting board, wherein the control printed circuit board comprises an original high potential driving voltage input terminal and a high potential driving voltage output terminal, the original high potential driving voltage output from the setting board is input to the original high potential driving voltage input terminal, and the high potential driving voltage output terminal outputs the high potential driving voltage to the display panel, and the controller controls the main power management circuit to reduce the voltage level of the original high potential driving voltage output from the setting board.

[0330] The above description has been presented to enable any person skilled in the art to make and use the technical concept of the present invention, and has been provided in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The above description and accompanying drawings provide examples of the technical concept of the present invention for illustrative purposes only. That is, the embodiments disclosed herein are intended to illustrate the scope of the technical concept of the present invention. Therefore, the scope of the present invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the present invention should be understood based on the following claims, and all technical concepts within the scope of their equivalents should be understood to be included within the scope of the present invention.

Claims

1. A display device, include: A display panel comprising a plurality of gate lines, a plurality of sub-pixels, and a plurality of reference voltage lines electrically connected to the plurality of sub-pixels, each of the plurality of sub-pixels comprising a driving transistor and a light emitting element; as well as a gate driving circuit configured to supply gate signals to the plurality of gate lines, There are three or more time periods during which, when the gate driving circuit applies a gate signal of an on-level voltage to any one of the multiple sub-pixels, the voltage change slope of the reference voltage line electrically connected to any one of the sub-pixels decreases and then recovers.

2. The display device according to claim 1, further comprising a data driving circuit, wherein the data driving circuit include: an initialization switch configured to switch an electrical connection between each of the plurality of reference voltage lines and a reference voltage supply node; an analog-to-digital converter configured to sample voltages of the plurality of reference voltage lines; as well as a sampling switch configured to switch an electrical connection between the analog-to-digital converter and each of the plurality of reference voltage lines, When the sampling switch is turned on and then turned off, the voltage change slope of the reference voltage line electrically connected to the sampling switch decreases and then recovers, and Wherein, when the data driving circuit samples the voltage of the reference voltage line three or more times, a voltage change slope of the reference voltage line at a specific sampling time after a second sampling time in the three or more samplings is different from a voltage change slope of the reference voltage line immediately before sampling at the specific sampling time, a voltage level of the high potential driving voltage applied to the display panel changes depending on the voltage applied to the reference voltage line at the sampling time immediately before the specific sampling time.

3. The display device according to claim 2, further comprising a controller configured to drive the gate driving circuit and the data driving circuit, in, The controller calculates a voltage change slope of the reference voltage line at the corresponding sampling time from a voltage difference between a voltage sampled at the corresponding sampling time and a voltage sampled at an immediately preceding sampling time, starting from the second sampling time at which the second sampling of the three or more samplings is performed, and compares a voltage change slope of the reference voltage line after a third sampling time of the three or more samplings with the voltage change slope of the reference voltage line at the second sampling time, and Wherein, the voltage level of the high potential driving voltage applied to the display panel is reduced according to the comparison result.

4. The display device according to claim 3, in, When the voltage change slope of the reference voltage line at the specific sampling time is less than the voltage change slope of the reference voltage line at the second sampling time, the controller is configured to calculate a target driving voltage based on the voltage of the reference voltage line sampled at a sampling time immediately before the specific sampling time.

5. The display device according to claim 2, in, Each of the plurality of sub-pixels further comprises: a scan transistor configured to be controlled by a scan pulse of the gate signal and configured to transmit a data voltage supplied from one of a plurality of data lines included in the display device to a first node of the driving transistor; a sensing transistor configured to be controlled by a sensing pulse of the gate signal and configured to switch an electrical connection between a second node of the driving transistor and the reference voltage line; and a storage capacitor including a first terminal electrically connected to the first node of the drive transistor and a second terminal electrically connected to the second node of the drive transistor, The second node of the driving transistor is electrically connected to the first electrode of the light emitting element. The third node of the driving transistor is electrically connected to the driving voltage line. Wherein, a driving voltage for operating the driving transistor and driving the light emitting element is applied to the driving voltage line.

6. The display device according to claim 5, further comprising a controller configured to drive the gate driving circuit and the data driving circuit, in, The display device has a plurality of sampling process periods during which a plurality of sampling processes are performed to sample the voltage of the reference voltage line three or more times, The plurality of sampling process time periods include a first time period, a second time period, a third time period and a fourth time period. wherein, during the first period, the sensing pulse of the on-level voltage is applied to the sensing transistor, the initialization switch is turned on, and the voltage of the second node of the driving transistor is initialized to a reference voltage, wherein during the second period, the scan pulse of the on-level voltage is applied to the scan transistor, and a data voltage is applied to the plurality of data lines, wherein, during the third period, the scanning transistor is turned off, and During the fourth period, the initialization switch is turned off, the voltage of the second node of the driving transistor increases, and when the voltage of the second node increases, the sampling switch is switched three or more times.

7. The display device according to claim 6, in, The controller is configured to calculate a voltage change slope of the second node of the driving transistor at a sampling time based on a sampled voltage value of the second node of the driving transistor, and store a voltage value sampled immediately before the voltage change slope decreases as a driving voltage calculation variable.

8. The display device according to claim 7, in, The controller is configured to calculate and store the driving voltage calculation variable for each of the plurality of sub-pixels.

9. The display device according to claim 8, in, The controller is configured to calculate a target driving voltage using a minimum value among the driving voltage calculation variables calculated for corresponding sub-pixels among the plurality of sub-pixels.

10. The display device according to claim 1, further comprising a controller configured to drive the gate driving circuit, in, The controller is configured to control the gate driving circuit to supply a gate signal of the on-level voltage to a sub-pixel having the smallest mobility among the plurality of sub-pixels, and The voltage change slope of the reference voltage line electrically connected to the sub-pixel having the minimum mobility decreases three or more times and then recovers.

11. The display device according to claim 1, in, For each of the three time periods during which the voltage change slope of the reference voltage line decreases and then recovers, the voltage rise width per unit time of the reference voltage line before the voltage change slope of the reference voltage line decreases is equal to the voltage rise width per unit time of the reference voltage line after the voltage change slope of the reference voltage line recovers.

12. The display device according to claim 4, further comprising a driving circuit configured to drive the display panel. in, The driving circuit comprises: an original high potential driving voltage input terminal, to which the original high potential driving voltage is input; A high potential driving voltage output terminal, which outputs a high potential driving voltage to the display panel; a driving voltage via line electrically connecting the original high potential driving voltage input terminal with the high potential driving voltage output terminal; A reference resistor located on the driving voltage via line; a resistor unit electrically connected to the driving voltage via a line; and A switch unit is configured to switch a connection between the resistor unit and a low potential power source.

13. The display device according to claim 12, in, A voltage level of the high potential driving voltage is lower than a voltage level of the original high potential driving voltage.

14. The display device according to claim 13, in, The resistor unit includes two or more resistors having different resistances, wherein each of the two or more resistors includes a first end electrically connected to the driving voltage via line and a second end electrically connected to the switching unit, wherein each of the two or more resistors is connected in parallel to the drive voltage via line, and The switch unit includes the same number of switch elements as the number of the resistors included in the resistor unit.

15. The display device according to claim 12, in, The controller is configured to control the switching unit to reduce the voltage level of the high potential driving voltage within a range of voltage levels equal to or higher than a voltage level of the target driving voltage, and to control the switching unit to minimize a voltage level difference between the high potential driving voltage and the target driving voltage.

16. The display device according to claim 4, further comprising a main power management circuit configured to adjust a voltage level of the original high potential driving voltage, in, The controller is configured to control the main power management circuit so that a voltage level of the original high potential driving voltage can be equal to a voltage level of the target driving voltage.

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