Display device and display driving method

Abstract

Embodiments of the present disclosure relate to a display apparatus and a display driving method, and more particularly one of the embodiments can provide a display apparatus including a display panel on which a plurality of sub-pixels are disposed; a timing controller configured to transmit an image control signal to a host system to receive image data from the host system; a data driving circuit configured to convert the image data transmitted from the timing controller into a data voltage and configured to supply the data voltage to the display panel; and a semi-break switch circuit configured to control the image control signal such that the image data is cut off from the host system during a semi-break period of a predetermined time from a time at which a break monitoring signal is transmitted from the host system in response to a power break signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0103609, filed on August 6, 2021, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device and a display driving method capable of rapidly performing a power-on process for a display panel when a power-on signal is supplied while a disconnection process is in progress. Background Technology

[0004] With the development of the information society, there is an ever-increasing demand for various types of image display devices. In this regard, a range of display devices such as liquid crystal displays and organic light-emitting diode displays have recently been widely used.

[0005] Among these display devices, organic light-emitting display devices have excellent characteristics such as fast response speed, high contrast, high luminous efficiency, high brightness, and wide viewing angle because they use self-emissive organic light-emitting diodes as light-emitting elements.

[0006] Such an organic light-emitting display device may include organic light-emitting diodes disposed in a plurality of sub-pixels arranged in a display panel, and the light emission of the organic light-emitting diodes can be controlled by controlling the current flowing through the light-emitting diodes, thereby displaying an image while controlling the brightness of the sub-pixels.

[0007] Since such a display device can send power-on or power-off signals via a remote control and a power button, the power-on or power-off processing of the display panel according to the user's intention may occur frequently.

[0008] In this context, as the size and number of functions of the display device increase, the time for the power-on processing in response to the power-on signal and the time for the power-off processing in response to the power-off signal may increase. In particular, when a power-on signal is supplied while the power-off processing is in progress, the display panel may take a long time to drive because the power-on processing will be executed again after the power-off processing is completed.

[0009] In particular, recently, processing has been used to detect and compensate for deviations in the characteristic values ​​(threshold voltage or mobility) of driving transistors in sub-pixels of a display panel. Since the compensation processing is performed primarily in the disconnection process after the generation of a power-off signal or in the power-on process after the generation of a power-on signal, it may take more time to re-drive the display panel while the disconnection process is in progress. SUMMARY

[0010] Accordingly, the inventors of the present disclosure invented a display apparatus and a display driving method capable of reducing a time for performing a turn-on process.

[0011] Embodiments of the present disclosure can provide a display apparatus and a display driving method capable of quickly performing a turn-on process of a display panel when a supply power turn-on signal is supplied while a turn-off process is being performed.

[0012] In addition, embodiments of the present disclosure can provide a display apparatus and a display driving method capable of reducing a display driving time by performing a half turn-off process for a certain period of time when a supply power turn-off signal is supplied and performing a quick start process when a supply power turn-on signal is supplied for a period of the half turn-off process.

[0013] One of the embodiments of the present disclosure can provide a display apparatus including a display panel on which a plurality of sub-pixels are disposed; a timing controller configured to transmit an image control signal to a host system to receive image data from the host system; a data driving circuit configured to convert the image data transmitted from the timing controller into a data voltage and configured to supply the data voltage to the display panel; and a half turn-off switching circuit configured to control the image control signal such that the image data is cut off from the host system during a half turn-off period of a first predetermined time from a time at which a turn-off monitoring signal is transmitted from the host system in response to a power turn-off signal.

[0014] One of the embodiments of the present disclosure can provide a display driving method for controlling a display apparatus including a display panel on which a plurality of sub-pixels are disposed; a timing controller configured to control an operation of a host system to supply image data through an image control signal; and a data driving circuit configured to convert the image data transmitted from the timing controller into a data voltage and to supply the data voltage to the display panel; the display driving method including determining whether a power turn-off signal is supplied, performing a half turn-off process for blocking the image data while maintaining a driving power supplied to the data driving circuit when the power turn-off signal is supplied, performing a quick start process when a power turn-on signal is supplied for a half turn-off period, and cutting off the driving power when the power turn-on signal is not supplied for the half turn-off period.

[0015] One of the embodiments of the present disclosure can provide a display apparatus including a display panel on which a plurality of sub-pixels are disposed; a timing controller configured to transmit an image control signal to a host system to receive image data from the host system; a data driving circuit configured to convert the image data transmitted from the timing controller into a data voltage and configured to supply the data voltage to the display panel; and a semi-off switching circuit configured to control the timing controller to perform a semi-off process for cutting off the image data while maintaining driving power supplied to the data driving circuit during a semi-off period when a power-on signal is supplied from the host system, and to perform a fast boot process for supplying the image data when a power-on signal is supplied within the semi-off period.

[0016] According to one of the embodiments of the present disclosure, a display apparatus or a display driving method capable of reducing a time for performing a turn-on process can be provided.

[0017] According to one of the embodiments of the present disclosure, a display apparatus or a display driving method capable of quickly performing a turn-on process of a display panel when a power-on signal is supplied while an off process is being performed can be provided.

[0018] According to one of the embodiments of the present disclosure, a display apparatus or a display driving method capable of reducing a display driving time by performing a semi-off process for a certain period of time when a power-off signal is supplied and performing a fast boot process when a power-on signal is supplied within the semi-off process period can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0019] In the drawings:

[0020] Figure 1 A schematic diagram of a display apparatus according to an embodiment of the present disclosure is shown;

[0021] Figure 2 A system diagram of a display apparatus according to an embodiment of the present disclosure is shown;

[0022] Figure 3 A circuit diagram of a sub-pixel in a display apparatus according to an embodiment of the present disclosure is shown;

[0023] Figure 4 A diagram of a turn-on process and an off process in a display apparatus is shown;

[0024] Figure 5 A case where a fast boot process is performed when a power-on signal is supplied during a semi-off process in a display apparatus according to an embodiment of the present disclosure is shown;

[0025] Figure 6 A flowchart illustrating the sending of signals from a host system in relation to an embodiment of the display driving method according to this disclosure is shown;

[0026] Figure 7 A block diagram showing the configuration of a display device according to an embodiment of the present disclosure is illustrated;

[0027] Figure 8 The Vbyone interface of a display device according to an embodiment of the present disclosure is shown;

[0028] Figure 9 The signal flow for processing image data transmitted via the Vbyone interface is shown;

[0029] Figure 10 A signal flow diagram is shown in a display driving method according to an embodiment of the present disclosure when a power-on signal is supplied during a half-off period;

[0030] Figure 11 The signal flow in a display driving method according to an embodiment of the present disclosure is shown when no power-on signal is supplied during a half-off period;

[0031] Figure 12 A flowchart of a display driving method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0032] In the following description, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0033] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0034] When it is mentioned that a first element is "connected or coupled to", "contacts or overlaps" a second element, etc., it should be understood that not only can the first element be "directly connected or coupled to" or "directly contact or overlap" the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or coupled" to each other, "contact or overlap" each other, etc. via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled" to each other, "contact or overlap" each other, etc.

[0035] When time-related terms such as "after", "subsequently", "next", "before", etc. are used to describe the processing or operation of an element or configuration, or the flow or step in an operation, processing, manufacturing method, these terms can be used to describe non-continuous or non-sequential processing or operation, unless the term "directly" or "immediately" is used together.

[0036] In addition, when any dimension, relative size, etc. is mentioned, it should be considered that the numerical value or corresponding information (e.g. horizontal, range, etc.) of the element or feature includes a tolerance or error range that can be caused by various factors (e.g. processing elements, internal or external influences, noise, etc.), even if the relevant description is not specified. In addition, the term "may" fully includes all the meanings of the term "can".

[0037] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 A schematic diagram of a display device according to an embodiment of the present disclosure is shown.

[0039] Referring to Figure 1 The display device 100 according to an embodiment of the present disclosure can include a display panel 110 connected to a plurality of gate lines GL and a plurality of data lines DL, in which a plurality of sub-pixels SP are arranged in rows and columns; a gate driving circuit 120 for supplying a scan signal to the plurality of gate lines GL and a data driving circuit 130 for supplying a data voltage to the plurality of data lines DL; a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0040] The display panel 110 displays an image based on a scan signal supplied from the gate driving circuit 120 through the plurality of gate lines GL and a data voltage supplied from the data driving circuit 130 through the plurality of data lines DL.

[0041] In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates, and a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane Switching) mode, an FFS (Fringe Field Switching) mode can operate in any known mode. In the case of an organic light emitting display device, the display panel 110 can be implemented in a top emission method, a bottom emission method, or a dual emission method.

[0042] In the display panel 110, a plurality of pixels can be provided in a matrix form. Each pixel can be composed of sub-pixels SP of different colors, such as a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel, for example. Each sub-pixel SP can be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0043] The sub-pixel SP can include a thin film transistor (TFT) disposed in an area where the data line DL and the gate line GL intersect, a light emitting element such as a light emitting diode that emits light according to a data voltage, and a storage capacitor for maintaining the data voltage by being electrically connected to the light emitting element.

[0044] For example, when the display device 100 having a 2,160 x 3,840 resolution includes four sub-pixels SP of white W, red R, green G, and blue B, 3,840 x 4 = 15,360 data lines DL can be provided by 2,160 gate lines GL and 3840 data lines DL connected to the 4 sub-pixels WRGB, respectively. Each of the plurality of sub-pixels SP can be provided in an area where the plurality of gate lines GL and the plurality of data lines DL overlap.

[0045] The gate driving circuit 120 is controlled by the timing controller 140 and controls a driving timing of the plurality of sub-pixels SP by sequentially supplying a scan signal to the plurality of gate lines GL provided in the display panel 110.

[0046] In the display device 100 having a 2,160 x 3,840 resolution, an operation of sequentially supplying a scan signal to 2,160 gate lines GL from a first gate line GL1 to a 2,160th gate line GL2160 can be referred to as a 2,160-phase driving operation. Otherwise, an operation of sequentially supplying a scan signal to every four gate lines GL, such as a case where a scan signal is sequentially supplied from a first gate line GL1 to a fourth gate line GL4 and then sequentially supplied from a fifth gate line GL5 to an eighth gate line GL8, can be referred to as a 4-phase driving operation. As described above, an operation in which a scan signal is sequentially supplied to every N number of gate lines can be referred to as an N-phase driving operation.

[0047] The gate driving circuit 120 can include one or more gate driving integrated circuits (GDICs), which can be disposed on one or both sides of the display panel 110 according to a driving method. Alternatively, the gate driving circuit 120 can be implemented in a gate-in-panel (GIP) structure embedded in a bezel area of the display panel 110.

[0048] The data driving circuit 130 receives digital image data DATA from the timing controller 140, and converts the received digital image data DATA into an analog data voltage. Then, the data driving circuit 130 supplies the analog data voltage to each of the data lines DL as a scan signal is supplied through the gate line GL, so that each of the sub-pixels SP connected to the data line DL emits light having a corresponding luminance in response to the analog data voltage.

[0049] Likewise, the data driving circuit 130 can include one or more source driving integrated circuits (SDICs). Each of the source driving integrated circuits SDICs can be connected to a bonding pad of the display panel 110 through tape automated bonding (TAB) or chip on glass (COG), or can be directly mounted on the display panel 110.

[0050] In some cases, each of the source driving integrated circuits (SDICs) can be integrated with the display panel 110. In addition, each of the source driving integrated circuits (SDICs) can be implemented with a chip on film (COF) structure. In this case, the source driving integrated circuits SDICs can be mounted on a circuit film to be electrically connected to the data lines DL in the display panel 110 via the circuit film.

[0051] The timing controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the timing controller 140 controls the gate driving circuit 120 to supply a scan signal in response to a time implemented by each frame, and on the other hand, transmits image data DATA from an external source to the data driving circuit 130.

[0052] Here, the timing controller 140 receives various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a master clock MCLK from the external host system 200.

[0053] The host system 200 can be any one of a TV (television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

[0054] Accordingly, the timing controller 140 generates control signals using various timing signals received from external sources, and supplies the control signals to the gate driving circuit 120 and the data driving circuit 130.

[0055] For example, the timing controller 140 generates various gate control signals including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE, in order to control the gate driving circuit 120. Here, the gate start pulse GSP is used to control the start timing of one or more gate driving integrated circuits GDIC of the gate driving circuit 120. In addition, the gate clock GCLK is a clock signal commonly supplied to the one or more gate driving integrated circuits GDIC for controlling the shift timing of a scan signal. The gate output enable signal GOE specifies timing information of the one or more gate driving integrated circuits GDIC.

[0056] In addition, the timing controller 140 generates various data control signals including a source start pulse SSP, a source sampling clock SSC, and a source output enable signal SOE, in order to control the data driving circuit 130. Here, the source start pulse SSP is used to control the start timing of data sampling of one or more source driving integrated circuits SDIC of the data driving circuit 130. The source sampling clock SSC is a clock signal for controlling the timing of data sampling in each of the source driving integrated circuits SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

[0057] The display device 100 can further include a power management circuit 150 for supplying or controlling various voltages or currents to or for the display panel 110, the gate driving circuit 120, and the data driving circuit 130.

[0058] The power management circuit 150 generates power required for driving the display panel 100, the gate driving circuit 120, and the data driving circuit 130, by controlling a DC input voltage Vin supplied from the host system 200.

[0059] The sub-pixels SP are located at points where the gate lines GL and the data lines DL intersect, and a light emitting element can be disposed in each of the sub-pixels SP. For example, an organic light emitting display device can include a light emitting element such as a light emitting diode in each of the sub-pixels SP, and can display an image by controlling a current flowing through the light emitting element in response to a data voltage.

[0060] The display device 100 can be various types of devices such as a liquid crystal display, an organic light emitting display, and a plasma display panel.

[0061] Figure 2 A system diagram of a display apparatus according to an embodiment of the present disclosure is illustrated.

[0062] As an example, Figure 2 Each of the source driving integrated circuits in the source driving integrated circuits SDIC in the data driving circuit 130 and each of the gate driving integrated circuits in the gate driving integrated circuits GDIC in the gate driving circuit 120 in the display apparatus 100 according to an embodiment of the present disclosure is implemented in a COF type among various structures such as a TAB, a COG, and a COF.

[0063] One or more gate driving integrated circuits GDIC included in the gate driving circuit 120 can be mounted on a gate film GF, respectively, and one side of the gate film GF can be electrically connected to the display panel 110. In addition, wires can be provided on the gate film GF to electrically connect the gate driving integrated circuits GDIC and the display panel 110.

[0064] Likewise, the data driving circuit 130 can include one or more source driving integrated circuits SDIC that can be mounted on a source film SF, respectively. A portion of the source film SF can be electrically connected to the display panel 110. In addition, wires can be provided on the source film SF to electrically connect the source driving integrated circuits SDIC and the display panel 110.

[0065] The display apparatus 100 can include at least one source printed circuit board SPCB for connecting the plurality of source driving integrated circuits SDIC to other apparatuses through a circuit, and a control printed circuit board CPCB for mounting various control components and electronic elements.

[0066] Another portion of the source film SF on which the source driving integrated circuits SDIC are mounted can be connected to the at least one source printed circuit board SPCB. That is, a portion of the source film SF on which the source driving integrated circuits SDIC are mounted can be electrically connected to the display panel 110, and another portion of the source film SF can be electrically connected to the source printed circuit board SPCB.

[0067] The timing controller 140 and the power management circuit 150 can be mounted on the control printed circuit board CPCB. The timing controller 140 can control operations of the data driving circuit 130 and the gate driving circuit 120. The power management integrated circuit 150 can supply driving voltages and driving currents, or control voltages and currents for the data driving circuit 130 and the gate driving circuit 120.

[0068] The at least one source printed circuit board SP CB and the control printed circuit board CPCB can have an electrical connection through at least one connection member. The connection member CBL can be, for example, a flexible printed circuit FPC, a flexible flat cable FFC, or the like. In this case, the connection member for connecting the at least one source printed circuit board SP CB and the control printed circuit board CPCB can be variously changed according to the size and type of the display apparatus 100. The at least one source printed circuit board SP CB and the control printed circuit board CPCB can be integrated into a single printed circuit board.

[0069] In the display apparatus 100 having the above-described configuration, the power management circuit 150 supplies a driving voltage required for a display driving operation or a sensing operation of a characteristic value to the source printed circuit board SP CB through the flexible printed circuit FPC or the flexible flat cable FFC. The driving voltage supplied to the source printed circuit board SP CB is transmitted via the source driving integrated circuit SDIC to cause a specific sub-pixel SP in the display panel 110 to emit light or to be sensed.

[0070] Each of the sub-pixels SP arranged in the display panel 110 of the display apparatus 100 can include an organic light emitting diode as a light emitting element and circuit elements such as a driving transistor for driving the organic light emitting diode.

[0071] The type and number of the circuit elements constituting each of the sub-pixels SP can be variously determined according to a function, a design, or the like.

[0072] Figure 3 A circuit diagram of a sub-pixel in a display apparatus according to an embodiment of the disclosure is illustrated.

[0073] Referring to Figure 3 Each of the sub-pixels SP arranged in the display apparatus 100 according to an embodiment of the disclosure can include one or more transistors, a capacitor, and an organic light emitting diode OLED as a light emitting element.

[0074] For example, the sub-pixel SP can include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and an organic light emitting diode OLED.

[0075] The driving transistor DRT can have a first node N1, a second node N2, and a third node N3. When the switching transistor SWT is turned on, the first node N1 of the driving transistor DRT can be a gate node to which a data voltage Vdata is supplied through a data line DL. The second node N2 of the driving transistor DRT can be electrically connected to an anode electrode of the light emitting element OLED, and can be a drain node or a source node. The third node N3 of the driving transistor DRT can be electrically connected to a driving voltage line DVL for supplying a driving voltage EVDD, and can be a source node or a drain node.

[0076] Here, the driving voltage EVDD for displaying an image can be supplied to the driving voltage line DVL in a display driving period. For example, the driving voltage EVDD for displaying an image can be about 27 V.

[0077] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and operates in response to a scan signal SCAN supplied to the switching transistor SWT through a gate line GL connected to a gate node. In addition, when the switching transistor SWT is turned on, it controls the operation of the driving transistor DRT by transmitting the data voltage Vdata to the gate node of the driving transistor DRT through the data line DL.

[0078] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and a reference voltage line RVL, and operates in response to a sensing signal SENSE supplied through the gate line GL connected to the gate node. When the sensing transistor SENT is turned on, a reference voltage Vref supplied from the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0079] That is, the voltages of the first node N1 and the second node N2 of the driving transistor DRT can be controlled by controlling the switching transistor SWT and the sensing transistor SENT. Accordingly, a current for causing the organic light emitting diode OLED to emit light can be supplied.

[0080] Each of the gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a single gate line GL or to different gate lines GL. Here, an exemplary structure in which the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL is shown. In this case, the switching transistor SWT and the sensing transistor SENT are independently controlled by the scan signal SCAN and the sensing signal SENSE transmitted from the different gate lines GL.

[0081] On the other hand, when the switching transistor SWT and the sensing transistor SENT are connected to a single gate line GL, the switching transistor SWT and the sensing transistor SENT are simultaneously controlled by a scan signal SCAN or a sensing signal SENSE transmitted from the single gate line GL, and thus the aperture ratio of the sub-pixel SP can be improved.

[0082] In addition, the transistor provided in the sub-pixel SP can not only be an n-type transistor, but also a p-type transistor. Here, an exemplary structure of an n-type transistor is shown.

[0083] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and functions to hold a data voltage Vdata during one frame.

[0084] According to the type of the driving transistor DRT, such a storage capacitor Cst can be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode electrode of the organic light emitting diode OLED can be electrically connected to the second node N2 of the driving transistor DRT, and a base voltage EVSS can be supplied to the cathode electrode of the organic light emitting diode OLED.

[0085] Here, the base voltage EVSS can be a ground voltage, or can be a voltage higher or lower than the ground voltage. In addition, the base voltage EVSS can vary depending on the driving conditions. For example, the base voltage EVSS during a display driving period can be different from the base voltage EVSS during a sensing period.

[0086] The structure of the above-described sub-pixel SP is, for example, a 3T (transistor) 1C (capacitor) structure (described only as an example), and further includes one or more transistors, or in some cases, one or more capacitors. Alternatively, each of a plurality of sub-pixels SP can have the same structure, or some of the plurality of sub-pixels SP can have different structures.

[0087] Figure 4 A diagram showing the turn-on process and the turn-off process in the display apparatus is shown.

[0088] Referring to Figure 4 The display apparatus 100 is caused to normally display a display driving operation in which an image is displayed on the display panel 110 by a power-on signal Power On, and the operation of the display panel 110 is terminated by a power-off signal Power Off.

[0089] More specifically, when the power-off signal Power Off is generated in a process in which a display driving operation for displaying an image through the display panel 110 is normally displayed, the display device 100 performs an off process. During the off process, the input power Vin supplied from the host system 200 can be disconnected, and various types of driving power supplied from the power management circuit 150 to the display panel 110 can be individually disconnected.

[0090] Meanwhile, during a period of the off process, an image displayed before the power-off signal Power Off is supplied can appear as a residual image.

[0091] In addition, the power-on signal Power On can occur in a case where individual power-off operations for various types of voltages are not completed within the off process caused by the power-off signal Power Off. As such, when the power-on signal Power On occurs within the off process, the display device 100 waits until all of the off processes are completed, and performs an on process again when all of the off processes are completed.

[0092] Accordingly, the display device 100 can perform the on process for the display panel 110 only after a certain time elapses from the power-off signal Power Off. This time delay can be referred to as an on time delay.

[0093] Recently, a process for detecting and compensating for a deviation in a characteristic value (threshold voltage or mobility) of a driving transistor DRT in a sub-pixel SP of the display panel 110 has been used. Since the compensation process is performed in the off process performed mainly after the power-off signal Power Off is generated or in the on process performed after the power-on signal Power On is generated, it can take more time to drive the display panel 110 again after the power-off signal Power Off is supplied.

[0094] Accordingly, after the power-on signal Power On is generated, there is a problem in that more time is taken in the on process for resetting circuit elements including the timing controller 140, the gate driving circuit 120, and the data driving circuit 130 and for reading data about a display driving operation.

[0095] The display device 100 of the disclosure can reduce a driving time of the display panel 110 by performing a half-off process in a predetermined time when the power-off signal Power Off is supplied to the display panel 110 and by performing a fast boot process when the power-on signal Power On is supplied within a period of the half-off process.

[0096] Figure 5A case where a quick start process is executed when a power-on signal is supplied during a semi-off process in a display device according to an embodiment of the disclosure is shown.

[0097] Referring to Figure 5 According to an embodiment of the disclosure, the display device 100 can execute a semi-off process when a power-off signal Power Off is supplied during a normal display period of a display driving operation in which an image is displayed on the display panel 110.

[0098] Unlike the off process, since the input power Vin supplied from the host system 200 remains unchanged during the semi-off process, various driving powers supplied to the display panel 110 generated at the power management circuit 150 are also normally generated. However, some of the driving powers supplied to the display panel 110 can be turned off.

[0099] On the other hand, since the image data DATA is not transmitted from the host system 200, the data voltage Vdata is not supplied to the display panel 110 during a semi-off period in which the semi-off process is executed.

[0100] The semi-off period in which the semi-off process is executed is a time interval during which the user can turn off the display device 100 and then turn on the display device 100 again. It can be statistically determined by analyzing the usage pattern of the user with respect to the display device 100. For example, the semi-off period can be determined as a time interval of tens of seconds to several minutes from a time point at which the power-off signal Power Off is supplied.

[0101] During the semi-off period in which the semi-off process is executed, the image data DATA from the host system 200 is not transmitted, but the various driving powers supplied to the display panel 110 can be normally maintained.

[0102] Therefore, when the power-on signal Power On is supplied by the user during the semi-off period in which the semi-off process is executed, the quick start process of transmitting the image data DATA from the host system 200 can be executed with the various driving powers supplied to the display panel 110 maintained in the on state.

[0103] Therefore, in the quick start process, the operation of transmitting the image data DATA from the host system 200 is changed with the various driving powers supplied to the display panel 110 maintained in the on state. Therefore, the time taken for the operation of both the driving power and the image data DATA is shorter than the time taken for the on process.

[0104] Therefore, the time of the normal display of the display driving operation in which the image is displayed on the display panel 110 can be reduced.

[0105] On the other hand, if the semi-disconnection period is terminated in a state in which the user does not supply the power on signal Power On during the semi-disconnection period in which the semi-disconnection process is being performed, the display device 100 can be placed in the disconnected state by blocking various driving powers supplied to the display panel 110 and by cutting off the input power Vin supplied from the host system 200.

[0106] On the other hand, the display device 100 of the present disclosure can perform a disconnection sensing process for sensing a characteristic value (threshold voltage or mobility) of the driving transistor DRT when the semi-disconnection period is terminated.

[0107] Figure 6 A flowchart of a display driving method according to an embodiment of the present disclosure is shown.

[0108] Referring to Figure 6 The display driving method according to an embodiment of the present disclosure performs a semi-disconnection process when the user supplies the power off signal Power Off. The host system 200 maintains the input power Vin supplied to the display device 100 in a high state during the semi-disconnection period, and supplies the disconnection monitoring signal Off_MNT informing that the power off signal Power Off is supplied to the display device 100.

[0109] That is, since the input power Vin supplied from the host system 200 to the display device 100 is maintained in a high state during the semi-disconnection period, the display device 100 can supply various driving powers to the gate driving circuit 120 and the data driving circuit 130 as they are during a predetermined time interval after the power off signal Power Off is supplied.

[0110] On the other hand, since the disconnection monitoring signal Off_MNT is transmitted from the host system 200 when the power off signal Power Off is supplied, the display device 100 can cut off the data voltage Vdata supplied to the display panel 110 by recognizing that the power off signal Power Off is supplied.

[0111] Accordingly, the display device 100 can maintain the driving power supplied to the gate driving circuit 120 and the data driving circuit 130 in the on state, but cut off the data voltage Vdata transmitted to the display panel 110 according to the disconnection monitoring signal Off_MNT transmitted from the host system 200.

[0112] Accordingly, when the user supplies the power-on signal Power On again during the half-off period, the display device 100 of the disclosure can perform a fast booting process for resuming a display driving operation normal display in a short time by supplying the data voltage Vdata to the display panel 110 without the off process.

[0113] At this time, the host system 200 can generate the off monitoring signal Off_MNT when the user supplies the power-off signal Power Off, and cut off the input power Vin after the half-off period using a timer therein.

[0114] At this time, the display device 100 can perform an off sensing process for sensing a characteristic value (threshold voltage or mobility) of the driving transistor DRT when the power-on signal is not supplied during the half-off period, and then display an off state.

[0115] Meanwhile, here, an exemplary case in which the host system 200 supplies the off monitoring signal Off_MNT after the half-off period when the power-off signal Power Off is supplied and cuts off the input power Vin has been shown. However, if there is an internal power source inside the display device 100, the display device 100 can perform a half-off process by blocking the data voltage Vdata when the power-off signal Power Off is supplied and by maintaining the internal driving power in an on state during the half-off period.

[0116] Figure 7 A block diagram showing a configuration of a display device according to an embodiment of the disclosure is shown.

[0117] Referring to Figure 7 The display device 100 according to an embodiment of the disclosure can include a display panel 110, a gate driving circuit 120, a data driving circuit 130, a timing controller 140, a power management circuit 150, and a half-off switching circuit 160.

[0118] A plurality of gate lines GL, a plurality of data lines DL, and a plurality of sub-pixels SP are disposed on the display panel 110. The gate driving circuit 120 supplies a scan signal SCAN to the plurality of gate lines GL. The data driving circuit 130 converts image data DATA into a data voltage Vdata and supplies the data voltage Vdata to the plurality of data lines DL.

[0119] The power management circuit 150 generates various driving powers for driving the gate driving circuit 120 and the data driving circuit 130 using an input power Vin supplied from a host system 200.

[0120] The timing controller 140 controls training and transmission of the image data DATA supplied from the host system 200 using the image control signals LOCKN, HTPDN. For example, the host system 200 can supply the image data DATA to the timing controller 140 while transmitting the image control signals LOCKN, HTPDN having a low level from the timing controller 140. In contrast, when the image control signals LOCKN, HTPDN having a high level are transmitted from the timing controller 140, the host system 200 can block the image data DATA without supplying the image data DATA to the timing controller 140. Here, the levels of the image control signals LOCKN, HTPDN for supplying the image data DATA can be differently changed.

[0121] The semi-disconnection switching circuit 160 can control the image control signals LOCKN, HTPDN to perform the semi-disconnection process during the semi-disconnection period according to the disconnection monitoring signal Off_MNT of the host system 200.

[0122] For example, when the user supplies the power-off signal Power Off, the host system 200 can maintain the input power Vin supplied to the display apparatus 100 in a high state during a predetermined semi-disconnection period, and can transmit the disconnection monitoring signal Off_MNT indicating the supply of the power-off signal Power Off to the display apparatus 100.

[0123] As described above, when the disconnection monitoring signal Off_MNT having a high level is transmitted from the host system 200, the semi-disconnection switching circuit 160 can change the image control signals LOCKN, HTPDN to a high level by supplying power having a high level to signal lines for transmitting the image control signals LOCKN, HTPDN.

[0124] Accordingly, the host system 200 can block the image data DATA while maintaining the input power Vin supplied to the display apparatus 100 in a high state during the semi-disconnection period. Accordingly, the display apparatus 100 can block the data voltage supplied to the display panel 110 while supplying driving power to the gate driving circuit 120 and the data driving circuit 130 during the semi-disconnection period.

[0125] The semi-disconnection switching circuit 160 can be located inside or outside the timing controller 140. When the semi-disconnection switching circuit 160 is located outside the timing controller 140, the semi-disconnection switching circuit 160 can be disposed on the control printed circuit board CPCB. Here, a case in which the semi-disconnection switching circuit 160 is disposed on the control printed circuit board CPCB has been shown.

[0126] Meanwhile, the host system 200 and the display apparatus 100 can be connected through various interfaces.

[0127] In this case, the number of interface cables of the control printed circuit board CPCB connecting the host system 200 and the display apparatus 100 can be determined by the amount of data to be transmitted and a clock signal.

[0128] For example, when the display apparatus 100 is driven in full high definition 120Hz, the interface cable between the host system 200 and the control printed circuit board CPCB of the display apparatus 100 needs to have 48 signal lines in an LVDS (Low Voltage Differential Signaling) interface. Thus, even if the LVDS interface is applied, the number of signal lines of the interface cable and the number of pins of the connector for connecting the interface cable can increase.

[0129] In this case, the cost for the interface cable and the connector increases, and an electromagnetic interference (EMI) problem can occur due to a high-frequency clock signal transmitted through the interface cable.

[0130] To improve this problem, recently, an interface having less EMI and a smaller number of signal lines than the LVDS interface is used. For example, a Vbyone interface developed by THine Electronics, Inc. has better signal transmission quality than the existing LVDS interface since an equalizer function is introduced, and also realizes high-speed data processing of a maximum of 3.75 Gbps per 1 pair. In addition, the Vbyone interface solves a skew adjustment problem occurring in clock transmission of the LVDS interface by employing a clock data recovery (CDR). Since the Vbyone interface does not have a clock transmission function required for the existing LVDS interface, EMI noise caused by clock transmission can be reduced.

[0131] Since the Vbyone interface can effectively cope with an increase in the amount of data and a faster driving, it has attracted attention as an alternative technology to the existing LVDS interface.

[0132] The display apparatus 100 according to an embodiment of the disclosure can be connected to the host system 200 through various interfaces, but a case using the Vbyone interface will be described as an example.

[0133] Figure 8 A Vbyone interface of a display apparatus according to an embodiment of the disclosure is illustrated, and Figure 9 A signal flow of a process of transmitting image data through the Vbyone interface is illustrated.

[0134] Reference will now be made in detail to Figure 8The Vbyone interface of the display apparatus 100 according to the embodiment of the disclosure can include a transmitter Tx of the host system 200 and a receiver Rx of the display apparatus 100.

[0135] To transmit the image data DATA through the Vbyone interface, a main link Vxl main link for transmitting the image data DATA between the host system 200 and the display apparatus 100 is required, and an auxiliary link for transmitting the off-monitor signal Off_MNT and the image control signals LOCKN, HTPDN. In addition, it can include a power link for transmitting input power Vin to the display apparatus 100.

[0136] As described above, the host system 200 can supply the off-monitor signal Off_MNT to the display apparatus 100 when the user transmits the power off signal Power Off, and can cut off the input power after a half-off period.

[0137] Referring to Figure 9 The display apparatus 100 using the Vbyone interface according to the embodiment of the disclosure generates the HTPDN signal corresponding to the image control signal at a low level after the power-on communication signal Power on is supplied.

[0138] The host system 200 transmits the CDR training mode signal CDR Train to the display apparatus 100 in response to the HTPDN signal having a low level.

[0139] The display apparatus 100 includes a CDR circuit for restoring a clock. The CDR circuit receives the CDR training mode signal CDR Train and locks the phase and frequency of the image data DATA.

[0140] In a state in which the phase and frequency of the image data DATA are locked, the display apparatus 100 transmits the LOCKN signal at a low level. In response to the LOCKN signal having a low level, the host system 200 transmits the image data DATA after transmitting the alignment training pattern signal ALN Train to the display apparatus 100 for a predetermined time.

[0141] The alignment training pattern signal ALN Train can include alignment data that is not displayed on the display panel 110. The alignment data allows the display apparatus 100 to determine data reception start timing according to a communication protocol of the Vbyone interface. When the alignment data is received, the display apparatus 100 can determine start timing of the image data DATA to be displayed on the display panel 110.

[0142] Figure 10 A signal flow diagram when the power-on communication signal is supplied during a half-off period in a display driving method according to an embodiment of the disclosure is illustrated.

[0143] Referring to Figure 10 According to the display driving method according to the embodiment of the disclosure, when a user supplies a power off signal Power Off to the display device 100 in a normal display of a display driving operation, a semi-off process is performed in a semi-off period of a predetermined time to display an image through the display panel 110.

[0144] For the above operation, the host system 200 maintains the input power Vin transmitted to the display device 100 at a high level during the semi-off period from the time when the power off signal is supplied to the display device 100, but supplies an off monitoring signal Off_MNT indicating that the power off signal Power Off has been supplied to the display device 100.

[0145] Therefore, the display device 100 can supply various driving powers to the gate driving circuit 120 and the data driving circuit 130 as they are, because the input power Vin transmitted from the host system 200 to the display device 100 is maintained at a high level during the semi-off period.

[0146] On the other hand, when the power off signal Power Off is supplied, the off monitoring signal Off_MNT having a high level can be supplied from the host system 200. Therefore, the display device 100 recognizes that the power off signal Power Off has been supplied, and converts the image control signals LOCKN, HTPDN for controlling the supply of the image data DATA to a high level. Therefore, the host system 200 terminates the supply of the image data DATA to the display device 100. Therefore, the data voltage Vdata supplied to the display panel 110 in the display device 100 is cut off.

[0147] Therefore, the display device 100 maintains the driving power supplied to the gate driving circuit 120 and the data driving circuit 130, but cuts off the data voltage Vdata transmitted to the display panel 110 during the semi-off period according to the off monitoring signal Off_MNT transmitted from the host system 200.

[0148] The semi-off period can have a time interval of several tens of seconds to several minutes.

[0149] If the user transmits the power on signal Power On again during the semi-off period in which the semi-off process is performed, the fast boot process can be performed because the off monitoring signal OFF_MNT is switched to a low level.

[0150] The image control signals LOCKN, HTPDN of the display device 100 are sequentially switched to low levels by the off monitoring signal Off_MNT having a low level when the fast boot-up process is being performed. That is, when the off monitoring signal Off_MNT is switched to a low level and the fast boot-up process is performed, the HTPDN signal for CDR training is switched to a low level, and then the LOCKN signal for alignment training can be sequentially switched to a low level while the input power Vin is at a high level.

[0151] Accordingly, the host system 200 transmits the CDR training mode signal CDR training and the alignment training mode signal ALN training in the case where the image control signals LOCKN, HTPDN having low levels are received, and restarts transmission of the image data DATA according to the start timing, so that the data voltage Vdata can be supplied to the display panel 110.

[0152] As described above, the image data DATA is cut off during the half-off period from the time when the power-off signal Power Off is supplied, but the input power Vin supplied to the display device 100 is maintained at a high level. Accordingly, even if the power-on signal Power On is again supplied during the half-off period, the fast boot-up process for quickly recovering the display driving operation NormalDisplay without going through the off process can be performed.

[0153] Figure 11 A signal flow when the power-on signal is not supplied during the half-off period in the display driving method according to the embodiment of the present disclosure is shown.

[0154] Referring to Figure 11 The display driving method according to the embodiment of the present disclosure performs a half-off process in a half-off period of a predetermined time within the display driving operation NormalDisplay when the user supplies the power-off signal Power Off to display an image through the display panel 110 in the display device 100.

[0155] The host system 200 maintains the input power Vin transmitted to the display device 100 at a high level during the half-off period from the time when the power-off signal is supplied to the display device 100, but supplies the off monitoring signal Off_MNT indicating that the power-off signal Power Off has been supplied to the display device 100.

[0156] Accordingly, the display device 100 can supply various driving powers to the gate driving circuit 120 and the data driving circuit 130 as they are, because the input power Vin transmitted from the host system 200 to the display device 100 is maintained at a high level during the half-off period.

[0157] On the other hand, when the power off signal Power Off is supplied, the off monitoring signal Off_MNT having a high level can be supplied from the host system 200. Thus, the display device 100 recognizes that the power off signal Power Off has been supplied, and the image control signals LOCKN, HTPDN for controlling the supply of the image data DATA are converted to high levels. Thus, the host system 200 terminates the supply of the image data DATA to the display device 100.

[0158] If the user does not supply the power on signal Power On again during the half-off period in which the half-off processing is being performed, the input power Vin supplied from the host system 200 is cut off when the half-off period terminates.

[0159] When the input power Vin supplied from the host system 200 is cut off, the gate driving circuit 120 and the data driving circuit 130 of the display device 100 terminate operation, so that the display panel 110 is in a display-off state.

[0160] Thus, when the half-off period terminates, the input power Vin is cut off and the display device 100 is turned off, so that the image control signals LOCKN, HTPN are cut off regardless of whether the off monitoring signal Off_MNT is at a high level or a low level.

[0161] At this time, the off sensing processing for sensing the characteristic value (threshold voltage or mobility) of the drive transistor DRT at the end of the half-off period can be performed.

[0162] If the user supplies the power on signal Power On after the display device 100 is turned off, the display device 100 can perform the on processing according to a predetermined order.

[0163] Figure 12 A flowchart of a display driving method according to an embodiment of the present disclosure is shown.

[0164] Referring to Figure 12 , the display driving method according to an embodiment of the present disclosure can include a step S100 of determining whether a power off signal Power Off is supplied, a step S200 of performing a half-off processing for blocking image data while maintaining driving power when the power off signal Power Off is supplied, steps S300, S400 of performing a quick start processing when a power on signal Power On is supplied within a half-off period, and a step S500 of performing an off processing for cutting off driving power when the power on signal Power On is not supplied within the half-off period.

[0165] When the quick start-up process is completed, a normal display driving operation S700 can be performed. Also, when a power-on signal Power On is supplied in the display-off state, a normal display driving operation can be performed through the turn-on process S800.

[0166] Brief descriptions of the above-described embodiments of the present disclosure are as follows.

[0167] The display device 100 according to the embodiments of the present disclosure can include a display panel 110 on which a plurality of sub-pixels SP are disposed, a timing controller 140 configured to transmit image control signals LOCKN, HTPDN to a host system 200 to receive image data DATA from the host system 200, a data driving circuit 130 configured to convert the image data DATA transmitted from the timing controller 140 into a data voltage Vdata and configured to supply the data voltage Vdata to the display panel 110, and a half-off switching circuit 160 configured to control the image control signals LOCKN, HTPDN so that the image data DATA is cut off from the host system 200 during a half-off period of a predetermined time from a time when an off-monitor signal Off_MNT is transmitted from the host system 200 in response to a power-off signal Power Off.

[0168] The host system 200 is configured to cut off input power after the off-monitor signal Off_MNT is transmitted and the half-off period ends.

[0169] During the half-off period, driving power supplied to the data driving circuit 130 is maintained in a turn-on state.

[0170] The half-off switching circuit 160 is configured to control the image control signals LOCKN, HTPDN so that the image data DATA is supplied from the host system 200 when a power-on signal Power On is supplied during the half-off period.

[0171] When the power-on signal Power On is not supplied during the half-off period, driving power supplied to the data driving circuit 130 becomes an off state.

[0172] An off-sensing process for sensing a characteristic value of a driving transistor DRT disposed on the display panel 110 is performed at the end of the half-off period.

[0173] The Vbyone interface is used for communication with the host system 200.

[0174] The image control signals LOCKN, HTPDN include an HTPDN signal for causing the host system 200 to transmit a CDR training mode signal CDR training in a predetermined time, and a LOCKN signal for causing the host system 200 to transmit an alignment training mode signal in a predetermined time.

[0175] The half-off period is a time interval of several tens of seconds to several minutes.

[0176] In addition, the display driving method for controlling the display apparatus 100 according to the embodiment of the disclosure can include determining whether a power-off signal Power Off is supplied, performing a half-off process for blocking image data DATA while maintaining supply of driving power to a data driving circuit 130 when the power-off signal Power Off is supplied, performing a fast boot process when a power-on signal Power On is supplied within a half-off period, and cutting off the driving power when the power-on signal Power On is not supplied within the half-off period; the display apparatus 100 includes a display panel 110 on which a plurality of sub-pixels SP are disposed, a timing controller 140 configured to control an operation of supplying image data DATA to a host system 200 through image control signals LOCKN, HTPDN, and the data driving circuit 130 configured to convert the image data DATA transmitted from the timing controller 140 into a data voltage Vdata and supply the data voltage Vdata to the display panel 110.

[0177] The half-off process includes an operation of controlling the image control signals LOCKN, HTPDN such that the image data DATA is cut off from the host system 200 for a half-off period from a time at which an off-monitor signal Off_MNT is transmitted from the host system 200 in response to the power-off signal Power Off.

[0178] The fast boot process includes an operation of controlling the image control signals LOCKN, HTPDN such that the image data DATA is supplied from the host system 200.

[0179] In addition, the display device 100 according to the embodiment of the present disclosure can include a display panel 110 on which a plurality of sub-pixels SP are disposed, a timing controller 140 configured to transmit an image control signal LOCKN, HTPDN to a host system 200 to receive image data DATA from the host system 200, a data driving circuit 130 configured to convert the image data DATA transmitted from the timing controller 140 into a data voltage Vdata and configured to supply the data voltage Vdata to the display panel 110, and a semi-off switching circuit 160 configured to control the timing controller 140 to perform a semi-off process for cutting off the image data DATA while maintaining the driving power supplied to the data driving circuit 130 during a semi-off period when a supply-off monitoring signal Off_MNT indicating a power-off signal Power Off is received from the host system 200, and to perform a fast boot process for supplying the image data DATA when a power-on signal Power On is supplied within the semi-off period.

[0180] The above description and drawings are merely illustrative of the technical idea of the present disclosure. It will be understood by those of ordinary skill in the art to which the present disclosure pertains that various modifications and changes can be made, for example, in the form of combinations, separations, replacements, and changes, without departing from the essential characteristics of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are intended to illustrate the scope of the technical idea of the present disclosure, and the scope of the present disclosure is not limited by the embodiments. The scope of the present disclosure should be interpreted in the following manner based on the appended claims: all technical ideas included within the scope equivalent to the claims belong to the present disclosure.

Claims

1. A display device, comprising: A display panel is provided with a plurality of sub-pixels; A timing controller configured to send image control signals to a host system to receive image data from the host system; A data driving circuit, configured to convert the image data sent from the timing controller into a data voltage and configured to supply the data voltage to the display panel; as well as A semi-disconnect switch circuit is configured to control the image control signal such that the image data is cut off from the host system during a first predetermined period of time, from the time when a disconnection monitoring signal is sent from the host system in response to a power disconnection signal until the execution of a disconnection sensing process for sensing characteristic values ​​of driving transistors disposed on the display panel.

2. The display device according to claim 1, wherein, The host system is configured to cut off the input power supplied for display drive operation after the disconnection monitoring signal is sent and the half-disconnection period ends.

3. The display device according to claim 1, wherein, The drive power supplied to the data drive circuit is kept in the on state during the half-off period.

4. The display device according to claim 1, wherein, The semi-disconnect switch circuit is configured to control the image control signal such that the image data is supplied from the host system when a power-on signal is supplied during the semi-disconnect period.

5. The display device according to claim 1, wherein, When no power-on signal is supplied during the half-disconnection period, the drive power supplied to the data drive circuit becomes disconnected.

6. The display device according to claim 1, wherein, The disconnection sensing process is performed at the end of the half-disconnection period.

7. The display device according to claim 1 further includes a Vbyone interface for communicating with the host system.

8. The display device according to claim 7, wherein, The image control signal includes: HTPDN signal, the HTPDN signal being used to cause the host system to send a CDR training mode signal at a second predetermined time; and The LOCKN signal is used to cause the host system to send an alignment training mode signal at a third predetermined time.

9. The display device according to claim 1, wherein, The semi-disconnection period is a time interval ranging from tens of seconds to several minutes.

10. A display driving method for controlling a display device, the display device comprising: A display panel is provided with a plurality of sub-pixels; A timing controller configured to control the operation of the host system supplying image data via image control signals; And a data driving circuit configured to convert the image data sent from the timing controller into a data voltage and supply the data voltage to the display panel; The display driving method includes: Determine if a power outage signal has been received; In the event that the power disconnection signal is supplied, during the half-disconnection period of the first predetermined time, a half-disconnection process for blocking the image data is performed while maintaining the drive power supplied to the data drive circuit. A fast start-up process is performed when a power-on signal is supplied during the half-disconnection period; and The drive power is cut off when no power-on signal is supplied during the half-disconnection period. The first predetermined time is the time period from the time when the host system sends a disconnection monitoring signal in response to the power disconnection signal to the time before the execution of disconnection sensing processing for sensing the characteristic values ​​of the driving transistors disposed on the display panel.

11. The display driving method according to claim 10, wherein, The semi-disconnect processing includes the following operation: controlling the image control signal such that the image data is cut off from the host system during the semi-disconnect period starting from the time when a disconnection monitoring signal is sent from the host system in response to the power disconnection signal.

12. The display driving method according to claim 10, wherein, The fast startup process includes the following operation: controlling the image control signal to supply the image data from the host system.

13. The display driving method according to claim 12, wherein, The display device also includes a Vbyone interface for communicating with the host system.

14. The display driving method according to claim 13, wherein, The image control signal includes HTPDN signal, the HTPDN signal being used to enable the host system to send CDR training mode signal at a second predetermined time; as well as The LOCKN signal is used to cause the host system to send an alignment training mode signal at a third predetermined time.

15. The display driving method according to claim 10, further comprising: The disconnection sensing process is performed at the end of the half-disconnection period.

16. The display driving method according to claim 10, wherein, The semi-disconnection period is a time interval ranging from tens of seconds to several minutes.

17. A display device, comprising: A display panel is provided with a plurality of sub-pixels; A timing controller configured to send image control signals to a host system to receive image data from the host system; A data driving circuit, configured to convert the image data sent from the timing controller into a data voltage and configured to supply the data voltage to the display panel; as well as A partial disconnect switch circuit is configured to control the timing controller to, upon receiving a disconnection monitoring signal from the host system indicating a power disconnection signal, perform a partial disconnection process during a first predetermined partial disconnection period to cut off the image data while maintaining the drive power supply to the data drive circuit during the partial disconnection period; and to perform a fast start-up process to supply the image data when a power-on signal is supplied during the partial disconnection period. The first predetermined time is the time period from the time when the host system sends a disconnection monitoring signal in response to the power disconnection signal to the time before the execution of disconnection sensing processing for sensing the characteristic values ​​of the driving transistors disposed on the display panel.

Images