Semiconductor device and method of operating a semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method of operating a semiconductor device. The semiconductor device includes a charge pump circuit configured to generate an output voltage by pumping an input voltage according to a first master clock and a second master clock; a voltage detection circuit configured to generate a comparison signal by comparing the output voltage with a reference voltage; and a drive control circuit configured to: selectively invert the first external clock and the second external clock at a start time of an active period of the comparison signal to receive the inverted clocks as first internal clocks and second internal clocks; generate the first master clock and the second master clock according to the first internal clocks and the second internal clocks while controlling a transition order such that the second master clock transitions after the first master clock transitions during the active period of the comparison signal; and store logic levels of the first master clock and the second master clock as a first preliminary clock and a second preliminary clock, respectively, at an end time of the active period of the comparison signal.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to a semiconductor design technique, and more specifically, to a semiconductor device including a charge pump circuit. Background Technology

[0002] In the operation of non-volatile memory devices such as flash memory or electrically erasable programmable read-only memory (EEPROM) devices, or volatile memory devices such as dynamic random access memory (DRAM) devices, high voltages are required for programming and erasing operations. These high voltages can be generated internally at levels higher than the external power supply voltage. Charge pump circuits can be used to generate such high voltages.

[0003] Currently, charge pump circuits are being developed in various fields to improve voltage multiplier efficiency and power efficiency. Summary of the Invention

[0004] Various embodiments of this disclosure are directed to semiconductor devices capable of reducing the input current consumed by the clock supplied to the charge pump circuit.

[0005] According to an embodiment of the present disclosure, a semiconductor device includes: a charge pump circuit adapted to generate an output voltage by pumping an input voltage according to a first master clock and a second master clock; a voltage detection circuit adapted to generate a comparison signal by comparing the output voltage with a reference voltage; and a drive control circuit adapted to generate the first master clock and the second master clock according to a first external clock and a second external clock during an activation period of the comparison signal, while controlling a transition sequence such that the second master clock transitions after the first master clock transitions.

[0006] According to an embodiment of the present disclosure, a method of operating a semiconductor device includes: generating an output voltage by pumping an input voltage according to a first master clock and a second master clock; comparing the output voltage with a reference voltage to generate and output a comparison signal; generating an output enable signal by determining, during an activation period of the comparison signal, whether a transition sequence of a first external clock and a second external clock satisfies a condition based on the logic levels of a first preliminary clock and a second preliminary clock; outputting a first master clock and a second master clock by latching the first external clock and the second external clock according to the output enable signal; and storing the first master clock and the second master clock as the first preliminary clock and the second preliminary clock, respectively, at the end of the activation period of the comparison signal.

[0007] According to an embodiment of the present disclosure, a method of operating a semiconductor device includes: generating a first master clock and a second master clock by latching a first external clock and a second external clock according to an output enable signal; generating an output voltage by pumping an input voltage according to the first master clock and the second master clock; generating a comparison signal by comparing the output voltage with a reference voltage; and generating the output enable signal by determining whether a transition sequence of the first external clock and the second external clock satisfies a condition during an activation time period of the comparison signal.

[0008] According to embodiments of the present disclosure, a semiconductor device may include: a charge pump circuit configured to generate an output voltage by pumping an input voltage according to a first master clock and a second master clock; a voltage detection circuit configured to generate a comparison signal by comparing the output voltage with a reference voltage; and a drive control circuit configured to: selectively invert a first external clock and a second external clock at the beginning of an activation period of the comparison signal to generate a first internal clock and a second internal clock; generate a first master clock and a second master clock according to the first internal clock and the second internal clock during the activation period of the comparison signal, while controlling the transition sequence such that the second master clock transitions after the first master clock transitions; and store the logic levels of the first master clock and the second master clock as a first preliminary clock and a second preliminary clock, respectively, at the end of the activation period of the comparison signal.

[0009] According to embodiments of the present disclosure, a method of operating a semiconductor device may include: generating an output voltage by pumping an input voltage according to a first master clock and a second master clock; generating a comparison signal by comparing the output voltage with a reference voltage; selectively inverting a first external clock and a second external clock at the start time of an activation period of the comparison signal to generate a first internal clock and a second internal clock; generating an output activation signal during the activation period of the comparison signal by determining whether the second internal clock transitions after the first internal clock transitions based on the logic levels of the first preliminary clock and the second preliminary clock; outputting the first master clock and the second master clock by latching the first internal clock and the second internal clock according to the output activation signal; and storing the first master clock and the second master clock as the first preliminary clock and the second preliminary clock, respectively, at the end time of the activation period of the comparison signal.

[0010] According to embodiments of this disclosure, an operation method of a semiconductor device may include: generating an output voltage by pumping an input voltage according to a first master clock and a second master clock; generating a comparison signal by comparing the output voltage with a reference voltage; generating a first internal clock and a second internal clock by selectively inverting a first external clock and a second external clock according to corresponding logic levels of the first internal clock, the second internal clock, a first detection signal, and a second detection signal at a time when the comparison signal becomes enabled; and generating a first master clock and a second master clock from the first internal clock and the second internal clock according to corresponding logic levels of the first internal clock, the second internal clock, the first detection signal, and the second detection signal while the comparison signal remains enabled. While the comparison signal remains enabled, the first detection signal and the second detection signal may represent corresponding logic levels of the first master clock and the second master clock at a time when the comparison signal becomes disabled. The first master clock and the second master clock may toggle at different timings.

[0011] The semiconductor device according to the present disclosure has the effect of reducing the input current of the charge pump circuit and reducing the total power, thereby improving power efficiency.

[0012] Furthermore, the semiconductor device according to the embodiments of this disclosure has the effect of minimizing the time required for operation of the charge pump circuit and reducing the ripple (noise) of the pump voltage level, thereby improving power efficiency. Attached Figure Description

[0013] Figure 1 This is a circuit diagram illustrating a cross-coupled charge pump circuit according to an embodiment of the present disclosure.

[0014] Figure 2 This describes embodiments such as those according to this disclosure. Figure 1 The timing diagram of the charge pump circuit shown is shown.

[0015] Figure 3 This illustrates an embodiment of the present disclosure in which features such as Figure 1 The diagram shows a block diagram of the semiconductor device for a charge pump circuit.

[0016] Figure 4A and Figure 4B This describes embodiments such as those according to this disclosure. Figure 3 The timing diagram shows the operation of the semiconductor device.

[0017] Figure 5 This is a block diagram illustrating a semiconductor device with an embedded charge pump circuit according to an embodiment of the present disclosure.

[0018] Figure 6 Examples of embodiments according to this disclosure are shown. Figure 5 The circuit diagram of the drive control circuit shown is shown.

[0019] Figure 7 This describes embodiments such as those according to this disclosure. Figure 6 The diagram shows the operation of the drive control circuit.

[0020] Figure 8 This is a timing diagram describing the operation of a semiconductor device according to embodiments of the present disclosure.

[0021] Figure 9A and Figure 9B These are timing diagrams that respectively describe the operation of a semiconductor device in the context of a comparative example and the operation of a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 10 This is a configuration diagram of a semiconductor device employing a charge pump circuit according to another embodiment of the present disclosure.

[0023] Figure 11 It is based on the embodiments of this disclosure. Figure 10 Detailed circuit diagram of the drive control circuit in the middle.

[0024] Figure 12 It is used to describe embodiments according to this disclosure. Figure 10 A diagram illustrating the operation of the drive control circuit.

[0025] Figure 13 It is used to describe embodiments according to this disclosure. Figure 10 Waveform diagram of the operation of the semiconductor device. Detailed Implementation

[0026] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0027] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “exemplary embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiment.

[0028] In this disclosure, the terms “comprising,” “having,” “containing,” and “including” are open-ended. As used in the appended claims, these terms indicate the presence of the referred elements and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components (e.g., interface units, circuitry, etc.).

[0029] In this disclosure, various units, circuits, or other components may be described or claimed as being "configured to" perform one or more tasks. In this context, "configured to" is used to represent a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component can be considered configured to perform a task even when the specified block / unit / circuit / component is not currently in operation (e.g., not turned on or activated). Blocks / units / circuits / components used with the "configured to" language include hardware such as circuits, memory storing program instructions executable to perform the operation, etc. Additionally, "configured to" may include general-purpose structures (e.g., general-purpose circuits) manipulated by software and / or firmware to operate in a manner capable of performing the tasks in question (e.g., an FPGA or a general-purpose processor executing software). "Configured to" may also include means (e.g., an integrated circuit) that adjusts a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture an apparatus for implementing or performing one or more tasks.

[0030] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) hardware circuit implementations only (e.g., implementations in analog and / or digital circuits only) and (b) combinations of circuits and software (and / or firmware), such as (if applicable): (i) combinations of processors or (ii) portions of processor / software (including digital signal processors), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions; and (c) circuits, such as microprocessors or portions of microprocessors, that require software or firmware to operate, even if the software or firmware is not physically present. This definition of “circuit” or “logic” applies to all use cases of the term included in any claim of this application. As another example, as used in this application, the terms “circuit” or “logic” also cover implementations of processors (or processors) or portions of processors and their accompanying software and / or firmware only. The terms “circuit” or “logic” also cover, for example (and if applicable to a particular claim element), integrated circuits used in storage devices.

[0031] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for nouns following the term and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that a first value must precede a second value. Furthermore, although terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0032] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. That is, the determination may be based solely on those factors or at least partially on those factors. For example, the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that the determination of A is also based on C. In other instances, A may be determined solely based on B.

[0033] Here, a data item, data entry, or data term can be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to one implementation, a data item may include discrete objects. According to another implementation, a data item may include information units within a transmission packet between two different components.

[0034] Various embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0035] Figure 1 This is a circuit diagram showing a cross-coupled type charge pump circuit 10 according to an embodiment of the present disclosure.

[0036] Reference Figure 1 The charge pump circuit 10 may include a first pump circuit 12, a second pump circuit 14, and an output capacitor COUT.

[0037] Although Figure 1A charge pump circuit 10 with two pump stages (i.e., first pump circuit 12 and second pump circuit 14) connected in series is shown, but the invention is not limited thereto. In one embodiment, the second pump circuit 14 may be configured to be connected in parallel to a switch (not shown). When the switch is on, the first output voltage VOUT_P from the first pump circuit 12 is directly supplied to the output terminal OUT_ND. In another embodiment, the charge pump circuit 10 may include two or more pump stages connected in series. In this case, the charge pump circuit 10 may additionally include one or more switches (not shown), each connected in parallel to a corresponding pump stage. The level of the output voltage can be adjusted by controlling the on / off state of the switch according to the load capacitance of the output terminal. As a result, the charge pump circuit 10 can be used generally by adjusting the level of the output voltage applied to the output terminal OUT_ND.

[0038] The first pump circuit 12 and the second pump circuit 14 can operate according to a pair of complementary clocks, each having an opposite phase. For example, the first complementary clock pair may include a first master clock CK00 and a first sub-clock CK00B, and the second complementary clock pair may include a second master clock CK90 and a second sub-clock CK90B. The first pump circuit 12 can generate a first output voltage VOUT_P by pumping an input voltage VIN at the input terminal IN_ND according to the first master clock CK00 and the first sub-clock CK00B. The first master clock CK00 may have an opposite phase to the first sub-clock CK00B and the same period as the first sub-clock CK00B. For example, when the first master clock CK00 is at a logic high level, the first sub-clock CK00B is at a logic low level. When the first master clock CK00 is at a logic low level, the first sub-clock CK00B is at a logic high level. The first sub-clock CK00B can be generated by inverting the first master clock CK00.

[0039] The second pump circuit 14 can generate a second output voltage VOUT at the output terminal OUT_ND by pumping the first output voltage VOUT_P according to the second master clock CK90 and the second sub-clock CK90B. The second master clock CK90 can have an opposite phase to the second sub-clock CK90B and the same period as the second sub-clock CK90B. For example, when the second master clock CK90 is at a logic high level, the second sub-clock CK90B is at a logic low level. When the second master clock CK90 is at a logic low level, the second sub-clock CK90B is at a logic high level. The second sub-clock CK90B can be generated by inverting the second master clock CK90. Preferably, the first master clock CK00 and the second master clock CK90 have a 90-degree phase difference, and the first sub-clock CK00B and the second sub-clock CK90B have a 90-degree phase difference.

[0040] The output capacitor COUT can be connected between the output terminal OUT_ND and the ground voltage (VSS) terminal.

[0041] The first pump circuit 12 may include a first transistor M1 to a fourth transistor M4, a first capacitor C1, and a second capacitor C2. The second pump circuit 14 may include a fifth transistor M5 to an eighth transistor M8, a third capacitor C3, and a fourth capacitor C4. The first capacitor C1 may have a first terminal for receiving a first master clock CK00, the second capacitor C2 may have a first terminal for receiving a first sub-clock CK00B, the third capacitor C3 may have a first terminal for receiving a second master clock CK90, and the fourth capacitor C4 may have a first terminal for receiving a second sub-clock CK90B.

[0042] Since the second pump circuit 14 has a configuration that is basically the same as that of the first pump circuit 12, the first pump circuit 12 will be used as an example for description.

[0043] The first transistor M1 can be connected between the input terminal IN_ND and the second terminal of the first capacitor C1, and has a gate for receiving the first sub-clock CK00B transmitted through the second capacitor C2. The second transistor M2 can be connected between the input terminal IN_ND and the second terminal of the second capacitor C2, and has a gate for receiving the first master clock CK00 transmitted through the first capacitor C1. The third transistor M3 can be connected between the second terminal of the second capacitor C2 and the output node that outputs the first output voltage VOUT_P, and has a gate for receiving the first master clock CK00 transmitted through the first capacitor C1. The fourth transistor M4 can be connected between the second terminal of the first capacitor C1 and the output node, and has a gate for receiving the first sub-clock CK00B transmitted through the second capacitor C2. Preferably, the first transistor M1 and the second transistor M2 can be implemented by N-channel metal-oxide-semiconductor (NMOS) transistors, and the third transistor M3 and the fourth transistor M4 can be implemented by P-channel metal-oxide-semiconductor (PMOS) transistors.

[0044] When the charge pump circuit 10 includes two or more pump stages connected in series, the series-connected odd-numbered pump stages can be driven according to the first master clock CK00 and the first sub-clock CK00B, while the series-connected even-numbered pump stages can be driven according to the second master clock CK90 and the second sub-clock CK90B.

[0045] Figure 2 This is a description of the embodiments according to the present disclosure. Figure 1 The timing diagram of the operation of the charge pump circuit 10 shown is shown.

[0046] Reference Figure 2 The operation of the first pump circuit 12 and the second pump circuit 14 is described.

[0047] [First Interval]

[0048] During the first interval or first time period, the first master clock CK00 goes high and the first sub-clock CK00B goes low. The first transistor M1 and the third transistor M3 are off, while the second transistor M2 and the fourth transistor M4 are on. The second master clock CK90 goes low and the second sub-clock CK90B goes high. The fifth transistor M5 and the seventh transistor M7 are on, while the sixth transistor M6 and the eighth transistor M8 are off.

[0049] As a result, the voltage charged at the first capacitor C1 is discharged and supplied to the second pump circuit 14 as the first output voltage VOUT_P. The first output voltage VOUT_P supplied to the second pump circuit 14 is charged at the third capacitor C3 through the fifth transistor M5. At this time, the input voltage VIN at the input terminal IN_ND is charged at the second capacitor C2 through the second transistor M2, and the voltage charged at the fourth capacitor C4 is discharged and output to the output terminal OUT_ND as the second output voltage VOUT.

[0050] [Second Interval]

[0051] During the second interval or second time period, while the first master clock CK00 and the first slave clock CK00B maintain the same phase as the first interval, the second master clock CK90 transitions to a logic high level, and the second slave clock CK90B transitions to a logic low level. The fifth transistor M5 and the seventh transistor M7 are turned off, while the sixth transistor M6 and the eighth transistor M8 are turned on. As a result, the voltage charged at the third capacitor C3 is discharged and provided as the second output voltage VOUT to the output terminal OUT_ND. At this time, the first output voltage VOUT_P is charged at the fourth capacitor C4 through the sixth transistor M6.

[0052] [Third Interval]

[0053] During the third interval or third time period, while the second master clock CK90 and the second sub-clock CK90B maintain the same phase as the second interval, the first master clock CK00 transitions to a logic low level, and the first sub-clock CK00B transitions to a logic high level. The first transistor M1 and the third transistor M3 are turned on. The voltage charged at the second capacitor C2 is discharged and supplied to the second pump circuit 14 as the first output voltage VOUT_P. Because the sixth transistor M6 is turned on, the first output voltage VOUT_P is charged at the fourth capacitor C4 through the sixth transistor M6. At this time, the input voltage VIN at the input terminal IN_ND is charged at the first capacitor C1 through the first transistor M1.

[0054] [Fourth Interval]

[0055] During the fourth interval or fourth time period, while the first master clock CK00 and the first slave clock CK00B maintain the same phase as the third interval, the second master clock CK90 transitions to logic low, and the second slave clock CK90B transitions to logic high. The fifth transistor M5 and the seventh transistor M7 are turned on, while the sixth transistor M6 and the eighth transistor M8 are turned off. The voltage charged at the fourth capacitor C4 is discharged and provided as the second output voltage VOUT to the output terminal OUT_ND. At this time, the first output voltage VOUT_P is charged at the third capacitor C3 through the fifth transistor M5.

[0056] As described above, the operation for the first to fourth intervals is repeatedly executed as the first master clock CK00 and the second master clock CK90, as well as the first sub-clock CK00B and the second sub-clock CK90, toggle. As a result, the second output voltage VOUT at the output terminal OUT_ND is measured by the output capacitor ( Figure 1 The voltage is charged at COUT, thus serving as the final output voltage.

[0057] Figure 3 This illustrates an embedded embodiment according to an embodiment of the present disclosure. Figure 1 The diagram shows a block diagram of the semiconductor device 20 of the charge pump circuit 10.

[0058] Reference Figure 3 The semiconductor device 20 may include a charge pump circuit 10, a voltage detection circuit 22, and a drive control circuit 24.

[0059] The charge pump circuit 10 can have the same characteristics as... Figure 1 and Figure 2 The structures and operations shown are essentially the same.

[0060] The voltage detection circuit 22 generates a comparison signal CMP by comparing the output voltage VOUT with the reference voltage VREF. The voltage detection circuit 22 may include a voltage divider 22A and a comparator 22B.

[0061] Voltage divider 22A can divide the output voltage VOUT according to a set ratio to output a detection voltage VFB. Voltage divider 22A may include a first resistor R1 and a second resistor R2 connected in series between the output terminal OUT_ND and the ground voltage (VSS) terminal. Voltage divider 22A can output the detection voltage VFB at the common terminal C_ND between the first resistor R1 and the second resistor R2. Comparator 22B can output a comparison signal CMP by comparing the detection voltage VFB with a reference voltage VREF. When the detection voltage VFB is lower than the reference voltage VREF, comparator 22B can activate the comparison signal CMP to a high level. Preferably, a band-gap voltage having a constant voltage level independent of changes in the external power supply voltage can be used as the reference voltage VREF.

[0062] The drive control circuit 24 can latch the first external clock CK00_EX and the second external clock CK90_EX according to the comparison signal CMP, so as to output the first master clock CK00 and the second master clock CK90. The drive control circuit 24 may include a latch circuit 24A and an output circuit 24B.

[0063] The latch circuit 24A can detect each rising edge of the first external clock CK00_EX and the second external clock CK90_EX during the active interval or active time period of the comparison signal CMP, and output the first intermediate clock CK00_L and the second intermediate clock CK90_L. The first intermediate clock CK00_L and the second intermediate clock CK90_L can each have an active interval that is substantially the same as that of the first external clock CK00_EX and the second external clock CK90_EX, respectively. During the active interval of the comparison signal CMP, the output circuit 24B can output the first intermediate clock CK00_L and the second intermediate clock CK90_L as the first master clock CK00 and the second master clock CK90, respectively. The output circuit 24B can include a first logic gate AND1 and a second logic gate AND2. The first logic gate AND1 can perform a logical AND operation on the first intermediate clock CK00_L and the comparison signal CMP to output the first master clock CK00. The second logic gate AND2 can perform a logical AND operation on the second intermediate clock CK90_L and the comparison signal CMP to output the second master clock CK90.

[0064] Figure 4A and Figure 4B This describes embodiments according to this disclosure. Figure 3The timing diagram shows the operation of the semiconductor device 20.

[0065] Reference Figure 4A and Figure 4B The voltage detection circuit 22 generates a comparison signal CMP by comparing the output voltage VOUT with the reference voltage VREF. When the detected voltage VFB is lower than the reference voltage VREF, the voltage detection circuit 22 can activate the comparison signal CMP to a high level. The latch circuit 24A can detect each rising edge of the first external clock CK00_EX and the second external clock CK90_EX during the active period of the comparison signal CMP, and output the first intermediate clock CK00_L and the second intermediate clock CK90_L. During the active period of the comparison signal CMP, the output circuit 24B can output the first intermediate clock CK00_L and the second intermediate clock CK90_L as the first master clock CK00 and the second master clock CK90, respectively. That is, during the active period of the comparison signal CMP, the drive control circuit 24 can activate the first master clock CK00 and the second master clock CK90 for a specific period of time by detecting each rising edge of the first external clock CK00_EX and the second external clock CK90_EX, and deactivate the first master clock CK00 and the second master clock CK90 at the end of the active period or period of the comparison signal CMP.

[0066] exist Figure 4A In the scenario shown, the first master clock CK00 and the second master clock CK90 can switch simultaneously at the end of the active interval / time period of the comparison signal CMP (i.e., the falling edge of the comparison signal CMP). Because the clock switching operation is performed simultaneously, the peak current consumed due to the switching operation may increase. Figure 4B In the scenario shown, during the active period of the comparison signal CMP, only the first master clock CK00 toggles. The second master clock CK90 does not toggle during this time. Since even if the first master clock CK00 toggles, the second master clock CK90 does not toggle, therefore... Figure 2 The operations described in the first to fourth intervals can be performed without repetition. Therefore, the charge pump circuit 10 does not pump the input voltage VIN. Even when the first master clock CK00 toggles, no output voltage VOUT is generated, which would increase current consumption due to unnecessary switching operations.

[0067] The following describes in detail a semiconductor device including a charge pump circuit that can minimize / reduce current consumption due to the input clock of the charge pump circuit.

[0068] Figure 5 This is a block diagram showing a semiconductor device 100 with a charge pump circuit embedded according to an embodiment of the present disclosure.

[0069] Reference Figure 5 The semiconductor device 100 may include a charge pump circuit 110, a voltage detection circuit 120, and a drive control circuit 130.

[0070] The charge pump circuit 110 can generate an output voltage VOUT by pumping the input voltage VIN according to a first master clock CK00 and a second master clock CK90. The charge pump circuit 110 can perform a pumping operation on the input voltage VIN according to the first master clock CK00 and the second master clock CK90 to increase the level of the output voltage VOUT. The charge pump circuit 110 can have... Figure 1 and Figure 2 The structure and operation of the charge pump circuit 110 are basically the same.

[0071] The voltage detection circuit 120 generates a comparison signal CMP by comparing the output voltage VOUT with a reference voltage VREF. The voltage detection circuit 120 may include a voltage divider 122 and a comparator 124.

[0072] Voltage divider 122 can divide the output voltage VOUT according to a set ratio to output a detection voltage VFB. Voltage divider 122 may include a first resistor R3 and a second resistor R4 connected in series between the output terminal OUT_ND and the ground voltage (VSS) terminal. Voltage divider 122 can output the detection voltage VFB at the common terminal C_ND between the first resistor R3 and the second resistor R4. Comparator 124 can output a comparison signal CMP by comparing the detection voltage VFB with a reference voltage VREF. When the detection voltage VFB is lower than the reference voltage VREF, comparator 124 can activate the comparison signal CMP to a high level. Preferably, a bandgap voltage having a constant voltage level independent of changes in the external power supply voltage can be used as the reference voltage VREF.

[0073] The drive control circuit 130 can generate a first master clock CK00 and a second master clock CK90 based on a first external clock CK00_EX and a second external clock CK90_EX during the active period of the comparison signal CMP. Specifically, according to the embodiment, the drive control circuit 130 can control the transitions of the first master clock CK00 and the second master clock CK90 according to the transition sequence. The drive control circuit 130 can control the transition sequence such that the second master clock CK90 transitions after the first master clock CK00 transitions. During the active period of the comparison signal CMP, after the first master clock CK00 transitions from logic low to logic high, the drive control circuit 130 can control the second master clock CK90 to transition from logic low to logic high. During the active period of the comparison signal CMP, after the first master clock CK00 transitions from logic high to logic low, the drive control circuit 130 can control the second master clock CK90 to transition from logic high to logic low. Furthermore, the drive control circuit 130 according to the embodiment can control the first master clock CK00 and the second master clock CK90 to maintain their logic levels at the end of the active interval / time period of the comparison signal CMP.

[0074] Specifically, the drive control circuit 130 may include a previous clock storage circuit 132, a sequence determination circuit 134, and an output control circuit 136.

[0075] The prior clock storage circuit 132 can store the first master clock CK00 and the second master clock CK90 as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively, according to the comparison signal CMP. The prior clock storage circuit 132 can also store the first master clock CK00 and the second master clock CK90 at the end of the active interval / time period of the comparison signal CMP (i.e., synchronously with the falling edge of the comparison signal CMP).

[0076] The sequence determination circuit 134 can generate an output enable signal SEQ_ON by determining, based on the first preliminary clock CK00_S and the second preliminary clock CK90_S, whether the transition sequence of the first external clock CK00_EX and the second external clock CK90_EX meets a specific condition during the active interval of the comparison signal CMP. The specific condition may be that the second external clock CK90_EX transitions from a logic low level to a logic high level after the first external clock CK00_EX transitions from a logic low level to a logic high level, or alternatively, the second external clock CK90_EX transitions from a logic high level to a logic low level after the first external clock CK00_EX transitions from a logic high level to a logic low level. Specifically, the sequence determination circuit 134 can generate a selection signal ( ) by decoding the logic levels of the first preliminary clock CK00_S and the second preliminary clock CK90_S. Figure 6The sequence determination circuit 134 can select one of the first external clock CK00_EX and its inverted signal (not shown) based on the selection signal SEL<3:0>, and output a first sequence selection signal (SEL<3:0>). Figure 6 The sequence determination circuit 134 can select one of the second external clock CK90_EX and its inverted signal (not shown) based on the selection signal SEL<3:0>, and output the second sequence selection signal (CK00_SEL). Figure 6 (CK90_SEL in the example). The sequence determination circuit 134 can generate an output enable signal SEQ_ON based on the comparison signal CMP, the first sequence selection signal CK00_SEL, and the second sequence selection signal CK90_SEL.

[0077] The output control circuit 136 can output the first master clock CK00 and the second master clock CK90 by latching the first external clock CK00_EX and the second external clock CK90_EX according to the output enable signal SEQ_ON.

[0078] As described above, the drive control circuit 130 according to the embodiment can control the transition sequence such that the second master clock CK90 transitions after the first master clock CK00 transitions. Furthermore, the drive control circuit 130 according to the embodiment can control the first master clock CK00 and the second master clock CK90 to maintain their logic levels at the end of the active interval / time period of the comparison signal CMP. Therefore, the semiconductor device 100 can control the first master clock CK00 and the second master clock CK90 to transition at different times, and can minimize / reduce current consumption caused by unnecessary switching operations.

[0079] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 5 The circuit diagram of the drive control circuit 130 shown is shown. Figure 7 This describes embodiments according to this disclosure. Figure 6 A diagram showing the operation of the drive control circuit 130.

[0080] Reference Figure 6 The diagram shows a detailed circuit diagram of the previous clock storage circuit 132, sequence determination circuit 134, and output control circuit 136.

[0081] The preceding clock storage circuit 132 may include a first memory 132A and a second memory 132B. The first memory 132A may store a first master clock CK00 at the end of the active interval / time period of the comparison signal CMP to output a first preliminary clock CK00_S. The second memory 132B may store a second master clock CK90 at the end of the active interval / time period of the comparison signal CMP to output a second preliminary clock CK90_S. Preferably, the first memory 132A and the second memory 132B may be implemented using D flip-flops synchronized with the falling edge of the comparison signal CMP.

[0082] The sequence determination circuit 134 may include a logic decoder 1342, a selector 1344, and an enable signal generator 1346.

[0083] The logic decoder 1342 can generate the selection signal SEL<3:0> by decoding the logic levels of the first preliminary clock CK00_S and the second preliminary clock CK90_S. For example, Figure 7 As shown, when both the first preliminary clock CK00_S and the second preliminary clock CK90_S are at a logic low level, the logic decoder 1342 can generate a selection signal SEL<3:0> of "0001". When the first preliminary clock CK00_S is at a logic high level and the second preliminary clock CK90_S is at a logic low level, the logic decoder 1342 can generate a selection signal SEL<3:0> of "0010". When the first preliminary clock CK00_S is at a logic low level and the second preliminary clock CK90_S is at a logic high level, the logic decoder 1342 can generate a selection signal SEL<3:0> of "0100". When both the first preliminary clock CK00_S and the second preliminary clock CK90_S are at a logic high level, the logic decoder 1342 can generate a selection signal SEL<3:0> of "1000".

[0084] The sequence determination circuit 134 may further include first inverters INV1 through fifth inverters INV5. First inverter INV1 inverts the first external clock CK00_EX to output a first negative clock CK00EB, and second inverter INV2 inverts the first negative clock CK00EB to output a first positive clock CK00ED. Third inverter INV3 inverts the second external clock CK90_EX to output a second negative clock CK90EB, and fourth inverter INV4 inverts the second negative clock CK90EB to output a second positive clock CK90ED. Fifth inverter INV5 inverts the comparator signal CMP to output an inverted comparator signal CMPB.

[0085] Selector 1344 can select one of the first positive clock CK00ED and the first negative clock CK00EB according to the selection signal SEL<3:0>, and output a first sequence selection signal CK00_SEL. Selector 1344 can also select one of the second positive clock CK90ED and the second negative clock CK90EB according to the selection signal SEL<3:0>, and output a second sequence selection signal CK90_SEL. For example, as... Figure 7 As shown, selector 1344 can select the first negative clock CK00EB and the second negative clock CK90EB according to the selection signal SEL<3:0> of “0001” to output the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL respectively. Selector 1344 can select the first positive clock CK00ED and the second negative clock CK90EB according to the selection signal SEL<3:0> of “0010” to output the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL respectively. Selector 1344 can select the first negative clock CK00EB and the second positive clock CK90ED according to the selection signal SEL<3:0> of “0100” to output the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL respectively. Selector 1344 can select the first positive clock CK00ED and the second positive clock CK90ED according to the selection signal SEL<3:0> of “1000” to output the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL respectively.

[0086] During the active period of the comparison signal CMP, the enable signal generator 1346 can activate the output enable signal SEQ_ON in response to the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL. The enable signal generator 1346 can deactivate the output enable signal SEQ_ON at the end of the active period / time interval of the comparison signal CMP. That is, the enable signal generator 1346 can deactivate the output enable signal SEQ_ON synchronously with the falling edge of the comparison signal CMP. Specifically, the enable signal generator 1346 may include a set signal generator 1346A and a set / reset (SR) latch 1346B.

[0087] The set signal generator 1346A can generate a set signal S based on the comparison signal CMP, the first sequence selection signal CK00_SEL, and the second sequence selection signal CK90_SEL. The set signal generator 1346A can be implemented using logic gates that perform a logical AND operation on the comparison signal CMP, the first sequence selection signal CK00_SEL, and the second sequence selection signal CK90_SEL. When both the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL become logic high, the set signal generator 1346A can activate the set signal S to a logic high level during the active period of the comparison signal CMP.

[0088] The SR latch 1346B can output an output enable signal SEQ_ON. The output enable signal SEQ_ON is activated in response to the set signal S and deactivated in response to the inverted compare signal CMPB.

[0089] The output control circuit 136 may include a first latch 136A and a second latch 136B. The first latch 136A can latch a first external clock CK00_EX and output a first master clock CK00 according to the output enable signal SEQ_ON. The first latch 136A can latch the first external clock CK00_EX to output the first master clock CK00 when the output enable signal SEQ_ON is activated, and maintain the level of the previously latched first master clock CK00 when the output enable signal SEQ_ON is deactivated. The second latch 136B can latch a second external clock CK90_EX and output a second master clock CK90 according to the output enable signal SEQ_ON. The second latch 136B can latch the second external clock CK90_EX to output the second master clock CK90 when the output enable signal SEQ_ON is activated, and maintain the level of the previously latched second master clock CK90 when the output enable signal SEQ_ON is deactivated.

[0090] In the following text, refer to Figures 5 to 8 The operation of the semiconductor device 100 is described in detail.

[0091] Figure 8 This is a timing diagram describing the operation of a semiconductor device according to embodiments of the present disclosure.

[0092] Reference Figure 8During the first interval t1, the detected voltage VFB is greater than or equal to the reference voltage VREF. The voltage detection circuit 120 deactivates the comparison signal CMP to a logic low level. The sequence determination circuit 134 deactivates the output enable signal SEQ_ON to a logic low level. The output control circuit 136 maintains the levels of the first master clock CK00 and the second master clock CK90 without toggling them. Therefore, the charge pump circuit 110 does not perform a pumping operation on the input voltage VIN. Since the previous clock storage circuit 132 stored the first preliminary clock CK00_S and the second preliminary clock CK90_S at logic low levels, the sequence determination circuit 134 outputs the first sequence selection signal CK00_SEL by inverting the first external clock CK00_EX according to the selection signal SEL<3:0> of “0001”, and outputs the second sequence selection signal CK90_SEL by inverting the second external clock CK90_EX.

[0093] During the second interval t2, the detected voltage VFB becomes lower than the reference voltage VREF. The voltage detection circuit 120 activates the comparison signal CMP to a logic high level. Since the previous clock storage circuit 132 still stores the first preliminary clock CK00_S and the second preliminary clock CK90_S at a logic low level, the sequence determination circuit 134 outputs the first sequence selection signal CK00_SEL by inverting the first external clock CK00_EX, and outputs the second sequence selection signal CK90_SEL by inverting the second external clock CK90_EX, according to the selection signal SEL<3:0> of “0001”. When both the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL become logic high, the sequence determination circuit 134 activates the set signal S during the active interval of the comparison signal CMP. The sequence determination circuit 134 activates the output enable signal SEQ_ON in response to the set signal S. The output control circuit 136 outputs the first master clock CK00 and the second master clock CK90 by latching the first external clock CK00_EX and the second external clock CK90_EX according to the output enable signal SEQ_ON. Therefore, the charge pump circuit 110 performs a pumping operation on the input voltage VIN to increase the level of the output voltage VOUT (i.e., the detection voltage VFB).

[0094] During the third interval t3, the detected voltage VFB becomes greater than the reference voltage VREF. The voltage detection circuit 120 deactivates the comparison signal CMP to a logic low level. The sequence determination circuit 134 deactivates the output enable signal SEQ_ON. The output control circuit 136 maintains the levels of the first master clock CK00 and the second master clock CK90 without toggling them. Therefore, the charge pump circuit 110 does not perform a pumping operation on the input voltage VIN. At the end of the activation interval / time period of the comparison signal CMP, the previous clock storage circuit 132 stores the logic high levels of the first master clock CK00 and the second master clock CK90 as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively. The sequence determination circuit 134 generates the "1000" selection signal SEL<3:0> based on the logic high levels of the first preliminary clock CK00_S and the second preliminary clock CK90_S. Based on the selection signal SEL<3:0> of “1000”, the sequence determination circuit 134 outputs the first external clock CK00_EX as the first sequence selection signal CK00_SEL, and outputs the second external clock CK90_EX as the second sequence selection signal CK90_SEL.

[0095] During the fourth interval t4, the detected voltage VFB becomes lower than the reference voltage VREF. The voltage detection circuit 120 activates the comparison signal CMP to a logic high level. Since the first preliminary clock CK00_S and the second preliminary clock CK90_S remain at logic high levels, the sequence determination circuit 134 outputs a first external clock CK00_EX as a first sequence selection signal CK00_SEL and a second external clock CK90_EX as a second sequence selection signal CK90_SEL. When both the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL become logic high, the sequence determination circuit 134 activates the set signal S during the active interval of the comparison signal CMP. The sequence determination circuit 134 activates the output enable signal SEQ_ON in response to the set signal S. Even if the comparison signal CMP is activated to a logic high level, the output enable signal SEQ_ON is not immediately activated; instead, it is activated when the transition sequence of the first external clock CK00_EX and the second external clock CK90_EX meets a specific condition. That is, when both the first sequence selection signal CK00_SEL and the second sequence selection signal CK90_SEL become logic high, the output enable signal SEQ_ON is activated. The output control circuit 136 outputs the first master clock CK00 and the second master clock CK90 by latching the first external clock CK00_EX and the second external clock CK90_EX according to the output enable signal SEQ_ON. Therefore, the charge pump circuit 110 performs a pumping operation on the input voltage VIN to increase the level of the output voltage VOUT (i.e., the detection voltage VFB).

[0096] During the fifth interval t5, the voltage detection circuit 120 deactivates the comparison signal CMP to a logic low level. The sequence determination circuit 134 deactivates the output enable signal SEQ_ON. At the end of the activation interval / time period of the comparison signal CMP, the previous clock storage circuit 132 stores the logic low-level first master clock CK00 and second master clock CK90 as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively. According to the selection signal SEL<3:0> of “0001”, the sequence determination circuit 134 outputs the first sequence selection signal CK00_SEL by inverting the first external clock CK00_EX, and outputs the second sequence selection signal CK90_SEL by inverting the second external clock CK90_EX.

[0097] As described above, during the active period of the comparison signal CMP, the drive control circuit 130 of the semiconductor device 100 according to the embodiment can output the first master clock CK00 and the second master clock CK90 based on the logic levels of the first preliminary clock CK00_S and the second preliminary clock CK90_S by determining whether the transition sequence of the first external clock CK00_EX and the second external clock CK90_EX satisfies a specific condition. Furthermore, at the end of the active period / time interval of the comparison signal CMP, the drive control circuit 130 can control the first master clock CK00 and the second master clock CK90 to maintain their logic levels by storing the first master clock CK00 and the second master clock CK90 as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively. Therefore, the semiconductor device 100 can control the first master clock CK00 and the second master clock CK90 to not transition simultaneously, and can minimize / reduce current consumption caused by unnecessary switching operations.

[0098] Figure 9A This is a timing diagram describing the operation of a semiconductor device according to a comparative example of an embodiment of the present disclosure. Figure 9B This is a timing diagram describing the operation of a semiconductor device according to embodiments of the present disclosure.

[0099] Reference Figure 9A In the case of a semiconductor device according to a comparative example, for example, in Figure 3In the case of semiconductor device 20, the first master clock CK00 and the second master clock CK90 switch simultaneously at the end of the active interval / time period of the comparison signal CMP. Therefore, the peak current consumed due to such switching operation can increase, thereby increasing the ripple voltage to as high as 1.395V. Furthermore, during the active interval of the comparison signal CMP, only the first master clock CK00 toggles, while the second master clock CK90 does not, which increases current consumption due to unnecessary switching operations.

[0100] Reference Figure 9B According to an implementation, in a semiconductor device, for example in Figure 5 In the semiconductor device 100, the first master clock CK00 and the second master clock CK90 maintain their logic levels at the end of the active interval / time period of the comparison signal CMP. Since the simultaneous transition of the first master clock CK00 and the second master clock CK90 is eliminated, the peak current can be reduced, thereby reducing the ripple to 0.986V. Furthermore, by controlling the transition sequence so that the second master clock CK90 transitions after the first master clock CK00, unnecessary switching operations are eliminated, thereby minimizing / reducing current consumption.

[0101] In the following, this disclosure proposes a semiconductor device that not only reduces the input current supplied to the clock of the charge pump circuit, but also minimizes the clock latency.

[0102] Figure 10 This is a configuration diagram of a semiconductor device 100 employing a charge pump circuit according to another embodiment of the present disclosure.

[0103] Reference Figure 10 The semiconductor device 100 may include a charge pump circuit 110, a voltage detection circuit 120, and a drive control circuit 630.

[0104] The charge pump circuit 110 can generate an output voltage VOUT by pumping an input voltage VIN according to a first master clock CK00 and a second master clock CK90. The charge pump circuit 110 can have a reference... Figure 1 and Figure 2 The configuration of the charge pump circuit 10 described is basically the same.

[0105] Voltage detection circuit 120 generates a comparison signal CMP by comparing the output voltage VOUT with a reference voltage VREF. Voltage detection circuit 120 may include a voltage divider 122 and a comparator 124. Voltage divider 122 divides the output voltage VOUT and provides the divided voltage as the detection voltage VFB. Voltage divider 122 may include a first resistor R3 and a second resistor R4 connected in series to the output terminal OUT_ND and the ground voltage VSS terminal, and the detection voltage VFB can be output from the common terminal C_ND of the first resistor R3 and the second resistor R4. Comparator 124 outputs the comparison signal CMP by comparing the reference voltage VREF with the detection voltage VFB. When the detection voltage VFB is less than or equal to the reference voltage VREF, comparator 124 can activate the comparison signal CMP to a high level and output the activated comparison signal CMP. Preferably, the reference voltage VREF can be a bandgap voltage (BANDGAP VOLTAGE) having a constant voltage level independent of changes in the externally supplied voltage.

[0106] The drive control circuit 630 can selectively invert the first external clock CK00_EX and the second external clock CK90_EX at the beginning of the activation period of the comparison signal CMP to generate the first internal clock CK00IN and the second internal clock CK90IN. Furthermore, at the end of the activation period of the comparison signal CMP, the drive control circuit 630 can store the logic levels of the first master clock CK00 and the second master clock CK90 as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively. Specifically, according to this disclosure, the drive control circuit 630 can selectively invert the first external clock CK00_EX and the second external clock CK90_EX based on the corresponding logic levels of the first preliminary clock CK00_S, the second preliminary clock CK90_S, the first external clock CK00_EX, and the second external clock CK90_EX to generate the first internal clock CK00IN and the second internal clock CK90IN.

[0107] Furthermore, during the active period of the comparison signal CMP, the drive control circuit 630 can generate a first master clock CK00 and a second master clock CK90 based on the first internal clock CK00IN and the second internal clock CK90IN. Specifically, according to the present disclosure, the drive control circuit 630 can control the transition sequence such that the first master clock CK00 transitions, and then the second master clock CK90 transitions. That is, during the active period of the comparison signal CMP, the drive control circuit 630 can control the transition sequence such that the first master clock CK00 transitions from logic low to logic high, and then the second master clock CK90 transitions from logic low to logic high, and the first master clock CK00 transitions from logic high to logic low, and then the second master clock CK90 transitions from logic high to logic low.

[0108] More specifically, the drive control circuit 630 may include a previous clock storage unit 632, a clock input unit 638, a clock sequence determination unit 634, and an output control unit 636. The clock input unit 638 may include a previous / current clock storage section 6381 and a clock selection section 6382.

[0109] The previous clock storage unit 632 can store the first master clock CK00 and the second master clock CK90 as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively, according to the comparison signal CMP. Preferably, at the end of the active period of the comparison signal CMP, that is, synchronously with the falling edge of the comparison signal CMP, the previous clock storage unit 632 can store the first master clock CK00 and the second master clock CK90 as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively.

[0110] The clock input unit 638 can selectively invert the first external clock CK00_EX and the second external clock CK90_EX based on the comparison signal CMP and the corresponding logic levels of the first preliminary clock CK00_S, the second preliminary clock CK90_S, the first internal clock CK00IN and the second internal clock CK90IN, so as to generate the first internal clock CK00IN and the second internal clock CK90IN.

[0111] The previous / current clock storage section 6381 included in the clock input unit 638 can store the corresponding logic levels of the first internal clock CK00IN, the second internal clock CK90IN, the first preliminary clock CK00_S, and the second preliminary clock CK90_S as the second selection signal SEL2<3:0> at the start of the activation period of the comparison signal CMP. More specifically, at the start of the activation period of the comparison signal CMP, the previous / current clock storage section 6381 can store the logic level of the first preliminary clock CK00_S and output the stored logic level as the first bit SEL2 of the second selection signal SEL2<3:0>. <0> It can store the logic level of the second preliminary clock CK90_S and output the stored logic level as the second bit SEL2 of the second selection signal SEL2<3:0>. <1> It can store the logic level of the first internal clock CK00IN and output the stored logic level as the third bit SEL2 of the second selection signal SEL2<3:0>. <2> It can also store the logic level of the second internal clock CK90IN and output the stored logic level as the fourth bit SEL2 of the second selection signal SEL2<3:0>. <3> .

[0112] The clock selection section 6382 included in the clock input unit 638 can selectively invert the first external clock CK00_EX and the second external clock CK90_EX in response to the second selection signal SEL2<3:0> to generate the first internal clock CK00IN and the second internal clock CK90IN. More specifically, the clock selection section 6382 can select one of the first external clock CK00_EX and the inverted first external clock CK00_EXB as the first internal clock CK00IN according to the second selection signal SEL2<3:0>, and select one of the second external clock CK90_EX and the inverted second external clock CK90_EXB as the second internal clock CK90IN according to the second selection signal SEL2<3:0>.

[0113] The clock sequence determination unit 634 can determine whether the transition order of the first internal clock CK00IN and the second internal clock CK90IN meets specific conditions based on the first preliminary clock CK00_S and the second preliminary clock CK90_S, and generate an output activation signal SEQ_ON during the activation period of the comparison signal CMP. Specific conditions may include the case where the first internal clock CK00IN transitions from logic low to logic high and then the second internal clock CK90IN transitions from logic low to logic high, and the case where the first internal clock CK00IN transitions from logic high to logic low and then the second internal clock CK90IN transitions from logic high to logic low. More specifically, the clock sequence determination unit 634 can generate a first selection signal SEL1<3:0> (see [reference]) by decoding the logic levels of the first preliminary clock CK00_S and the second preliminary clock CK90_S. Figure 11 According to the first selection signal SEL1<3:0>, one of the first internal clock CK00IN and the inverted first internal clock CK00INB is selected, and the selected clock is output as the first sequence determination signal CK00_SEL (see...). Figure 11 ), and selects one of the second internal clock CK90IN and the inverted second internal clock CK90INB according to the first selection signal SEL1<3:0>, and outputs the selected clock as the second sequence determination signal CK90_SEL (see Figure 11 Furthermore, the clock sequence determination unit 634 can generate the output activation signal SEQ_ON based on the comparison signal CMP, the first sequence determination signal CK00_SEL, and the second sequence determination signal CK90_SEL.

[0114] The output control unit 636 can latch the first internal clock CK00IN and the second internal clock CK90IN according to the output activation signal SEQ_ON, and output the first master clock CK00 and the second master clock CK90.

[0115] As described above, at the beginning of the activation period of the comparison signal CMP, the drive control circuit 630 according to this embodiment selectively inverts the first external clock CK00_EX and the second external clock CK90_EX to generate the first internal clock CK00IN and the second internal clock CK90IN. Therefore, when the phases of the first external clock CK00_EX and the second external clock CK90_EX do not have a preferred phase at the beginning of the activation period of the comparison signal CMP, the semiconductor device 100 according to this disclosure can selectively invert the first external clock CK00_EX and the second external clock CK90_EX to generate the first internal clock CK00IN and the second internal clock CK90IN with a preferred phase, instead of waiting until the first external clock CK00_EX and the second external clock CK90_EX have a preferred phase.

[0116] Furthermore, the drive control circuit 630 can control the second master clock CK90 to flip after the first master clock CK00 flips, thereby substantially maintaining the transition sequence of the first master clock CK00 and the second master clock CK90. Additionally, the drive control circuit 630 can control the logic levels of the first master clock CK00 and the second master clock CK90 to substantially remain at the end of the activation period of the comparison signal CMP. Therefore, the semiconductor device 100 according to this disclosure can control the first master clock CK00 and the second master clock CK90 to not flip simultaneously, thereby reducing the current consumed by unnecessary switching operations.

[0117] Figure 11 It is based on the embodiments of this disclosure. Figure 10 Detailed circuit diagram of the drive control circuit 630 in the middle. Figure 12 It is used to describe embodiments according to this disclosure. Figure 11 A diagram illustrating the operation of the drive control circuit 630.

[0118] exist Figure 11 The diagram shows a detailed circuit diagram of the preceding clock storage unit 632, clock input unit 638, clock sequence determination unit 634, and output control unit 636. Furthermore, in... Figure 11 The diagram shows a detailed circuit diagram of the previous / current clock storage section 6381 and the clock selection section 6382 included in the clock input unit 638.

[0119] The preceding clock storage unit 632 may include a first storage section 632A and a second storage section 632B. The first storage section 632A may store a first master clock CK00 at the end of the active period of the comparison signal CMP and output the stored first master clock CK00 as a first preliminary clock CK00_S. The second storage section 632B may store a second master clock CK90 at the end of the active period of the comparison signal CMP and output the stored second master clock CK90 as a second preliminary clock CK90_S. Preferably, each of the first storage section 632A and the second storage section 632B may be implemented as a D flip-flop.

[0120] The clock sequence determination unit 634 may include a logic decoder 6342, a first selector 6344, and an activation signal generation section 6346.

[0121] The logic decoder 6342 can generate the first selection signal SEL1<3:0> by decoding the logic levels of the first preliminary clock CK00_S and the second preliminary clock CK90_S. For example, Figure 12 As shown, when both the first preliminary clock CK00_S and the second preliminary clock CK90_S are at a logic low level, the logic decoder 6342 can generate a first selection signal SEL1<3:0> of "0001". When the first preliminary clock CK00_S is at a logic high level and the second preliminary clock CK90_S is at a logic low level, it can generate a first selection signal SEL1<3:0> of "0010". When the first preliminary clock CK00_S is at a logic low level and the second preliminary clock CK90_S is at a logic high level, it can generate a first selection signal SEL1<3:0> of "0100". And when both the first preliminary clock CK00_S and the second preliminary clock CK90_S are at a logic high level, it can generate a first selection signal SEL1<3:0> of "1000".

[0122] Additionally, the clock sequence determination unit 634 may further include first inverters INV1 to third inverters INV3. First inverter INV1 generates an inverted comparison signal CMPB by inverting the comparison signal CMP. Second inverter INV2 generates an inverted first internal clock CK00INB by inverting the first internal clock CK00IN. Third inverter INV3 generates an inverted second internal clock CK90INB by inverting the second internal clock CK90IN.

[0123] The first selector 6344 can select one of the first internal clock CK00IN and the inverted first internal clock CK00INB according to the first selection signal SEL1<3:0>, and output the selected clock as the first sequence determination signal CK00_SEL. It can also select one of the second internal clock CK90IN and the inverted second internal clock CK90INB according to the first selection signal SEL1<3:0>, and output the selected clock as the second sequence determination signal CK90_SEL. For example, as... Figure 12 As shown, the first selector 6344 can output the inverted first internal clock CK00INB and the inverted second internal clock CK90INB as the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL respectively, based on the first selection signal SEL1<3:0> of “0001”. The first selector 6344 can also output the first internal clock CK00INB and the inverted second internal clock CK90INB as the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL respectively, based on the first selection signal SEL1<3:0> of “0010”. Finally, the first selector 6344 can output the inverted first internal clock CK00INB and the second internal clock CK90INB as the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL respectively, based on the first selection signal SEL1<3:0> of “0100”. The first selector 6344 can output the first internal clock CK00IN and the second internal clock CK90IN as the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL respectively based on the first selection signal SEL1<3:0> of “1000”.

[0124] The activation signal generation section 6346 can activate the output activation signal SEQ_ON according to the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL during the activation period of the comparison signal CMP. The activation signal generation section 6346 can deactivate the output activation signal SEQ_ON at the end of the activation period of the comparison signal CMP, that is, according to the falling edge of the comparison signal CMP.

[0125] More specifically, the activation signal generation section 6346 may include a set signal generation section 6346A and an SR latch 636B.

[0126] The set signal generation section 6346A can generate a set signal S based on the comparison signal CMP, the first sequence determination signal CK00_SEL, and the second sequence determination signal CK90_SEL. Preferably, the set signal generation section 6346A can generate the set signal S by performing a logical AND operation on the comparison signal CMP, the first sequence determination signal CK00_SEL, and the second sequence determination signal CK90_SEL. That is, during the activation period of the comparison signal CMP, the set signal generation section 6346A can output a set signal S that is activated to a logic high level when both the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL are at a logic high level. The SR latch 6346B can generate an output activation signal SEQ_ON, which is activated according to the set signal S and deactivated according to the inverted comparison signal CMPB.

[0127] The previous / current clock storage section 6381 included in the clock input unit 638 may include a third storage section 6381A, a fourth storage section 6381B, a fifth storage section 6381C, and a sixth storage section 6381D. At the beginning of the activation period of the comparison signal CMP, the third storage section 6381A may store the first preliminary clock CK00_S and output the stored first preliminary clock CK00_S as the first bit SEL2 of the second selection signal SEL2<3:0>. <0> At the start of the activation period of the comparison signal CMP, the fourth storage section 6381B can store the second preliminary clock CK90_S and output the stored second preliminary clock CK90_S as the second bit SEL2 of the second selection signal SEL2<3:0>. <1> At the start of the activation period of the comparison signal CMP, the fifth storage section 6381C can store the first internal clock CK00IN and output the stored first internal clock CK00IN as the third bit SEL2 of the second selection signal SEL2<3:0>. <2> At the start of the activation period of the comparison signal CMP, the sixth storage section 6381D can store the second internal clock CK90IN and output the stored second internal clock CK90IN as the fourth bit SEL2 of the second selection signal SEL2<3:0>. <3> Preferably, each of the third storage portion 6381A, the fourth storage portion 6381B, the fifth storage portion 6381C, and the sixth storage portion 6381D can be implemented as a D flip-flop.

[0128] The clock selection section 6382 included in the clock input unit 638 may include a second selector 6383 and a fourth inverter INV4 to a seventh inverter INV7.

[0129] The fourth inverter INV4 generates the first clock bar CK00EB by inverting the first external clock CK00_EX, and the fifth inverter INV5 generates the first clock bar CK00ED by inverting the first clock bar CK00EB. The sixth inverter INV6 generates the second clock bar CK90EB by inverting the second external clock CK90_EX, and the seventh inverter INV7 generates the second clock bar CK90ED by inverting the second clock bar CK90EB.

[0130] The second selector 6383 can select one of the first clock bar CK00EB and the first clock CK00ED according to the second selection signal SEL2<3:0> and output the selected clock as the first internal clock CK00IN. It can also select one of the second clock bar CK90EB and the second clock CK90ED according to the second selection signal SEL2<3:0> and output the selected clock as the second internal clock CK90IN. For example, as... Figure 12As shown, the second selector 6383 can output the first clock CK00ED and the second clock CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of "1000". It can also output the first clock bar CK00EB and the second clock bar CK90EB as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of "0100". It can also output the first clock CK00ED and the second clock bar CK90EB as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of "0000". Furthermore, it can output the first clock bar CK00EB and the second clock CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of "1100". Furthermore, the second selector 6383 can output the first clock CK00ED and the second clock bar CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “1001”, the first clock bar CK00EB and the second clock CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “0101”, the first clock CK00ED and the second clock CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “0001”, and the first clock bar CK00EB and the second clock bar CK90EB as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “1101”.Furthermore, the second selector 6383 can output the first clock bar CK00EB and the second clock CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “1010”, the first clock bar CK00ED and the second clock bar CK90EB as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “0110”, the first clock bar CK00EB and the second clock bar CK90EB as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “0010”, and the first clock bar CK00ED and the second clock CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “1110”. Furthermore, the second selector 6383 can output the first clock bar CK00EB and the second clock bar CK90EB as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “1011”, the first clock CK00ED and the second clock CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “0111”, the first clock bar CK00EB and the second clock CK90ED as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “0011”, and the first clock bar CK00ED and the second clock bar CK90EB as the first internal clock CK00IN and the second internal clock CK90IN respectively according to the second selection signal SEL2<3:0> of “1111”.

[0131] The output control unit 636 may include a first latch 636A and a second latch 636B. The first latch 636A can latch a first internal clock CK00IN according to the output activation signal SEQ_ON, and use the latched clock output as the first master clock CK00. When the output activation signal SEQ_ON is activated, the first latch 636A can latch the first internal clock CK00IN and use the latched clock output as the first master clock CK00. When the output activation signal SEQ_ON is deactivated, the first latch 636A can substantially maintain the logic level of the currently latched first master clock CK00. The second latch 636B can latch a second internal clock CK90IN according to the output activation signal SEQ_ON, and use the latched clock output as the second master clock CK90. When the output activation signal SEQ_ON is activated, the second latch 636B can latch the second internal clock CK90IN and use the latched clock output as the second master clock CK90. When the output activation signal SEQ_ON is deactivated, the second latch 636B can essentially maintain the logic level of the currently latched second master clock CK90.

[0132] In the following text, reference will be made to Figures 10 to 13 To describe the operation of a semiconductor device according to embodiments of the present disclosure.

[0133] Figure 13 It is a waveform diagram used to describe the operation of a semiconductor device according to an embodiment of the present disclosure.

[0134] Reference Figure 13 During the first time period t1, since the detected voltage VFB is less than or equal to the reference voltage VREF, the voltage detection circuit 120 can be in a state where it outputs the comparison signal CMP at a logic high level. Since the first preliminary clock CK00_S and the second preliminary clock CK90_S, previously held at a logic low level by the clock storage unit 632, can receive the first external clock CK00_EX and the second external clock CK90_EX as the first internal clock CK00IN and the second internal clock CK90IN, respectively, when the first selection signal SEL1<3:0> is “0001” and the second selection signal SEL2<3:0> is “0100”, the clock input unit 638 can receive the first external clock CK00_EX and the second external clock CK90_EX as the first internal clock CK00IN and the second internal clock CK90IN, respectively. That is, the first external clock CK00_EX and the second external clock CK90_EX can be substantially the same as the first internal clock CK00IN and the second internal clock CK90IN, respectively. When the first selection signal SEL1<3:0> is “0001”, the operation of the clock sequence determination unit 634 is the same as... Figure 8 The operation of the clock sequence determination circuit 134 disclosed herein is essentially the same. Therefore, please refer to it together. Figure 8The clock sequence determination unit 634 can invert the first internal clock CK00IN according to the first selection signal SEL1<3:0> of "0001" and output the inverted first internal clock CK00INB as the first sequence determination signal CK00_SEL. It can also invert the second internal clock CK90IN according to the first selection signal SEL1<3:0> of "0001" and output the inverted second internal clock CK90INB as the second sequence determination signal CK90_SEL. When both the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL are at a logic high level, the output activation signal SEQ_ON can be activated according to the activated set signal S. The output control unit 636 can latch the first internal clock CK00IN and the second internal clock CK90IN according to the output activation signal SEQ_ON and output the latched clock as the first master clock CK00 and the second master clock CK90. Therefore, the charge pump circuit 110 can perform a pumping operation, thereby increasing the output voltage VOUT, i.e., the detection voltage VFB.

[0135] During the second time period t2, the detected voltage VFB becomes greater than the reference voltage VREF. The voltage detection circuit 120 outputs a comparison signal CMP at a logic low level. The clock sequence determination unit 634 deactivates the output activation signal SEQ_ON and outputs the deactivated output activation signal SEQ_ON, and the output control unit 636 does not toggle the first master clock CK00 and the second master clock CK90. Therefore, the charge pump circuit 110 does not perform pumping operation. At the end of the activation period of the comparison signal CMP, the previous clock storage unit 632 stores the first master clock CK00 and the second master clock CK90, which are at a logic high level, as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively. At this time, since the first preliminary clock CK00_S and the second preliminary clock CK90_S are at a logic high level, the clock sequence determination unit 634 can output the first internal clock CK00IN and the second internal clock CK90IN as the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL, respectively, according to the first selection signal SEL1<3:0> of "1000".

[0136] During the third time period t3, the detected voltage VFB becomes less than or equal to the reference voltage VREF. The voltage detection circuit 120 outputs the comparison signal CMP at a logic high level. At this time, since the first preliminary clock CK00_S and the second preliminary clock CK90_S remain essentially at a logic high level, the first external clock CK00_EX is at a logic low level, and the second external clock CK90_EX is at a logic high level, the previous / current clock storage section 6381 included in the clock input unit 638 can output the second selection signal SEL2<3:0> as "1011". Therefore, the clock selection section 6382 included in the clock input unit 638 can invert the first external clock CK00_EX and the second external clock CK90_EX to generate an inverted first internal clock CK00INB and an inverted second internal clock CK90INB.

[0137] Since the first preliminary clock CK00_S and the second preliminary clock CK90_S remain essentially at a logic high level, the clock sequence determination unit 634 can output the first internal clock CK00IN as the first sequence determination signal CK00_SEL, and output the second internal clock CK90IN as the second sequence determination signal CK90_SEL. That is, since the first preliminary clock CK00_S and the second preliminary clock CK90_S remain essentially at a logic high level, the clock sequence determination unit 634 can output the inverted first external clock CK00_EXB as the first sequence determination signal CK00_SEL, and output the inverted second external clock CK90_EXB as the second sequence determination signal CK90_SEL.

[0138] Furthermore, the clock sequence determination unit 634 activates the set signal S when both the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL are at logic high level, thereby activating the output activation signal SEQ_ON. At this time, even if the comparison signal CMP is activated, the output activation signal SEQ_ON may not be activated. Moreover, the output activation signal SEQ_ON can be activated when the transition order of the first internal clock CK00IN and the second internal clock CK90IN meets a specific condition, i.e., when both the first sequence determination signal CK00_SEL and the second sequence determination signal CK90_SEL are at logic high level.

[0139] The output control unit 636 can latch the first internal clock CK00IN and the second internal clock CK90IN according to the output activation signal SEQ_ON, and output the latched clock as the first master clock CK00 and the second master clock CK90.

[0140] The charge pump circuit 110 can perform a pumping operation, thereby increasing the output voltage VOUT, i.e., the detection voltage VFB.

[0141] In the fourth time period t4, the voltage detection circuit 120 outputs a comparison signal CMP at a logic low level, and the clock sequence determination unit 634 deactivates the output activation signal SEQ_ON. Furthermore, at the end of the activation period of the comparison signal CMP, the previous clock storage unit 632 stores the first master clock CK00 and the second master clock CK90, which are at a logic low level, as the first preliminary clock CK00_S and the second preliminary clock CK90_S, respectively. The clock sequence determination unit 634 can, according to the first selection signal SEL1<3:0> of "0001", invert the first internal clock CK00IN to output the inverted clock as the first sequence determination signal CK00_SEL, and invert the second internal clock CK90IN to output the inverted clock as the second sequence determination signal CK90_SEL.

[0142] As described above, the drive control circuit 630 of the semiconductor device 100 according to this disclosure can selectively invert the first external clock CK00_EX and the second external clock CK90_EX at the beginning of the activation period of the comparison signal CMP to generate the first internal clock CK00IN and the second internal clock CK90IN. Therefore, when the phases of the first external clock CK00_EX and the second external clock CK90_EX are not the desired phases at the beginning of the activation period of the comparison signal CMP, the drive control circuit 630 can selectively invert the first external clock CK00_EX and the second external clock CK90_EX to generate the first internal clock CK00IN and the second internal clock CK90IN with the desired phases, instead of waiting until the phases of the first external clock CK00_EX and the second external clock CK90_EX become the desired phases.

[0143] Furthermore, during the active period of the comparison signal CMP, the drive control circuit 630 can determine whether the transition sequence of the first internal clock CK00IN and the second internal clock CK90IN meets specific conditions based on the previously stored logic levels of the first preliminary clock CK00_S and the second preliminary clock CK90_S, and output the first master clock CK00 and the second master clock CK90. Additionally, the drive control circuit 630 can store the first master clock CK00 and the second master clock CK90 as the first preliminary clock CK00_S and the second preliminary clock CK90_S respectively at the end of the active period of the comparison signal CMP, thereby controlling the logic levels of the first master clock CK00 and the second master clock CK90 to remain substantially constant. Therefore, the semiconductor device 100 according to this disclosure can reduce the current consumed by unnecessary switching operations of the first master clock CK00 and the second master clock CK90.

[0144] While the technical spirit of this disclosure has been specifically described with reference to the above embodiments, it should be noted that the above embodiments are for description and not for limitation. Furthermore, those skilled in the art will understand that various embodiments can be made within the scope of the technical spirit of this disclosure and the appended claims.

[0145] For example, the location and type of the logic gates and transistors disclosed in the above embodiments can be implemented differently depending on the polarity of the input signal. Furthermore, these embodiments can be combined to form additional embodiments.

[0146] Cross-reference to related applications

[0147] This application claims priority to Korean Patent Application No. 10-2021-0102622, filed on August 4, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A charge pump circuit that generates an output voltage by pumping an input voltage according to a first master clock and a second master clock; A voltage detection circuit generates a comparison signal by comparing the output voltage with a reference voltage; as well as The drive control circuit, wherein the drive control circuit: At the start of the activation period of the comparison signal, the first external clock and the second external clock are selectively inverted according to the corresponding logic levels of the first preliminary clock and the second preliminary clock, as well as the first external clock and the second external clock, to generate the first internal clock and the second internal clock. During the activation period of the comparison signal, the first master clock and the second master clock are generated according to the first internal clock and the second internal clock, while controlling the transition sequence so that the second master clock transitions after the first master clock transitions. At the end of the active period of the comparison signal, the logic levels of the first master clock and the second master clock are stored as the first preliminary clock and the second preliminary clock, respectively.

2. The semiconductor device according to claim 1, wherein, The drive control circuit includes: A prior clock storage unit, wherein the prior clock storage unit stores the first master clock and the second master clock as the first preliminary clock and the second preliminary clock respectively according to the comparison signal; A clock input unit selectively inverts the first external clock and the second external clock according to the corresponding logic levels of the stored first preliminary clock and the second preliminary clock, as well as the stored first internal clock and the second internal clock, to generate the first internal clock and the second internal clock. A clock sequence determination unit determines whether the transition order of the first internal clock and the second internal clock satisfies a specific condition based on the first preliminary clock and the second preliminary clock, in order to generate an output activation signal during the activation period of the comparison signal; and An output control unit latches the first internal clock and the second internal clock according to the output activation signal to output the first master clock and the second master clock.

3. The semiconductor device according to claim 2, wherein, The prior clock storage unit includes: A first storage portion stores the first master clock as the first preliminary clock at the end of the activation period of the comparison signal; and The second storage section stores the second master clock as the second preliminary clock at the end of the activation period of the comparison signal.

4. The semiconductor device according to claim 2, wherein, The clock sequence determination unit includes: A logic decoder generates a first selection signal by decoding the logic levels of the first preliminary clock and the second preliminary clock; Selector, the selector: The first selection signal is used to select one of the first internal clock and the inverted first internal clock. The selected one of the first internal clock and the inverted first internal clock is output as the first sequence determination signal. Select one of the second internal clock and the inverted second internal clock according to the first selection signal, and Output the selected one of the second internal clock and the inverted second internal clock as the second sequence determination signal; and The activation signal generation section includes: During the activation period of the comparison signal, the output activation signal is activated according to the first sequence determination signal and the second sequence determination signal; and The output activation signal is deactivated at the end of the activation period of the comparison signal.

5. The semiconductor device according to claim 4, wherein, The activation signal generation section includes: A set signal generation section, wherein the set signal generation section generates a set signal according to the first sequence determination signal and the second sequence determination signal during the activation period of the comparison signal; and An SR latch generates the output activation signal, which is activated according to the set signal and deactivated at the end of the activation period of the comparison signal.

6. The semiconductor device according to claim 2, wherein, The clock input unit includes: The clock selection section, the clock selection section: In response to a second selection signal, the first external clock and the second external clock are selectively inverted to generate the first internal clock and the second internal clock; and The previous / current clock storage section stores the corresponding logic levels of the first internal clock and the second internal clock, as well as the first preliminary clock and the second preliminary clock, as the second selection signal at the start time of the activation period of the comparison signal.

7. The semiconductor device according to claim 6, wherein, The previous / current clock storage portion includes: The third storage section stores the first preliminary clock as the first bit of the second selection signal at the start time of the activation period of the comparison signal, and outputs the first bit of the second selection signal. The fourth storage section stores the second preliminary clock as the second bit of the second selection signal at the start time of the activation period of the comparison signal, and outputs the second bit of the second selection signal; The fifth storage section stores the first internal clock as the third bit of the second selection signal at the start time of the activation period of the comparison signal, and outputs the third bit of the second selection signal; and The sixth storage section stores the second internal clock as the fourth bit of the second selection signal at the start time of the activation period of the comparison signal, and outputs the fourth bit of the second selection signal.

8. The semiconductor device according to claim 6, in, The clock selection section selects one of the first external clock and the inverted first external clock as the first internal clock according to the second selection signal, and The second internal clock is selected from the second external clock and the inverted second external clock according to the second selection signal.

9. The semiconductor device according to claim 2, wherein, The output control unit includes: A first latch, wherein the first latch latches the first internal clock according to the output activation signal, and uses the latched clock as the first master clock; and The second latch latches the second internal clock according to the output activation signal, and uses the latched clock as the second master clock.

10. The semiconductor device according to claim 1, wherein, The charge pump circuit includes at least two pump stages and generates the output voltage in the following manner: The odd-numbered pump stages are driven according to the first master clock and the first sub-clock, which is the inverted signal of the first master clock. as well as The even-numbered pump stages are driven according to the second master clock and the second sub-clock, which is the inverted signal of the second master clock.

11. The semiconductor device according to claim 1, wherein, The phase difference between the first master clock and the second master clock is 90°.

12. A method of operating a semiconductor device, the method comprising the following steps: The output voltage is generated by pumping the input voltage according to the first master clock and the second master clock; A comparison signal is generated by comparing the output voltage with a reference voltage; At the start of the activation period of the comparison signal, the first external clock and the second external clock are selectively inverted to generate the first internal clock and the second internal clock. During the activation period of the comparison signal, an output activation signal is generated by determining whether the second internal clock changes after the first internal clock transitions, based on the logic levels of the first and second preliminary clocks. The first master clock and the second master clock are output by latching the first internal clock and the second internal clock according to the output activation signal; as well as At the end of the active period of the comparison signal, the first master clock and the second master clock are stored as the first preliminary clock and the second preliminary clock, respectively.

13. The method according to claim 12, wherein, Based on the corresponding logic levels of the first preliminary clock and the second preliminary clock, as well as the first external clock and the second external clock, the first external clock and the second external clock are selectively inverted to generate the first internal clock and the second internal clock.

14. The method according to claim 13, wherein, The step of determining how to generate the output activation signal includes the following steps: A first selection signal is generated by decoding the logic levels of the first preliminary clock and the second preliminary clock. Select one of the first internal clock and the inverted first internal clock according to the first selection signal; Output the selected one of the first internal clock and the inverted first internal clock as the first sequence determination signal; Select one of the second internal clock and the inverted second internal clock according to the first selection signal; Output the selected one of the second internal clock and the inverted second internal clock as the second sequence determination signal; and During the activation period of the comparison signal, the output activation signal is generated according to the first sequence determination signal and the second sequence determination signal.

15. The method according to claim 14, wherein, The step of generating the output activation signal based on the first sequence determination signal and the second sequence determination signal includes the following steps: During the activation period of the comparison signal, a set signal is generated based on the first sequence determination signal and the second sequence determination signal; The output activation signal is activated according to the set signal; and The output activation signal is deactivated at the end of the activation period of the comparison signal.

16. The method according to claim 13, wherein, The selective inversion step includes the following steps: In response to a second selection signal, the first external clock and the second external clock are selectively inverted to generate the first internal clock and the second internal clock; and At the start time of the activation period of the comparison signal, the corresponding logic levels of the first internal clock and the second internal clock, as well as the first preliminary clock and the second preliminary clock, are stored as the second selection signal.

17. The method according to claim 16, wherein, The step of selectively inverting the first external clock and the second external clock in response to the second selection signal includes the following steps: The first internal clock is selected as either the first external clock or the inverted first external clock according to the second selection signal; and The second internal clock is selected from the second external clock and the inverted second external clock according to the second selection signal.

18. The method according to claim 12, wherein, The steps for generating the output voltage include the following: The odd-numbered pump stages are driven according to the first master clock and the first sub-clock, which is the inverted signal of the first master clock; and The even-numbered pump stages are driven according to the second master clock and the second sub-clock, which is the inverted signal of the second master clock.

19. The method according to claim 12, wherein, The phase difference between the first master clock and the second master clock is 90°.

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