Memory devices and integrated circuits

Abstract

The present disclosure provides a memory device and integrated circuit including a computer readable medium for managing page buffer circuits in a memory device. One aspect of the present disclosure is a memory device including a memory array, memory cell lines coupled to respective lines of memory cells, and page buffer circuits having page buffers coupled to the memory cell lines. Each page buffer includes a sense latch circuit and a storage latch circuit. The sense latch circuit includes a sense transistor coupled to a sense node and at least one sense latch cell. The storage latch circuit includes at least one storage latch cell having a third node and a fourth node coupled to the sense node, and a gate terminal coupled to the sense transistor. A second terminal of the sense transistor is coupled to a ground terminal.

Description

Technical Field

[0001] The present disclosure relates to data storage technology, and more particularly to a memory device and an integrated circuit. Background Art

[0002] Integrated circuit memory devices are becoming increasingly smaller and faster. One limitation on the size of memory devices is the size of the sense capacitors in the page buffer circuits. To sense the data stored in the memory devices, the sense capacitors must have a large capacitance, resulting in a large area. Therefore, a page buffer circuit that provides a large and stable capacitance while maintaining a small footprint is highly desirable.

[0003] Public content

[0004] The present disclosure describes systems and techniques for managing a page buffer in a memory device, which may be a non-volatile memory such as flash memory.

[0005] One aspect of the present disclosure is a memory device comprising: a memory array comprising a plurality of memory cells; a plurality of memory cell lines respectively connected to a plurality of lines of memory cells in the memory array; and a page buffer circuit comprising a plurality of page buffers coupled to the memory cell lines. Each page buffer comprises a sense latch circuit and a storage latch circuit. The sense latch circuit comprises a sense transistor, wherein the sense transistor is coupled to a sense node and at least one sense latch unit, the sense latch unit having a first node coupled to the sense node and a second node coupled to the sense transistor. The storage latch circuit comprises at least one storage latch unit, wherein the storage latch unit comprises a third node and a fourth node, the third node and the fourth node being coupled to the sense node. The sense transistor comprises a first terminal, a gate terminal, and a second terminal. The first terminal is coupled to the second node of the at least one sense latch unit, the gate terminal is coupled to the sense node and the third and fourth nodes of the at least one storage latch unit, and the second terminal is coupled to ground.

[0006] In some embodiments, at least one sensing latch unit includes: a first latch including a first inverter; a first latch control circuit coupled to the first latch and a first terminal of a sensing transistor; and at least one storage latch unit includes: a second latch including a second inverter; and a second latch control circuit coupled to the second latch and a gate terminal of the sensing transistor.

[0007] In some embodiments, the second latch control circuit includes a first control transistor and a second control transistor. Source terminals of the first control transistor and the second control transistor are coupled to the sensing node and the gate terminal of the sensing transistor.

[0008] In some embodiments, each sensing latch unit includes a first coupling circuit and a first latch. The first coupling circuit is coupled to the sensing node. Each storage latch unit further includes a second coupling circuit and two latches. The second coupling circuit is coupled to the sensing node.

[0009] In some embodiments, each page buffer further includes a pre-charge circuit coupled to the sensing node and configured to pre-charge the sensing node during a pre-charge phase, and a bit line control circuit including a first control node and a second control node. The first control node is coupled to a bit line of one of the memory cells, and the second control node is coupled to the sensing node. The bit line control circuit is configured to charge the bit line during the pre-charge phase, and discharge the bit line during a discharge phase after the pre-charge phase by turning on the sensing node and the bit line to provide a sensing current to the one of the memory cells.

[0010] In some embodiments, the page buffer is configured to disconnect the bit line from the sensing node during the pre-charge phase, and turn on the sensing node during the discharge phase.

[0011] In some embodiments, the storage latch circuit is configured to turn on one or more latch control circuits of the at least one storage latch unit to update the sensing results of one or more latches of the at least one storage latch unit.

[0012] In some embodiments, the number of sensing latch units in the sensing latch circuit and the number of storage latch units in the storage latch circuit are associated with the memory type of the memory cells.

[0013] In some embodiments, the number of storage latch units in the storage latch circuit is determined by the number of storable bits of the memory type.

[0014] In some embodiments, the sensing latch circuit and the storage latch circuit are configured to include one sensing latch unit and one storage latch unit when the memory type of the memory cells is Single Level Cell (SLC), include one sensing latch unit and two storage latch units when the memory type of the memory cells is Multi Level Cell (MLC), include two sensing latch units and three storage latch units when the memory type of the memory cells is Triple Level Cell (TLC), and include two sensing latch units and four storage latch units when the memory type of the memory cells is Quad-level cells (QLC).

[0015] In some embodiments, the storage latch circuit does not include a transistor that is substantially identical to the sensing transistor.

[0016] In some embodiments, the sensing latch circuit includes one or more transistors substantially identical to the sensing transistor. The sensing latch circuit includes a plurality of sensing latch units, and the number of the one or more transistors is smaller than the number of the sensing latch units.

[0017] Another aspect of the present disclosure is an integrated circuit comprising a sense latch circuit and a storage latch circuit. The sense latch circuit comprises: a sense transistor coupled to a sense node; at least one sense latch unit comprising a first node and a second node, wherein the first node is coupled to the sense node and the second node is coupled to the sense transistor. The storage latch circuit comprises: at least one storage latch unit comprising a third node and a fourth node, wherein the third node and the fourth node are coupled to the sense node. The sense transistor comprises: a first terminal coupled to the second node of the at least one sense latch unit; a second terminal coupled to ground; and a gate terminal coupled to the sense node and the third and fourth nodes of the at least one storage latch unit.

[0018] In some embodiments, each sensing latch unit includes a first latch including a first inverter and a first latch control circuit coupled to the first latch and a first terminal of the sensing transistor. Each storage latch unit includes a second latch including a second inverter and a second latch control circuit coupled to the second latch and a gate terminal of the sensing transistor.

[0019] In some embodiments, the first latch control circuit includes a first transistor for receiving a set signal and a second transistor for receiving a reset signal.

[0020] In some embodiments, each sensing latch unit includes a first coupling circuit coupled to the sensing node and the first latch, and each storage latch unit includes a second coupling circuit coupled to the sensing node and the second latch.

[0021] In some embodiments, the sensing latch unit includes a plurality of sensing latch units, each of which includes a first node and a second node. The first node is coupled to the sensing node, and the second node is coupled to the drain terminal of the sensing transistor. The storage latch unit includes a plurality of storage latch units, each of which includes a third node and a fourth node. The third node is coupled to the sensing node, and the fourth node is coupled to the gate terminal of the sensing transistor.

[0022] In some embodiments, the sensing latch circuit includes at least one sensing transistor, and the at least one storage latch unit does not include a transistor substantially identical to the sensing transistor.

[0023] In some embodiments, the sensing latch circuit and the storage latch circuit are configured to have an equivalent capacitance associated with a gate capacitance associated with the sensing transistor and one or more junction capacitances associated with the transistors in the sensing latch circuit and the storage latch circuit.

[0024] In some embodiments, equivalent capacitance is associated with one or more metal wirings in the sensing latch circuit and the storage latch circuit.

[0025] In some embodiments, the gate capacitance has a larger capacitance variation closer to the threshold voltage than the junction capacitance.

[0026] In some embodiments, a precharge circuit and a bit line control circuit are further included. The precharge circuit is coupled to the sensing node and is configured to precharge the sensing node during a precharge phase. The bit line control circuit includes a first control node and a second control node. The first control node is coupled to a bit line in a memory cell, and the second control node is coupled to the sensing node. The bit line control circuit is configured to: precharge the bit line during the precharge phase; and, in a discharge phase following the precharge phase, discharge the sensing node by conducting the sensing node and the bit line to provide a sensing current to the memory cell.

[0027] In some embodiments, the bit line control circuit is configured to disconnect the bit line from the sensing node during the precharge phase.

[0028] In some embodiments, the sense latch circuit is configured to: when a memory cell stores a 0 bit, a sense voltage on a sense node is greater than a threshold value, and a sense transistor is turned on to change the bit value latched by the at least one sense latch unit to 0; and when a memory cell stores a 1 bit, a sense voltage on the sense node is less than or equal to a threshold value, and the sense transistor is turned off to maintain the bit value latched by the at least one sense latch unit at 1.

[0029] In some embodiments, the storage latch circuit is configured to: direct one or more latch control circuits in at least one storage latch unit to update sensing results of one or more latches in at least one storage latch unit.

[0030] In some embodiments, the sensing latch unit includes a first type latch and the storage latch unit includes a second type latch, where the first type latch is different from the second type latch.

[0031] In some embodiments, one of the first type and the second type of latch is a triple-state latch or a fighting latch.

[0032] Another aspect of the present disclosure is an integrated circuit comprising a first latch circuit and a second latch circuit. The first latch circuit comprises a sensing transistor and one or more first latch units. The sensing transistor is coupled to a sensing node, and the first latch unit is coupled to the sensing transistor. The second latch circuit comprises one or more second latch units. Each second latch unit is identical to a first latch unit. The sensing transistor differs from the transistors in the second latch circuit in that the gate terminal of the sensing transistor is coupled to the sensing node and serves as a gate capacitor.

[0033] In some embodiments, the integrated circuit further includes a third circuit configured to: precharge a sense node and a bit line, respectively, in a first phase, wherein the bit line is coupled to a memory cell in the memory device and is configured to disconnect the sense node; and, in a second phase following the first phase, discharge a sense voltage at the sense node based on an equivalent capacitance by connecting the sense node to the bit line, thereby generating a sense current in the memory cell through the bit line. The equivalent capacitance is based on a gate capacitance associated with the sense transistor. The equivalent capacitance is also based on one or more junction capacitances associated with multiple transistors in the first latch unit and the second latch unit. The total capacitance of the junction capacitance is substantially greater than the capacitance of the gate capacitance. The first latch circuit is configured to update data latched by the first latch circuit based on the discharged sense voltage at the sense node after the second phase. The second latch circuit is configured to turn on at least one of the second transistors to update the data latched by the first latch circuit to at least one latch in the second latch circuit.

[0034] In some embodiments, the overall capacitance of the junction capacitance is substantially greater than the capacitance of the gate capacitance.

[0035] In some embodiments, the first latch unit is configured to: turn on the sensing transistor to change the bit value latched to 0 by the sensing latch when the memory cell stores a bit 0 and the sensing voltage value of the sensing node is greater than a threshold voltage; or turn off the sensing transistor to maintain the bit value latched to 1 by the sensing latch unit when the memory cell stores a bit 1 and the sensing voltage value of the sensing node is less than or equal to the threshold voltage.

[0036] Another aspect of the present disclosure is a method for managing a page buffer in a memory device, comprising the following steps: precharging a bit line coupled to a memory cell in the memory device; precharging a sensing node in the page buffer, wherein the page buffer comprises a sensing latch circuit and a storage latch circuit, the sensing latch circuit comprising a sensing transistor coupled to the sensing node and at least one sensing latch unit, the sensing latch unit having a first node coupled to the sensing node and a second node coupled to the first end of the sensing transistor, the storage latch circuit comprising at least one storage latch unit, the storage latch unit having a third node and a fourth node coupled to the sensing node and the gate end of the sensing transistor, the second end of the sensing node being coupled to ground; turning on the bit line and the sensing node to discharge a sensing voltage on the sensing node to provide a sensing current to the memory cell through the bit line; and updating data latched by the sensing latch circuit based on the sensing voltage discharged on the sensing node.

[0037] In some embodiments, a method for updating data latched by a sense latch circuit based on a sense voltage discharged on a sense node includes: turning on a sense transistor to change the bit value latched at 0 by at least one sense latch unit when a memory cell stores a bit value of 0 and a sense voltage on the sense node is greater than a threshold voltage; or turning off the sense transistor to maintain the bit value latched at 1 by the sense latch unit when a memory cell stores a bit value of 1 and the sense voltage on the sense node is greater than or equal to the threshold voltage.

[0038] In some embodiments, the method further includes turning on one or more latch control circuits in the storage latch unit to write the sensing result into one or more storage latch units in the storage latch unit.

[0039] Another aspect of the present disclosure is a flash memory comprising a page buffer circuit and a bit line. The page buffer circuit comprises a subcircuit and a precharge circuit. The subcircuit comprises a clamp circuit coupled between a bit line node and a sensing terminal (or sensing node). The precharge circuit is coupled between a power supply node and the sensing terminal. The clamp circuit is used to stabilize the current flowing through the clamp circuit. The precharge circuit is used to provide a precharge voltage to the sensing terminal. The power supply node is coupled to a power supply. The bit line node is coupled to the bit line. The page buffer circuit further comprises a sensing latch circuit and a storage latch circuit. The sensing latch circuit comprises a sensing transistor and a first latch unit. The storage latch circuit comprises a second latch unit.

[0040] In some embodiments, the first latch unit includes a latch circuit, a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the latch circuit is coupled between a data line node and a data line inverting node. The first transistor is coupled between a switch node and a data line inverting node. The gate of the first transistor is used to receive a first control signal. The second transistor is coupled between the switch node and the data line node. The gate of the second transistor is used to receive a second control signal. The third transistor is coupled between a sensing connection node and a connection node. The gate of the third transistor is used to receive a third control signal. The fourth transistor is coupled between the connection node and a ground terminal. The gate of the fourth transistor is coupled to the data line node. The sensing transistor is coupled between the switch node and the ground terminal. The gate of the sensing transistor is coupled to a sensing connection node. The sensing connection node is coupled to a sensing terminal. The sensing latch circuit is used to discharge a voltage on the sensing terminal according to the third control signal and a signal on the data line node, and to sense the voltage on the sensing terminal through the sensing transistor.

[0041] In some embodiments, the second latch unit includes a latch circuit, a first transistor, a second transistor, a third transistor, and a fourth transistor. The latch circuit is coupled between a data line node and a data line inverting node. The first transistor is coupled between a switching node and a data line inverting node. The gate of the first transistor is used to receive a first control signal. The second transistor is coupled between the switching node and the data line node. The gate of the second transistor is used to receive a second control signal. The third transistor is coupled between a sensing connection node and a connecting node, and the sensing connection node is coupled to the switching node. The gate of the third transistor is used to receive a third control signal. The fourth transistor is coupled between the connecting node and a ground terminal. The gate of the fourth transistor is coupled to the data line node. The switching node of the second latch unit is coupled to the gate of the sensing transistor. The storage latch circuit is used to latch the voltage of the sensing terminal to a preset level.

[0042] Implementations of the above-mentioned technology include methods, systems, circuits, computer program products, and computer-readable storage media. In one embodiment, a method can be executed in a non-volatile memory, and the method can include the above-mentioned actions, for example, actions for managing a page buffer circuit. In another embodiment, a computer program product as described above can be appropriately implemented in a non-transitory machine-readable medium storing instructions executed by one or more processors. The above-mentioned actions can be performed by instructions configured in one or more processors. The above-mentioned computer-readable medium is used to store instructions, and when executed by one or more processors, these instructions are used to cause one or more processors to perform the above-mentioned actions.

[0043] The technology can be implemented by a circuit or device having multiple latches of any type and capable of performing various functions. The latches can be divided into two or more groups, each group being configured to perform a corresponding function. These groups can use different types of latches, for example, tri-state latches or inhibiting latches. The technology of the present disclosure can reduce device area (for example, the size of page buffer circuits and / or storage devices), minimize capacitor variations (for example, through gate capacitance), reduce power consumption (for example, through large area capacitance), and improve device performance (for example, sensing accuracy).

[0044] For example, a page buffer in a memory device includes multiple latches configured to implement operations including read, write, and erase functions. Rather than treating all latches as identical, the present disclosure allows latches in a page buffer to be categorized into at least two types of circuits: a sense latch circuit and a storage latch circuit. The sense latch circuit includes a sense transistor having a gate terminal. The gate terminal is coupled to a sense node for sensing data via a bit line. The storage latch circuit does not perform sensing but only stores data from a cache data latch (CDL) circuit or a sense latch circuit. Therefore, the storage latch circuit may not include a sense transistor. Because the gate capacitance associated with the sense transistor has a large capacitance variation near the threshold voltage, minimizing the number of sense transistors can significantly reduce capacitance variation, thereby increasing the stability of the capacitance at the sense node. For example, due to different PVT (process-voltage-temperature) effects, sensing accuracy and / or sensing yield can be improved.

[0045] The present disclosure can be implemented using any type of storage transistor (or storage cell), any type of metal oxide silicon (MOS) transistor (e.g., n-channel and / or p-channel transistor), any type of bipolar junction transistor (BJT), and any type of operational amplifier. These techniques can be applied to various types of storage systems, such as two-dimensional (2D) storage systems or three-dimensional (3D) storage systems. These techniques can be applied to various memory types, such as SLC devices, MLC devices such as two-level cell devices (2-level), or TLC devices. These techniques can be applied to various types of non-volatile storage devices, such as static random access memory (SRAM), dynamic random access memory (DRAM), cache memory (e.g., NOR and / or NAND), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), and the like. In addition, these techniques can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), solid-state drives (SSDs), embedded systems, and the like.

[0046] The following description and accompanying drawings illustrate the details of the embodiments of the present disclosure. The embodiments, accompanying drawings and claims clearly present the various features, viewpoints and advantages of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1A is a schematic diagram of a memory system according to some embodiments of the present disclosure.

[0048] Figure 1B Schematic diagram of a two-dimensional (2D) memory according to some embodiments of the present disclosure.

[0049] Figure 1C Schematic diagram of a three-dimensional (3D) memory according to some embodiments of the present disclosure.

[0050] Figure 2 FIG. 1 is a schematic diagram of a page buffer circuit having multiple page buffers according to some embodiments of the present disclosure.

[0051] Figure 3 FIG. 1 is a schematic diagram of the relationship between the voltage-capacitance of the junction capacitance and the gate capacitance in some embodiments according to the present disclosure.

[0052] Figure 4 FIG. 1 is a schematic diagram of a page buffer having a sensing latch circuit and a storage latch circuit according to some embodiments of the present disclosure.

[0053] Figure 5 Schematic diagram of a latch unit according to some embodiments of the present disclosure.

[0054] Figures 6A to 6C for Figure 5 Schematic diagram of the page buffer at different stages.

[0055] Figure 7 According to some embodiments of the present disclosure, Figures 6A to 6C Schematic diagram of voltage changes at different nodes of the page buffer at different stages.

[0056] Figure 8 The present invention is a flow chart of a method for managing a page buffer of a memory device according to some embodiments of the present disclosure.

[0057] Description of Reference Numerals

[0058] 100: System

[0059] 110: Device

[0060] 112: Device controller

[0061] 113: Processor

[0062] 114: Internal memory

[0063] 116: Memory

[0064] 120: Host

[0065] 140: Two-dimensional storage block

[0066] 141: Memory unit

[0067] 142-150: Transistors

[0068] 152: Storage Paging

[0069] 154: Storage Serial

[0070] 156: Serial select line

[0071] 157: Memory unit

[0072] 158: Ground selection line

[0073] 159: Common source line

[0074] 200: Memory device

[0075] 202: Memory interface

[0076] 204: Control Logic Circuit

[0077] 206: X-Decoder

[0078] 208: Data buffer

[0079] 210: Memory Array

[0080] 215: bit line

[0081] 220: Page buffer circuit

[0082] 222: Page Buffer

[0083] 230: Cache data latch circuit

[0084] 300: Voltage and Capacitance Relationship Diagram

[0085] 302: Curve

[0086] 304: Curve

[0087] 306: Line

[0088] 402: Discharge circuit

[0089] 406: Junction capacitance

[0090] 408: Gate capacitance

[0091] 410: Pre-charge circuit

[0092] 420: Bit line control circuit

[0093] 430: Inductive latch circuit

[0094] 440a-460c: Latch unit

[0095] 450: Storage latch circuit

[0096] 410: Pre-charge circuit

[0097] 420: Bit line control circuit

[0098] 430: Inductive latch circuit

[0099] 450: Storage latch circuit

[0100] 500: Latch unit

[0101] 502: First node

[0102] 504: Second Node

[0103] 510: Coupling circuit

[0104] 520: Latch

[0105] 522: First inverter

[0106] 524: Second inverter

[0107] 530: Latch control circuit

[0108] SST: Serial Select Transistor

[0109] SSL: Serial Select Line

[0110] GSL: Ground Select Line

[0111] CSL: Common Source Line

[0112] BL0-BL n : Bit line

[0113] WL0-WL n :Word line

[0114] V Th : Threshold voltage

[0115] VDDI: supply voltage

[0116] POS: Signal

[0117] STB: Signal

[0118] PRE: Signal

[0119] PSEN: signal

[0120] DISCH: Signal

[0121] BLC1-BLC3: Signal

[0122] R: Signal

[0123] 802-808: Steps DETAILED DESCRIPTION

[0124] The following drawings illustrate various embodiments of the present disclosure. For clarity, many practical details will be included in the following description. However, it should be understood that these practical details should not be construed as limiting the present disclosure. In other words, these practical details are not essential to some embodiments of the present disclosure. Furthermore, to simplify the drawings, some commonly used structures and components are shown in simplified schematic form.

[0125] As used herein, when an element is referred to as being "connected" or "coupled," it may refer to being "electrically connected" or "electrically coupled." "Connected" or "coupled" may also refer to the coordinated operation or interaction between two or more elements. Furthermore, while terms such as "first," "second," etc. are used herein to describe different elements, these terms are intended solely to distinguish between elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms are not intended to specifically designate or imply a sequence or order, nor are they intended to limit this disclosure.

[0126] Figure 1A 1 is a schematic diagram for illustrating system 100. System 100 includes a device 110 and a host 120. Device 110 includes a device controller 112 and a memory 116. Device controller 112 includes a processor 113 and an internal memory 114. In some embodiments, device 110 includes multiple memories 116 coupled to device controller 112.

[0127] In some embodiments, device 110 is a storage device. For example, device 110 can be an embedded multimedia card (EMMC), a secure digital card (SD), a solid-state drive (SSD), or any other suitable storage medium. In some embodiments, device 110 is a smartwatch, a digital camera, or a media player. In some embodiments, device 110 is a client device coupled to host 120. For example, device 110 is an SD card installed in host 120, such as a digital camera or a media player.

[0128] Device controller 112 is a general-purpose microprocessor or an application-specific microcontroller. In some embodiments, device controller 112 is a memory controller for device 110. The following description is based on various techniques implemented when device controller 112 is a memory controller. However, some of the techniques described below are also applicable to other situations where device controller 112 is not a memory controller.

[0129] Processor 113 is used to execute instructions and process data. Instructions include firmware instructions and / or other program instructions, which are stored as firmware code and / or other program code in auxiliary memory. Data includes program data corresponding to the firmware and / or other programs executed by the processor, as well as other appropriate data. In some embodiments, processor 113 is a general-purpose microprocessor or a dedicated microcontroller. Processor 113 also serves as a central processing unit (CPU).

[0130] Processor 113 processes (accesses) instructions and data from internal memory 114. In some embodiments, internal memory 114 is static random access memory (SRAM) or dynamic random access memory (DRAM). For example, in some embodiments, when device 110 is an eMMC, SD card, or smartwatch, internal memory 114 is SRAM. In some embodiments, when device 110 is a digital camera or media player, internal memory 114 is DRAM.

[0131] In some embodiments, the internal memory is a cache memory included in the device controller 112, such as Figure 1A The internal memory 114 is used to store instruction codes and / or data required by the processor 113 during operation. The instruction codes correspond to instructions executed by the processor 113.

[0132] Device controller 112 transfers instruction codes and / or data from memory 116 to internal memory 114. Memory 116 may be a semiconductor device. In some embodiments, memory 116 is a non-volatile memory for long-term storage of instructions and / or data, such as a NAND cache device or other suitable non-volatile memory. In embodiments where memory 116 is a NAND cache, device 110 is a cache device, such as a memory card, and device controller 112 is a NAND cache controller. For example, in some embodiments, when device 110 is an eMMC or SD card, memory 116 is a NAND cache; in some embodiments, when device 110 is a digital camera, memory 116 is an SD card. In some embodiments, when device 110 is a media player, memory 116 is hardware.

[0133] The memory 116 includes a plurality of memory blocks. The memory 116 can be a two-dimensional memory including two-dimensional memory blocks. The memory 116 can also be a three-dimensional memory including three-dimensional memory blocks.

[0134] Figure 1B FIG2 shows a schematic diagram of a two-dimensional memory block 140 according to some embodiments of the present disclosure, when the memory 116 is a two-dimensional memory. The memory block 140 includes memory cells 141. The memory cells 141 are connected in series and coupled to a plurality of bit lines (BL) BL0, BL1, ..., BL n-1 and BL n To form a plurality of memory strings 144. The memory cells 141 are further coupled to a plurality of word lines (WL) WL0, WL1, ..., WL n-1 and WL n To form a plurality of storage pages 142 .

[0135] Each memory cell in a memory block includes a transistor structure having a gate, a drain, a source, and a channel defined by the drain and source. Each memory cell is located at the intersection of a word line and a bit line, with the gate connected to the word line, the drain connected to the bit line, and the source connected to the source line, thereby sequentially connecting the memory cells to ground. In some embodiments, the gate of a flash memory cell has a dual-gate structure, including a control gate and a floating gate, where the floating gate is suspended between two oxide layers to trap electrons used to program the cell.

[0136] Each memory cell in a memory block includes a transistor structure having a gate, a drain, a source, and a channel defined by the drain and source. Each memory cell is located at the intersection of a word line and a bit line, with the gate connected to the word line, the drain connected to the bit line, and the source connected to the source line, thereby sequentially connecting the memory cells to ground. In some embodiments, the gate of a flash memory cell has a dual-gate structure, including a control gate and a floating gate, where the floating gate is suspended between two oxide layers to trap electrons used to program the cell.

[0137] The storage string 144 includes a plurality of memory cells 141, a string select transistor (SST) 143, and a ground select transistor (GST) 145 connected in series. The gate of the string select transistor 143 is connected to a string select line (SSL) 146. The gates of the string select transistors 143 in different storage strings are connected to the same string select line (SSL). The gates of the memory cells 141 are connected to word lines WL0, WL1, …, WLn-1, WLn, respectively. The storage string 144 or the memory cell 141 is connected to a common source line (CSL) 149 through the ground select transistor 145 (GST). The common source line (CSL) 149 can be coupled to a ground. The gate of the ground select transistor (GST) 145 is connected to a ground select line (GSL) 148. The gates of the ground select transistors (GST) 145 in different storage strings 144 are connected to the same ground select line (GSL) 148.

[0138] The storage page 142 includes a plurality of memory cells 141. The gates of the memory cells 141 in the storage page 142 are connected to word lines (WL) in series, respectively. When an input voltage is applied to a word line, the input voltage is also applied to the memory cells 141 in the storage page 142. In a read operation, to read a storage page 142 of the storage block 140, a lower voltage is applied to the word line corresponding to the specific storage page 142. Meanwhile, a higher voltage is applied to other storage pages in the storage block 140.

[0139] Figure 1C A schematic diagram of a 3D storage block 150 is shown, when the memory 116 (as shown) is a 3D memory, according to some embodiments of the present disclosure. Figure 1A A schematic diagram of a 3D storage block 150 is shown, when the memory 116 (as shown) is a 3D memory, according to some embodiments of the present disclosure. Figure 1B The memory cells 157 are arranged in three dimensions, for example, XYZ coordinate system, and coupled to a plurality of word lines to form a plurality of storage pages (conductive layers or word line layers) 152, and coupled to a plurality of bit lines to form a plurality of storage strings 154. The storage pages 152 can be layers in the XY plane, and the memory cells 157 on the same layer can be coupled to one word line and have the same voltage. Each storage page 152 can be connected to a respective contact pad in a driving circuit, for example, an X-decoder (or scan driver).

[0140] Memory string 154 includes a plurality of memory cells 157 vertically connected in series along the Z direction. Each memory cell can be configured as a string select transistor SST coupled to a string select line (SSL) 156, and a memory cell can be configured as a ground select transistor GST coupled to a ground select line (GSL) 158. Memory string 154 is connected to one or more drivers, such as a data driver. The memory string 154 of memory cells 157 is connected to a common source line (CSL) 159 via the ground select transistors (GST). Common source line CSL 159 can be a conductive layer (or multiple conductive lines) formed on the substrate of the 3D memory. Common source line CSL 159 can be coupled to ground.

[0141] Figure 2 FIG. 2 is a diagram illustrating an exemplary configuration of a memory device 200. The memory device 200 may be implemented as Figure 1A The memory device 200 includes a memory array 210. The memory array 210 includes a plurality of memory cells connected in series, for example Figure 1B The memory unit 141 or Figure 1C Memory cells 157 are shown coupled to multiple column word lines and multiple row bit lines.

[0142] The memory cell includes a storage transistor configured as a storage element. The storage transistor may include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating-gate transistor, a nitride read-only memory (NROM) transistor, or any suitable non-volatile MOS device that can store charge.

[0143] Memory device 200 includes a memory interface 202 having a plurality of input / output (I / O) ports for receiving data, for example, from a memory controller, such as device controller 112 of FIG. 1 , or a plurality of input / output (I / O) ports for outputting data from memory array 210. Memory device 200 includes a data buffer 208 configured to buffer data received and output via memory interface 202.

[0144] Memory device 200 also includes an X-decoder (or column decoder) 206 and a Y-decoder (not shown). Each memory cell is coupled to X-decoder 206 via a respective word line and to Y-decoder via a respective bit line 215 (BL1, BL2, ..., BLn). Thus, X-decoder 206 and Y-decoder can select each memory cell for a read or write operation via the corresponding word line and bit line 215.

[0145] Memory device 200 includes a page buffer circuit 220 comprising a plurality of page buffers 222. Each page buffer 222 (PB1, PB2, PB3, ..., PBn) is connected to memory array 210 via a corresponding bit line 215 (BL1, BL2, BL3, ..., BLn). In some embodiments, page buffer 222 is connected to a Y decoder via a data line associated with the corresponding bit line 215, which is connected to a corresponding line of memory cells in memory array 210. The page buffer is used to control the voltage of the corresponding bit line to perform operations, such as reading, programming, or erasing, on the memory cells coupled to the corresponding bit line.

[0146] In some embodiments, the memory device 200 further includes a cache data buffer circuit 230 (CDL) coupled between the page buffer circuit 220 and the data buffer 208. During a program or erase operation, the cache data buffer circuit 230 is used to store memory data or output data to one or more page buffers 222 in the page buffer circuit 220. During a read operation, the cache data buffer circuit 230 is used to store data from one or more page buffers 222 in the page buffer circuit 220 or output data to the data buffer 208.

[0147] The memory device 200 further includes a control logic circuit 204, a data buffer 208, a page buffer circuit 220, and a cache data buffer circuit 230. The control logic circuit 204 is coupled to the components in the memory device 200. The memory device 200 includes an X-decoder and a Y-decoder. The control logic circuit 204 is used to receive commands, address information, and / or data, such as from a memory interface 202. Figure 1A The control logic circuit 204 may also process commands, address information, and / or data, for example, to generate physical address information (eg, of a block or page) in the memory array 210 .

[0148] In some embodiments, the control logic circuit 204 includes a data register, an SRAM buffer, an address generator, a mode logic circuit, and a state machine. The mode logic circuit is used to determine whether a read or write operation occurs and provide the determination result to the state machine.

[0149] During a write operation, the data register in the control logic circuit 204 can temporarily store input data from the memory interface 202, and the address generator in the control logic circuit 204 can generate a corresponding physical address to store the input data in a specified memory cell of the memory array 210. The address generator can connect to and control the X-decoder 206 and the Y-decoder to select a specified memory cell via the corresponding word line and bit line. As long as the supply voltage is available, the SRAM buffer can retain the input data from the data register in its memory. The state machine is used to process the write signal from the SRAM buffer and provide a control signal to the voltage generator. The voltage generator can provide a write voltage to the X-decoder 206 and / or the Y-decoder. The Y-decoder is used to output the write voltage to multiple bit lines (BL) to store the input data in the specified multiple memory cells.

[0150] During a read operation, the state machine can provide control signals to the voltage generator and page buffer circuit 220. The voltage generator provides a read voltage to the X-decoder 206 and the Y-decoder to select a memory cell. The page buffer 222 can sense a low-power signal (e.g., a current signal) representing a data bit ("1" or "0") stored in the selected memory cell via a bit line 215 coupled to the page buffer 222 and the selected memory cell. The sense amplifier can amplify the swing of the low-power signal to a recognizable logic level so that the data bit can be correctly interpreted by logic circuitry within or external to the memory device 200. In some embodiments, the sense amplifier includes the page buffer circuit 220 and / or the cache data latch circuit 230. The data buffer 208 can receive the amplified voltage from the sense amplifier and output the amplified power signal to logic circuitry external to the memory device 200 via the memory interface 202.

[0151] To sense the data stored in the memory cell by sensing the current flowing through the corresponding bit line, the page buffer needs to have a capacitance on the sensing node to pre-charge or discharge the sensing node. During the pre-charge phase of the page buffer, the capacitance of the sensing node is pre-charged to a pre-determined sensing voltage. Then, during the discharge phase after the pre-charge phase, the charge stored in the capacitance is discharged by a sensing current flowing through the corresponding bit line to the memory cell. The bit value latched by one or more latches of the page buffer can be updated to a sensed value according to the discharge sensing voltage V SEN updated.

[0152] During the sensing phase (or strobing phase) after the discharge phase, if the bit stored in the memory cell is "0", the discharge sensing voltage V SEN on the sensing node can be greater than a pre-determined threshold voltage V Th , for example, a strobe voltage V Strobe associated with the latches in the page buffer. Accordingly, the page buffer can be used to update the bit value "1" latched by one or more latches to a sensed value "0", or to latch a sensed value "0" to one or more latches. Conversely, if the bit value stored in the memory cell is "1", the discharge sensing voltage V SEN on the sensing node can be less than or equal to the threshold voltage V Th . Accordingly, the page buffer can be used to maintain (or keep) the bit value "1" latched by one or more latches.

[0153] If the capacitance value on the sensing node is not stable and changes suddenly, for example, approaching the threshold voltage VTh, the sensing result can be incorrect. If the capacitance on the sensing node is too small, the pre-charge and discharge phases will not be able to be performed completely for sensing. Therefore, the page buffer needs a large and stable capacitance value so that the capacitance on the sensing node can be pre-charged or discharged completely, thereby achieving accurate sensing.

[0154] In some embodiments, transistors (e.g., MOSFETs) are used as the capacitance (e.g., MOS capacitance) coupled to the sensing node of the page buffer. However, transistors with high capacitance values tend to have large volumes and thus occupy large areas, resulting in an increase in the overall area of the page buffer.

[0155] In some embodiments, the page buffer includes a plurality of latch units. Each latch unit includes a latch coupled between a corresponding sense transistor and a corresponding coupling transistor, where the sense transistor and the coupling transistor are both coupled to a sense node. Each sense transistor has a gate terminal coupled to the sense node and can act as a gate capacitance. Each coupling transistor has a drain terminal (or source) coupled to the sense node and can act as a junction capacitance. Instead of MOS capacitors in the page buffer, the equivalent capacitance on the sense node of the page buffer is determined by the "gate capacitance associated with the corresponding sense transistor in the latch unit", the "junction capacitance associated with the corresponding coupling transistor in the latch unit", and the "metal line routing in the page buffer".

[0156] Figure 3 Fig. 3 shows a schematic diagram 300 of the voltage-capacitance relationship of the junction capacitance and the gate capacitance, according to some embodiments of the present disclosure. When the voltage VGS between the gate and the source of the sense transistor changes, the capacitance value of the junction capacitance changes according to a capacitance-voltage (CV) curve 302, and the capacitance value of the gate capacitance changes according to a CV curve 304. The line 306 represents the sensing operating range of the page buffer. The CV curves 302 and 304 represent that near the threshold voltage VTH, the capacitance value of the gate capacitance has a greater change (e.g., change in slope) than the capacitance value of the junction capacitance. Thus, if the ratio of the number of gate capacitances to the number of junction capacitors is large, e.g., equal to 1, the capacitance value at the sense node can have a significant change near the predetermined threshold voltage VTH, which can result in an erroneous sensing result. GS Th Th

[0157] The present disclosure provides a page buffer with a large and stable capacitance value to detect the data stored in a memory cell, e.g., by minimizing the effect of the gate capacitance in the page buffer. In some embodiments, as discussed in more detail below, the latch units in the page buffer can be classified into at least two types of circuits: "sense latch circuits" and "storage latch circuits". A sense latch circuit includes one or more latch units that are coupled to a sense transistor and have their gates connected to a sense node for sensing data through a bit line. The one or more latch units share the sense transistor. A storage latch circuit does not participate in sensing and only stores data in the sense latch circuits or cache data latch circuits (e.g., the cache data latch circuit 230 shown in Fig. 2). Thus, a storage latch circuit can not include the sense transistor. Accordingly, the effect of the gate capacitance associated with the sense transistor in the page buffer can be minimized to increase the stability of the capacitance value at the sense node, thereby improving the sensing accuracy and / or yield of the page buffer. Figure 4 Figure 2 ​​​​​

[0158] In some embodiments, the number of latch units in the page buffer is determined by the memory cell type of the memory cells of the memory array. For example, if the memory cell type of the memory cell is SLC, the page buffer of the memory cell may include two latch units. If the memory cell type of the memory cell is MLC, the page buffer of the memory cell may include three latch units. If the memory cell type of the memory cell is TLC, the page buffer of the memory cell may include five latch units. If the memory cell type of the memory cell is QLC, the page buffer of the memory cell may include six latch units. For example only, the following description includes a page buffer suitable for TLC that includes five latch units.

[0159] Figure 4 FIG. 4 is a schematic diagram of a page buffer 400 according to some embodiments of the present disclosure. The page buffer 400 may be composed of Figure 2 The page buffer 400 is implemented by the page buffer 222. The page buffer 400 includes five latch units 440a, 440b, 460a, 460b, and 460c, and these five latch units can be classified into two types of circuits: a "sensing latch circuit 430" and a "storage latch circuit 450". The sensing latch circuit 430 is used to sense the data stored in the memory cell through the bit line 401. The storage latch circuit 450 is used to store the sensing latch circuit 430 or the cache data latch circuit (such as Figure 2 Cache data latch circuit 230).

[0160] Each of the five latch units described above can have the same structure. As shown in FIG5 , latch unit 500 includes a first node (e.g., input node) 502 and a second node (e.g., output node) 504. Latch unit 500 includes a latch 520. Latch 520 is coupled between a coupling circuit 510 and a latch control circuit 530. Coupling circuit 510 is coupled to the first node, and latch control circuit 530 is coupled to the second node.

[0161] Latch 520 includes a pair of first inverters 522 and second inverters 524. Latch 520 can be a tri-state latch or an inhibited latch. First inverter 522 is configured to receive a corresponding signal POS. Second inverter 524 is configured to receive a corresponding standby signal STB. The voltage at node LB 521 is opposite to the voltage at node L 523. Node LB 521 is located between inverters 522 and 524, and node L 523 is located between inverters 522 and 524. Latch 520 stores data by updating the values ​​at node LB 521 and / or node L 523.

[0162] The coupling circuit 510 includes a first coupling transistor 512 and a second coupling transistor 514. Both the first coupling transistor 512 and the second coupling transistor 514 can be N-channel transistors (NMOS). The first coupling transistor 512 includes a gate terminal, a drain terminal, and a source terminal. The gate terminal is configured to receive a control signal RD. The drain terminal is coupled to the first node 502, and the source terminal is coupled to the drain terminal of the second coupling transistor 514. The source terminal of the second coupling transistor 514 is coupled to ground, and the gate terminal is coupled to the first inverter 522 (e.g., coupled to the L node 523).

[0163] The latch control circuit 530 includes a latch set transistor 532 and a latch reset transistor 534. The latch set transistor 532 is coupled between the LB node 521 and the second node 504. The latch reset transistor 534 is coupled between the L node 523 and the second node 504. The latch set transistor 532 has a gate for receiving a set signal S, a drain coupled to the LB node 521, and a source coupled to the second node 504. The latch reset transistor 534 has a gate for receiving a reset signal R, a drain coupled to the L node 523, and a source coupled to the second node 504. Therefore, the sources of the latch set transistor 532 and the latch reset transistor 534 are both coupled to the sense node 504.

[0164] For the page buffer in the present disclosure, either the sensing latch circuit and the storage latch circuit includes at least one latch unit. For a lower level memory, such as SLC or MLC, the sensing latch circuit may have only one latch unit. For a higher level memory, such as TLC or QLC, the sensing latch circuit may include one or more other latch units to perform a quick pass write (QPW) operation. For example, the sensing latch circuit may include two latch units for TLC and QLC. The number of latch units in the storage latch circuit depends on the bit value stored in the memory cell. For example, the storage latch circuit may include one latch unit for SLC, two latch units for MLC, three latch units for TLC, and four latch units for QLC.

[0165] Please refer to Figure 4 For a TLC memory cell, the sense latch circuit 430 includes two sense latch units (or sense latches) 440a and 440b (collectively referred to herein as a plurality of sense latch units 440 or individually as a sense latch unit 440). The storage latch circuit 450 includes three latch units (or storage latches) 460a, 460b, and 460c (collectively referred to herein as a plurality of storage latch units 460 or individually as a sense latch unit 460).

[0166] The sense latch circuit 430 further includes a sense transistor 432 coupled to the plurality of sense latch units 440. The storage latch circuit 450 does not include a sense transistor. The latches in the sense latch circuit 430 and the storage latch circuit 450 can be tri-state latches, inhibit latches, or any other suitable type of latch. In some embodiments, these latches are of the same type. In some embodiments, because the sense latch circuit 430 and the storage latch circuit 450 are used to perform different functions, such as sensing data versus storing data, the latches in the sense latch circuit 430 and the storage latch circuit 450 can also be of different types.

[0167] The gate terminal of the sensing transistor 432 is coupled to the sensing node (SEN) 431, the source terminal thereof is coupled to the ground terminal, and the drain terminal thereof is coupled to the sensing latch unit 440. The sensing transistor 432 functions as the gate capacitor 408. The first node (e.g., Figure 5 The first node 502 is coupled to the sensing node 431. For example, the coupling circuit of the sensing latch unit 440 (eg, Figure 5 The first coupling transistor (eg, Figure 5 The first coupling transistor is coupled to the sensing node 431. The first coupling transistor functions as a junction capacitor 406. The second node (eg, Figure 5 The second node 504 is coupled to the drain terminal of the sensing transistor 432. For example, the latch control circuit (eg, Figure 5 The latch control circuit 530 is coupled to the drain terminal of the sensing transistor 432. The sensing latch circuit 430 updates the DLB node or the L1B node (eg, Figure 5 LB node 521)" and / or "DL node or L1 node (e.g. Figure 5 The data is sensed by the value of the L node 523)" shown.

[0168] In some embodiments, the sensing latch circuit 430 includes a discharge transistor 434 having a gate for receiving a discharge signal, a source coupled to the ground, and a drain coupled to the sensing latch unit 440 , eg, the second node of the sensing latch unit 440 .

[0169] The storage latch circuit 450 includes three storage latch units 460 that can be connected in parallel. The third node (e.g. Figure 5 The first node 502 shown in FIG. 5 is coupled to the sensing node 431, and the fourth node (eg, Figure 5 504) is coupled to the sensing node 431. For example, the first coupling transistor (eg, Figure 5 The coupling transistor 512 is coupled to the sensing node 431. Therefore, the first coupling transistor functions as the junction capacitor 406. Similarly, the transistors of the latch control circuit in the storage latch unit 460 (eg, Figure 5 The latch set transistor 532 and the latch reset transistor 534 are also shown coupled to the sensing node 431 and the gate of the sensing transistor 432. Thus, the transistors in the latch control circuit of the storage latch circuit 460 can also function as the junction capacitor 406.

[0170] The equivalent capacitance of the sensing node 431 of the page buffer 400 is determined by the gate capacitance 408, the junction capacitance 406, and the metal wiring of the page buffer 400. Figure 4 As shown, each of the first coupling transistor in the sensing latch unit 440, the first coupling transistor in the storage latch unit 460, and the latch setting transistor and the latch reset transistor in the latch control circuit of the storage latch unit 460 can serve as the junction capacitor 406. In contrast, only one sensing transistor 432 serves as the gate capacitor 408. Therefore, in the page buffer 400, the ratio of the number of gate capacitors to the number of junction capacitors can be significantly reduced, such as 1 / 11. Accordingly, the capacitance value of the sensing transistor 432 is substantially smaller than the overall capacitance value of the junction capacitor 406, and the influence of the gate capacitance on the equivalent capacitance (and the equivalent capacitance value) can be significantly suppressed, thereby increasing the equivalent capacitance value at the threshold voltage V Th (eg: V Strobe ) near stability.

[0171] In some embodiments, Figure 4 As shown, page buffer 400 includes a precharge circuit 410 and a bit line control circuit (or clamp circuit) 420. Precharge circuit 410 is coupled to a sensing node 431. A first control node of bit line control circuit 420 is coupled to bit line 401, and a second control node thereof is coupled to sensing node 431. Figures 6A to 6C and Figure 7 The details are as follows: the precharge circuit 410 is used to precharge the sensing node 431 during the precharge phase. The bit line control circuit 420 is used to precharge the bit line 401 during the precharge phase and discharge the sensing node 431 during the discharge phase after the precharge phase.

[0172] like Figure 4As shown, the precharge circuit includes two P-channel transistors 412 and 414 (e.g., PMOS transistors) connected in series between a supply voltage VDDI and a sensing node 431. The source terminal of transistor 412 is configured to receive the supply voltage VDDI, and the gate terminal thereof is configured to receive a precharge control signal PRE. The gate terminal of transistor 414 is configured to receive a precharge enable signal PSEN, and the source terminal thereof is coupled to the drain terminal of transistor 412, and the drain terminal thereof is coupled to the sensing node 431.

[0173] like Figure 4 As shown, bit line control circuit 420 includes a P-channel transistor 422, three N-channel transistors 424, 426, and 428, and an N-channel transistor 427. P-channel transistor 422 is configured to receive a supply voltage VDDI. N-channel transistors 424, 426, and 428 are configured to receive bit line control signals BLC1, BLC2, and BLC3, respectively. N-channel transistor 427 is coupled to ground. The source terminal of transistor 422 is configured to receive the supply voltage VDDI, and the gate terminal thereof is coupled to the DLB node in the latch of sense latch circuit 430, such as sense latch unit 440a. The drain terminal of transistor 426 is coupled to the drain terminal of transistor 422, the gate terminal thereof is configured to receive the bit line control signal BLC2, and the source terminal thereof is coupled to the drain terminal of transistor 427. The source terminal of transistor 427 is coupled to ground, and the gate terminal thereof is coupled to the gate terminal of transistor 422. Precharge circuit 410 is coupled to bit line control circuit 420 by connecting a node between the drain of transistor 412 and the source of transistor 414 and a node between the drain of transistor 422 and the drain of transistor 426. Transistor 424 has a drain coupled to bit line 401, and a gate coupled to a node between the source of transistor 426 and the drain of transistor 427. Transistor 428 has a drain coupled to the source of transistor 424, a source coupled to sensing node 431, and a gate coupled to receive bit line control signal BLC3.

[0174] In some embodiments, the page buffer 400 includes a discharge circuit 402 including a discharge transistor 404, such as an N-channel transistor. The discharge transistor 404 has a drain coupled to the drain of the transistor 424, a gate for receiving a discharge signal DISCH, and a source coupled to ground.

[0175] Figures 6A to 6C for Figure 4 The circuit diagrams 600 , 630 , and 650 of the page buffer in different stages (or steps) are shown, including a pre-charge stage (STEP 1 ), a discharge stage (STEP 2 ), and a sensing stage (STEP 3 ). Figure 7 The page buffer 400 is shown to operate in Figures 6A to 6CThe voltage change timing diagram of different nodes in each stage.

[0176] Initially, as shown in FIG. 6 , in the sensing latch circuit 430 , the DLB node of the sensing latch unit 440 maintains a low voltage corresponding to bit “0” (eg, V SS ), and the LB node is at a high voltage corresponding to bit “1”. The P-channel transistor 422 is turned on when its gate terminal is coupled to the DLB node, and the N-channel transistor 427 is turned off when its gate terminal is coupled to the DLB node.

[0177] During the pre-charge phase, if Figure 6A and Figure 7 As shown in STEP 1 of FIG. 1 , transistor 414 is turned on by receiving a corresponding signal PSEN (a low voltage level) at its gate terminal. Consequently, precharge circuit 410 is turned on to precharge sensing node 431 from a lower voltage level (e.g., corresponding to bit "0") to a higher voltage level (e.g., a predetermined sensing voltage). Sensing node 431 can be precharged from the supply voltage along current path 602 via transistor 422 and transistor 414.

[0178] During the precharge phase, N-channel transistors 424 and 426 are turned on by receiving corresponding control signals BLC1 and BLC2, while N-channel transistor 428 is turned off. Consequently, bitline 401 is precharged to a predetermined bitline voltage via the supply voltage through current path 604 of transistors 422, 426, and 424. When transistor 428 is turned off, the bitline is disconnected from sense node 431. The predetermined sense voltage on sense node 431 can be higher than the predetermined bitline voltage on bitline 401.

[0179] During the discharge phase after the pre-charge phase, if Figure 6B and Figure 7 As shown in STEP 2 of FIGURE 4, transistor 414 is turned off by changing the signal PSEN at its gate terminal from a low voltage to a high voltage. Consequently, current path 602 is also closed. Consequently, sensing node 431 is no longer charged by precharge circuit 410. Conversely, transistor 428 is turned on by receiving enable signal BLC3 (high voltage) at its gate terminal, and the sensing node is electrically connected to bit line 401. Consequently, the preset sensing voltage on sensing node 431 is discharged by the sensing current provided to bit line 401. The sensing current flows along current path 632 through transistors 428 and 424 to bit line 401.

[0180] In the pre-charge stage and discharge stage, such as Figure 7 As shown, the latch control circuit of the sensing latch unit 440 (eg: Figure 5The latch control circuit 530 shown is turned off, for example, by maintaining the latch reset transistor (eg, Figure 5 The latch reset transistor 534 shown is turned off. The first inverter in the latch of the sensing latch unit 440 (eg, Figure 5 The inverter 522 is turned on by receiving the low-level signal POS0, so that the bit value stored in the sense latch unit 440 (eg, "1" on the DL node) will maintain the same value.

[0181] At the end of the discharge phase, the sensed voltage on the sense node 431 after discharge can be expressed as a voltage V SEN The latched bit value in the sensing latch unit 440 will be determined according to the discharged sensing voltage V SEN In the sensing phase (or gating phase) after the discharge phase, the latch control circuit is turned on, for example, by changing the control signal R0 to a high level to turn on the latch reset transistor. The first inverter in the sensing latch unit 440 is turned off, for example, by changing the signal POS0 of the first inverter to a high level. The second inverter in the sensing latch unit 440 (e.g., Figure 5 The second inverter 524 shown can be turned on to make the bit values ​​of the DL node and the DLB node opposite.

[0182] When the bit value stored in the memory cell coupled to the bit line 401 is “1”, the voltage V SEN Less than (or equal to) the threshold voltage, for example: V Strobe , and the sensing transistor 432 is turned off. Therefore, the bit value “1” on the DL node remains unchanged to correspond to the bit value “1” stored in the memory cell.

[0183] When the bit value stored in the memory cell coupled to the bit line is “0”, the voltage V SEN The voltage of the latch 440 is greater than the threshold voltage to turn on the sensing transistor 432. As shown in FIG6C and FIG7 in STEP 3, since the latch reset transistor is turned on, the high potential corresponding to the bit value "1" on the DL node will be discharged to the low potential corresponding to the bit value "0" along the current path 652. Accordingly, the bit value "0" on the DLB node will be changed to the bit value "1" through the second inverter of the sensing latch unit 440. Therefore, the bit value "0" on the DL node of the latch in the sensing latch unit 440 will be updated to the bit value "0" stored in the memory cell.

[0184] In some embodiments, the storage latch circuit 450 is used to turn on one or more latch control circuits in the storage latch unit 460 to write the sensing result to one or more latches in the storage latch unit 460, for example, during the sensing phase or during the storage phase after the sensing phase. For example, to store the sensing result "0", the latch control circuit (e.g., Figure 5 The latch control circuit 530 shown is turned on, for example, by changing the control signal S2 from a low level to a high level. Since the sense voltage is greater than the threshold voltage, the voltage corresponding to the bit value "0" on the L1B node of the latch in the storage latch unit 460 is pulled high to the voltage corresponding to the bit value "1", and the voltage corresponding to the bit value "1" on the L1 node of the latch in the storage latch unit 460 is pulled down to the voltage corresponding to the bit value "0".

[0185] Figure 8 A process 800 is used to illustrate managing a page buffer circuit in a memory device according to some embodiments of the present disclosure. The memory device may be Figure 1A The memory 116 shown, or Figure 2 The memory device 200 shown includes a memory array having a plurality of memory cells, e.g. Figure 1B The memory unit 141 or Figure 1C The memory cells are connected in series in multiple columns and connected to memory cell lines (eg, bit lines). The page buffer circuit can be Figure 2 The page buffer circuit 220 shown in FIG. The page buffer circuit includes multiple page buffers, such as Figure 2 The page buffer 222 or Figure 4 The page buffer 400 is shown. Each page buffer is coupled to a corresponding memory cell via a corresponding bit line. Each page buffer can be managed or controlled by a control logic circuit, for example: Figure 2 The control logic circuit 204 in the memory device is shown. The process 800 can be performed by the control logic circuit that manages the page buffer.

[0186] The page buffer includes a sense latch circuit (eg: Figure 4 The sensing latch circuit 430 shown) and the storage latch circuit (eg: Figure 4 The storage latch circuit 450 is shown. The sensing latch circuit includes a sensing transistor coupled to a sensing node (e.g., Figure 4 The sensing transistor 432 is shown as: Figure 4 The sensing node 431 shown) and at least one sensing latch unit (eg: Figure 4The first node of at least one sensing latch unit is coupled to the sensing node, and the second node thereof is coupled to the sensing transistor. The storage latch circuit includes at least one storage latch unit (e.g., Figure 4 In the example of the storage latch unit 460 shown, the third node and the fourth node of at least one storage latch unit are both coupled to the sensing node. A first terminal (e.g., a drain terminal) of the sensing transistor is coupled to the second node of the at least one sensing latch unit, a gate terminal is coupled to the sensing node and the third and fourth nodes of the at least one storage latch unit, and a second terminal (e.g., a source terminal) of the sensing transistor is coupled to ground.

[0187] The sensing latch circuit and the storage latch circuit can be configured to have a sensing capacitor (or an equivalent capacitor) that is associated with the gate capacitance (e.g., Figure 4 The gate capacitance 408 shown) and one or more parasitic junction capacitances in the sensing latch circuit and the storage latch circuit (e.g., Figure 4 (See junction capacitance 406 for details). Gate capacitance is associated with the sensing transistor. Sensing capacitance may also be associated with one or more metal traces in the sensing latch circuit and the storage latch circuit. Compared to junction capacitance, gate capacitance can have a greater capacitance variation around the threshold voltage.

[0188] In some embodiments, the storage latch circuit does not include a sensing transistor. The sensing latch circuit includes only one sensing transistor. In some embodiments, the sensing latch circuit includes multiple sensing transistors and multiple sensing latch units, and the number of sensing transistors is less than the number of sensing latch units.

[0189] The sensing latch unit and the storage latch unit can have the same type of latch unit, such as: Figure 5 In some embodiments, each of the at least one sensing latch unit comprises a first latch (e.g., Figure 5 The latch 520 shown in FIG. Figure 5 The first latch has a first inverter (such as Figure 5 The first latch control circuit is coupled to the first latch and the first end of the sensing transistor. Each at least one sensing latch unit may further include a first coupling circuit (e.g., Figure 5 As shown in the coupling circuit 510, the first coupling circuit is coupled to the sensing node and the first latch.

[0190] In some embodiments, each of the at least one storage latch unit includes a second latch (e.g. Figure 5 Latch 520 shown) and the second latch control circuit (such as Figure 5The second latch has a second inverter (such as Figure 5 The second latch control circuit is coupled to the second latch and the gate terminal of the sensing transistor. Each at least one storage latch unit may further include a second coupling circuit (such as Figure 5 As shown in the coupling circuit 510, the second coupling circuit is coupled to the sensing node and the second latch.

[0191] In some embodiments, the sensing latch unit includes a first type of latch and the storage latch unit includes a second type of latch, wherein the first type of latch is different from the second type of latch. Either the first type of latch or the second type of latch may be a tri-state latch or an inhibiting latch. The first type of latch is different from the second type of latch.

[0192] In some embodiments, the page buffer may further include a precharge circuit (e.g. Figure 4 The precharge circuit 410 shown in FIG. Figure 4 The bit line control circuit 402 is shown. The precharge circuit is coupled to the sensing node. The first control node of the bit line control circuit is coupled to the bit line, and the second control node thereof is coupled to the sensing node. The page buffer may also include a discharge circuit, such as Figure 4 The discharge circuit 402 is shown coupled to the bit line control circuit.

[0193] In some embodiments, the number of at least one sense latch unit in the sense latch circuit and the number of at least one storage latch unit in the storage latch circuit are related to the memory cell type of the memory cell. The number of at least one storage latch unit in the storage latch circuit can be determined based on the number of bit values ​​stored in the memory type. The sense latch circuit may include two or more sense latch units, for example, for quick pass write (QPW) operations.

[0194] In some embodiments, the memory cell type of the memory cell is SLC, the sense latch circuit includes one sense latch unit, and the storage latch circuit includes one storage latch unit. In some embodiments, the memory cell type of the memory cell is MLC, the sense latch circuit includes one sense latch unit, and the storage latch circuit includes two storage latch units. In some embodiments, the memory cell type of the memory cell is TLC, the sense latch circuit includes two sense latch units, and the storage latch circuit includes three storage latch units. In some embodiments, the memory cell type of the memory cell is QLC, the sense latch circuit includes two sense latch units, and the storage latch circuit includes four storage latch units.

[0195] In step 802, in a precharge phase, the bit lines of the memory cells coupled to the memory device are precharged by the page buffers corresponding to the bit lines. Figure 6A and Figure 7 As shown, the bit line control circuit will be turned on to follow the current path (such as Figure 6A The current path 604 shown in FIG. 60 is used to precharge the bit line. The bit line control circuit includes a plurality of transistors, such as Figure 4 Transistors 422, 424, 426, 427, and 428 are shown. When control signal BLC2 turns on transistor 426 and transistor 424 is turned on by the control signal, the bit line control circuit can be turned on. The bit line control circuit is used to disconnect the bit line from the sense node, for example by keeping transistor 428 off.

[0196] In step 804, in the precharge phase, the sensing node of the sensing latch circuit of the page buffer is precharged. Figure 6A and Figure 7 As shown, the precharge circuit of the page buffer is turned on to form a current path (such as Figure 6A The current path 602 shown in FIG. 1 is used to precharge the sensing node to a predetermined sensing voltage. The transistor coupled to the sensing node (e.g., Figure 4 The transistor 414 shown in FIG. 4 is provided, and the pre-charge circuit can be turned on accordingly.

[0197] In step 806, in a discharge phase after the pre-charge phase, the preset sensing voltage on the sensing node is discharged through the bit line connected to the sensing node to provide a sensing current to the memory cell through the bit line. Figure 6B and Figure 7 As shown, the precharge circuit is turned off to stop charging the sense node (e.g., by turning off a transistor coupled to the sense node). The sense node is then connected to the bit line, such as by turning on transistor 428 in the bit line control circuit. The preset sense voltage is greater than the bit line voltage. Therefore, a current path (e.g., current path 632) is formed to discharge the sense voltage at the sense node. At the end of the discharge phase, the discharged sense voltage can be reduced to a voltage V SEN .

[0198] In step 808, in the sensing phase after the discharge phase, the data latched by the sensing latch circuit is updated according to the sensing voltage discharged on the sensing node. Figure 6C and Figure 7As shown, the data of the node of the latch in the sensing latch circuit (e.g., the DL node) is sensed, and the bit value latched by the sensing latch circuit is "1", and the bit value of another node of the latch in the sensing latch circuit (e.g., the DLB node) is "0". When in the sensing stage, the latch control circuit of the sensing latch circuit will be turned on.

[0199] In some embodiments, if the bit value stored in the memory cell is "1", the discharge sensing voltage V SEN is less than or equal to the threshold voltage (e.g., V Figure 7 As shown, V Strobe ), the sensing transistor will be turned off, and the bit value "1" latched by the latch in the sensing latch circuit will be kept fixed, i.e., corresponding to the bit value "1" stored in the memory cell.

[0200] In some embodiments, if the bit value stored in the memory cell is "0", the discharge sensing voltage V SEN is greater than the threshold voltage, the sensing transistor will be turned on, and the bit value "1" latched by the latch in the sensing latch circuit will be changed to "0", i.e., corresponding to the bit value "0" stored in the memory cell.

[0201] In some embodiments, in the sensing stage or the storage stage after the sensing stage, the storage latch circuit is used to turn on one or more latch control circuits to write the sensing result in one or more latches of the storage latch circuit. In some embodiments, the data latched by the storage latch circuit will also be cached by the cache data latch circuit CDL (e.g., as shown). Figure 2

[0202] Embodiments of the present disclosure can be implemented as one or more computer program product(s), such as one or more modules of computer program instructions, encoded on a computer-readable medium for execution by, or to control the operation of, data processing apparatus. The computer-readable storage medium can be a machine-readable storage device, a machine-readable storage substrate, a memory, or a combination of one or more of them. The foregoing "data processing apparatus" includes all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The data processing apparatus can include, in addition to a hardware processor, software for establishing, implementing, or maintaining the operational environment in which the hardware processor is used to process data, e.g., a code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0203] ​A system may encompass all devices, equipment, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a data processing device may also include code that establishes an execution environment for a computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more.

[0204] A computer program (or program, software, application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A computer program may be stored as part of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or portions of code). A computer program may be deployed for execution on one or more computers, located at one site or distributed across multiple sites, and connected to a communications network.

[0205] The processes and logic described in this disclosure may be performed by one or more programmable processors that execute one or more computer programs to perform the functions described in this disclosure. The processes and logic may also be performed by dedicated logic circuits, and the data processing device may also be implemented as a dedicated logic circuit, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0206] Processors suitable for executing computer programs include, for example, general-purpose and special-purpose microprocessors, and any one or more processors in any type of data computer. Generally speaking, the processor will receive instructions and data from a read-only memory, a random access memory, or both. The basic elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally speaking, a computer may also include or be operatively coupled to receive, transmit data, or both, from one or more large-capacity storage devices (e.g., magnetic memory, magneto-optical memory, or optical disks) for storing data. However, the aforementioned devices are not required. Readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory and memory devices, such as EPROM, EEPROM, and cache memory, optical disks, etc. of semiconductor storage devices. The processor and memory may be implemented by dedicated logic circuits or incorporated into dedicated logic circuits.

[0207] Although many details are described in this disclosure, these details should not be interpreted as limitations on the scope of the claims or the content of the protection claimed, but are merely used to describe the unique features of a particular embodiment. The various features described in the context of a separate embodiment of the present disclosure may also be implemented in combination in other single embodiments. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although some features act on specific combinations, in other cases, these combination restrictions may be deleted, and one or more features in a protected combination may be directed to other sub-combinations or variations of sub-combinations. Similarly, although the operation is described in a specific order in the drawings, this should not be understood as requiring the present disclosure to be performed in this specific order, and should not be understood as requiring all operations in the drawings to achieve its function.

[0208] Although the present disclosure has been disclosed in the form of an implementation method as described above, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the appended claims.

Claims

1. A memory device comprising: a memory array comprising a plurality of memory cells; a plurality of memory cell lines, respectively connected to a plurality of lines of the memory cells in the memory array; A page buffer circuit includes a plurality of page buffers coupled to the memory cell lines, wherein each of the page buffers includes: A sensing latch circuit includes a sensing transistor, wherein the sensing transistor is coupled to a sensing node and at least one sensing latch unit, the at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to the sensing transistor; as well as A storage latch circuit includes at least one storage latch unit, wherein the at least one storage latch unit includes a third node and a fourth node, the third node and the fourth node are coupled to the sensing node; wherein the sensing transistor comprises a first terminal, a gate terminal, and a second terminal, the first terminal being coupled to the second node of the at least one sensing latch unit, the gate terminal being coupled to the sensing node and the third and fourth nodes of the at least one storage latch unit, and the second terminal being coupled to a ground terminal; The sensing latch circuit includes one or more transistors substantially identical to the sensing transistor, the sensing latch circuit includes a plurality of sensing latch units, and the number of the one or more transistors is smaller than the number of the sensing latch units.

2. The memory device of claim 1 , wherein each of the at least one sensing latch unit comprises: a first latch comprising a first inverter; and a first latch control circuit coupled to the first latch and the first end of the sensing transistor; wherein the at least one storage latch unit comprises: a second latch comprising a second inverter; and A second latch control circuit is coupled to the second latch and the gate terminal of the sensing transistor.

3. The memory device of claim 2 , wherein the second latch control circuit comprises a first control transistor and a second control transistor, wherein source terminals of the first control transistor and the second control transistor are coupled to the sensing node and the gate terminal of the sensing transistor.

4. The memory device according to claim 2 , wherein each of the at least one sensing latch unit further comprises a first coupling circuit and the first latch, the first coupling circuit being coupled to the sensing node; Each of the at least one storage latch unit further includes a second coupling circuit and the two latches, and the second coupling circuit is coupled to the sensing node.

5. The memory device of claim 1 , wherein each of the page buffers further comprises: a precharge circuit coupled to the sensing node and configured to precharge the sensing node in a precharge phase; and a bit line control circuit comprising a first control node and a second control node, wherein the first control node is coupled to a bit line of one of the memory cells, and the second control node is coupled to the sensing node; The bit line control circuit is used to: charging the bit line in the precharge phase; and In a discharge phase after the pre-charge phase, the bit line is discharged by connecting the sensing node and the bit line to provide a sensing current to one of the memory cells.

6. The memory device according to claim 5, wherein the storage latch circuit is configured to: One or more latch control circuits in the at least one storage latch unit are turned on to update a sensing result of one or more latches in the at least one storage latch unit. 7 . The memory device of claim 1 , wherein the number of the at least one sense latch unit in the sense latch circuit and the number of the at least one storage latch unit in the storage latch circuit are associated with a memory type of the memory cells.

8. The memory device of claim 1, wherein the storage latch circuit does not include a transistor substantially identical to the sensing transistor.

9. An integrated circuit comprising: A sensing latch circuit comprising: a sensing transistor coupled to a sensing node; at least one sensing latch unit comprising a first node and a second node, wherein the first node is coupled to the sensing node, and the second node is coupled to the sensing transistor; as well as A storage latch circuit comprising: at least one storage latch unit comprising a third node and a fourth node, wherein the third node and the fourth node are coupled to the sensing node; The sensing transistor comprises: a first terminal coupled to the second node of the at least one sensing latch unit; a second terminal coupled to a ground terminal; and a gate terminal coupled to the sensing node and the third node and the fourth node of the at least one storage latch unit; wherein the at least one sensing latch unit includes a plurality of sensing latch units, and each of the sensing latch units includes a first node and a second node, wherein the first node is coupled to the sensing node, and the second node is coupled to a drain terminal of the sensing transistor; as well as The at least one storage latch unit includes a plurality of storage latch units, each of which includes a third node and a fourth node, wherein the third node is coupled to the sensing node, and the fourth node is coupled to the gate terminal of the sensing transistor.

10. The integrated circuit of claim 9, wherein each of the at least one sensing latch unit comprises: a first latch comprising a first inverter; and a first latch control circuit coupled to the first latch and the first end of the sensing transistor; wherein the at least one storage latch unit comprises: a second latch comprising a second inverter; and A second latch control circuit is coupled to the second latch and the gate terminal of the sensing transistor.

11. The integrated circuit of claim 10 , wherein each of the at least one sensing latch unit comprises: a first coupling circuit coupled to the sensing node and the first latch; and Each of the at least one storage latch unit comprises: A second coupling circuit is coupled to the sensing node and the second latch. 12 . The integrated circuit of claim 9 , wherein the sense latch circuit comprises at least one sense transistor, and the at least one storage latch unit does not comprise a transistor substantially identical to the sense transistor.

13. The integrated circuit of claim 9 , wherein the sensing latch circuit and the storage latch circuit are configured to have an equivalent capacitance, the equivalent capacitance being associated with a gate capacitance, the gate capacitance being associated with the sensing transistor, the equivalent capacitance being further associated with one or more junction capacitances, and the one or more junction capacitances being associated with a plurality of transistors in the sensing latch circuit and the storage latch circuit.

14. The integrated circuit of claim 9, further comprising: a precharge circuit coupled to the sensing node and configured to precharge the sensing node in a precharge phase; A bit line control circuit comprising a first control node and a second control node, wherein the first control node is coupled to a bit line in a memory cell, and the second control node is coupled to the sensing node; The bit line control circuit is used to: In the precharge phase, the bit line is precharged; and In a discharge phase after the pre-charge phase, the sensing node is discharged by conducting the sensing node and the bit line to provide a sensing current to the memory cell.

15. The integrated circuit of claim 14 , wherein the sensing latch circuit is configured to: When the memory cell stores a 0 bit, a sensing voltage on the sensing node is greater than a threshold, and the sensing transistor is turned on to change a bit value latched by the at least one sensing latch unit to 0; as well as When the memory cell stores a 1 bit, a sensing voltage on the sensing node is less than or equal to the threshold, and the sensing transistor is turned off to maintain the bit value latched by the at least one sensing latch unit as 1; The storage latch circuit is used to: One or more latch control circuits in the at least one storage latch unit are turned on to update a sensing result of one or more latches in the at least one storage latch unit. 16 . The integrated circuit of claim 9 , wherein the at least one sensing latch unit comprises a first type latch, and the at least one storage latch unit comprises a second type latch, wherein the first type latch is different from the second type latch.

17. An integrated circuit comprising: a first latch circuit comprising a sensing transistor and one or more first latch units, wherein the sensing transistor is coupled to a sensing node, and the one or more first latch units are coupled to the sensing transistor; as well as a second latch circuit comprising one or more second latch units, wherein each of the one or more second latch units is identical to the one or more first latch units; The difference between the sensing transistor and each transistor in the second latch circuit is that a gate terminal of the sensing transistor is coupled to the sensing node and serves as a gate capacitor; wherein the one or more first latch units include a plurality of first latch units, and each of the first latch units includes a first node and a second node, wherein the first node is coupled to the sensing node, and the second node is coupled to a drain terminal or a source terminal of the sensing transistor; as well as The one or more second latch units include a plurality of second latch units, each of which includes a third node and a fourth node, wherein the third node is coupled to the sensing node, and the fourth node is coupled to the gate terminal of the sensing transistor.

18. The integrated circuit of claim 17, further comprising: a third circuit for: In a first phase, the sensing node and a bit line are precharged respectively, wherein the bit line is coupled to a memory cell in a memory device and is disconnected from the sensing node; as well as In a second phase after the first phase, a sense voltage at the sense node is discharged according to an equivalent capacitance by connecting the sense node to the bit line, thereby generating a sense current in the memory cell through the bit line, wherein the equivalent capacitance is based on the gate capacitance and one or more junction capacitances, the gate capacitance being associated with the sense transistor, the one or more junction capacitances being associated with a plurality of transistors in the one or more first latch units and the one or more second latch units; wherein a total capacitance of the one or more junction capacitances is substantially greater than a capacitance of the gate capacitance; The first latch circuit is configured to: update the data latched by the first latch circuit according to the sense voltage released on the sense node after the second stage; as well as The second latch circuit is configured to turn on at least one of the one or more second transistors to update the data latched by the first latch circuit to at least one latch in the second latch circuit.

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