Memory device with four data line bias levels

Abstract

This application relates to memory devices with four data line bias levels. A memory device can include a first latch to store a first data bit, a second latch to store a second data bit, a data line selectively connected to the first latch, the second latch, and a string of series connected memory cells, and a controller configured to bias the data line during a program operation of a selected memory cell. The controller can bias the data line to a first voltage level if the first data bit is equal to 0 and the second data bit is equal to 0, to a second voltage level if the first data bit is equal to 1 and the second data bit is equal to 0, to a third voltage level if the first data bit is equal to 0 and the second data bit is equal to 1, and to a fourth voltage level if the first data bit is equal to 1 and the second data bit is equal to 1.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more particularly in one or more embodiments, this disclosure relates to programming operations within a memory device using four data line bias levels. Background Technology

[0002] Memory (e.g., memory devices) is typically provided in computers or other electronic devices as internal semiconductor integrated circuit devices. Many different types of memory exist, including random-access memory (RAM), read-only memory (ROM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), and flash memory.

[0003] Flash memory has evolved into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that support high memory density, high reliability, and low power consumption. By programming the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0004] NAND flash memory is a common type of flash memory device, so named because of the logical form of its basic memory cell configuration. Typically, the memory cell arrays used in NAND flash memory are arranged such that the control gates of each memory cell in a row of the array are connected together to form access lines, such as word lines. Columns in the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates, such as between a source select transistor and a drain select transistor. Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known.

[0005] In memory programming, memory cells can be broadly programmed as memory cells commonly referred to as single-level cells (SLCs) or multi-level cells (MLCs). An SLC can use a single memory cell to represent a digital (e.g., one bit) of data. For example, in an SLC, a Vt of 2.5V can indicate a programmed memory cell (e.g., representing logic 0), while a Vt of -0.5V can indicate an erased cell (e.g., representing logic 1). For example, the erased state in an SLC can be represented by any threshold voltage less than or equal to 0V, while the programmed data state can be represented by any threshold voltage greater than 0V.

[0006] MLCs use more than two Vt ranges, each indicating a different data state. As is generally known, margins such as dead space (e.g., a certain volt) can separate adjacent Vt ranges, for example, to facilitate distinction between data states. Multilevel cells can leverage the analog properties of traditional non-volatile memory cells by assigning bit patterns to specific Vt ranges. While MLCs typically use memory cells to represent one data state from a binary number (e.g., 4, 8, 16, ...), memory cells operating as MLCs can be used to represent non-binary data states. For example, in the case of an MLC using three Vt ranges, two memory cells can be used to jointly represent one data state from eight data states.

[0007] In programming MLC memory, data values ​​are typically programmed in more than one pass; for example, one or more numbers are programmed in each pass. For instance, in a four-level MLC (often simply called an MLC), a first number, typically called the least significant bit (LSB) of the lower page (LP) data, is programmed into the memory cell in the first pass, thereby creating two (e.g., first and second) threshold voltage ranges. Subsequently, a second number, typically called the most significant bit (MSB) of the upper page (UP) data, is programmed into the memory cell in the second pass, typically moving a portion of those memory cells in the first threshold voltage range into a third threshold voltage range, and a portion of those memory cells in the second threshold voltage range into a fourth threshold voltage range. Similarly, an eight-level MLC (commonly referred to as a TLC) can represent a bit pattern containing the following three bits: a first digit, such as the least significant bit (LSB) or lower page (LP) data; a second digit, such as the upper page (UP) data; and a third digit, such as the most significant bit (MSB) or extra page (XP) data. When operating a TLC, the LP data is programmed into the memory cell in the first pass, generating two threshold voltage ranges, and then the UP and XP data are programmed into the memory cell in the second pass, generating eight threshold voltage ranges. Similarly, a sixteen-level MLC (commonly referred to as a QLC) can represent a four-bit bit pattern, and a 32-level MLC (commonly referred to as a PLC) can represent a five-bit bit pattern.

[0008] A read window, also known as the read window width, refers to the distance (e.g., in voltmeters) between neighboring Vt distributions at a specific localization error rate (BER). The read window budget (RWB) can refer to the cumulative value of read windows used for a set of programmed cells (e.g., one or more pages of a cell). For example, a TLC memory cell configured to store three data bits per cell can be programmed as one of eight different Vt distributions, each corresponding to a specific data state. In this example, the RWB could be the cumulative value (e.g., in voltmeters) of seven read windows between the eight Vt distributions. Summary of the Invention

[0009] One aspect of this disclosure provides a memory device comprising: a first latch for storing a first data bit; a second latch for storing a second data bit; a data line selectively connected to the first latch, the second latch, and a serially connected string of memory cells; and a controller configured to bias the data line during programming operations of selected memory cells connected to selected access lines of the serially connected string of memory cells, wherein the controller is further configured to: bias the data line to a first voltage level when the first data bit is equal to 0 and the second data bit is equal to 0; bias the data line to a second voltage level when the first data bit is equal to 1 and the second data bit is equal to 0; bias the data line to a third voltage level when the first data bit is equal to 0 and the second data bit is equal to 1; and bias the data line to a fourth voltage level when the first data bit is equal to 1 and the second data bit is equal to 1.

[0010] Another aspect of this disclosure provides a memory device comprising: a first latch for storing a first data bit; a second latch for storing a second data bit; a first node configured to receive a selected one of a first voltage level and a third voltage level greater than the first voltage level; a second node configured to receive a second voltage level greater than the third voltage level; a data line selectively connected to the first latch, the second latch, and a series-connected string of memory cells; a first switch selectively connected between the first node and the data line; a second switch selectively connected between the second node and the data line; and a controller configured to bias the data line during programming operations of selected memory cells connected to the selected access line in the series-connected string of memory cells, wherein the controller is further configured to: bias the data line during programming operations of the first data bit and the second data bit; the second data bit and the third data bit; the third data bit and the fourth data bit; the fourth data bit and the fifth data bit; the fifth data bit and the sixth data bit; the sixth data bit and the fifth data bit; the seventh data bit and the sixth data bit; the fifth data bit and the sixth data bit; the sixth data bit and the sixth data bit; the seventh data bit and the sixth data bit; the fifth data bit and the sixth data bit; the sixth data bit and the sixth data bit; the seventh data bit and the sixth data bit; the fifth data bit and the sixth data bit; the seventh data bit and the sixth data bit; the fifth data bit and the sixth data bit; the sixth data bit and the sixth data bit; the seventh data bit and the sixth data bit; the seventh data bit and the sixth data bit; the fifth data bit and the sixth data bit; the seventh data bit and the sixth data bit; the seventh data bit and the sixth data bit; the seventh data bit and the sixth data bit; the seventh data bit and the sixth data bit; the eighth ... eighth data bit and the sixth data bit; the seventh When the first data bit is 0 and the second data bit is 0, the first voltage level is applied to the first node, the first switch is turned on, and the second switch is turned off to bias the data line to the first voltage level; when the first data bit is 1 and the second data bit is 0, the first switch is turned off and the second switch is turned on to bias the data line to the second voltage level; when the first data bit is 0 and the second data bit is 1, the third voltage level is applied to the first node, the first switch is turned on, and the second switch is turned off to bias the data line to the third voltage level; and when the first data bit is 1 and the second data bit is 1, the first switch is turned off and the second switch is turned off to bias the data line to a fourth voltage level between the first voltage level and the third voltage level.

[0011] Another aspect of this disclosure provides a memory device comprising: a memory cell array including a plurality of serially connected memory cell strings; a plurality of data lines, wherein each of the plurality of serially connected memory cell strings is selectively electrically connected to a corresponding data line of the plurality of data lines; a plurality of access lines, each of the plurality of access lines being connected to a control gate of a corresponding memory cell of each of the plurality of serially connected memory cell strings; a page buffer connected to the plurality of data lines, wherein for each of the plurality of data lines, the page buffer includes: a corresponding first latch for storing a corresponding first data bit; a corresponding second latch for storing a corresponding second data bit; and a controller configured to connect to During programming operations to the corresponding memory cell of a selected access line among the plurality of access lines, each of the plurality of data lines is biased, wherein the controller is further configured for each of the plurality of data lines to: bias the corresponding data line to a first voltage level when the corresponding first data bit is equal to 0 and the corresponding second data bit is equal to 0; bias the corresponding data line to a second voltage level when the corresponding first data bit is equal to 1 and the corresponding second data bit is equal to 0; bias the corresponding data line to a third voltage level when the corresponding first data bit is equal to 0 and the corresponding second data bit is equal to 1; and bias the corresponding data line to a fourth voltage level when the corresponding first data bit is equal to 1 and the corresponding second data bit is equal to 1. Attached Figure Description

[0012] Figure 1 This is a simplified block diagram of a memory according to an embodiment, which communicates with a processor as part of an electronic system.

[0013] Figures 2A to 2C This can be used as a reference. Figure 1 A schematic diagram of a portion of the memory cell array in the described type of memory.

[0014] Figure 3 A group of memory cells of a TLC memory according to an embodiment is described.

[0015] Figure 4 This is a timing diagram depicting a portion of a programming operation that programs a selected TLC memory cell to a target threshold voltage, according to an embodiment.

[0016] Figure 5A and 5B A group of memory cells is depicted during a programming operation that programs selected memory cells to a target level, according to an embodiment.

[0017] Figure 6 It can be used as a reference. Figure 1 A schematic diagram of a portion of the page buffer used in the type of memory described.

[0018] Figure 7A and 7B It is a timing diagram depicting programming operations according to an embodiment.

[0019] Figures 8A to 8G This is a flowchart of a method for operating a memory according to an embodiment.

[0020] Figures 9A to 9G This is a flowchart of a method for operating a memory according to another embodiment.

[0021] Figure 10A and 10B This is a flowchart of a method for operating a memory according to another embodiment. Detailed Implementation

[0022] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate specific embodiments therein by means of illustration. Throughout the drawings, similar reference numerals describe substantially similar components. Other embodiments may be utilized without departing from the scope of this disclosure, and structural, logical, and electrical changes may be made. Therefore, the following detailed description should not be regarded in a limiting sense.

[0023] For example, as used herein, the term "semiconductor" can refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0024] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0025] This paper recognizes that even when values ​​are expected to be equal, the variability and precision of industrial processing and operation can still cause differences from their expected values. These variability and precision will generally depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then those values ​​are considered equal regardless of their resulting values.

[0026] Figure 1 This is a simplified block diagram illustrating communication between a first device in the form of a memory (e.g., a memory device) 100 and a second device in the form of a processor 130 as part of a third device in the form of an electronic system, according to one embodiment. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The processor 130 (e.g., a controller external to the memory device 100) may be a memory controller or other external host device.

[0027] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (collectively referred to as a word line), while memory cells in logical columns are typically selectively connected to the same data line (collectively referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed to be one of at least two target data states.

[0028] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 100, as well as outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0029] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to the command and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to an address. Control logic 116 may include an instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells in memory cell array 104, such as a reserved block of memory cells.

[0030] Control logic 116 may also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, such as that guided by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data may be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; subsequently, new data may be latched into cache register 118 from I / O control circuitry 112. During read operations, data may be transferred from cache register 118 to I / O control circuitry system 112 for output to external processor 130; subsequently, new data may be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 1(Not shown) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines of the memory cells connected to the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and control logic 116 to latch status information for output to the processor 130.

[0031] The memory device 100 receives control signals from the processor 130 at control logic 116 via control link 132. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received on control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0032] For example, commands can be received at the input / output (I / O) control circuitry 112 via I / O pins [7:0] of the I / O bus 134, and then written to the command register 124. Addresses can be received at the I / O control circuitry 112 via the input / output (I / O) pins [7:0] of the I / O bus 134, and then written to the address register 114. Data can be received at the I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and then written to the cache register 118. Data can then be written to the data register 120 for programming the memory cell array 104. In another embodiment, the cache register 118 can be omitted, and data can be written directly to the data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0033] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of the integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0034] Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0035] Figure 2A It can be, for example, as part of memory cell array 104 in reference Figure 1 A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the type of memory described. The memory array 200A includes access lines (e.g., word lines) 2020 to 2022. N And data lines (e.g., bit lines) 2040 to 204 M Access line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed on a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity to form a p-well, or n-type conductivity to form an n-well, for example.

[0036] The memory array 200A can be arranged in rows (each corresponding to an access line 202) and columns (each corresponding to a data line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended for storing data, and may also include other memory cells not intended for storing data, such as dummy memory cells. Dummy memory cells are generally not accessible to the user of the memory, and instead are usually incorporated into a series-connected string of memory cells to obtain well-known operational advantages.

[0037] Each memory cell 208 of the NAND string 206 may be connected in series between a select gate 210 (e.g., a field-effect transistor) and a select gate 212 (e.g., a field-effect transistor), wherein the select gate 210 is, for example, select gates 2100 to 210. M (For example, it can be one of the source-select transistors, often referred to as the select-gate-source transistor), with select-gate 212 being, for example, select-gate 2120 to 212. M (For example, one of the drain-select transistors, often referred to as the select-gate-drain transistor). Select-gate 2100 to 210 M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent multiple select gates connected in series, each selected gate configured in series to receive the same or independent control signals.

[0038] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0039] The drain of each select gate 212 can be connected to the data line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the data line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0040] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and data line 204 extend in a generally parallel plane. Alternatively, Figure 2AThe memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 extends substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the data line 204, and the plane containing the data line is substantially parallel to the plane containing the common source 216.

[0041] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that determines the data state of the memory cell (e.g., by a change in threshold voltage), and a control gate 236, such as Figure 2A As shown in the diagram. Data storage structure 234 may include both conductive and dielectric structures, while control gate 236 is typically formed of one or more conductive materials. In some cases, memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. Control gate 236 of memory cell 208 is connected to (and in some cases forms) access line 202.

[0042] A column of memory cells 208 may be a NAND string 206 or multiple NAND strings 206 selectively connected to a given data line 204. A row of memory cells 208 may consist of memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may (but does not necessarily) contain all memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given access line 202. For example, commonly connected to access line 202 N Furthermore, memory cells 208 selectively connected to even-numbered data lines 204 (e.g., data lines 2040, 2042, 2044, etc.) can be memory cells 208 that are physical pages (e.g., even-numbered memory cells), while being commonly connected to access lines 202. N Furthermore, the memory cells 208 selectively connected to the odd-numbered data lines 204 (e.g., data lines 2041, 2043, 2045, etc.) can be memory cells 208 of another physical page (e.g., odd-numbered memory cells). Although data lines 2043 to 2045 are not explicitly depicted in... Figure 2A However, it is obvious from the diagram that the data line 204 of the memory cell array 200A can be from data line 2040 to data line 204. MMemory cells 208 that are commonly connected to a given access line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given access line may be considered as physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower memory cell page) may be considered as a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to access lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing common access line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell.

[0043] Although discussing in conjunction with NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0044] Figure 2B As per reference Figure 1 Another schematic diagram of a memory cell array 200B, for example, which is part of a memory cell array 104 and can be used in a memory of the type described. Figure 2B The same numbered elements in the text correspond to about Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to data lines 2040 to 2046 via a select transistor 212 (e.g., which may be a drain select transistor, commonly referred to as a select gate drain). M And selectively connected to a common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected via selection lines 2150 to 215... KBias selectively activates specific select transistors 212, each connected to its corresponding data line 204, between the NAND string 206 and the data line 204. Select transistor 210 can be activated by biasing select line 214. Each access line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells commonly connected to each other via specific access lines 202 can be collectively referred to as a hierarchy.

[0045] A three-dimensional NAND memory array 200B may be formed on a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems for accessing the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel transistors and p-channel transistors formed on the same semiconductor substrate; this process is collectively referred to as CMOS or complementary metal-oxide-semiconductor. Although CMOS typically no longer utilizes a strictly metal-oxide-semiconductor construction due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0046] Figure 2C It can be, for example, as part of memory cell array 104 in reference Figure 1 Another schematic diagram of a portion of the memory cell array 200C used in the type of memory described. Figure 2C Elements with the same number in the middle correspond to, for example, those about Figure 2A The provided description. The memory cell array 200C may include, for example: Figure 2A The memory cell array 200A depicts a series-connected string of memory cells (e.g., a NAND string) 206, an access (e.g., a word) line 202, a data (e.g., a bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216. For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C. Figure 2C The NAND string 206 is divided into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may contain those NAND strings 206 that are commonly associated with a single select line 215 (e.g., select line 2150). The source 216 of memory cell block 250 may be associated with memory cell block 250. L The source 216 is the same as the source. For example, each memory cell block 2500 to 250 LThey can be selectively connected together to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 can be connected to memory cell blocks 2500 to 2500 respectively. L Access lines 202 and select lines 214 and 215 of any other memory cell blocks are not directly connected.

[0047] Data cable 2040 to 204 M It can be connected (e.g., selectively connected) to buffer portion 240, which may be part of a data buffer for memory. Buffer portion 240 may correspond to a memory plane (e.g., memory cell blocks 2500 to 250). L The buffer section 240 may include sensing circuitry for sensing the data value indicated on the corresponding data line 204. Figure 2C (Not shown in the text).

[0048] Although Figure 2C Each memory cell block 250 is depicted as having only one select line 215, but the memory cell block 250 may contain NAND strings 206 that are commonly associated with more than one select line 215. For example, the select line 2150 of the memory cell block 2500 may correspond to Figure 2B The selection line 2150 of the memory array 200B, and Figure 2C The memory cell blocks of the memory array 200C can further include... Figure 2B Selection line 2151 to 215 K The associated NAND strings 206. In such a memory cell block 250 having NAND strings 206 associated with multiple select lines 215, those NAND strings 206 typically associated with a single select line 215 may be referred to as memory cell sub-blocks. Each such memory cell sub-block may be selectively connected to the buffer section 240 in response to its respective select line 215.

[0049] Figure 3 A group of memory cells 300 for a memory according to an embodiment is depicted. For simplicity, Figure 3 and afterwards Figure 4The programming operations will be assumed to be for TLC memory cells, which are, for example, eight-level memory cells that use eight threshold voltage ranges to represent data states L0, L1, L2, L3, L4, L5, L6, and L7, with each threshold voltage range representing a bit pattern corresponding to three digits. Although the discussion refers to TLC memory cells, the programming operations performed on lower-density memory cells (e.g., SLC (two data states)) or higher-density memory cells (e.g., QLC (16 data states) or PLC (32 data states) memory cells) are equally applicable.

[0050] In this example, memory cell group 310 may be an erased memory cell representing the logical data value '111', memory cell group 311 may represent the logical data value '011', memory cell group 312 may represent the logical data value '001', memory cell group 313 may represent the logical data value '101', memory cell group 314 may represent the logical data value '100', memory cell group 315 may represent the logical data value '000', memory cell group 316 may represent the logical data value '010', and memory cell group 317 may represent the logical data value '110'. The rightmost digit may represent the lower page data of a memory cell having a threshold voltage within the threshold voltage range of its respective memory cell group, the middle digit may represent the upper page data of the memory cell, and the leftmost digit may represent additional page data of the memory cell. Although a specific example of binary representation is provided, embodiments may use other arrangements of bit patterns to represent various data states.

[0051] At 320, a read window is indicated between memory cell group 310 and memory cell group 311, which is the distance (e.g., in voltmeters) between the neighboring Vt distributions of memory cells representing data states L0 and L1. At 321, a read window is indicated between memory cell group 311 and memory cell group 312, which is the distance (e.g., in voltmeters) between the neighboring Vt distributions of memory cells representing data states L1 and L2. Similarly, at 322, 323, 324, 325, and 326, read windows are indicated between memory cell groups 312, 313, 314, 315, and 316 and memory cell groups 313, 314, 315, 316, and 317, respectively, which are the distances between the neighboring Vt distributions of memory cells representing data states L2, L3, L4, L5, L6, and L7. The read window budget (RWB) may refer to the cumulative value of the read windows used for a set of programmed cells (e.g., one or more pages of cells). In this example, RWB can be the cumulative value (e.g., in voltmeter form) of the seven reading windows 320 to 326 between the eight Vt distributions.

[0052] Figure 4 According to the description of the embodiment, selected TLC memory cells are programmed to target levels L0 to L7 (e.g., as shown in the example). Figure 3 This is a timing diagram of a portion of the programming operation (as shown in the figure). Once a selected memory cell has been programmed to its target level, further programming of the memory cell is disabled. Before time t0, the selected memory cells for programming are erased such that each selected memory cell has a threshold voltage corresponding to level L0. At time t0, a first programming pulse is applied to the selected access line (e.g., 236) connected to the control gate (e.g., 208) of the selected memory cell (e.g., 208). Figure 2A (202). After the first programming pulse, a programming verification operation can be performed to verify whether the target group of selected memory cells has been programmed to level L1 or L2. At time t1, a second programming pulse, for example higher than the first programming pulse, is applied to the selected access line connected to the control gate of the selected memory cell. After the second programming pulse, a programming verification operation can be performed to verify whether the target group of selected memory cells has been programmed to level L1 or L2.

[0053] At time t2, a third programming pulse, for example higher than the second programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the third programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L1, L2, or L3. At time t3, a fourth programming pulse, for example higher than the third programming pulse, is applied to the selected access line connected to the control gate of the selected memory cell. After the fourth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L2, L3, or L4. At time t4, a fifth programming pulse, for example higher than the fourth programming pulse, is applied to the selected access line connected to the control gate of the selected memory cell. After the fifth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L2, L3, L4, or L5.

[0054] At time t5, a sixth programming pulse, for example higher than the fifth programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the sixth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L3, L4, L5, or L6. At time t6, a seventh programming pulse, for example higher than the sixth programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the seventh programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L3, L4, L5, L6, or L7. At time t7, an eighth programming pulse, for example higher than the seventh programming pulse, can be applied to a selected access line connected to the control gate of the selected memory cell, and the process can be repeated until the selected memory cell has been programmed to its target level.

[0055] Figure 5A The memory cell group 500 is depicted as follows: after a specific programming pulse indicating a programming operation that programs a selected memory cell to a target level, as indicated by the memory cell group 502. The use of different voltage levels on the data line for programming enable may occur in a programming scheme called Selective Slow Programming Convergence (SSPC), in which memory cells closer to their respective predetermined data states are programmed more slowly (e.g., partially enabled for programming) compared to memory cells further away from their respective predetermined data states (e.g., fully enabled for programming), while receiving the same voltage level at their respective control gates. The target level may correspond to a minimum threshold voltage (PV) for the target level. 目标 504, which can be referred to as the final programming verification level for the target level. A first pre-programming verification level (PPV1) 506 can be selected to be less than the final programming verification level 504 to enable slow SSPC programming. A second pre-programming verification level (PPV2) 508 can be selected to be less than the slow SSPC programming verification level 506 to enable fast SSPC programming.

[0056] Following a specific programming pulse, a programming verification operation is performed to sense the threshold voltage of each memory cell within the memory cell group 500. Memory cells having a threshold voltage less than the second pre-programming verification level 508, as indicated, for example at 510, are biased for non-SSPC programming (e.g., programming is fully enabled). Memory cells having a threshold voltage between the second pre-programming verification level 508 and the first pre-programming verification level 506, as indicated, for example at 512, are biased for fast SSPC programming (e.g., programming at a first rate is partially enabled) because the memory cells are within the fast SSPC range. Memory cells having a threshold voltage between the first pre-programming verification level 506 and the final programming verification level 504, as indicated, for example at 514, are biased for slow SSPC programming (e.g., programming at a second rate less than the first rate is partially enabled) because the memory cells are within the slow SSPC range. Memory cells having a threshold voltage greater than the final programming verification level 504, as indicated, for example at 516, are prevented from further programming.

[0057] like Figure 5B As illustrated, when each memory cell within a group of memory cells 500 is biased for non-SSPC programming, fast SSPC programming, slow SSPC programming, or programming disabled, a subsequent programming pulse is applied to the group of memory cells 500 to increase the threshold voltage of the memory cell to a target level as indicated by the group of memory cells 502. The subsequent programming pulse may immediately follow a specific programming pulse. When memory cell 510 is biased for non-SSPC programming, the threshold voltage of memory cell 510 may be increased above the final programming verification level 504 in response to a subsequent programming pulse, as indicated by 520. When memory cell 512 is biased for fast SSPC programming, the threshold voltage of memory cell 512 may be increased above the final programming verification level 504 in response to a subsequent programming pulse, as indicated by 522. When memory cell 514 is biased for slow SSPC programming, the threshold voltage of memory cell 514 may be increased above the final programming verification level 504 in response to a subsequent programming pulse, as indicated by 524. Following a subsequent programming pulse, a programming verification operation is performed to sense the threshold voltage of each memory cell within the memory cell group 502. In this example, all memory cells have a threshold voltage greater than the final programming verification level 504 and are prohibited from further programming.

[0058] Memory cells can be biased for fast SSPC programming by biasing the data lines connected to the memory cell to a fast SSPC level during a programming pulse. Memory cells can be biased for slow SSPC programming by biasing the data lines connected to the memory cell to a slow SSPC level during a programming pulse. Memory cells can be biased for non-SSPC programming by biasing the data lines connected to the memory cell to a non-SSPC level during a programming pulse. Memory cells can be disabled for programming by biasing the data lines connected to the memory cell to an inhibit level during a programming pulse. The fast SSPC level (e.g., 0.75V) can be greater than the non-SSPC level (e.g., 0V). The slow SSPC level (e.g., 1.5V) can be greater than the fast SSPC level and less than the inhibit level (e.g., 3V). By using four data line bias levels during programming, the number of programming pulses required to program a selected memory cell to its target level can be reduced compared to the number of programming pulses required to program a selected memory cell to its target level using fewer than four data line bias levels, thereby reducing programming time. Additionally, by using four data line bias levels, programming time can be reduced without reducing the read window budget.

[0059] Figure 6 It can be used as a reference. Figure 1 A schematic diagram of a portion of a page buffer 600 used in a memory of the described type. The page buffer 600 may be... Figure 2C This is a portion of the buffer section 240. The page buffer 600 includes a selected access line (e.g., a word line) 202, selected memory cells 208 of a serially connected string of memory cells (not shown), and a selected data line (e.g., a bit line) 204. The selected access line 202 is connected to the control gate of the selected memory cell 208. The source of the selected memory cell 208 is connected to a common source 216 (e.g., via other memory cells in the serially connected string of memory cells and a corresponding select gate 210). The drain of the selected memory cell 208 is connected to the selected data line 204 (e.g., via other memory cells in the serially connected string of memory cells and a corresponding select gate 212).

[0060] Page buffer 600 also includes transistors 602, 603, 609, 610, 613, 617, 622, 623, 627, 630, 631, 634, 642, 646, 662, 670, 678, and 696, a sensing capacitor 654, a sensing amplifier latch 686, a first latch 691, and a second latch 692. Transistor 622 may be a p-channel metal-oxide-semiconductor (PMOS) transistor, while transistors 602, 603, 609, 610, 613, 617, 623, 627, 630, 631, 634, 642, 646, 662, 670, 678, and 696 may be n-channel metal-oxide-semiconductor (NMOS) transistors. The sense amplifier latch 686 includes inverters 683 and 684 and transistors 687 and 688 (e.g., NMOS transistors). Data line 204 is connected to one side of the source-drain path of transistor 602 and one side of the source-drain path of transistor 631. The gate of transistor 631 is connected to the SRC_GATE control signal path 633. The other side of the source-drain path of transistor 631 is connected to the common source 216. The gate of transistor 602 is connected to the DW_GATE control signal path 604. The other side of the source-drain path of transistor 602 is connected to one side of the source-drain path of transistor 610 via signal path 606. The gate of transistor 610 is connected to the BLCLAMP control signal path 612. The other side of the source-drain path of transistor 610 is connected via signal path 614 to one side of the source-drain path of transistor 630, one side of the source-drain path of transistor 634, and one side of the source-drain path of transistor 646. The gate of transistor 630 is connected to the BLCLAMP2 control signal path 632. The other side of the source-drain path of transistor 630 is connected via signal path 626 to one side of the source-drain path of transistor 622. The gate of transistor 622 is connected via the BL_SA_OUT signal path 690 to one side of the source-drain path of transistor 617 and the gate of transistor 642. The gate of transistor 617 is connected to the SAB_BL_PRE control signal path 619. The other side of the source-drain path of transistor 617 is connected via the SA_OUT signal path 621 to the input of inverter 683, the output of inverter 684, and one side of the source-drain path of transistor 687. The other side of the source-drain path of transistor 622 is connected to a power node (e.g., VREG2) 618. The gate of transistor 634 is connected to the EN_DATA control signal path 636. The other side of the source-drain path of transistor 634 is connected to one side of the source-drain path of transistor 642 via signal path 638. The other side of the source-drain path of transistor 642 is connected to a power node (e.g., VREG0) 639.

[0061] The gate of transistor 646 is connected to the TC_ISO control signal path 648. The other side of the source-drain path of transistor 646 is connected via the TC signal path 650 to one side of the sensing capacitor 654, one side of the source-drain path of transistor 662, and the gate of transistor 678. The other side of the sensing capacitor 654 is connected to the sensing capacitor bias node (e.g., boost node) 658. The gate of transistor 662 is connected to the BLC1 control signal path 664. The other side of the source-drain path of transistor 662 is connected via the TDC_INT signal path 666 to one side of the source-drain path of transistor 670, the other side of the source-drain path of transistor 687, one side of the source-drain path of transistor 688, one side of the source-drain path of transistor 603, one side of the source-drain path of transistor 609, one side of the source-drain path of transistor 696, and the gate of transistor 623. The gate of transistor 670 is connected to the SEN control signal path 672. The other side of the source-drain path of transistor 670 is connected to one side of the source-drain path of transistor 678 via signal path 674. The other side of the source-drain path of transistor 678 is connected to a source bias node (e.g., SRC_GND) 682. Transistor 678 may be referred to as a sensing transistor.

[0062] The gate of transistor 687 in sense amplifier latch 686 is connected to the DRST_SA control signal path 675. The gate of transistor 688 is connected to the DST_SA signal path 676. The other side of the source-drain path of transistor 688 is connected to the output of inverter 683 and the input of inverter 684 via signal path 677. The control input of inverter 683 is connected to the SEN_SAB control signal path 685. The control input of inverter 684 is connected to the LAT_SAB control signal path 689.

[0063] The gate of transistor 603 is connected to the TDCINT_DIS control signal path 605. The other side of the source-drain path of transistor 603 is connected to a common or ground (e.g., GND) node 607. The gate of transistor 609 is connected via the DATA_TRANSFER signal path 693 to the other side of the source-drain path of transistor 696, one side of the source-drain path of transistor 623, the first latch 691, and the second latch 692. The other side of the source-drain path of transistor 609 is connected via signal path 611 to one side of the source-drain path of transistor 613. The gate of transistor 613 is connected to the EN_SA control signal path 615. The other side of the source-drain path of transistor 613 is connected to a common or ground node 607. The gate of transistor 696 is connected to the BLC2 control signal path 697. The other side of the source-drain path of transistor 623 is connected via signal path 625 to one side of the source-drain path of transistor 627. The gate of transistor 627 is connected to the EN_LATCH control signal path 629. The other side of the source-drain path of transistor 627 is connected to the common or ground node 607.

[0064] Control logic (e.g., Figure 1 116) can be connected to the SRC_GATE control signal path 633, DW_GATE control signal path 604, BLCLAMP control signal path 612, BLCLAMP2 control signal path 632, EN_DATA control signal path 636, TC_ISO control signal path 648, BLC1 control signal path 664, SEN control signal path 672, SAB_BL_PRE control signal path 619, LAT_SAB control signal path 689, SEN_SAB control signal path 685, DRST_SA control signal path 675, DST_SA control signal path 676, TDCINT_DIS control signal path 605, EN_SA control signal path 615, BCL2 control signal path 697, and EN_LATCH control signal path 629 to control the operation of page buffer 600. The control logic can activate transistor 631 to selectively connect data line 204 to common source 216. The control logic can activate transistor 602 to selectively connect data line 204 to signal path 606. The control logic can activate transistor 610 to selectively connect signal path 606 to signal path 614. The control logic can activate transistor 630 to selectively connect signal path 614 to signal path 626. The control logic can activate transistor 634 to selectively connect signal path 614 to signal path 638.

[0065] Control logic can activate transistor 617 to selectively connect the SA_OUT signal path 621 to the BL_SA_OUT signal path 690. Control logic can activate transistor 646 to selectively connect signal path 614 to the TC signal path 650. Control logic can activate transistor 662 to selectively connect the TC signal path 650 to the TDC_INT signal path 666. Control logic can activate transistor 670 to selectively connect the TDC_INT signal path 666 to signal path 674. Control logic can activate transistor 687 of the sense amplifier latch 686 to selectively connect the TDC_INT signal path 666 to the SA_OUT signal path 621. Control logic can activate transistor 688 to selectively connect the TDC_INT signal path 666 to signal path 677. Control logic can control inverter 683 to latch the state of the sensed selected memory cell into the sense amplifier latch 686. The control logic controls inverter 684 to output a latched state from sense amplifier latch 686. The control logic activates transistor 603 to selectively connect TDC_INT signal path 666 to common or ground node 607. The control logic activates transistor 696 to selectively connect TDC_INT signal path 666 to DATA_TRANSFER signal path 693. The control logic activates transistor 613 to selectively connect signal path 611 to common or ground node 607. The control logic activates transistor 627 to selectively connect signal path 625 to common or ground node 607.

[0066] Page buffer 600 can be used to sense the state of selected memory cell 208 during a read operation or a program verification operation and latch the sensed state in sense amplifier latch 686. Page buffer 600 can also be used to program a target state to selected memory cell 208 based on the state of sense amplifier latch 686, the state of first latch 691, the state of second latch 692, and / or the state of additional latches (not shown). After each program verification operation, the first data bit stored in first latch 691 and the second data bit stored in second latch 692 can be updated to indicate whether data line 204 is biased for non-SSPC programming, fast SSPC programming, slow SSPC programming, or programming disabled during the next programming pulse. See below for reference. Figure 7A and 7B The programming operation of programming the selected memory cell 208 to the target level is described in more detail.

[0067] Biasing the data line 204 for non-SSPC programming, fast SSPC programming, slow SSPC programming, or disabled programming based on the data bits stored in the first latch 691 and the second latch 692 can be implemented in three stages as shown in the following three tables. In each table, the first latch field indicates the data bits stored in the first latch 691, the second latch field indicates the data bits stored in the second latch 692, and the BL mode field indicates whether the data line is biased for programming, disabled, slow SSPC, or fast SSPC mode. Additionally, the BL level field indicates the voltage level applied to the data line 204, the BL_SA_OUT field indicates the state of the signal on the BL_SA_OUT signal path 690, the SA_OUT field indicates the state of the signal on the SA_OUT signal path 621, and the origin field indicates the source of the BL_SA_OUT state or the SA_OUT state. In the origin field, L1 refers to the first latch 691 and L2 refers to the second latch 692. In the BL level field, SSPC_S refers to the voltage level used to bias data line 204 for slow SSPC programming, and SSPC_F refers to the voltage level used to bias data line for fast SSPC programming.

[0068] Table 1: Stage 1 of Programming Operation

[0069] First latch Second latch BL mode BL level BL_SA_OUT origin 0 0 programming VSS 1 L1 1 0 prohibit VCC 0 L1 0 1 Slow SSPC VSS 1 L1 1 1 Fast SSPC VSS 1 L1

[0070] Table 2: Stage 2 of Programming Operation

[0071] First latch Second latch BL mode BL level BL_SA_OUT origin 0 0 programming VSS 1→0 L1 / L2 1 0 prohibit VCC 0 L1 / L2 0 1 Slow SSPC SSPC_S 1 L1 / L2 1 1 Fast SSPC VSS 1 L1 / L2

[0072] Table 3: Stage 3 of Programming Operation

[0073] First latch Second latch BL mode BL level SA_OUT origin 0 0 programming VSS 0 L1 / L2 1 0 prohibit VCC 1 L1 / L2 0 1 Slow SSPC SSPC_S 1 L1 / L2 1 1 Fast SSPC SSPC_F 1 L1 / L2

[0074] Figure 7A This is a timing diagram 700A depicting programming operations according to an embodiment. Figure 7A In the middle, trace 702 can represent Figure 6 The voltage level on data line 204. Trace 704 can represent the voltage applied to... Figure 6 The voltage level of node 639 in VREG0. Trace 706 can represent Figure 6 The TC_ISO control signal on signal path 648. Trace 708 can represent Figure 6 The BLCLAMP2 control signal on signal path 632. Trace 710 can represent... Figure 6 The SAB_BL_PRE control signal on signal path 619. In other embodiments, trace 706 may represent... Figure 6The BLC1 control signal on signal path 664 or the DRST_SA control signal on signal path 675.

[0075] At time t0, Phase 1 of the programming operations, as outlined in Table 1 above, begins. During Phase 1, GND is applied to the VREG0 node. GND is applied to the TC_ISO control signal path to disconnect signal path 614 from TC signal path 650. The voltage applied to the BLCLAMP2 control signal path is increased from GND to a voltage (e.g., VSG) sufficient to activate transistor 630 to connect signal path 614 to signal path 626. A voltage (e.g., VSG) sufficient to activate transistor 617 is applied to the SAB_BL_PRE control signal path to connect SA_OUT signal path 621 to BL_SA_OUT signal path 690. Data bits stored in the first latch 691 and the second latch 692 determine the state of the SA_OUT signal on signal path 621 and therefore the state of the BL_SA_OUT signal on signal path 690. As indicated by Table 1, BL_SA_OUT is a logic "1" (e.g., VCC) for programmed, slow SSPC, and fast SSCBL modes, and a logic "0" (e.g., GND) for disabled BL mode.

[0076] In response to a first latch storing a data bit equal to 0 and a second latch storing a data bit equal to 0 indicating a programming BL mode, data line 204 is biased to a first voltage level (e.g., VSS or GND) as indicated in 720. In response to a first latch storing a data bit equal to 0 and a second latch storing a data bit equal to 1 indicating a slow SSPC BL mode, data line 204 is also biased to the first voltage level as indicated in 720. In response to a first latch storing a data bit equal to 1 and a second latch storing a data bit equal to 1 indicating a fast SSPC BL mode, data line 204 is also biased to the first voltage level as indicated in 720. Data line 204 is biased to the first voltage level via VREG0 node 639 through activated transistors 602, 610, 634, and 642.

[0077] In response to the first latch storing a data bit equal to 1 and the second latch storing a data bit equal to 0 indicating that BL mode is disabled, data line 204 is biased to a second voltage level (e.g., VCC) as indicated in 722. Data line 204 is biased to the second voltage level via VREG2 node 618 (where VCC is applied to VREG2 node 618) through activated transistors 602, 610, 630 and 622.

[0078] At time t1, Phase 1 of the programming operation is completed and Phase 2 of the programming operation begins, as outlined in Table 2 above. During Phase 2, a third voltage level (e.g., SSPC_S) may be applied to the VREG0 node. GND remains applied to the TC_ISO control signal path. The voltage applied to the BLCLAMP2 control signal path decreases to a voltage (e.g., GND) sufficient to deactivate transistor 630 to disconnect signal path 614 from signal path 626. A voltage sufficient to activate transistor 617 (e.g., VSG) remains applied to the SAB_BL_PRE control signal path. During Phase 2, as indicated in Table 2, BL_SA_OUT changes from logic "1" to logic "0" for the programming BL mode. For the disabled, slow SSPC, and fast SSPC BL modes, BL_SA_OUT remains constant. Therefore, for the programming and fast SSPC BL modes, data line 204 is floated above GND as indicated in 724. For the slow SSCBL mode, data line 204 is biased to SSPC_S as indicated in 726. For the disabled BL mode, data line 204 is floated above VCC as indicated in 728. The increase in the voltage level of the VREG0 node to SSPC_S may be delayed (TDELAY) between phase 3 of the programming operation at time t2 to mitigate capacitive coupling between data line 204 and adjacent data lines.

[0079] At time t2, phase 2 of the programming operation is completed and phase 3 of the programming operation begins, as outlined in Table 3 above. During phase 3, SSPC_S may remain applied to the VREG0 node. For the fast SSPC BL mode, a fourth voltage level (e.g., SSPC_F) plus the threshold voltage (VTN) of transistor 646 may be applied to the TC_ISO control signal path. The voltage applied to the BLCLAMP2 control signal path is maintained at a voltage sufficient to deactivate transistor 630 (e.g., GND). The voltage applied to the SAB_BL_PRE control signal path is reduced to a voltage sufficient to deactivate transistor 617 (e.g., GND) to disconnect the BL_SA_OUT signal path 690 from the SA_OUT signal path 621. During phase 3, as indicated by Table 2, SA_OUT is logic "0" for the programming BL mode and logic "1" for the disabled, slow SSPC, and fast SSPC BL modes. Therefore, for the programmed BL mode, as indicated in 730, the data line 204 is biased to a first voltage level VSS or GND via the sense amplifier latch 686. For the slow SSPC BL mode, the data line 204 remains biased to a third voltage level SSPC_S. For the disabled BL mode, the data line 204 remains floating at a second voltage level VCC. For the fast SSPC mode, as indicated in 732, the data line 204 is biased to a fourth voltage level SSPC_F via the sense amplifier latch 686 and transistor 646.

[0080] Figure 7B It is a timing diagram 700B depicting programming operations according to other embodiments. Figure 7B The programming operations described herein can be used to reduce capacitive coupling between data lines. (Except for...) Figure 7A Outside of traces 702, 704, 706, 708, and 710, Figure 7B The middle trace line 712 can represent Figure 6 The BLCLAMP control signal on signal path 612. In other embodiments, trace 712 may represent... Figure 6The EN_DATA control signal is applied to signal path 636. At time t0, phase 1 of the programming operation begins. During phase 1, GND is applied to the VREG0 node. GND is applied to the TC_ISO control signal path to disconnect signal path 614 from TC signal path 650. The voltage applied to the BCLAMP control signal path and the BLCLAMP2 control signal path is increased from GND to a voltage (e.g., VSG) sufficient to activate transistors 610 and 630 to connect signal path 606 to signal path 626. A voltage (e.g., VSG) sufficient to activate transistor 617 is applied to the SAB_BL_PRE control signal path to connect SA_OUT signal path 621 to BL_SA_OUT signal path 690. Data bits stored in the first latch 691 and the second latch 692 determine the state of the SA_OUT signal on signal path 621 and therefore the state of the BL_SA_OUT signal on signal path 690.

[0081] In response to a first latch storing a data bit equal to 0 and a second latch storing a data bit equal to 0 indicating a programming BL mode, data line 204 is biased to a first voltage level (e.g., VSS or GND) as indicated in 740. In response to a first latch storing a data bit equal to 0 and a second latch storing a data bit equal to 1 indicating a slow SSPC BL mode, data line 204 is also biased to the first voltage level as indicated in 740. In response to a first latch storing a data bit equal to 1 and a second latch storing a data bit equal to 1 indicating a fast SSPC BL mode, data line 204 is also biased to the first voltage level as indicated in 740. Data line 204 is biased to the first voltage level via VREG0 node 639 through activated transistors 602, 610, 634, and 642.

[0082] In response to the first latch storing a data bit equal to 1 and the second latch storing a data bit equal to 0 indicating that BL mode is disabled, the data line level is biased to a second voltage level (e.g., VCC) as indicated in 742. The data line 204 is biased to the second voltage level via VREG2 node 618 (where VCC is applied to VREG2 node 618) through activated transistors 602, 610, 630 and 622.

[0083] At time t1, phase 1 of the programming operation is completed and phase 2 of the programming operation begins. During phase 2, VCC may be applied to the VREG0 node. GND remains applied to the TC_ISO control signal path. The voltage applied to the BLCLAMP2 control signal path is reduced to a voltage (e.g., GND) sufficient to deactivate transistor 630 to disconnect signal path 614 from signal path 626. The voltage applied to the BLCLAMP control signal path is reduced to voltage SSPC+VTN, which may be equal to voltage level SSPC_F plus the threshold voltage of transistor 610. A voltage sufficient to activate transistor 617 (e.g., VSG) remains applied to the SAB_BL_PRE control signal path. Therefore, for programming and fast SSPC BL mode, data line 204 is floated to GND as indicated in 744. For slow SSPC BL mode, data line 204 is biased to SSPC as indicated in 746. For disabled BL mode, data line 204 is floated to VCC as indicated in 748. The increase in voltage level to VCC at the VREG0 node may be delayed (TDELAY) between phase 3 of the programming operation at time t2 to reduce capacitive coupling between data line 204 and adjacent data lines.

[0084] At time t2, phase 2 of the programming operation is completed and phase 3 of the programming operation begins. During phase 3, VCC may be maintained at the VREG0 node. For the fast SSPC BL mode, SSPC_F plus the threshold voltage (VTN) of transistor 646 may be applied to the TC_ISO control signal path. The voltage applied to the BLCLAMP2 control signal path is maintained at a voltage sufficient to deactivate transistor 630 (e.g., GND). The voltage applied to the BLCLAMP control signal path may be increased to SSPC_S plus the threshold voltage (VTN) of transistor 610. The voltage applied to the SAB_BL_PRE control signal path is decreased to a voltage sufficient to deactivate transistor 617 (e.g., GND) to disconnect the BL_SA_OUT signal path 690 from the SA_OUT signal path 621. Therefore, for the programming BL mode, as indicated at 750, data line 204 is biased to VSS or GND via the sense amplifier latch 686. For slow SSPC BL mode, data line 204 is biased to SSPC_S as indicated in 752. For disabled BL mode, data line 204 remains floating at VCC. For fast SSPC mode, data line 204 is biased to SSPC_F via sense amplifier latch 686 and transistor 646 as indicated in 754.

[0085] Figures 8A to 8G This is a flowchart of a method 800 for operating a memory according to an embodiment. Method 800 may at least partially correspond to Figures 6 to 7B For example, Figures 8A to 8G This can represent a method of programming one or more memory cells, such as logical pages of memory cells. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0086] Method 800 may be implemented within a memory device (e.g., 100), the memory device comprising: a first latch (e.g., 691) for storing a first data bit; a second latch (e.g., 692) for storing a second data bit; a data line (e.g., 204) selectively connected to the first latch, the second latch, and a serially connected string of memory cells (e.g., 206); and a controller (e.g., 116) configured to bias the data line during programming operations of selected memory cells connected to a selected access line (e.g., 202) of the serially connected string of memory cells, as previously at least referred to Figures 1 to 2C And 6 are described. For example... Figure 8A As shown in 802, the controller can bias the data line to a first voltage level when the first data bit is equal to 0 and the second data bit is equal to 0. In 804, the controller can bias the data line to a second voltage level when the first data bit is equal to 1 and the second data bit is equal to 0. In 806, the controller can bias the data line to a third voltage level when the first data bit is equal to 0 and the second data bit is equal to 1. In 808, the controller can bias the data line to a fourth voltage level when the first data bit is equal to 1 and the second data bit is equal to 1.

[0087] The first voltage level may be lower than the second voltage level, the third voltage level may be between the first and second voltage levels, and the fourth voltage level may be between the first and third voltage levels. The first voltage level may be a programming voltage level (e.g., VSS), the second voltage level may be an inhibit voltage level (e.g., VCC), the third voltage level may be a slow selective slow programming convergence voltage level (e.g., SSPC_S), and the fourth voltage level may be a fast selective slow programming convergence voltage level (e.g., SSPC_F). In one embodiment, the third voltage level may be at halfway between the first and second voltage levels, and the fourth voltage level may be at halfway between the first and third voltage levels.

[0088] Figure 8BAdditional details are provided regarding the implementation by the controller under the condition that the first data bit is equal to 0 and the second data bit is equal to 0, according to the embodiment. At 810, the controller may further bias the data line to a first voltage level in the first stage. At 812, the controller may further float the data line in a second stage following the first stage. At 814, the controller may bias the data line to the first voltage level in a third stage following the second stage.

[0089] Figure 8C Additional details are provided regarding what the controller can implement according to the embodiment when the first data bit is equal to 1 and the second data bit is equal to 0. At 816, the controller may further bias the data line to a second voltage level in the first phase. At 818, the controller may further allow the data line to float in a second phase following the first phase.

[0090] Figure 8D Additional details are provided regarding what the controller can implement according to the embodiment when the first data bit is equal to 0 and the second data bit is equal to 1. At 820, the controller may further bias the data line to a first voltage level in the first stage. At 822, the controller may further bias the data line to a third voltage level in a second stage following the first stage.

[0091] Figure 8E Additional details are provided regarding implementation by the controller according to another embodiment, where the first data bit is equal to 0 and the second data bit is equal to 1. At 824, the controller may further bias the data line to a first voltage level in the first stage. At 826, the controller may further bias the data line to a fourth voltage level in a second stage following the first stage. At 828, the controller may further bias the data line to a third voltage level in a third stage following the second stage.

[0092] Figure 8F Additional details are provided regarding the implementation by the controller according to the embodiment, where the first data bit is equal to 1 and the second data bit is equal to 1. At 830, the controller may further bias the data line to a first voltage level in the first stage. At 832, the controller may further float the data line in a second stage following the first stage. At 834, the controller may further bias the data line to a fourth voltage level in a third stage following the second stage.

[0093] like Figure 8G As illustrated in Figure 836, the controller can further apply programming pulses to selected access lines when the data lines are biased to a first voltage level, a second voltage level, a third voltage level, or a fourth voltage level.

[0094] Figures 9A to 9G This is a flowchart of a method 900 for operating a memory according to an embodiment. Method 900 may at least partially correspond to... Figures 6 to 7B For example, Figures 9A to 9G This can represent a method of programming one or more memory cells, such as logical pages of memory cells. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0095] Method 900 can be implemented within a memory device (e.g., 100), the memory device comprising: a first latch (e.g., 691) for storing a first data bit; a second latch (e.g., 692) for storing a second data bit; a first node (e.g., 639) configured to receive a selected one of a first voltage level and a third voltage level greater than the first voltage level; a second node (e.g., 618) configured to receive a second voltage level greater than the third voltage level; and a data line (e.g., 204) for selecting... The data line is selectively connected to a first latch, a second latch, and a serially connected string of memory cells (e.g., 206); a first switch (e.g., transistor 642) selectively connected between a first node and a data line; a second switch (e.g., transistor 622) selectively connected between a second node and a data line; and a controller (e.g., 116) configured to bias the data line during programming operations of selected memory cells connected to selected access lines (e.g., 202) of the serially connected string of memory cells, as previously at least referenced. Figures 1 to 2C And 6 are described.

[0096] like Figure 9A As illustrated in Figure 902, the controller can apply a first voltage level to the first node, turn on the first switch, and turn off the second switch to bias the data line to the first voltage level when the first data bit is equal to 0 and the second data bit is equal to 0. In Figure 904, the controller can turn off the first switch and turn on the second switch to bias the data line to the second voltage level when the first data bit is equal to 1 and the second data bit is equal to 0. In Figure 906, the controller can apply a third voltage level to the first node, turn on the first switch, and turn off the second switch to bias the data line to the third voltage level when the first data bit is equal to 0 and the second data bit is equal to 1. In Figure 908, the controller can turn off the first switch and turn off the second switch to bias the data line to a fourth voltage level between the first and third voltage levels when the first and second data bits are both equal to 1.

[0097] Figure 9BAdditional details are provided regarding what can be implemented by the controller according to the embodiment when the first data bit is equal to 0 and the second data bit is equal to 0. At 910, the controller may further disconnect the first switch and allow the data line to float when the data line is biased to a first voltage level.

[0098] The memory device implementing method 900 may further include a sense amplifier latch (e.g., 686) selectively connected to a data line. Figure 9C Additional details are provided regarding what can be implemented by the controller according to the embodiment when the first data bit is equal to 0 and the second data bit is equal to 0. In 912, the controller may further connect the data line to the sense amplifier latch to maintain the data line at the first voltage level when the data line is floating.

[0099] Figure 9D Additional details are provided regarding what can be implemented by the controller according to the embodiment when the first data bit is equal to 1 and the second data bit is equal to 0. In 914, the controller may further float the data line when it is biased to a second voltage level.

[0100] The memory device implementing method 900 may further include a transistor (e.g., 646) connected between a data line and a sense amplifier latch. Figure 9E Additional details are provided regarding the implementation by the controller under the condition that the first data bit is equal to 1 and the second data bit is equal to 1, according to the embodiment. At 916, the controller may further apply a fourth voltage level plus the threshold voltage of the transistor to the control gate of the transistor such that the data line is biased to the fourth voltage level via the sense amplifier and the transistor.

[0101] The memory device implementing method 900 may further include a transistor (e.g., 610) connected between a data line and a sense amplifier latch. Figure 9F Additional details are provided regarding the implementation by the controller according to the embodiment, where the first data bit is equal to 0 and the second data bit is equal to 1. At 918, the controller may further apply a fifth voltage level to the control gate of the transistor before biasing the data line to the third voltage level, such that the data line is biased to the fourth voltage level. At 920, the controller may further apply a sixth voltage level, greater than the fifth voltage level, to the control gate of the transistor to bias the data line to the third voltage level.

[0102] like Figure 9G As illustrated in Figure 922, the controller can further apply programming pulses to selected access lines when the data lines are biased to a first voltage level, a second voltage level, a third voltage level, or a fourth voltage level.

[0103] Figure 10A and 10BThis is a flowchart of a method 1000 for operating a memory according to an embodiment. Method 1000 may at least partially correspond to Figures 6 to 7B For example, Figure 10A and 10B This can represent a method of programming one or more memory cells, such as logical pages of memory cells. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0104] Method 1000 can be implemented within a memory device (e.g., 100), the memory device comprising: a memory cell array (e.g., 104) including a plurality of serially connected memory cell strings (e.g., 206); a plurality of data lines (e.g., 204), wherein each of the plurality of serially connected memory cell strings is selectively electrically connected to a corresponding data line among the plurality of data lines; a plurality of access lines (e.g., 202), each of the plurality of access lines being connected to a control gate (e.g., 236) of a corresponding memory cell (e.g., 208) of each of the plurality of serially connected memory cell strings; and a page buffer (e.g., 240) connected to the plurality of data lines. For each of the plurality of data lines, the page buffer may include: a corresponding first latch (e.g., 691) for storing a corresponding first data bit; and a corresponding second latch (e.g., 692) for storing a corresponding second data bit. The memory device may also include a controller (e.g., 116) configured to bias each of the plurality of data lines during programming operations of a corresponding memory cell connected to a selected access line among the plurality of access lines. The memory cell array may include a TLC memory cell array, a QLC memory cell array, or a PLC memory cell array. The memory cell array may include a three-dimensional NAND memory array.

[0105] like Figure 10A As illustrated in diagram 1002, the controller can bias the corresponding data line to a first voltage level when the corresponding first data bit is equal to 0 and the corresponding second data bit is equal to 0. In diagram 1004, the controller can bias the corresponding data line to a second voltage level when the corresponding first data bit is equal to 1 and the corresponding second data bit is equal to 0. In diagram 1006, the controller can bias the corresponding data line to a third voltage level when the corresponding first data bit is equal to 0 and the corresponding second data bit is equal to 1. In diagram 1008, the controller can bias the corresponding data line to a fourth voltage level when the corresponding first data bit is equal to 1 and the corresponding second data bit is equal to 1.

[0106] The first voltage level may be lower than the second voltage level, the third voltage level may be between the first and second voltage levels, and the fourth voltage level may be between the first and third voltage levels. The first voltage level may be a programming voltage level, the second voltage level may be an inhibiting voltage level, the third voltage level may be a slow selective slow programming convergence voltage level, and the fourth voltage level may be a fast selective slow programming convergence voltage level. In one embodiment, the third voltage level may be located at halfway between the first and second voltage levels, and the fourth voltage level may be located at halfway between the first and third voltage levels.

[0107] like Figure 10B As illustrated in 1010, the controller can further apply a programming pulse to the selected access line when each corresponding data line is biased to a first voltage level, a second voltage level, a third voltage level, or a fourth voltage level. In 1012, the controller can further sense a threshold voltage for each corresponding memory cell connected to the selected access line. In 1014, the controller can further respond to a sensed threshold voltage of the corresponding memory cell being less than a first programming verification level (e.g., ...). Figure 5A (PPV2), for the corresponding data line connected to the corresponding memory cell, the corresponding first data bit is set to equal to 0 and the corresponding second data bit is set to equal to 0. In 1016, the controller may further respond to the sensed threshold voltage of the corresponding memory cell at a first programming verification level and a second programming verification level greater than the first programming verification level (e.g., ...). Figure 5A Between PPV1, for the corresponding data line connected to the corresponding memory cell, the corresponding first data bit is set to equal to 1 and the corresponding second data bit is set to equal to 1. At 1018, the controller may further respond to the sensed threshold voltage of the corresponding memory cell at a second programming verification level and a final programming verification level greater than the second programming verification level (e.g., ...). Figure 5A PV 目标 Between 1020 and 1020, the controller may further respond to a sensed threshold voltage of the corresponding memory cell being greater than the final programming verification level by setting the corresponding first data bit to 1 and the corresponding second data bit to 0 for the corresponding data line connected to the corresponding memory cell.

[0108] in conclusion

[0109] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement that achieves the same purpose can be calculated to replace the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory device comprising: The first latch is used to store the first data bit; The second latch is used to store the second data bit; Data lines, which are selectively connected to the first latch, the second latch, and a series-connected string of memory cells; as well as A controller configured to bias the data line during programming operations of selected memory cells connected to selected access lines in the serially connected string of memory cells. The controller is further configured to: When the first data bit is equal to 0 and the second data bit is equal to 0, the data line is biased to a first voltage level; When the first data bit is equal to 1 and the second data bit is equal to 0, the data line is biased to the second voltage level; When the first data bit is equal to 0 and the second data bit is equal to 1, the data line is biased to a third voltage level; as well as When the first data bit is equal to 1 and the second data bit is equal to 1, the data line is biased to the fourth voltage level.

2. The memory device of claim 1, wherein the first voltage level is less than the second voltage level, the third voltage level is between the first voltage level and the second voltage level, and the fourth voltage level is between the first voltage level and the third voltage level.

3. The memory device of claim 1, wherein the first voltage level is a programming voltage level, the second voltage level is an inhibit voltage level, the third voltage level is a slow selective slow programming convergence voltage level, and the fourth voltage level is a fast selective slow programming convergence voltage level.

4. The memory device of claim 1, wherein the third voltage level is halfway between the first voltage level and the second voltage level, and the fourth voltage level is halfway between the first voltage level and the third voltage level.

5. The memory device of claim 1, wherein the controller is further configured to, when the first data bit is equal to 0 and the second data bit is equal to 0: In the first stage, the data line is biased to the first voltage level; In the second stage following the first stage, the data line is made to float; as well as In the third stage following the second stage, the data line is biased to the first voltage level.

6. The memory device of claim 1, wherein the controller is further configured to, when the first data bit is equal to 1 and the second data bit is equal to 0: In the first stage, the data line is biased to the second voltage level; and In the second stage following the first stage, the data line is made to float.

7. The memory device of claim 1, wherein the controller is further configured to, when the first data bit is equal to 0 and the second data bit is equal to 1: In the first stage, the data line is biased to the first voltage level; and In the second stage following the first stage, the data line is biased to the third voltage level.

8. The memory device of claim 1, wherein the controller is further configured to, when the first data bit is equal to 0 and the second data bit is equal to 1: In the first stage, the data line is biased to the first voltage level; In the second stage following the first stage, the data line is biased to the fourth voltage level; as well as In the third stage following the second stage, the data line is biased to the third voltage level.

9. The memory device of claim 1, wherein the controller is further configured to, when the first data bit is equal to 1 and the second data bit is equal to 1: In the first stage, the data line is biased to the first voltage level; In the second stage following the first stage, the data line is made to float; as well as In the third stage following the second stage, the data line is biased to the fourth voltage level.

10. The memory device of claim 1, wherein when the data line is biased to the first voltage level, the second voltage level, the third voltage level, or the fourth voltage level, the controller is further configured to apply a programming pulse to the selected access line.

11. A memory device comprising: The first latch is used to store the first data bit; The second latch is used to store the second data bit; A first node is configured to receive a selected one of a first voltage level and a third voltage level greater than the first voltage level; The second node is configured to receive a second voltage level greater than the third voltage level; Data lines, which are selectively connected to the first latch, the second latch, and a series-connected string of memory cells; A first switch is selectively connected between the first node and the data line; A second switch is selectively connected between the second node and the data line; as well as A controller configured to bias the data line during programming operations of selected memory cells connected to selected access lines in the serially connected string of memory cells. The controller is further configured to: When the first data bit is equal to 0 and the second data bit is equal to 0, the first voltage level is applied to the first node, the first switch is turned on, and the second switch is turned off to bias the data line to the first voltage level; When the first data bit is equal to 1 and the second data bit is equal to 0, the first switch is turned off and the second switch is turned on to bias the data line to the second voltage level. When the first data bit is equal to 0 and the second data bit is equal to 1, the third voltage level is applied to the first node, the first switch is turned on, and the second switch is turned off to bias the data line to the third voltage level; as well as When the first data bit is equal to 1 and the second data bit is equal to 1, the first switch is turned off and the second switch is turned off to bias the data line to a fourth voltage level between the first voltage level and the third voltage level.

12. The memory device of claim 11, wherein the controller is further configured to, when the first data bit is equal to 0 and the second data bit is equal to 0: When the data line is biased to the first voltage level, the first switch is turned off and the data line is allowed to float.

13. The memory device of claim 12, further comprising: A sense amplifier latch, which is selectively connected to the data line, The controller is further configured to, in the case where the first data bit is equal to 0 and the second data bit is equal to 0: When the data line is floating, connect the data line to the sense amplifier latch to maintain the data line at the first voltage level.

14. The memory device of claim 11, wherein the controller is further configured to, when the first data bit is equal to 1 and the second data bit is equal to 0: When the data line is biased to the second voltage level, the data line is made to float.

15. The memory device of claim 11, further comprising: Sensing amplifier latch; as well as A transistor connected between the data line and the sense amplifier latch. The controller is further configured to, in the case where the first data bit is equal to 1 and the second data bit is equal to 1: The fourth voltage level plus the threshold voltage of the transistor is applied to the control gate of the transistor so that the data line is biased to the fourth voltage level via the sense amplifier and the transistor.

16. The memory device of claim 11, further comprising: Sensing amplifier latch; as well as A transistor, which is connected between the data line and the first switch. The controller is further configured to, in the case where the first data bit is equal to 0 and the second data bit is equal to 1: Before biasing the data line to the third voltage level, a fifth voltage level is applied to the control gate of the transistor so that the data line is biased to the fourth voltage level; as well as A sixth voltage level, greater than the fifth voltage level, is applied to the control gate of the transistor to bias the data line to the third voltage level.

17. The memory device of claim 11, wherein when the data line is biased to the first voltage level, the second voltage level, the third voltage level, or the fourth voltage level, the controller is further configured to apply a programming pulse to the selected access line.

18. A memory device comprising: A memory cell array comprising multiple strings of memory cells connected in series; Multiple data lines, wherein each of the multiple series-connected memory cell strings is selectively electrically connected to a corresponding data line among the multiple data lines; Multiple access lines, each of the multiple access lines being connected to the control gate of a corresponding memory cell in each of the multiple series-connected memory cell strings; A page buffer connected to the plurality of data lines, wherein for each of the plurality of data lines, the page buffer includes: A corresponding first latch is used to store the corresponding first data bit; A corresponding second latch, which is used to store the corresponding second data bit; and A controller configured to bias each of the plurality of data lines during programming operations of a corresponding memory cell connected to a selected access line among the plurality of access lines. The controller is further configured for each of the plurality of data lines to: When the corresponding first data bit is equal to 0 and the corresponding second data bit is equal to 0, the corresponding data line is biased to the first voltage level; When the corresponding first data bit is equal to 1 and the corresponding second data bit is equal to 0, the corresponding data line is biased to the second voltage level; When the corresponding first data bit is equal to 0 and the corresponding second data bit is equal to 1, the corresponding data line is biased to a third voltage level; and When the corresponding first data bit is equal to 1 and the corresponding second data bit is equal to 1, the corresponding data line is biased to the fourth voltage level.

19. The memory device of claim 18, wherein the first voltage level is less than the second voltage level, the third voltage level is between the first voltage level and the second voltage level, and the fourth voltage level is between the first voltage level and the third voltage level.

20. The memory device of claim 18, wherein the first voltage level is a programming voltage level, the second voltage level is an inhibit voltage level, the third voltage level is a slow selective slow programming convergence voltage level, and the fourth voltage level is a fast selective slow programming convergence voltage level.

21. The memory device of claim 18, wherein the third voltage level is halfway between the first voltage level and the second voltage level, and the fourth voltage level is halfway between the first voltage level and the third voltage level.

22. The memory device of claim 18, wherein the controller is further configured to: When each corresponding data line is biased to the first voltage level, the second voltage level, the third voltage level, or the fourth voltage level, a programming pulse is applied to the selected access line; Sensing the threshold voltage of each corresponding memory cell connected to the selected access line; In response to the sensed threshold voltage of the corresponding memory cell being less than a first programming verification level, the corresponding first data bit is set to 0 and the corresponding second data bit is set to 0 for the corresponding data line connected to the corresponding memory cell; In response to the sensed threshold voltage of the corresponding memory cell being between the first programming verification level and a second programming verification level greater than the first programming verification level, the corresponding first data bit is set to equal to 1 and the corresponding second data bit is set to equal to 1 for the corresponding data line connected to the corresponding memory cell; In response to the sensed threshold voltage of the corresponding memory cell being between the second programming verification level and a final programming verification level greater than the second programming verification level, the corresponding first data bit is set to 0 and the corresponding second data bit is set to 1 for the corresponding data line connected to the corresponding memory cell; as well as In response to the sensed threshold voltage of the corresponding memory cell being greater than the final programming verification level, the corresponding first data bit is set to 1 and the corresponding second data bit is set to 0 for the corresponding data line connected to the corresponding memory cell.

23. The memory device of claim 18, wherein the memory cell array comprises a TLC memory cell array, a QLC memory cell array, or a PLC memory cell array.

24. The memory device of claim 18, wherein the memory cell array comprises a three-dimensional NAND memory array.

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