Power management techniques

Abstract

This application relates to power management techniques. A memory system can receive a command to exit a first power mode and enter a second power mode. Power consumption of the first power mode can be lower than the second power mode. The memory system can determine, based on receiving the command to exit the first power mode, whether a duration of an idle period associated with the first power mode satisfies a threshold. The memory system can receive another command associated with performing a refresh operation and perform one or more power management operations based on receiving the command and determining that the duration satisfies the threshold.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 397,733, entitled “Power Management Technologies,” filed August 9, 2021, by PORZIO et al., which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The following text generally relates to one or more systems for memory, and more specifically, to power management technology. The technical field involves power management technology. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time, even in the absence of an external power supply. Summary of the Invention

[0006] Describe a device. The device may include a memory device and a controller, the controller being coupled to the memory device and configured to cause the device to: receive a first command to exit a first power mode and enter a second power mode, the first power mode having lower power consumption than the second power mode; determine, at least in part based on exiting the first power mode, whether the duration of an idle period associated with the first power mode satisfies a threshold; receive a second command associated with performing a refresh operation; and perform one or more power management operations, at least in part based on receiving the second command and determining that the duration satisfies the threshold.

[0007] A non-transitory computer-readable medium storing code is described. The code may contain instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a first command to exit a first power mode and enter a second power mode, the first power mode having lower power consumption than the second power mode; determine, at least in part based on exiting the first power mode, whether the duration of an idle period associated with the first power mode satisfies a threshold; receive a second command associated with performing a refresh operation; and, at least in part based on receiving the second command and determining that the duration satisfies the threshold, perform one or more power management operations.

[0008] Describe a method. The method may include: receiving a first command to exit a first power mode and enter a second power mode, the first power mode having lower power consumption than the second power mode; determining, at least in part based on exiting the first power mode, whether the duration of an idle period associated with the first power mode satisfies a threshold; receiving a second command associated with performing a refresh operation; and performing one or more power management operations, at least in part based on receiving the second command and determining that the duration satisfies the threshold. Attached Figure Description

[0009] Figure 1 Examples of systems supporting power management technologies, based on the examples disclosed herein, are shown.

[0010] Figure 2 An example of a timing diagram for a power management technology supported according to the examples disclosed herein is shown.

[0011] Figure 3 An example of a flowchart illustrating a power management technology based on the examples disclosed herein.

[0012] Figure 4 An example of a flowchart illustrating a power management technology based on the examples disclosed herein.

[0013] Figure 5A block diagram of a memory system supporting power management technology according to the examples disclosed herein is shown.

[0014] Figure 6 The flowcharts shown below illustrate one or more methods supporting power management techniques, based on examples disclosed herein. Detailed Implementation

[0015] Some memory systems may have multiple power modes for various situations. For example, a memory system may have a first power mode for performing access operations, a second power mode for saving power (e.g., a low-power mode), and a third power mode (e.g., a hibernation mode) in response to the memory system being idle for a certain duration. In some cases, after entering hibernation mode, the memory system may want to transition to a low-power mode to save more power. To transition from hibernation mode to low-power mode, the memory system may transition to an active mode to perform one or more memory management operations as part of entering low-power mode. For example, the memory system may enter an active mode to transfer information stored in a cache (e.g., a volatile memory device) to a non-volatile memory device (e.g., a NAND device). This series of power management operations performed before entering low-power mode can increase the latency of entering low-power mode after receiving a command to enter low-power mode. For example, the sequence of transitioning from hibernation mode to low-power mode may include: receiving a command to exit hibernation mode, receiving a cache synchronization command, and finally receiving a command that enables the memory system to enter low-power mode (e.g., a start stop unit (SSU) command). Furthermore, entering low-power mode and performing power management operations consumes power and can subject the memory system to performance degradation, potentially increasing latency for other operations related to the host system. Overall memory system performance may decrease, potentially impairing read, write, and erase speeds on the host system. Techniques to improve the efficiency of entering low-power mode and reduce latency in this mode may be needed.

[0016] This document describes techniques, systems, and apparatuses for increasing performance and reducing latency by performing a series of power management operations before entering a low-power mode. For example, a memory system may detect a command pattern, which, if detected, instructs the memory system to transition from a sleep mode to a low-power mode (intermediately transitioning to an active mode to perform one or more power management operations). For example, the memory system may receive a command to exit sleep mode and, upon receiving the command, determine whether the duration of an idle period during sleep mode meets a threshold. The memory system may then receive a command to perform a refresh operation (e.g., a cache synchronization command). If the idle period is determined to meet the threshold, the memory system may anticipate that the final command to enter the low-power mode is likely to arrive. The memory system may perform one or more power management operations after determining that the duration of the idle period meets the threshold and receiving the command to perform the refresh operation. The power management operations may be performed after receiving the command to perform the refresh operation and before receiving the command to enter the low-power mode. Such power management operations are typically performed after receiving the command to enter the low-power mode. By performing power management operations early in the process, the latency of the memory system entering the low-power mode after receiving the command to enter the low-power mode can be reduced.

[0017] By using power management techniques, memory systems can reduce operational latency when entering low-power mode by performing some power management operations after receiving a synchronous cache command and before receiving a command to enter low-power mode. Using power management techniques improves the overall efficiency of memory systems, resulting in improved read, write, and erase speeds, reduced power consumption, improved processing time, and reduced memory cell wear.

[0018] The features of this disclosure are firstly in reference to Figure 1 The features of this disclosure are described in the context of the system. Figure 2-4 The timing and flowcharts are described in the context of this disclosure. These and other features of this disclosure are further supported by references. Figure 5-6 Device diagrams and flowcharts involving power management technologies are shown and described in the context of the device diagrams and flowcharts.

[0019] Figure 1 An example of a system 100 supporting power management technology according to the examples disclosed herein is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0022] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to instances described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more chips, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in host system controller 106 of host system 105 and memory system controller 115 of memory system 110 or otherwise supported between them. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130—and other such operations—collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations described herein belonging to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0029] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130 to perform the functions described herein as belonging to memory system controller 115. Generally, one or more functions described herein as belonging to memory system controller 115 may actually be performed in some cases by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 that is at least partially managed by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a single piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity in the supporting circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, a single block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations can be performed. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d located respectively in planes 165-a, 165-b, 165-c, and 165-d, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, performing parallel operations in different planes 165 may have one or more restrictions, such as parallel operations being performed on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may be alternatively referred to as a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., partially parallel programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., partially parallel erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0037] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. For example, in some cases, such copying and remapping may be performed to account for latency or attrition, rather than erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0038] In some cases, L2P tables can be maintained, and data can be marked as valid or invalid at the page granularity level, and page 175 may contain valid data, invalid data, or no data. Invalid data can be outdated data due to a more recent or updated version of the data being stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175 but may no longer be associated with a valid logical address, such as the logical address referenced by host system 105. Valid data can be the latest version of such data stored on memory device 130. Page 175 that does not contain data can be a page 175 that has never been written to or has been erased.

[0039] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked, causing block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0040] System 100 may include any number of non-transitory computer-readable media supporting power management technologies. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, such instructions, if executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0041] In some cases, memory system 110 may use memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0042] In some instances, memory system 110 may receive a command to exit sleep mode (e.g., a first command). Sleep mode may be an instance of a first power mode. The memory system may determine whether the duration of an idle period meets a threshold. In some cases, the duration of the idle period may extend from receiving a command to enter sleep mode to receiving a command to exit sleep mode. In some cases, the duration of the idle period may extend from an empty command queue to receiving a command to exit sleep mode. In some instances, the memory system may receive a synchronization / sync cache command (e.g., a second command) after determining whether the duration of the idle period meets a threshold.

[0043] If the duration of the idle period fails to meet a threshold (e.g., is below the threshold) and a synchronization cache command is received, the memory system may prevent power management operations from being performed before receiving a command to enter a low-power mode (e.g., an SSU command). In practice, the memory system may perform power management operations after receiving the SSU command. If the duration of the idle period meets a threshold (e.g., is equal to or higher than the threshold) and a synchronization cache command is received, the memory system may perform at least a portion of the power management operations before and after receiving the SSU command. By performing a portion of the power management operations before receiving the SSU command, the memory system can reduce the latency associated with executing the SSU command after receiving it, and can increase the overall performance and efficiency of the memory system.

[0044] Figure 2 An example of a timing diagram 200 supporting power management technology according to the examples disclosed herein is shown. Timing diagram 200 may include an idle period during portion 205, an activation period during portion 210, an idle period evaluation during portion 215, a refresh operation execution during portion 220, the deactivation of some devices during portion 225, and the deactivation of the remaining devices during portion 230. Timing diagram 200 depicts the sequence and duration of events that vary with time t.

[0045] In some cases, a memory system may experience a delay between receiving a command to enter low-power mode and actually entering low-power mode. This delay can increase the power consumption of the memory system. Before entering low-power mode, the memory system may perform power management operations, such as completing ongoing housekeeping tasks. These operations may take time to complete. In some systems, the memory system may begin operations associated with entering low-power mode after receiving the SSU command at the memory system. In these cases, performing the operation can delay the SSU command delay, thus impacting the overall user experience and reducing the overall efficiency of the memory system.

[0046] In these situations, techniques to reduce the power consumption and latency associated with entering a low-power mode may be necessary. For example, the latency and power consumption for transitioning from sleep mode to low-power mode (via an intermediate action mode) can be reduced. By predicting whether the memory system can enter a low-power mode after exiting sleep mode, the memory system can shorten the duration of entering a low-power mode. For example, the memory system can determine (e.g., predict) that the next incoming command is likely an SSU command. Based on this prediction, the memory system can begin operations associated with the SSU command before receiving it at the memory system. By performing power management operations before receiving the SSU command, the memory system can complete the operation before the SSU command arrives, thereby reducing the duration between receiving the SSU command and entering a low-power mode.

[0047] The memory system can determine a threshold associated with the duration of an idle period to determine whether a power management operation can be performed before receiving an SSU command. Determining the duration threshold could be an instance of a training phase (not shown). The memory system can estimate the duration of the idle period between entering and exiting a sleep mode. To estimate the duration, a timer can be allocated each time the memory system receives a command to enter sleep mode (e.g., the memory system enters sleep mode). The memory system can receive a command to exit sleep mode after the duration of the idle period. Upon detecting an exit sleep command, the timer can stop, and the value of the duration can be stored in a register of the memory system (i.e., the timer stops upon receiving the exit sleep command). If the exit sleep command is followed by a cache synchronization command and then an SSU command, the value stored in the register is the threshold and is identified as the target time for the low-power mode. In these cases, the duration of the idle period could be an instance of the amount of time the memory system spends entering a low-power mode.

[0048] In some instances, the host system can inform the memory system of a threshold (e.g., the target time value for a low-power mode). In these cases, the host system can indicate the duration of idle periods to the memory system. For example, the memory system can perform a write operation in a descriptor register based on the threshold received from the host system. Using this technique, the memory system can skip the training phase and determine the threshold with the help of the host system.

[0049] In some cases, a memory system integrated with an automotive system or other vehicle system may implement aspects of timing diagram 200. However, the memory system may detect that the command buffer is empty for a certain duration (e.g., no pending commands to execute) rather than performing power management operations based on a threshold determined from the training phase. In these cases, the host system may prevent the transmission of sleep entry and exit commands. If the memory system determines that the duration of the idle period meets a threshold (e.g., the duration the command buffer is empty), then the memory system may begin performing power management operations. In these cases, threshold determination may be performed before receiving sync cache commands and SSU commands. In some instances, a sleep command may not be present in the memory system; if a sync cache command is received, the memory system may evaluate the threshold, which can enhance battery management of the memory system.

[0050] After the memory system identifies a threshold, it can implement power management techniques. At time t0, a hibernation command 201 can be received. For example, the memory system can enter a hibernation mode (e.g., a first power mode). The memory system can receive the hibernation command 201 from the host system. In hibernation mode, a portion of the memory device in the memory system can be deactivated (e.g., turned off). For example, during hibernation mode, the memory system can deactivate (e.g., disconnect) a protocol layer, which can disconnect the communication line between the host system and the memory system. The memory system can enter a power-saving mode at time t0. For example, the first power mode can be an idle mode, a power-down mode, or an instance of both.

[0051] Section 205 may extend from time t0 to time t1. During section 205, a timer may be activated to determine the duration of an idle period (e.g., idle time). When the memory system is in hibernation mode, the duration of the idle period may span from time t0 to time t1. For example, an idle period may be an instance of a period during which the memory system is in hibernation mode. In some cases, the duration of the idle period may be an instance of 3 seconds or 5 seconds. During section 205, the memory system may perform almost no operations. In some cases, the memory system may perform some memory management operations (e.g., background operations initiated by the memory system) because the memory system is not used to execute commands from the host system. An idle period may be an instance where the command buffer is empty and there is no command to execute for a specified duration.

[0052] At time t1, an exit hibernation command 206 may be received. For example, the memory system may receive an exit hibernation command 206 transmitted by the host system. In these cases, the memory system may exit hibernation mode upon receiving the exit hibernation command. The memory system may deactivate (e.g., stop) a timer associated with the duration of an idle period at time t1. In these cases, exiting hibernation mode may notify the memory system that the duration of the idle period is complete. At time t1, the memory system may be powered on. For example, the memory system may enter an active mode (e.g., a second power mode) in response to exiting hibernation mode. During section 210, the memory system may be powered on. Section 210 may span from time t1 to time t2 and includes the duration of the memory system being powered on (e.g., activated). The second power mode may be an instance of a higher power mode that consumes more energy than hibernation mode. The second power mode may be associated with executing the received command.

[0053] At time t2, the idle period can be evaluated. For example, the memory system can evaluate whether the duration of the idle period during the portion 215 from time t2 to time t3 meets a threshold. For example, the memory system can compare the duration of the idle period with a value stored in a register (e.g., the threshold). If the duration of the idle period is equal to or greater than the threshold, then the memory system can evaluate what steps to take to enter low-power mode. If the duration of the idle period is less than the threshold, then the memory system can prevent the evaluation of what steps to take to enter low-power mode until SSU command 226 is received.

[0054] At time t3, a synchronization cache command 216 may be received. Synchronization cache command 216 may be an instance of a command ensuring that pending data in a volatile cache (e.g., SRAM) can be transferred to a non-volatile cache (e.g., NAND). In these cases, the host system may issue synchronization cache command 216, and the memory system may perform operations associated with the synchronization cache command after receiving it. In some instances, one or more synchronization cache commands may be received at time t3.

[0055] Section 220 may extend from time t3 to time t4. During section 220, the memory system may begin power management operations to prepare for entering a low-power mode based on determining that the duration of the idle period meets a threshold and receiving a synchronization cache command. In some cases, the memory system may perform a refresh operation during section 220. A refresh operation may be an instance of transferring data from cache and volatile memory to non-volatile memory. For example, the memory system may transfer information stored in volatile memory to non-volatile memory during section 220. In these cases, after the memory system exits low-power mode, it can resume operation without re-initializing some or all of the operating parameters.

[0056] The memory system can verify that the contents of the volatile cache have been written to the NAND device and that related information has been successfully transferred. In some cases, the volatile cache may not contain data. The memory system can refresh the data contents (except for the L2P mapping portion), terminate or interrupt ongoing housekeeping operations, or a combination thereof, to prepare for entering a low-power mode. During portion 220, the memory system can transfer copies of the various mappings (e.g., L2P mappings or Physical Validity (PVT) mappings) stored in the volatile cache to the non-volatile memory device (e.g., NAND). In these cases, the memory system can anticipate receiving a command to enter a low-power mode. Based on this anticipation, the memory system can begin the process of entering a low-power mode after receiving a synchronization cache command. In these cases, the memory system can begin performing housekeeping operations during the duration during which the memory system waits to receive SSU command 226 to fully enter low-power mode.

[0057] In some systems, the memory system may initiate the execution of one or more power management operations in response to receiving SSU command 226 (e.g., a third command). By executing the one or more power management operations in response to receiving a synchronization cache command (e.g., before receiving SSU command 226), the memory system can reduce the latency associated with entering a low-power mode. The one or more power management operations may be a refresh operation associated with the memory system's cache during portion 220, a refresh operation associated with the memory system's tables during portion 220, or an example of both.

[0058] In some cases, the memory system may have already performed a refresh operation before entering hibernation mode. In these cases, the memory system may receive a synchronize cache command 216 and may prevent the disconnection of a portion of the memory device and the performance of a refresh operation, since these operations were performed before receiving the synchronize cache command 216. The memory system may prevent the activation of a portion of the memory system during portion 210 in response to performing a refresh operation before entering hibernation mode.

[0059] At time t4, the activation of the memory device can be revoked. For example, the memory system may revoke activation of a portion of the memory device starting at time t4. In these cases, the memory system may continue to perform power management operations during portion 225 before receiving SSU command 226. Portion 225 may extend from time t4 to time t5. During portion 225, some components of the memory system may be revoked (e.g., disconnected). However, the memory system may keep the controller of the memory system active (e.g., on). For example, the memory system may keep the portion of the memory system that receives SSU command 226 active.

[0060] During section 225, the memory system may perform clock gating on at least some of the one or more components, deactivate volatile memory devices associated with the memory system, deactivate one or more components of the memory system, or a combination thereof. The memory system may deactivate volatile memory devices during section 225 based on information transfer during section 220. For example, the memory system may disconnect SRAM. In some cases, the memory system may deactivate a first portion of one or more components associated with the memory system based on performing the one or more power management operations and save an internal pointer table to internal storage.

[0061] At time t5, SSU command 226 (e.g., a third command) can be received. For example, the memory system can receive SSU command 226 and enter a low-power mode (e.g., a third power mode). The host system can issue SSU command 226 to notify the memory system to enter a low-power mode. At time t5, the memory system can begin entering a low-power mode by deactivating the remaining devices during section 230. The low-power mode can be a sleep mode, a power-down mode, or an instance of both. In these cases, SSU command 226 can be an instance of a sleep command, a low-power mode command, a power-down command, or a combination thereof. In these cases, the low-power mode of the memory system consumes less energy compared to hibernation mode and active mode.

[0062] Section 230 may extend from time t5 to time t6. In some instances, the memory system may disconnect some or all of the remaining memory devices during section 230, which may include components that remain active during section 225. For example, the memory system may deactivate a controller configured to receive SSU command 226. The low-power mode may be an example of a sleep mode. For example, the power consumption of the low-power mode may be lower than that of hibernation mode and active mode.

[0063] The duration of portion 230 may be less than the duration during which the memory system blocks power management operations until SSU command 226 is received. The duration of portion 230 can be shortened by initiating power management operations at time t3 instead of time t5. In these cases, the SSU command execution time can be shortened, and the duration between receiving SSU command 226 and disconnecting the memory device can be reduced. At time t6, the memory system can be disconnected (e.g., into a low-power mode). For example, the memory system can be completely powered down at time t6 (e.g., entering a low-power mode).

[0064] The SSU command can be included in the SCSI command set. Although Figure 2 While the SSU command can be described, the same functionality and commands can be performed in other instances. In these cases, the memory system may receive other commands that enable the memory system to enter a low-power mode. For example, in a memory system containing eMMC, the memory system may receive a PON SLEEP notification, which could be an instance of a command that enables the memory system to enter a low-power mode.

[0065] Figure 3 An example of a flowchart 300 supporting power management technology according to the examples disclosed herein is shown. Operation of flowchart 300 can be implemented by any of the devices or components described herein. For example, operation of flowchart 300 can be implemented by reference to... Figure 1-2 The memory system described herein is executed. Alternative examples may be implemented, in which some steps are performed in a different order or not at all. Some steps may additionally include features not mentioned below. Flowchart 300 illustrates a technique in which the memory system can implement power management techniques. Flowchart 300 may be represented in conjunction with reference to... Figure 2 The timing diagram 200 describes a similar operation.

[0066] Various aspects of flowchart 300 may be implemented by a controller and other components. Alternatively, aspects of flowchart 300 may be implemented as instructions stored in a controller (e.g., a controller coupled to a memory system). For example, when executed by the controller (e.g., memory system controller 115), the instructions may cause the controller to perform the operations of flowchart 300.

[0067] At point 305, a hibernation command can be received. For example, the memory system can receive a command (e.g., a fourth command) to enter hibernation mode (e.g., a first power mode). The host system can transmit the hibernation command, and the memory system can receive the hibernation command. In these cases, the memory system can directly enter hibernation mode in response to receiving the command.

[0068] At 310, a timer can be activated. For example, the memory system can activate a timer associated with an idle period in response to (or directly in response to) receiving a command. In some instances, the memory system can start the timer simultaneously with or after receiving a command to enter sleep mode. The timer measures the duration of the idle period between entering and exiting sleep mode.

[0069] At point 315, an exit-sleep command may be received. For example, the memory system may receive a command to exit sleep mode (e.g., a first command). The command may contain instructions to exit sleep mode and enter an active mode (e.g., a second power mode). In these cases, the power consumption of sleep mode may be lower than that of active mode. The host system may transmit the exit-sleep command, and the memory system may enter active mode in response to receiving the command. In some instances, the memory system may directly deactivate a timer associated with an idle cycle in response to receiving the exit-sleep command. For example, the memory system may stop a timer after receiving the exit-sleep command.

[0070] At 320, it can be determined whether a synchronization cache command has been received. For example, the memory system can determine whether a synchronization cache command (e.g., a second command) can be received. The synchronization cache command may be associated with performing a refresh operation. In some instances, the memory system can determine whether the host system has transmitted the synchronization cache command. In these cases, the memory system can determine whether the synchronization cache command is intended for the memory system before receiving it. The memory system can determine whether to receive the synchronization cache command directly in response to receiving an exit-from-sleep command. In other instances, the memory system can determine whether to receive the synchronization cache command directly in response to determining that the duration of an idle period meets a threshold.

[0071] At point 325, if the memory system determines that no synchronous cache command has been received, then the command may be executed. The memory system may determine that a different command (asynchronous cache command) or a different command is expected for the memory system. For example, the memory system may receive a read command to retrieve data from a non-volatile memory device, or it may receive a write command to store data in a non-volatile memory device. In these cases, the memory system may determine that a command different from a synchronous cache command has been received. The command may be an instance of a read command, a write command, an erase command, or a combination thereof. The memory system may receive the command during an active mode. The memory system may execute the command in response to determining that no synchronous cache command has been received at the memory system. In some cases, the memory system may skip (e.g., block) the execution of power management operations and discard power management operations in the queue.

[0072] At 330, if the memory system determines that a synchronization cache command has been received, it can then determine whether the duration of the idle period associated with the sleep mode meets a threshold. In some cases, the determination at 330 can be completed after receiving an exit sleep command (e.g., at 315) and before determining whether the memory system has received a synchronization cache command (e.g., at 320). The memory system can determine whether the duration of the idle period meets the threshold in response to exiting the sleep mode. In some cases, the memory can begin evaluating the duration of the idle period after determining that a synchronization cache command is expected to be used by the memory system but before receiving the synchronization cache command. The threshold can be an instance of a value stored in a register of the memory system. In some cases, the memory system can determine whether the duration meets the threshold based on activating and deactivating a timer and determining the duration of the idle period.

[0073] In some cases, the memory system may receive a synchronized cache command after determining whether the duration of the idle period meets a threshold. In other instances, the memory system may receive a synchronized cache command before determining whether the duration of the idle period meets a threshold. In some cases, the memory system may receive a synchronized cache command during active mode.

[0074] In other instances, the memory system may determine that the duration of an idle cycle fails to meet a threshold. In these cases, an SSU command may be received at 335. For example, the memory system may receive a command to enter a low-power mode in response to determining that the duration of an idle cycle fails to meet a threshold. The power consumption of the low-power mode may be lower than that of the sleep mode and the active mode. In some cases, the memory system may receive an SSU command after receiving a synchronized cache command.

[0075] At 340, one or more power management operations can be performed. For example, the memory system can perform one or more power management operations in response to receiving an SSU command. In these cases, the memory system can deactivate a first portion of one or more components associated with the memory system and a second portion of said one or more components in response to receiving an SSU command. For example, the memory system can disconnect some or all of the components associated with the memory system after receiving an SSU command. In some instances, in response to receiving an SSU command, the memory system can perform a refresh operation associated with the memory system's cache, perform a refresh operation associated with the memory system's tables, perform clock gating on at least some of said one or more components, deactivate a volatile memory device (e.g., SRAM) associated with the memory system, deactivate one or more components of the memory system, or a combination thereof. The memory system can disconnect (e.g., deactivate) the SRAM after transferring information stored in the SRAM to a non-volatile memory device (e.g., NAND) of the memory system. The information may contain a mapping between logical addresses included in the command and physical addresses associated with the NAND.

[0076] In other instances, the memory system may determine that the duration of an idle period meets a threshold. In these cases, at point 345, one or more power management operations may be performed before receiving an SSU command. For example, the memory system may perform one or more power management operations directly in response to determining that the duration of an idle period meets a threshold and receiving a synchronization cache command.

[0077] The memory system can deactivate a first portion of one or more components associated with the memory system. For example, the memory system can disconnect some components before receiving an SSU command, while keeping the remaining components on. The remaining components can be instances of devices configured to receive SSU commands and other components. In response to determining that the duration of an idle cycle meets a threshold and receiving a synchronization cache command, the memory system can perform a refresh operation associated with the memory system's cache, perform a refresh operation associated with the memory system's tables, perform clock gating on at least some of the one or more components, deactivate a volatile memory device associated with the memory system, deactivate one or more components of the memory system, or a combination thereof. The memory system can transfer information stored in the memory system's SRAM to the memory system's NAND, and deactivate the SRAM at least in part based on the transferred information. The transferred information includes a mapping between logical addresses contained in the command and physical addresses associated with non-volatile memory devices.

[0078] At 350, an SSU command may be received. For example, the memory system may receive a command to enter a low-power mode (e.g., a third power mode) (e.g., a third command). The memory system may receive the SSU command after performing one or more power management operations or in response to performing one or more power management operations. For example, the memory system may receive the SSU command in response to deactivating a first portion of the one or more components.

[0079] At 355, the remaining memory devices of the memory system can be deactivated (e.g., disconnected). For example, the memory system can deactivate a second portion of the one or more components in response to receiving an SSU command. In these cases, the memory system can disconnect the remaining devices after receiving the SSU command. The memory system can enter a low-power mode in response to deactivating the second portion.

[0080] The SSU command can be included in the SCSI command set. Although Figure 3 While the SSU command can be described, the same functionality and commands can be performed in other instances. In these cases, the memory system may receive other commands that enable the memory system to enter a low-power mode. For example, in a memory system containing eMMC, the memory system may receive a PON SLEEP notification, which could be an instance of a command that enables the memory system to enter a low-power mode.

[0081] Figure 4 An example of a flowchart 400 supporting power management technology according to the examples disclosed herein is shown. Operation of flowchart 400 can be implemented by any of the devices or components described herein. For example, operation of flowchart 400 can be implemented by reference to... Figure 1-3 The memory system described herein is executed. Alternative examples may be implemented, in which some steps are performed in a different order or not at all. Some steps may additionally include features not mentioned below. Flowchart 400 may illustrate techniques in which the memory system determines thresholds for power management techniques. In some cases, flowchart 400 may be a reference. Figure 2 An example of the training phase described.

[0082] Various aspects of flowchart 400 may be implemented by a controller and other components. Alternatively, aspects of flowchart 400 may be implemented as instructions stored in a controller (e.g., a controller coupled to a memory system). For example, when executed by the controller (e.g., memory system controller 115), the instructions may cause the controller to perform the operations of flowchart 400.

[0083] At point 405, a hibernation command can be received. For example, the memory system can receive a command (e.g., a fourth command) to enter hibernation mode (e.g., a first power mode). The host system can transmit the hibernation command. In these cases, the memory system can receive the command and enter hibernation mode directly in response to receiving the command.

[0084] At 410, a timer can be activated. For example, the memory system can activate a timer associated with an idle period directly in response to receiving the command. In some instances, the memory system can start the timer simultaneously with or after receiving a command to enter sleep mode. The timer can measure the duration of the idle period. The idle period can be the duration between entering and exiting sleep mode.

[0085] At 415, an exit hibernation command may be received. For example, the memory system may receive a command to exit hibernation mode (e.g., a first command). The command may contain instructions to exit hibernation mode and enter an active mode (e.g., a second power mode). In these cases, the power consumption of hibernation mode may be lower than that of active mode. The host system may transmit the exit hibernation command, and the memory system may then enter active mode in response to receiving the command. In some instances, the memory system may directly deactivate a timer associated with an idle cycle in response to receiving the exit hibernation command. For example, the memory system may stop a timer after receiving the exit hibernation command.

[0086] At 420, the duration of the idle period can be determined. For example, the memory system can determine the duration of the idle period in response to receiving an exit hibernation command. Alternatively, the memory system can determine the duration of the idle period and store the value in a register. In these cases, the memory system can directly store the value of the idle period duration in a register in response to determining the duration of the idle period. The memory system can also determine the duration of the idle period and store the value after deactivating the timer.

[0087] At 425, a synchronization cache command can be received. For example, the memory system can receive a command associated with performing a refresh operation (e.g., a second command). The host system can transmit the synchronization cache command, and the memory system can receive the synchronization cache command after determining the duration of an idle period. In some cases, the memory system can receive the synchronization cache command during an active mode.

[0088] At 430, an SSU command can be received. For example, the memory system can receive a command (e.g., a third command) to enter a low-power mode (e.g., a third power mode). The power consumption of the low-power mode can be lower than that of the sleep mode and the active mode. The memory system can receive the SSU command after receiving a synchronous cache command or in response to receiving a synchronous cache command.

[0089] At 435, a threshold can be determined. For example, the memory system can determine that the value stored in the register meets the threshold in response to receiving a synchronous cache command and an SSU command. In these cases, the memory system can determine that the value stored in the register is the threshold based on receiving a synchronous cache command and an SSU command after exiting sleep mode. The memory system can identify the stored value as the target time for low-power mode. The threshold determined at 435 can be the threshold that the memory system... Figure 3 The threshold used at 330.

[0090] The SSU command can be included in the SCSI command set. Although Figure 4 While the SSU command can be described, the same functionality and commands can be performed in other instances. In these cases, the memory system may receive other commands that enable the memory system to enter a low-power mode. For example, in a memory system containing eMMC, the memory system may receive a PON SLEEP notification, which could be an instance of a command that enables the memory system to enter a low-power mode.

[0091] Figure 5 A block diagram 500 of a memory system 520 supporting power management technology according to an example disclosed herein is shown. The memory system 520 may be a reference... Figures 1 to 3 Examples of various aspects of the described memory system. Memory system 520 or its various components may be examples of constructs for implementing various aspects of the power management techniques described herein. For example, memory system 520 may include a hibernation component 525, an idle component 530, a synchronous cache component 535, a power management operator 540, a low-power component 545, a command receiver 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0092] The hibernation component 525 may be configured or otherwise supported to include means for receiving a first command to exit a first power mode and enter a second power mode, wherein the power consumption of the first power mode is lower than that of the second power mode. The idle component 530 may be configured or otherwise supported to include means for determining, at least in part, whether the duration of an idle period associated with the first power mode meets a threshold based on exiting the first power mode. The synchronous cache component 535 may be configured or otherwise supported to include means for receiving a second command associated with performing a refresh operation. The power management operator 540 may be configured or otherwise supported to include means for performing one or more power management operations, at least in part, based on receiving the second command and determining that the duration meets a threshold.

[0093] In some instances, the low-power component 545 may be configured or otherwise support a component for receiving a third command to enter a third power mode with power consumption lower than the first power mode after at least a portion of the one or more power management operations are performed.

[0094] In some instances, the power management operator 540 may be configured or otherwise supported to deactivate a first portion of one or more components associated with a memory system, at least in part based on performing the one or more power management operations, wherein receiving a third command is at least in part based on deactivating the first portion of the one or more components. In some instances, the power management operator 540 may be configured or otherwise supported to deactivate a second portion of the one or more components, at least in part based on receiving a third command.

[0095] In some instances, the hibernation component 525 may be configured or otherwise supported to include means for receiving a fourth command to enter a first power mode. In some instances, the idle component 530 may be configured or otherwise supported to include means for activating a timer associated with an idle period, at least in part based on receiving the fourth command, wherein determining whether a duration satisfies a threshold is at least in part based on activating the timer.

[0096] In some instances, the idle component 530 may be configured or otherwise support a means for revoking the activation of a timer associated with an idle period based at least in part on receiving a first command, wherein determining whether a duration satisfies a threshold is based at least in part on revoking the timer.

[0097] In some instances, the idle component 530 may be configured or otherwise supported to include means for determining the duration of an idle period based at least in part on the receipt of a first command. In some instances, the idle component 530 may be configured or otherwise supported to include means for storing a value of the duration of an idle period in a register based at least in part on the determination of the duration of the idle period, wherein the determination of whether the duration satisfies a threshold is based at least in part on the stored value.

[0098] In some instances, the low-power component 545 may be configured or otherwise supported for receiving a third command, at least in part, to enter a third power mode with power consumption lower than the first power mode based on receiving a second command. In some instances, the idle component 530 may be configured or otherwise supported for determining, at least in part, based on receiving both the second and third commands, that a value stored in a register satisfies a threshold, wherein determining whether a duration satisfies the threshold is at least in part based on determining that the value stored in the register satisfies the threshold.

[0099] In some instances, the power management operator 540 may be configured or otherwise support components for: performing refresh operations associated with the cache of the memory system, performing refresh operations associated with the tables of the memory system, performing clock gating on one or more components, deactivating volatile memory devices associated with the memory system, deactivating one or more components of the memory system, or a combination thereof.

[0100] In some instances, the power management operator 540 may be configured or otherwise support means for transferring information stored in a volatile memory device of a memory system to a non-volatile memory device of the memory system. In some instances, the power management operator 540 may be configured or otherwise support means for deactivating a volatile memory device, at least in part, based on the transferred information.

[0101] In some instances, the volatile memory device comprises the static random access memory of the memory system. In some instances, the non-volatile memory device comprises the NAND memory of the memory system. In some instances, the information contains a mapping between the logical address contained in the command and the physical address associated with the non-volatile memory device.

[0102] In some instances, the first command includes an exit hibernation command. In some instances, the second command includes a cache synchronization command.

[0103] Figure 6A flowchart illustrating an example disclosed herein shows a method 600 supporting power management technology. The operation of method 600 may be implemented by a memory system or its components as described herein. For example, the operation of method 600 may be provided by reference to... Figures 1 to 5 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the function. Alternatively, the memory system may use dedicated hardware to perform aspects of the function.

[0104] At 605, a first command may be received. For example, the method may include receiving a first command to exit a first power mode and enter a second power mode, the first power mode having lower power consumption than the second power mode. Operation 605 may be performed according to the examples disclosed herein. In some examples, aspects of operation 605 may be referenced... Figure 5 The described hibernation component 525 is executed.

[0105] At 610, the duration of the idle cycle can be determined. For example, the method may include determining, at least in part, whether the duration of the idle cycle associated with the first power mode satisfies a threshold based on exiting the first power mode. Operation 610 can be performed according to the examples disclosed herein. In some instances, aspects of operation 610 may be referenced from... Figure 5 The described idle component 530 is executed.

[0106] At point 615, a second command may be received. For example, the method may include receiving a second command associated with performing a refresh operation. Operation 615 may be performed according to the examples disclosed herein. In some instances, aspects of operation 615 may be derived from references. Figure 5 The described synchronous cache component 535 is executed.

[0107] At 620, one or more power management operations may be performed. For example, the method may include performing one or more power management operations at least in part based on receiving a second command and determining that the duration meets a threshold. Operation 620 may be performed according to the examples disclosed herein. In some instances, aspects of operation 620 may be referenced from... Figure 5 The power management operator 540 described is executed.

[0108] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a first command to exit a first power mode and enter a second power mode, the first power mode consuming less power than the second power mode; determining, at least in part, based on exiting the first power mode, whether the duration of an idle period associated with the first power mode satisfies a threshold; receiving a second command associated with performing a refresh operation; and performing one or more power management operations, at least in part, based on receiving the second command and determining that the duration satisfies the threshold.

[0109] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for receiving a third command to enter a third power mode with power consumption lower than a first power mode after performing at least a portion of the one or more power management operations.

[0110] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: deactivating a first portion of one or more components associated with a memory system at least in part based on performing the one or more power management operations, wherein receiving a third command may be at least in part based on deactivating the first portion of the one or more components, and deactivating a second portion of the one or more components may be at least in part based on receiving the third command.

[0111] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: receiving a fourth command to enter a first power mode and activating a timer associated with an idle period, at least in part based on receiving the fourth command, wherein determining whether a duration satisfies a threshold may be at least in part based on activating the timer.

[0112] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: deactivating a timer associated with an idle period, at least in part based on receiving a first command, wherein determining whether a duration satisfies a threshold may be based at least in part on deactivating the timer.

[0113] Method 600 and some instances of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: determining the duration of an idle period at least in part based on receiving a first command, and storing a value of the duration of the idle period in a register at least in part based on the determined duration of the idle period, wherein determining whether the duration satisfies a threshold may be based at least in part on the stored value.

[0114] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: receiving a third command to enter a third power mode with power consumption lower than a first power mode, at least in part based on receiving a second command, and determining, at least in part based on receiving both the second and third commands, that a value stored in a register satisfies a threshold, wherein determining whether a duration satisfies the threshold may be at least in part based on determining that a value stored in a register satisfies the threshold.

[0115] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: performing a refresh operation associated with a cache of the memory system, performing a refresh operation associated with a table of the memory system, performing clock gating on one or more components, deactivating a volatile memory device associated with the memory system, deactivating one or more components of the memory system, or a combination thereof.

[0116] Method 600 and some examples of the apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: transferring information stored in a volatile memory device of a memory system to a non-volatile memory device of the memory system, and deactivating a volatile memory device at least in part based on the transferred information.

[0117] In some instances of method 600 and the device described herein, the volatile memory device includes static random access memory of a memory system, the non-volatile memory device includes NAND memory of a memory system, and the information includes a mapping between the logical address contained in the command and the physical address associated with the non-volatile memory device.

[0118] In some instances of method 600 and the device described herein, the first command includes an exit hibernation command and the second command includes a cache synchronization command.

[0119] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0120] Describe a device. The device may include a memory device and a controller, the controller being coupled to the memory device and configured to cause the device to: receive a first command to exit a first power mode and enter a second power mode, the first power mode having lower power consumption than the second power mode; determine, at least in part based on exiting the first power mode, whether the duration of an idle period associated with the first power mode satisfies a threshold; receive a second command associated with performing a refresh operation; and perform one or more power management operations, at least in part based on receiving the second command and determining that the duration satisfies the threshold.

[0121] In some instances, the controller may be further configured to cause the device to receive a third command to enter a third power mode with lower power consumption than the first power mode after performing at least a portion of the one or more power management operations.

[0122] In some instances, the controller may be further configured to cause the device to: at least in part deactivate a first portion of one or more components associated with the memory system based on performing the one or more power management operations, wherein receiving a third command is at least in part based on deactivating the first portion of the one or more components, and deactivating a second portion of the one or more components is at least in part based on receiving the third command.

[0123] In some instances, the controller may be further configured to cause the device to: receive a fourth command to enter a first power mode, and activate a timer associated with an idle period based at least in part on the receipt of the fourth command, wherein determining whether the duration satisfies a threshold is based at least in part on the activation of the timer.

[0124] In some instances, the controller may be further configured to cause the device to: at least in part deactivate a timer associated with an idle period based on receiving a first command, wherein determining whether a duration satisfies a threshold is at least in part based on deactivating the timer.

[0125] In some instances, the controller may be further configured to cause the device to: determine the duration of the idle period at least in part based on receiving a first command, and store a value of the duration of the idle period in a register at least in part based on the determined duration of the idle period, wherein determining whether the duration satisfies a threshold is based at least in part on the stored value.

[0126] In some instances, the controller may be further configured to cause the device to: receive a third command to enter a third power mode with power consumption lower than the first power mode, at least in part based on receiving the second command, and determine, at least in part based on receiving both the second and third commands, that a value stored in a register satisfies a threshold, wherein determining whether the duration satisfies the threshold is at least in part based on determining that the value stored in the register satisfies the threshold.

[0127] In some instances, in order to perform the one or more power management operations, the controller may be further configured to cause the device to: perform a refresh operation associated with the cache of the memory system, perform a refresh operation associated with the table of the memory system, perform clock gating on one or more components, deactivate volatile memory devices associated with the memory system, deactivate one or more components of the memory system, or a combination thereof.

[0128] In some instances, in order to perform the one or more power management operations, the controller may be further configured to cause the device to: transfer information stored in a volatile memory device of the memory system to a non-volatile memory device of the memory system, and deactivate the volatile memory device at least in part based on the transferred information.

[0129] In some instances, the volatile memory device includes the static random access memory of the memory system, the non-volatile memory device includes the NAND memory of the memory system, and the information includes a mapping between the logical address contained in the command and the physical address associated with the non-volatile memory device.

[0130] In some instances, the first command includes an exit hibernation command, and the second command includes a cache synchronization command.

[0131] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0132] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0133] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If, for example, one component of a controller couples other components together, then that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0134] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0135] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, these terms are used interchangeably if they describe the connection between conditional actions, conditional processes, or process parts.

[0136] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0137] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other condition or action.

[0138] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0139] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0140] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0141] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0142] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0143] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0144] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0145] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0146] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the device to: Receive a first command to exit sleep mode and enter active mode, wherein the power consumption of sleep mode is lower than that of active mode; Based at least in part on exiting the hibernation mode, it is determined whether the duration of the idle period between performing a refresh operation in the active mode and transitioning from the active mode to the sleep mode meets a threshold, wherein the power consumption of the sleep mode is lower than that of the hibernation mode; During the idle period, a second command associated with performing the refresh operation is received; as well as Before receiving a third command to enter the sleep mode, one or more power management operations associated with entering the sleep mode are performed, at least in part based on determining that the duration of the idle cycle meets the threshold.

2. The device of claim 1, wherein the controller is further configured to cause the device to: After performing at least a portion of the one or more power management operations associated with entering the sleep mode, the third command to enter a sleep mode with lower power consumption than the hibernation mode is received.

3. The device of claim 2, wherein the controller is further configured to cause the device to: At least in part based on performing the one or more power management operations, the activation of a first portion of one or more components associated with the memory system is revoked, wherein receiving the third command is at least in part based on revoking the activation of the first portion of the one or more components; and At least in part based on receiving the third command, the second part of activating one or more components is deactivated.

4. The device of claim 1, wherein the controller is further configured to cause the device to: Receive a fourth command to enter the hibernation mode; and At least in part based on receiving the fourth command, a timer associated with the idle period is activated, wherein determining whether the duration satisfies the threshold is at least in part based on activating the timer.

5. The device of claim 4, wherein the controller is further configured to cause the device to: At least in part based on receiving the first command, the activation of the timer associated with the idle period is revoked, wherein determining whether the duration satisfies the threshold is at least in part based on revoking the activation of the timer.

6. The device of claim 1, wherein the controller is further configured to cause the device to: The duration of the idle period is determined, at least in part, based on receiving the first command; and The value of the duration of the idle period is stored in a register, at least in part based on determining the duration of the idle period, wherein determining whether the duration satisfies the threshold is at least in part based on storing the value.

7. The device of claim 6, wherein the controller is further configured to cause the device to: At least in part based on receiving the second command, receiving the third command to enter a sleep mode with lower power consumption than the hibernation mode; and The value stored in the register is determined to satisfy the threshold, at least in part based on receiving the second command and receiving the third command, wherein determining whether the duration satisfies the threshold is at least in part based on determining that the value stored in the register satisfies the threshold.

8. The device of claim 1, wherein, in order to perform the one or more power management operations, the controller is configured to cause the device to: Perform refresh operations associated with the cache of the memory system, perform refresh operations associated with the tables of the memory system, perform clock gating on one or more components, deactivate volatile memory devices associated with the memory system, deactivate one or more components of the memory system, or a combination thereof.

9. The device of claim 1, wherein, in order to perform the one or more power management operations, the controller is configured to cause the device to: Transferring information stored in a volatile memory device of the memory system to a non-volatile memory device of the memory system; and The activation of the volatile memory device is deactivated, at least in part, based on the transmission of the information.

10. The device according to claim 9, wherein: The volatile memory device includes the static random access memory of the memory system; The non-volatile memory device includes the NAND memory of the memory system; and The information includes a mapping between the logical address contained in the command and the physical address associated with the non-volatile memory device.

11. The device according to claim 1, wherein: The first command includes an exit hibernation command; and The second command includes a cache synchronization command.

12. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive a first command to exit sleep mode and enter active mode, wherein the power consumption of sleep mode is lower than that of active mode; Based at least in part on exiting the hibernation mode, it is determined whether the duration of the idle period between performing a refresh operation in the active mode and transitioning from the active mode to the sleep mode meets a threshold, wherein the power consumption of the sleep mode is lower than that of the hibernation mode; During the idle period, a second command associated with performing the refresh operation is received; as well as Before receiving a third command to enter the sleep mode, one or more power management operations associated with entering the sleep mode are performed, at least in part based on determining that the duration of the idle cycle meets the threshold.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: After performing at least a portion of the one or more power management operations, the third command to enter a sleep mode with power consumption lower than the hibernation mode is received.

14. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: At least in part based on performing the one or more power management operations, the activation of a first portion of one or more components associated with the memory system is revoked, wherein receiving the third command is at least in part based on revoking the activation of the first portion of the one or more components; and At least in part based on receiving the third command, the second part of activating one or more components is deactivated.

15. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Receive a fourth command to enter the hibernation mode; and At least in part based on receiving the fourth command, a timer associated with the idle period is activated, wherein determining whether the duration satisfies the threshold is at least in part based on activating the timer.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: At least in part based on receiving the first command, the activation of the timer associated with the idle period is revoked, wherein determining whether the duration satisfies the threshold is at least in part based on revoking the activation of the timer.

17. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The duration of the idle period is determined, at least in part, based on receiving the first command; and The value of the duration of the idle period is stored in a register, at least in part based on determining the duration of the idle period, wherein determining whether the duration satisfies the threshold is at least in part based on storing the value.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: At least in part based on receiving the second command, receiving the third command to enter a sleep mode with lower power consumption than the hibernation mode; and The value stored in the register is determined to satisfy the threshold, at least in part based on receiving the second command and receiving the third command, wherein determining whether the duration satisfies the threshold is at least in part based on determining that the value stored in the register satisfies the threshold.

19. The non-transitory computer-readable medium of claim 12, wherein, in order to perform the one or more power management operations, the instructions, when executed by the processor of the electronic device, cause the electronic device to: Perform refresh operations associated with the cache of the memory system, perform refresh operations associated with the tables of the memory system, perform clock gating on one or more components, deactivate volatile memory devices associated with the memory system, deactivate one or more components of the memory system, or a combination thereof.

20. The non-transitory computer-readable medium of claim 12, wherein, in order to perform the one or more power management operations, the instructions, when executed by the processor of the electronic device, cause the electronic device to: Transferring information stored in a volatile memory device of the memory system to a non-volatile memory device of the memory system; and The activation of the volatile memory device is deactivated, at least in part, based on the transmission of the information.

21. The non-transitory computer-readable medium of claim 20, wherein: The volatile memory device includes the static random access memory of the memory system; The non-volatile memory device includes the NAND memory of the memory system; and The information includes a mapping between the logical address contained in the command and the physical address associated with the non-volatile memory device.

22. The non-transitory computer-readable medium according to claim 12, wherein: The first command includes an exit hibernation command; and The second command includes a cache synchronization command.

23. A method comprising: Receive a first command to exit sleep mode and enter active mode, wherein the power consumption of sleep mode is lower than that of active mode; Based at least in part on exiting the hibernation mode, it is determined whether the duration of the idle period between performing a refresh operation in the active mode and transitioning from the active mode to the sleep mode meets a threshold, wherein the power consumption of the sleep mode is lower than that of the hibernation mode; During the idle period, a second command associated with performing the refresh operation is received; as well as Before receiving a third command to enter the sleep mode, one or more power management operations associated with entering the sleep mode are performed, at least in part based on determining that the duration meets the threshold.

24. The method of claim 23, further comprising: After performing at least a portion of the one or more power management operations associated with entering the sleep mode, the third command to enter a sleep mode with lower power consumption than the hibernation mode is received.

25. The method of claim 24, further comprising: The third command is received at least in part based on the execution of the one or more power management operations, to deactivate a first portion of one or more components associated with the memory system, wherein the third command is received at least in part based on the deactivation of the first portion of the one or more components. as well as At least in part based on receiving the third command, the second part of activating one or more components is deactivated.

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